1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 #define HNS3_MOD_VERSION "1.0" 12 13 extern const char hns3_driver_version[]; 14 15 enum hns3_nic_state { 16 HNS3_NIC_STATE_TESTING, 17 HNS3_NIC_STATE_RESETTING, 18 HNS3_NIC_STATE_INITED, 19 HNS3_NIC_STATE_DOWN, 20 HNS3_NIC_STATE_DISABLED, 21 HNS3_NIC_STATE_REMOVING, 22 HNS3_NIC_STATE_SERVICE_INITED, 23 HNS3_NIC_STATE_SERVICE_SCHED, 24 HNS3_NIC_STATE2_RESET_REQUESTED, 25 HNS3_NIC_STATE_MAX 26 }; 27 28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 36 37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 40 #define HNS3_RING_TX_RING_TC_REG 0x00050 41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 45 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 46 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 47 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 48 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 49 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 50 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 51 #define HNS3_RING_ASID_REG 0x0008C 52 #define HNS3_RING_EN_REG 0x00090 53 #define HNS3_RING_T0_BE_RST 0x00094 54 #define HNS3_RING_COULD_BE_RST 0x00098 55 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 56 57 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 58 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 59 #define HNS3_RX_RING_INT_STS_REG 0x000A8 60 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 61 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 62 #define HNS3_TX_RING_INT_STS_REG 0x000B4 63 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 64 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 65 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 66 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 67 68 #define HNS3_RING_MB_CTRL_REG 0x00100 69 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 70 71 #define HNS3_TX_REG_OFFSET 0x40 72 73 #define HNS3_RX_HEAD_SIZE 256 74 75 #define HNS3_TX_TIMEOUT (5 * HZ) 76 #define HNS3_RING_NAME_LEN 16 77 #define HNS3_BUFFER_SIZE_2048 2048 78 #define HNS3_RING_MAX_PENDING 32760 79 #define HNS3_RING_MIN_PENDING 72 80 #define HNS3_RING_BD_MULTIPLE 8 81 /* max frame size of mac */ 82 #define HNS3_MAC_MAX_FRAME 9728 83 #define HNS3_MAX_MTU \ 84 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 85 86 #define HNS3_BD_SIZE_512_TYPE 0 87 #define HNS3_BD_SIZE_1024_TYPE 1 88 #define HNS3_BD_SIZE_2048_TYPE 2 89 #define HNS3_BD_SIZE_4096_TYPE 3 90 91 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 92 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 93 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 94 #define HNS3_RX_FLAG_L4ID_UDP 0x0 95 #define HNS3_RX_FLAG_L4ID_TCP 0x1 96 97 #define HNS3_RXD_DMAC_S 0 98 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 99 #define HNS3_RXD_VLAN_S 2 100 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 101 #define HNS3_RXD_L3ID_S 4 102 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 103 #define HNS3_RXD_L4ID_S 8 104 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 105 #define HNS3_RXD_FRAG_B 12 106 #define HNS3_RXD_STRP_TAGP_S 13 107 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 108 109 #define HNS3_RXD_L2E_B 16 110 #define HNS3_RXD_L3E_B 17 111 #define HNS3_RXD_L4E_B 18 112 #define HNS3_RXD_TRUNCAT_B 19 113 #define HNS3_RXD_HOI_B 20 114 #define HNS3_RXD_DOI_B 21 115 #define HNS3_RXD_OL3E_B 22 116 #define HNS3_RXD_OL4E_B 23 117 #define HNS3_RXD_GRO_COUNT_S 24 118 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 119 #define HNS3_RXD_GRO_FIXID_B 30 120 #define HNS3_RXD_GRO_ECN_B 31 121 122 #define HNS3_RXD_ODMAC_S 0 123 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 124 #define HNS3_RXD_OVLAN_S 2 125 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 126 #define HNS3_RXD_OL3ID_S 4 127 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 128 #define HNS3_RXD_OL4ID_S 8 129 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 130 #define HNS3_RXD_FBHI_S 12 131 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 132 #define HNS3_RXD_FBLI_S 14 133 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 134 135 #define HNS3_RXD_BDTYPE_S 0 136 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 137 #define HNS3_RXD_VLD_B 4 138 #define HNS3_RXD_UDP0_B 5 139 #define HNS3_RXD_EXTEND_B 7 140 #define HNS3_RXD_FE_B 8 141 #define HNS3_RXD_LUM_B 9 142 #define HNS3_RXD_CRCP_B 10 143 #define HNS3_RXD_L3L4P_B 11 144 #define HNS3_RXD_TSIND_S 12 145 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 146 #define HNS3_RXD_LKBK_B 15 147 #define HNS3_RXD_GRO_SIZE_S 16 148 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 149 150 #define HNS3_TXD_L3T_S 0 151 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 152 #define HNS3_TXD_L4T_S 2 153 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 154 #define HNS3_TXD_L3CS_B 4 155 #define HNS3_TXD_L4CS_B 5 156 #define HNS3_TXD_VLAN_B 6 157 #define HNS3_TXD_TSO_B 7 158 159 #define HNS3_TXD_L2LEN_S 8 160 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 161 #define HNS3_TXD_L3LEN_S 16 162 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 163 #define HNS3_TXD_L4LEN_S 24 164 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 165 166 #define HNS3_TXD_OL3T_S 0 167 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 168 #define HNS3_TXD_OVLAN_B 2 169 #define HNS3_TXD_MACSEC_B 3 170 #define HNS3_TXD_TUNTYPE_S 4 171 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 172 173 #define HNS3_TXD_BDTYPE_S 0 174 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 175 #define HNS3_TXD_FE_B 4 176 #define HNS3_TXD_SC_S 5 177 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 178 #define HNS3_TXD_EXTEND_B 7 179 #define HNS3_TXD_VLD_B 8 180 #define HNS3_TXD_RI_B 9 181 #define HNS3_TXD_RA_B 10 182 #define HNS3_TXD_TSYN_B 11 183 #define HNS3_TXD_DECTTL_S 12 184 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 185 186 #define HNS3_TXD_MSS_S 0 187 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 188 189 #define HNS3_TX_LAST_SIZE_M 0xffff 190 191 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 192 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 193 194 #define HNS3_VECTOR_NOT_INITED 0 195 #define HNS3_VECTOR_INITED 1 196 197 #define HNS3_MAX_BD_SIZE 65535 198 #define HNS3_MAX_NON_TSO_BD_NUM 8U 199 #define HNS3_MAX_TSO_BD_NUM 63U 200 #define HNS3_MAX_TSO_SIZE \ 201 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM) 202 203 #define HNS3_MAX_NON_TSO_SIZE \ 204 (HNS3_MAX_BD_SIZE * HNS3_MAX_NON_TSO_BD_NUM) 205 206 #define HNS3_VECTOR_GL0_OFFSET 0x100 207 #define HNS3_VECTOR_GL1_OFFSET 0x200 208 #define HNS3_VECTOR_GL2_OFFSET 0x300 209 #define HNS3_VECTOR_RL_OFFSET 0x900 210 #define HNS3_VECTOR_RL_EN_B 6 211 212 #define HNS3_RING_EN_B 0 213 214 enum hns3_pkt_l2t_type { 215 HNS3_L2_TYPE_UNICAST, 216 HNS3_L2_TYPE_MULTICAST, 217 HNS3_L2_TYPE_BROADCAST, 218 HNS3_L2_TYPE_INVALID, 219 }; 220 221 enum hns3_pkt_l3t_type { 222 HNS3_L3T_NONE, 223 HNS3_L3T_IPV6, 224 HNS3_L3T_IPV4, 225 HNS3_L3T_RESERVED 226 }; 227 228 enum hns3_pkt_l4t_type { 229 HNS3_L4T_UNKNOWN, 230 HNS3_L4T_TCP, 231 HNS3_L4T_UDP, 232 HNS3_L4T_SCTP 233 }; 234 235 enum hns3_pkt_ol3t_type { 236 HNS3_OL3T_NONE, 237 HNS3_OL3T_IPV6, 238 HNS3_OL3T_IPV4_NO_CSUM, 239 HNS3_OL3T_IPV4_CSUM 240 }; 241 242 enum hns3_pkt_tun_type { 243 HNS3_TUN_NONE, 244 HNS3_TUN_MAC_IN_UDP, 245 HNS3_TUN_NVGRE, 246 HNS3_TUN_OTHER 247 }; 248 249 /* hardware spec ring buffer format */ 250 struct __packed hns3_desc { 251 __le64 addr; 252 union { 253 struct { 254 __le16 vlan_tag; 255 __le16 send_size; 256 union { 257 __le32 type_cs_vlan_tso_len; 258 struct { 259 __u8 type_cs_vlan_tso; 260 __u8 l2_len; 261 __u8 l3_len; 262 __u8 l4_len; 263 }; 264 }; 265 __le16 outer_vlan_tag; 266 __le16 tv; 267 268 union { 269 __le32 ol_type_vlan_len_msec; 270 struct { 271 __u8 ol_type_vlan_msec; 272 __u8 ol2_len; 273 __u8 ol3_len; 274 __u8 ol4_len; 275 }; 276 }; 277 278 __le32 paylen; 279 __le16 bdtp_fe_sc_vld_ra_ri; 280 __le16 mss; 281 } tx; 282 283 struct { 284 __le32 l234_info; 285 __le16 pkt_len; 286 __le16 size; 287 288 __le32 rss_hash; 289 __le16 fd_id; 290 __le16 vlan_tag; 291 292 union { 293 __le32 ol_info; 294 struct { 295 __le16 o_dm_vlan_id_fb; 296 __le16 ot_vlan_tag; 297 }; 298 }; 299 300 __le32 bd_base_info; 301 } rx; 302 }; 303 }; 304 305 struct hns3_desc_cb { 306 dma_addr_t dma; /* dma address of this desc */ 307 void *buf; /* cpu addr for a desc */ 308 309 /* priv data for the desc, e.g. skb when use with ip stack */ 310 void *priv; 311 u32 page_offset; 312 u32 length; /* length of the buffer */ 313 314 u16 reuse_flag; 315 316 /* desc type, used by the ring user to mark the type of the priv data */ 317 u16 type; 318 }; 319 320 enum hns3_pkt_l3type { 321 HNS3_L3_TYPE_IPV4, 322 HNS3_L3_TYPE_IPV6, 323 HNS3_L3_TYPE_ARP, 324 HNS3_L3_TYPE_RARP, 325 HNS3_L3_TYPE_IPV4_OPT, 326 HNS3_L3_TYPE_IPV6_EXT, 327 HNS3_L3_TYPE_LLDP, 328 HNS3_L3_TYPE_BPDU, 329 HNS3_L3_TYPE_MAC_PAUSE, 330 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 331 332 /* reserved for 0xA~0xB */ 333 334 HNS3_L3_TYPE_CNM = 0xc, 335 336 /* reserved for 0xD~0xE */ 337 338 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 339 }; 340 341 enum hns3_pkt_l4type { 342 HNS3_L4_TYPE_UDP, 343 HNS3_L4_TYPE_TCP, 344 HNS3_L4_TYPE_GRE, 345 HNS3_L4_TYPE_SCTP, 346 HNS3_L4_TYPE_IGMP, 347 HNS3_L4_TYPE_ICMP, 348 349 /* reserved for 0x6~0xE */ 350 351 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 352 }; 353 354 enum hns3_pkt_ol3type { 355 HNS3_OL3_TYPE_IPV4 = 0, 356 HNS3_OL3_TYPE_IPV6, 357 /* reserved for 0x2~0x3 */ 358 HNS3_OL3_TYPE_IPV4_OPT = 4, 359 HNS3_OL3_TYPE_IPV6_EXT, 360 361 /* reserved for 0x6~0xE */ 362 363 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 364 }; 365 366 enum hns3_pkt_ol4type { 367 HNS3_OL4_TYPE_NO_TUN, 368 HNS3_OL4_TYPE_MAC_IN_UDP, 369 HNS3_OL4_TYPE_NVGRE, 370 HNS3_OL4_TYPE_UNKNOWN 371 }; 372 373 struct ring_stats { 374 u64 io_err_cnt; 375 u64 sw_err_cnt; 376 u64 seg_pkt_cnt; 377 union { 378 struct { 379 u64 tx_pkts; 380 u64 tx_bytes; 381 u64 tx_err_cnt; 382 u64 restart_queue; 383 u64 tx_busy; 384 u64 tx_copy; 385 u64 tx_vlan_err; 386 u64 tx_l4_proto_err; 387 u64 tx_l2l3l4_err; 388 u64 tx_tso_err; 389 }; 390 struct { 391 u64 rx_pkts; 392 u64 rx_bytes; 393 u64 rx_err_cnt; 394 u64 reuse_pg_cnt; 395 u64 err_pkt_len; 396 u64 err_bd_num; 397 u64 l2_err; 398 u64 l3l4_csum_err; 399 u64 rx_multicast; 400 u64 non_reuse_pg; 401 }; 402 }; 403 }; 404 405 struct hns3_enet_ring { 406 u8 __iomem *io_base; /* base io address for the ring */ 407 struct hns3_desc *desc; /* dma map address space */ 408 struct hns3_desc_cb *desc_cb; 409 struct hns3_enet_ring *next; 410 struct hns3_enet_tqp_vector *tqp_vector; 411 struct hnae3_queue *tqp; 412 int queue_index; 413 struct device *dev; /* will be used for DMA mapping of descriptors */ 414 415 /* statistic */ 416 struct ring_stats stats; 417 struct u64_stats_sync syncp; 418 419 dma_addr_t desc_dma_addr; 420 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 421 u16 desc_num; /* total number of desc */ 422 int next_to_use; /* idx of next spare desc */ 423 424 /* idx of lastest sent desc, the ring is empty when equal to 425 * next_to_use 426 */ 427 int next_to_clean; 428 429 u32 pull_len; /* head length for current packet */ 430 u32 frag_num; 431 unsigned char *va; /* first buffer address for current packet */ 432 433 u32 flag; /* ring attribute */ 434 435 int pending_buf; 436 struct sk_buff *skb; 437 struct sk_buff *tail_skb; 438 } ____cacheline_internodealigned_in_smp; 439 440 enum hns3_flow_level_range { 441 HNS3_FLOW_LOW = 0, 442 HNS3_FLOW_MID = 1, 443 HNS3_FLOW_HIGH = 2, 444 HNS3_FLOW_ULTRA = 3, 445 }; 446 447 #define HNS3_INT_GL_MAX 0x1FE0 448 #define HNS3_INT_GL_50K 0x0014 449 #define HNS3_INT_GL_20K 0x0032 450 #define HNS3_INT_GL_18K 0x0036 451 #define HNS3_INT_GL_8K 0x007C 452 453 #define HNS3_INT_RL_MAX 0x00EC 454 #define HNS3_INT_RL_ENABLE_MASK 0x40 455 456 struct hns3_enet_coalesce { 457 u16 int_gl; 458 u8 gl_adapt_enable; 459 enum hns3_flow_level_range flow_level; 460 }; 461 462 struct hns3_enet_ring_group { 463 /* array of pointers to rings */ 464 struct hns3_enet_ring *ring; 465 u64 total_bytes; /* total bytes processed this group */ 466 u64 total_packets; /* total packets processed this group */ 467 u16 count; 468 struct hns3_enet_coalesce coal; 469 }; 470 471 struct hns3_enet_tqp_vector { 472 struct hnae3_handle *handle; 473 u8 __iomem *mask_addr; 474 int vector_irq; 475 int irq_init_flag; 476 477 u16 idx; /* index in the TQP vector array per handle. */ 478 479 struct napi_struct napi; 480 481 struct hns3_enet_ring_group rx_group; 482 struct hns3_enet_ring_group tx_group; 483 484 cpumask_t affinity_mask; 485 u16 num_tqps; /* total number of tqps in TQP vector */ 486 struct irq_affinity_notify affinity_notify; 487 488 char name[HNAE3_INT_NAME_LEN]; 489 490 unsigned long last_jiffies; 491 } ____cacheline_internodealigned_in_smp; 492 493 enum hns3_udp_tnl_type { 494 HNS3_UDP_TNL_VXLAN, 495 HNS3_UDP_TNL_GENEVE, 496 HNS3_UDP_TNL_MAX, 497 }; 498 499 struct hns3_udp_tunnel { 500 u16 dst_port; 501 int used; 502 }; 503 504 struct hns3_nic_priv { 505 struct hnae3_handle *ae_handle; 506 u32 enet_ver; 507 u32 port_id; 508 struct net_device *netdev; 509 struct device *dev; 510 511 /** 512 * the cb for nic to manage the ring buffer, the first half of the 513 * array is for tx_ring and vice versa for the second half 514 */ 515 struct hns3_enet_ring *ring; 516 struct hns3_enet_tqp_vector *tqp_vector; 517 u16 vector_num; 518 519 /* The most recently read link state */ 520 int link; 521 u64 tx_timeout_count; 522 523 unsigned long state; 524 525 struct timer_list service_timer; 526 527 struct work_struct service_task; 528 529 struct notifier_block notifier_block; 530 /* Vxlan/Geneve information */ 531 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 532 struct hns3_enet_coalesce tx_coal; 533 struct hns3_enet_coalesce rx_coal; 534 }; 535 536 union l3_hdr_info { 537 struct iphdr *v4; 538 struct ipv6hdr *v6; 539 unsigned char *hdr; 540 }; 541 542 union l4_hdr_info { 543 struct tcphdr *tcp; 544 struct udphdr *udp; 545 struct gre_base_hdr *gre; 546 unsigned char *hdr; 547 }; 548 549 struct hns3_hw_error_info { 550 enum hnae3_hw_error_type type; 551 const char *msg; 552 }; 553 554 static inline int ring_space(struct hns3_enet_ring *ring) 555 { 556 /* This smp_load_acquire() pairs with smp_store_release() in 557 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 558 */ 559 int begin = smp_load_acquire(&ring->next_to_clean); 560 int end = READ_ONCE(ring->next_to_use); 561 562 return ((end >= begin) ? (ring->desc_num - end + begin) : 563 (begin - end)) - 1; 564 } 565 566 static inline int is_ring_empty(struct hns3_enet_ring *ring) 567 { 568 return ring->next_to_use == ring->next_to_clean; 569 } 570 571 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 572 { 573 return readl(base + reg); 574 } 575 576 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 577 { 578 u8 __iomem *reg_addr = READ_ONCE(base); 579 580 writel(value, reg_addr + reg); 581 } 582 583 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev) 584 { 585 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET || 586 ae_dev->reset_type == HNAE3_FLR_RESET || 587 ae_dev->reset_type == HNAE3_VF_FUNC_RESET || 588 ae_dev->reset_type == HNAE3_VF_FULL_RESET || 589 ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET)); 590 } 591 592 #define hns3_read_dev(a, reg) \ 593 hns3_read_reg((a)->io_base, (reg)) 594 595 static inline bool hns3_nic_resetting(struct net_device *netdev) 596 { 597 struct hns3_nic_priv *priv = netdev_priv(netdev); 598 599 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 600 } 601 602 #define hns3_write_dev(a, reg, value) \ 603 hns3_write_reg((a)->io_base, (reg), (value)) 604 605 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 606 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 607 608 #define ring_to_dev(ring) ((ring)->dev) 609 610 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 611 612 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 613 DMA_TO_DEVICE : DMA_FROM_DEVICE) 614 615 #define hns3_buf_size(_ring) ((_ring)->buf_size) 616 617 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 618 { 619 #if (PAGE_SIZE < 8192) 620 if (ring->buf_size > (PAGE_SIZE / 2)) 621 return 1; 622 #endif 623 return 0; 624 } 625 626 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 627 628 /* iterator for handling rings in ring group */ 629 #define hns3_for_each_ring(pos, head) \ 630 for (pos = (head).ring; pos; pos = pos->next) 631 632 #define hns3_get_handle(ndev) \ 633 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 634 635 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 636 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 637 638 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 639 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 640 641 void hns3_ethtool_set_ops(struct net_device *netdev); 642 int hns3_set_channels(struct net_device *netdev, 643 struct ethtool_channels *ch); 644 645 void hns3_clean_tx_ring(struct hns3_enet_ring *ring); 646 int hns3_init_all_ring(struct hns3_nic_priv *priv); 647 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 648 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 649 void hns3_fini_ring(struct hns3_enet_ring *ring); 650 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 651 bool hns3_is_phys_func(struct pci_dev *pdev); 652 int hns3_clean_rx_ring( 653 struct hns3_enet_ring *ring, int budget, 654 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 655 656 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 657 u32 gl_value); 658 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 659 u32 gl_value); 660 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 661 u32 rl_value); 662 663 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 664 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags); 665 666 #ifdef CONFIG_HNS3_DCB 667 void hns3_dcbnl_setup(struct hnae3_handle *handle); 668 #else 669 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 670 #endif 671 672 void hns3_dbg_init(struct hnae3_handle *handle); 673 void hns3_dbg_uninit(struct hnae3_handle *handle); 674 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 675 void hns3_dbg_unregister_debugfs(void); 676 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 677 #endif 678