1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_RD_FIRST_STATS_NUM 2 21 #define HCLGE_RD_OTHER_STATS_NUM 4 22 23 #define HCLGE_INVALID_VPORT 0xffff 24 25 #define HCLGE_PF_CFG_BLOCK_SIZE 32 26 #define HCLGE_PF_CFG_DESC_NUM \ 27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 28 29 #define HCLGE_VECTOR_REG_BASE 0x20000 30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 31 32 #define HCLGE_VECTOR_REG_OFFSET 0x4 33 #define HCLGE_VECTOR_VF_OFFSET 0x100000 34 35 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 36 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 37 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 38 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 39 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 40 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 41 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 42 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 43 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 44 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 45 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100 46 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 47 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 48 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 49 50 /* bar registers for common func */ 51 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 52 #define HCLGE_RAS_OTHER_STS_REG 0x20B00 53 #define HCLGE_FUNC_RESET_STS_REG 0x20C00 54 #define HCLGE_GRO_EN_REG 0x28000 55 56 /* bar registers for rcb */ 57 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 58 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 59 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 60 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 61 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 62 #define HCLGE_RING_RX_TAIL_REG 0x80018 63 #define HCLGE_RING_RX_HEAD_REG 0x8001C 64 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 65 #define HCLGE_RING_RX_OFFSET_REG 0x80024 66 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 67 #define HCLGE_RING_RX_STASH_REG 0x80030 68 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 69 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 70 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 71 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 72 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 73 #define HCLGE_RING_TX_TC_REG 0x80050 74 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 75 #define HCLGE_RING_TX_TAIL_REG 0x80058 76 #define HCLGE_RING_TX_HEAD_REG 0x8005C 77 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 78 #define HCLGE_RING_TX_OFFSET_REG 0x80064 79 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 80 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 81 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 82 #define HCLGE_RING_EN_REG 0x80090 83 84 /* bar registers for tqp interrupt */ 85 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 86 #define HCLGE_TQP_INTR_GL0_REG 0x20100 87 #define HCLGE_TQP_INTR_GL1_REG 0x20200 88 #define HCLGE_TQP_INTR_GL2_REG 0x20300 89 #define HCLGE_TQP_INTR_RL_REG 0x20900 90 91 #define HCLGE_RSS_IND_TBL_SIZE 512 92 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 93 #define HCLGE_RSS_KEY_SIZE 40 94 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 95 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 96 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 97 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 98 #define HCLGE_RSS_CFG_TBL_NUM \ 99 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 109 #define HCLGE_RSS_TC_SIZE_0 1 110 #define HCLGE_RSS_TC_SIZE_1 2 111 #define HCLGE_RSS_TC_SIZE_2 4 112 #define HCLGE_RSS_TC_SIZE_3 8 113 #define HCLGE_RSS_TC_SIZE_4 16 114 #define HCLGE_RSS_TC_SIZE_5 32 115 #define HCLGE_RSS_TC_SIZE_6 64 116 #define HCLGE_RSS_TC_SIZE_7 128 117 118 #define HCLGE_UMV_TBL_SIZE 3072 119 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 120 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 121 122 #define HCLGE_TQP_RESET_TRY_TIMES 10 123 124 #define HCLGE_PHY_PAGE_MDIX 0 125 #define HCLGE_PHY_PAGE_COPPER 0 126 127 /* Page Selection Reg. */ 128 #define HCLGE_PHY_PAGE_REG 22 129 130 /* Copper Specific Control Register */ 131 #define HCLGE_PHY_CSC_REG 16 132 133 /* Copper Specific Status Register */ 134 #define HCLGE_PHY_CSS_REG 17 135 136 #define HCLGE_PHY_MDIX_CTRL_S 5 137 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 138 139 #define HCLGE_PHY_MDIX_STATUS_B 6 140 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 141 142 /* Factor used to calculate offset and bitmap of VF num */ 143 #define HCLGE_VF_NUM_PER_CMD 64 144 #define HCLGE_VF_NUM_PER_BYTE 8 145 146 enum HLCGE_PORT_TYPE { 147 HOST_PORT, 148 NETWORK_PORT 149 }; 150 151 #define HCLGE_PF_ID_S 0 152 #define HCLGE_PF_ID_M GENMASK(2, 0) 153 #define HCLGE_VF_ID_S 3 154 #define HCLGE_VF_ID_M GENMASK(10, 3) 155 #define HCLGE_PORT_TYPE_B 11 156 #define HCLGE_NETWORK_PORT_ID_S 0 157 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 158 159 /* Reset related Registers */ 160 #define HCLGE_PF_OTHER_INT_REG 0x20600 161 #define HCLGE_MISC_RESET_STS_REG 0x20700 162 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 163 #define HCLGE_GLOBAL_RESET_REG 0x20A00 164 #define HCLGE_GLOBAL_RESET_BIT 0 165 #define HCLGE_CORE_RESET_BIT 1 166 #define HCLGE_IMP_RESET_BIT 2 167 #define HCLGE_FUN_RST_ING 0x20C00 168 #define HCLGE_FUN_RST_ING_B 0 169 170 /* Vector0 register bits define */ 171 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 172 #define HCLGE_VECTOR0_CORERESET_INT_B 6 173 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 174 175 /* Vector0 interrupt CMDQ event source register(RW) */ 176 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 177 /* CMDQ register bits for RX event(=MBX event) */ 178 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 179 180 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 181 182 #define HCLGE_MAC_DEFAULT_FRAME \ 183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 184 #define HCLGE_MAC_MIN_FRAME 64 185 #define HCLGE_MAC_MAX_FRAME 9728 186 187 #define HCLGE_SUPPORT_1G_BIT BIT(0) 188 #define HCLGE_SUPPORT_10G_BIT BIT(1) 189 #define HCLGE_SUPPORT_25G_BIT BIT(2) 190 #define HCLGE_SUPPORT_50G_BIT BIT(3) 191 #define HCLGE_SUPPORT_100G_BIT BIT(4) 192 /* to be compatible with exsit board */ 193 #define HCLGE_SUPPORT_40G_BIT BIT(5) 194 #define HCLGE_SUPPORT_100M_BIT BIT(6) 195 #define HCLGE_SUPPORT_10M_BIT BIT(7) 196 #define HCLGE_SUPPORT_GE \ 197 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 198 199 enum HCLGE_DEV_STATE { 200 HCLGE_STATE_REINITING, 201 HCLGE_STATE_DOWN, 202 HCLGE_STATE_DISABLED, 203 HCLGE_STATE_REMOVING, 204 HCLGE_STATE_SERVICE_INITED, 205 HCLGE_STATE_SERVICE_SCHED, 206 HCLGE_STATE_RST_SERVICE_SCHED, 207 HCLGE_STATE_RST_HANDLING, 208 HCLGE_STATE_MBX_SERVICE_SCHED, 209 HCLGE_STATE_MBX_HANDLING, 210 HCLGE_STATE_STATISTICS_UPDATING, 211 HCLGE_STATE_CMD_DISABLE, 212 HCLGE_STATE_MAX 213 }; 214 215 enum hclge_evt_cause { 216 HCLGE_VECTOR0_EVENT_RST, 217 HCLGE_VECTOR0_EVENT_MBX, 218 HCLGE_VECTOR0_EVENT_ERR, 219 HCLGE_VECTOR0_EVENT_OTHER, 220 }; 221 222 #define HCLGE_MPF_ENBALE 1 223 224 enum HCLGE_MAC_SPEED { 225 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 226 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 227 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 228 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 229 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 230 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 231 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 232 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 233 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 234 }; 235 236 enum HCLGE_MAC_DUPLEX { 237 HCLGE_MAC_HALF, 238 HCLGE_MAC_FULL 239 }; 240 241 #define QUERY_SFP_SPEED 0 242 #define QUERY_ACTIVE_SPEED 1 243 244 struct hclge_mac { 245 u8 phy_addr; 246 u8 flag; 247 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 248 u8 mac_addr[ETH_ALEN]; 249 u8 autoneg; 250 u8 duplex; 251 u8 support_autoneg; 252 u8 speed_type; /* 0: sfp speed, 1: active speed */ 253 u32 speed; 254 u32 speed_ability; /* speed ability supported by current media */ 255 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 256 u32 fec_mode; /* active fec mode */ 257 u32 user_fec_mode; 258 u32 fec_ability; 259 int link; /* store the link status of mac & phy (if phy exit) */ 260 struct phy_device *phydev; 261 struct mii_bus *mdio_bus; 262 phy_interface_t phy_if; 263 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 264 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 265 }; 266 267 struct hclge_hw { 268 void __iomem *io_base; 269 struct hclge_mac mac; 270 int num_vec; 271 struct hclge_cmq cmq; 272 }; 273 274 /* TQP stats */ 275 struct hlcge_tqp_stats { 276 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 277 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 278 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 279 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 280 }; 281 282 struct hclge_tqp { 283 /* copy of device pointer from pci_dev, 284 * used when perform DMA mapping 285 */ 286 struct device *dev; 287 struct hnae3_queue q; 288 struct hlcge_tqp_stats tqp_stats; 289 u16 index; /* Global index in a NIC controller */ 290 291 bool alloced; 292 }; 293 294 enum hclge_fc_mode { 295 HCLGE_FC_NONE, 296 HCLGE_FC_RX_PAUSE, 297 HCLGE_FC_TX_PAUSE, 298 HCLGE_FC_FULL, 299 HCLGE_FC_PFC, 300 HCLGE_FC_DEFAULT 301 }; 302 303 #define HCLGE_PG_NUM 4 304 #define HCLGE_SCH_MODE_SP 0 305 #define HCLGE_SCH_MODE_DWRR 1 306 struct hclge_pg_info { 307 u8 pg_id; 308 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 309 u8 tc_bit_map; 310 u32 bw_limit; 311 u8 tc_dwrr[HNAE3_MAX_TC]; 312 }; 313 314 struct hclge_tc_info { 315 u8 tc_id; 316 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 317 u8 pgid; 318 u32 bw_limit; 319 }; 320 321 struct hclge_cfg { 322 u8 vmdq_vport_num; 323 u8 tc_num; 324 u16 tqp_desc_num; 325 u16 rx_buf_len; 326 u16 rss_size_max; 327 u8 phy_addr; 328 u8 media_type; 329 u8 mac_addr[ETH_ALEN]; 330 u8 default_speed; 331 u32 numa_node_map; 332 u8 speed_ability; 333 u16 umv_space; 334 }; 335 336 struct hclge_tm_info { 337 u8 num_tc; 338 u8 num_pg; /* It must be 1 if vNET-Base schd */ 339 u8 pg_dwrr[HCLGE_PG_NUM]; 340 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 341 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 342 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 343 enum hclge_fc_mode fc_mode; 344 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 345 u8 pfc_en; /* PFC enabled or not for user priority */ 346 }; 347 348 struct hclge_comm_stats_str { 349 char desc[ETH_GSTRING_LEN]; 350 unsigned long offset; 351 }; 352 353 /* mac stats ,opcode id: 0x0032 */ 354 struct hclge_mac_stats { 355 u64 mac_tx_mac_pause_num; 356 u64 mac_rx_mac_pause_num; 357 u64 mac_tx_pfc_pri0_pkt_num; 358 u64 mac_tx_pfc_pri1_pkt_num; 359 u64 mac_tx_pfc_pri2_pkt_num; 360 u64 mac_tx_pfc_pri3_pkt_num; 361 u64 mac_tx_pfc_pri4_pkt_num; 362 u64 mac_tx_pfc_pri5_pkt_num; 363 u64 mac_tx_pfc_pri6_pkt_num; 364 u64 mac_tx_pfc_pri7_pkt_num; 365 u64 mac_rx_pfc_pri0_pkt_num; 366 u64 mac_rx_pfc_pri1_pkt_num; 367 u64 mac_rx_pfc_pri2_pkt_num; 368 u64 mac_rx_pfc_pri3_pkt_num; 369 u64 mac_rx_pfc_pri4_pkt_num; 370 u64 mac_rx_pfc_pri5_pkt_num; 371 u64 mac_rx_pfc_pri6_pkt_num; 372 u64 mac_rx_pfc_pri7_pkt_num; 373 u64 mac_tx_total_pkt_num; 374 u64 mac_tx_total_oct_num; 375 u64 mac_tx_good_pkt_num; 376 u64 mac_tx_bad_pkt_num; 377 u64 mac_tx_good_oct_num; 378 u64 mac_tx_bad_oct_num; 379 u64 mac_tx_uni_pkt_num; 380 u64 mac_tx_multi_pkt_num; 381 u64 mac_tx_broad_pkt_num; 382 u64 mac_tx_undersize_pkt_num; 383 u64 mac_tx_oversize_pkt_num; 384 u64 mac_tx_64_oct_pkt_num; 385 u64 mac_tx_65_127_oct_pkt_num; 386 u64 mac_tx_128_255_oct_pkt_num; 387 u64 mac_tx_256_511_oct_pkt_num; 388 u64 mac_tx_512_1023_oct_pkt_num; 389 u64 mac_tx_1024_1518_oct_pkt_num; 390 u64 mac_tx_1519_2047_oct_pkt_num; 391 u64 mac_tx_2048_4095_oct_pkt_num; 392 u64 mac_tx_4096_8191_oct_pkt_num; 393 u64 rsv0; 394 u64 mac_tx_8192_9216_oct_pkt_num; 395 u64 mac_tx_9217_12287_oct_pkt_num; 396 u64 mac_tx_12288_16383_oct_pkt_num; 397 u64 mac_tx_1519_max_good_oct_pkt_num; 398 u64 mac_tx_1519_max_bad_oct_pkt_num; 399 400 u64 mac_rx_total_pkt_num; 401 u64 mac_rx_total_oct_num; 402 u64 mac_rx_good_pkt_num; 403 u64 mac_rx_bad_pkt_num; 404 u64 mac_rx_good_oct_num; 405 u64 mac_rx_bad_oct_num; 406 u64 mac_rx_uni_pkt_num; 407 u64 mac_rx_multi_pkt_num; 408 u64 mac_rx_broad_pkt_num; 409 u64 mac_rx_undersize_pkt_num; 410 u64 mac_rx_oversize_pkt_num; 411 u64 mac_rx_64_oct_pkt_num; 412 u64 mac_rx_65_127_oct_pkt_num; 413 u64 mac_rx_128_255_oct_pkt_num; 414 u64 mac_rx_256_511_oct_pkt_num; 415 u64 mac_rx_512_1023_oct_pkt_num; 416 u64 mac_rx_1024_1518_oct_pkt_num; 417 u64 mac_rx_1519_2047_oct_pkt_num; 418 u64 mac_rx_2048_4095_oct_pkt_num; 419 u64 mac_rx_4096_8191_oct_pkt_num; 420 u64 rsv1; 421 u64 mac_rx_8192_9216_oct_pkt_num; 422 u64 mac_rx_9217_12287_oct_pkt_num; 423 u64 mac_rx_12288_16383_oct_pkt_num; 424 u64 mac_rx_1519_max_good_oct_pkt_num; 425 u64 mac_rx_1519_max_bad_oct_pkt_num; 426 427 u64 mac_tx_fragment_pkt_num; 428 u64 mac_tx_undermin_pkt_num; 429 u64 mac_tx_jabber_pkt_num; 430 u64 mac_tx_err_all_pkt_num; 431 u64 mac_tx_from_app_good_pkt_num; 432 u64 mac_tx_from_app_bad_pkt_num; 433 u64 mac_rx_fragment_pkt_num; 434 u64 mac_rx_undermin_pkt_num; 435 u64 mac_rx_jabber_pkt_num; 436 u64 mac_rx_fcs_err_pkt_num; 437 u64 mac_rx_send_app_good_pkt_num; 438 u64 mac_rx_send_app_bad_pkt_num; 439 u64 mac_tx_pfc_pause_pkt_num; 440 u64 mac_rx_pfc_pause_pkt_num; 441 u64 mac_tx_ctrl_pkt_num; 442 u64 mac_rx_ctrl_pkt_num; 443 }; 444 445 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5) 446 struct hclge_hw_stats { 447 struct hclge_mac_stats mac_stats; 448 u32 stats_timer; 449 }; 450 451 struct hclge_vlan_type_cfg { 452 u16 rx_ot_fst_vlan_type; 453 u16 rx_ot_sec_vlan_type; 454 u16 rx_in_fst_vlan_type; 455 u16 rx_in_sec_vlan_type; 456 u16 tx_ot_vlan_type; 457 u16 tx_in_vlan_type; 458 }; 459 460 enum HCLGE_FD_MODE { 461 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 462 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 463 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 464 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 465 }; 466 467 enum HCLGE_FD_KEY_TYPE { 468 HCLGE_FD_KEY_BASE_ON_PTYPE, 469 HCLGE_FD_KEY_BASE_ON_TUPLE, 470 }; 471 472 enum HCLGE_FD_STAGE { 473 HCLGE_FD_STAGE_1, 474 HCLGE_FD_STAGE_2, 475 }; 476 477 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 478 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 479 * tuples of non-tunnel packet 480 */ 481 enum HCLGE_FD_TUPLE { 482 OUTER_DST_MAC, 483 OUTER_SRC_MAC, 484 OUTER_VLAN_TAG_FST, 485 OUTER_VLAN_TAG_SEC, 486 OUTER_ETH_TYPE, 487 OUTER_L2_RSV, 488 OUTER_IP_TOS, 489 OUTER_IP_PROTO, 490 OUTER_SRC_IP, 491 OUTER_DST_IP, 492 OUTER_L3_RSV, 493 OUTER_SRC_PORT, 494 OUTER_DST_PORT, 495 OUTER_L4_RSV, 496 OUTER_TUN_VNI, 497 OUTER_TUN_FLOW_ID, 498 INNER_DST_MAC, 499 INNER_SRC_MAC, 500 INNER_VLAN_TAG_FST, 501 INNER_VLAN_TAG_SEC, 502 INNER_ETH_TYPE, 503 INNER_L2_RSV, 504 INNER_IP_TOS, 505 INNER_IP_PROTO, 506 INNER_SRC_IP, 507 INNER_DST_IP, 508 INNER_L3_RSV, 509 INNER_SRC_PORT, 510 INNER_DST_PORT, 511 INNER_L4_RSV, 512 MAX_TUPLE, 513 }; 514 515 enum HCLGE_FD_META_DATA { 516 PACKET_TYPE_ID, 517 IP_FRAGEMENT, 518 ROCE_TYPE, 519 NEXT_KEY, 520 VLAN_NUMBER, 521 SRC_VPORT, 522 DST_VPORT, 523 TUNNEL_PACKET, 524 MAX_META_DATA, 525 }; 526 527 struct key_info { 528 u8 key_type; 529 u8 key_length; 530 }; 531 532 static const struct key_info meta_data_key_info[] = { 533 { PACKET_TYPE_ID, 6}, 534 { IP_FRAGEMENT, 1}, 535 { ROCE_TYPE, 1}, 536 { NEXT_KEY, 5}, 537 { VLAN_NUMBER, 2}, 538 { SRC_VPORT, 12}, 539 { DST_VPORT, 12}, 540 { TUNNEL_PACKET, 1}, 541 }; 542 543 static const struct key_info tuple_key_info[] = { 544 { OUTER_DST_MAC, 48}, 545 { OUTER_SRC_MAC, 48}, 546 { OUTER_VLAN_TAG_FST, 16}, 547 { OUTER_VLAN_TAG_SEC, 16}, 548 { OUTER_ETH_TYPE, 16}, 549 { OUTER_L2_RSV, 16}, 550 { OUTER_IP_TOS, 8}, 551 { OUTER_IP_PROTO, 8}, 552 { OUTER_SRC_IP, 32}, 553 { OUTER_DST_IP, 32}, 554 { OUTER_L3_RSV, 16}, 555 { OUTER_SRC_PORT, 16}, 556 { OUTER_DST_PORT, 16}, 557 { OUTER_L4_RSV, 32}, 558 { OUTER_TUN_VNI, 24}, 559 { OUTER_TUN_FLOW_ID, 8}, 560 { INNER_DST_MAC, 48}, 561 { INNER_SRC_MAC, 48}, 562 { INNER_VLAN_TAG_FST, 16}, 563 { INNER_VLAN_TAG_SEC, 16}, 564 { INNER_ETH_TYPE, 16}, 565 { INNER_L2_RSV, 16}, 566 { INNER_IP_TOS, 8}, 567 { INNER_IP_PROTO, 8}, 568 { INNER_SRC_IP, 32}, 569 { INNER_DST_IP, 32}, 570 { INNER_L3_RSV, 16}, 571 { INNER_SRC_PORT, 16}, 572 { INNER_DST_PORT, 16}, 573 { INNER_L4_RSV, 32}, 574 }; 575 576 #define MAX_KEY_LENGTH 400 577 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 578 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 579 #define MAX_META_DATA_LENGTH 32 580 581 enum HCLGE_FD_PACKET_TYPE { 582 NIC_PACKET, 583 ROCE_PACKET, 584 }; 585 586 enum HCLGE_FD_ACTION { 587 HCLGE_FD_ACTION_ACCEPT_PACKET, 588 HCLGE_FD_ACTION_DROP_PACKET, 589 }; 590 591 struct hclge_fd_key_cfg { 592 u8 key_sel; 593 u8 inner_sipv6_word_en; 594 u8 inner_dipv6_word_en; 595 u8 outer_sipv6_word_en; 596 u8 outer_dipv6_word_en; 597 u32 tuple_active; 598 u32 meta_data_active; 599 }; 600 601 struct hclge_fd_cfg { 602 u8 fd_mode; 603 u16 max_key_length; 604 u32 proto_support; 605 u32 rule_num[2]; /* rule entry number */ 606 u16 cnt_num[2]; /* rule hit counter number */ 607 struct hclge_fd_key_cfg key_cfg[2]; 608 }; 609 610 struct hclge_fd_rule_tuples { 611 u8 src_mac[6]; 612 u8 dst_mac[6]; 613 u32 src_ip[4]; 614 u32 dst_ip[4]; 615 u16 src_port; 616 u16 dst_port; 617 u16 vlan_tag1; 618 u16 ether_proto; 619 u8 ip_tos; 620 u8 ip_proto; 621 }; 622 623 struct hclge_fd_rule { 624 struct hlist_node rule_node; 625 struct hclge_fd_rule_tuples tuples; 626 struct hclge_fd_rule_tuples tuples_mask; 627 u32 unused_tuple; 628 u32 flow_type; 629 u8 action; 630 u16 vf_id; 631 u16 queue_id; 632 u16 location; 633 }; 634 635 struct hclge_fd_ad_data { 636 u16 ad_id; 637 u8 drop_packet; 638 u8 forward_to_direct_queue; 639 u16 queue_id; 640 u8 use_counter; 641 u8 counter_id; 642 u8 use_next_stage; 643 u8 write_rule_id_to_bd; 644 u8 next_input_key; 645 u16 rule_id; 646 }; 647 648 struct hclge_vport_mac_addr_cfg { 649 struct list_head node; 650 int hd_tbl_status; 651 u8 mac_addr[ETH_ALEN]; 652 }; 653 654 enum HCLGE_MAC_ADDR_TYPE { 655 HCLGE_MAC_ADDR_UC, 656 HCLGE_MAC_ADDR_MC 657 }; 658 659 struct hclge_vport_vlan_cfg { 660 struct list_head node; 661 int hd_tbl_status; 662 u16 vlan_id; 663 }; 664 665 struct hclge_rst_stats { 666 u32 reset_done_cnt; /* the number of reset has completed */ 667 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 668 u32 pf_rst_cnt; /* the number of PF reset */ 669 u32 flr_rst_cnt; /* the number of FLR */ 670 u32 core_rst_cnt; /* the number of CORE reset */ 671 u32 global_rst_cnt; /* the number of GLOBAL */ 672 u32 imp_rst_cnt; /* the number of IMP reset */ 673 u32 reset_cnt; /* the number of reset */ 674 }; 675 676 /* time and register status when mac tunnel interruption occur */ 677 struct hclge_mac_tnl_stats { 678 u64 time; 679 u32 status; 680 }; 681 682 /* For each bit of TCAM entry, it uses a pair of 'x' and 683 * 'y' to indicate which value to match, like below: 684 * ---------------------------------- 685 * | bit x | bit y | search value | 686 * ---------------------------------- 687 * | 0 | 0 | always hit | 688 * ---------------------------------- 689 * | 1 | 0 | match '0' | 690 * ---------------------------------- 691 * | 0 | 1 | match '1' | 692 * ---------------------------------- 693 * | 1 | 1 | invalid | 694 * ---------------------------------- 695 * Then for input key(k) and mask(v), we can calculate the value by 696 * the formulae: 697 * x = (~k) & v 698 * y = (k ^ ~v) & k 699 */ 700 #define calc_x(x, k, v) ((x) = (~(k) & (v))) 701 #define calc_y(y, k, v) \ 702 do { \ 703 const typeof(k) _k_ = (k); \ 704 const typeof(v) _v_ = (v); \ 705 (y) = (_k_ ^ ~_v_) & (_k_); \ 706 } while (0) 707 708 #define HCLGE_MAC_TNL_LOG_SIZE 8 709 #define HCLGE_VPORT_NUM 256 710 struct hclge_dev { 711 struct pci_dev *pdev; 712 struct hnae3_ae_dev *ae_dev; 713 struct hclge_hw hw; 714 struct hclge_misc_vector misc_vector; 715 struct hclge_hw_stats hw_stats; 716 unsigned long state; 717 unsigned long flr_state; 718 unsigned long last_reset_time; 719 720 enum hnae3_reset_type reset_type; 721 enum hnae3_reset_type reset_level; 722 unsigned long default_reset_request; 723 unsigned long reset_request; /* reset has been requested */ 724 unsigned long reset_pending; /* client rst is pending to be served */ 725 struct hclge_rst_stats rst_stats; 726 u32 reset_fail_cnt; 727 u32 fw_version; 728 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 729 u16 num_tqps; /* Num task queue pairs of this PF */ 730 u16 num_req_vfs; /* Num VFs requested for this PF */ 731 732 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 733 u16 alloc_rss_size; /* Allocated RSS task queue */ 734 u16 rss_size_max; /* HW defined max RSS task queue */ 735 736 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 737 u16 num_alloc_vport; /* Num vports this driver supports */ 738 u32 numa_node_mask; 739 u16 rx_buf_len; 740 u16 num_tx_desc; /* desc num of per tx queue */ 741 u16 num_rx_desc; /* desc num of per rx queue */ 742 u8 hw_tc_map; 743 u8 tc_num_last_time; 744 enum hclge_fc_mode fc_mode_last_time; 745 u8 support_sfp_query; 746 747 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 748 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 749 u8 tx_sch_mode; 750 u8 tc_max; 751 u8 pfc_max; 752 753 u8 default_up; 754 u8 dcbx_cap; 755 struct hclge_tm_info tm_info; 756 757 u16 num_msi; 758 u16 num_msi_left; 759 u16 num_msi_used; 760 u16 roce_base_msix_offset; 761 u32 base_msi_vector; 762 u16 *vector_status; 763 int *vector_irq; 764 u16 num_roce_msi; /* Num of roce vectors for this PF */ 765 int roce_base_vector; 766 767 u16 pending_udp_bitmap; 768 769 u16 rx_itr_default; 770 u16 tx_itr_default; 771 772 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 773 unsigned long service_timer_period; 774 unsigned long service_timer_previous; 775 struct timer_list service_timer; 776 struct timer_list reset_timer; 777 struct work_struct service_task; 778 struct work_struct rst_service_task; 779 struct work_struct mbx_service_task; 780 781 bool cur_promisc; 782 int num_alloc_vfs; /* Actual number of VFs allocated */ 783 784 struct hclge_tqp *htqp; 785 struct hclge_vport *vport; 786 787 struct dentry *hclge_dbgfs; 788 789 struct hnae3_client *nic_client; 790 struct hnae3_client *roce_client; 791 792 #define HCLGE_FLAG_MAIN BIT(0) 793 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 794 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 795 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 796 u32 flag; 797 798 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 799 u32 tx_buf_size; /* Tx buffer size for each TC */ 800 u32 dv_buf_size; /* Dv buffer size for each TC */ 801 802 u32 mps; /* Max packet size */ 803 /* vport_lock protect resource shared by vports */ 804 struct mutex vport_lock; 805 806 struct hclge_vlan_type_cfg vlan_type_cfg; 807 808 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 809 810 struct hclge_fd_cfg fd_cfg; 811 struct hlist_head fd_rule_list; 812 u16 hclge_fd_rule_num; 813 u8 fd_en; 814 815 u16 wanted_umv_size; 816 /* max available unicast mac vlan space */ 817 u16 max_umv_size; 818 /* private unicast mac vlan space, it's same for PF and its VFs */ 819 u16 priv_umv_size; 820 /* unicast mac vlan space shared by PF and its VFs */ 821 u16 share_umv_size; 822 struct mutex umv_mutex; /* protect share_umv_size */ 823 824 struct mutex vport_cfg_mutex; /* Protect stored vf table */ 825 826 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 827 HCLGE_MAC_TNL_LOG_SIZE); 828 }; 829 830 /* VPort level vlan tag configuration for TX direction */ 831 struct hclge_tx_vtag_cfg { 832 bool accept_tag1; /* Whether accept tag1 packet from host */ 833 bool accept_untag1; /* Whether accept untag1 packet from host */ 834 bool accept_tag2; 835 bool accept_untag2; 836 bool insert_tag1_en; /* Whether insert inner vlan tag */ 837 bool insert_tag2_en; /* Whether insert outer vlan tag */ 838 u16 default_tag1; /* The default inner vlan tag to insert */ 839 u16 default_tag2; /* The default outer vlan tag to insert */ 840 }; 841 842 /* VPort level vlan tag configuration for RX direction */ 843 struct hclge_rx_vtag_cfg { 844 u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */ 845 u8 strip_tag1_en; /* Whether strip inner vlan tag */ 846 u8 strip_tag2_en; /* Whether strip outer vlan tag */ 847 u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 848 u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 849 }; 850 851 struct hclge_rss_tuple_cfg { 852 u8 ipv4_tcp_en; 853 u8 ipv4_udp_en; 854 u8 ipv4_sctp_en; 855 u8 ipv4_fragment_en; 856 u8 ipv6_tcp_en; 857 u8 ipv6_udp_en; 858 u8 ipv6_sctp_en; 859 u8 ipv6_fragment_en; 860 }; 861 862 enum HCLGE_VPORT_STATE { 863 HCLGE_VPORT_STATE_ALIVE, 864 HCLGE_VPORT_STATE_MAX 865 }; 866 867 struct hclge_vlan_info { 868 u16 vlan_proto; /* so far support 802.1Q only */ 869 u16 qos; 870 u16 vlan_tag; 871 }; 872 873 struct hclge_port_base_vlan_config { 874 u16 state; 875 struct hclge_vlan_info vlan_info; 876 }; 877 878 struct hclge_vport { 879 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 880 881 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 882 /* User configured lookup table entries */ 883 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 884 int rss_algo; /* User configured hash algorithm */ 885 /* User configured rss tuple sets */ 886 struct hclge_rss_tuple_cfg rss_tuple_sets; 887 888 u16 alloc_rss_size; 889 890 u16 qs_offset; 891 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 892 u8 dwrr; 893 894 struct hclge_port_base_vlan_config port_base_vlan_cfg; 895 struct hclge_tx_vtag_cfg txvlan_cfg; 896 struct hclge_rx_vtag_cfg rxvlan_cfg; 897 898 u16 used_umv_num; 899 900 int vport_id; 901 struct hclge_dev *back; /* Back reference to associated dev */ 902 struct hnae3_handle nic; 903 struct hnae3_handle roce; 904 905 unsigned long state; 906 unsigned long last_active_jiffies; 907 u32 mps; /* Max packet size */ 908 909 struct list_head uc_mac_list; /* Store VF unicast table */ 910 struct list_head mc_mac_list; /* Store VF multicast table */ 911 struct list_head vlan_list; /* Store VF vlan table */ 912 }; 913 914 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 915 bool en_mc, bool en_bc, int vport_id); 916 917 int hclge_add_uc_addr_common(struct hclge_vport *vport, 918 const unsigned char *addr); 919 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 920 const unsigned char *addr); 921 int hclge_add_mc_addr_common(struct hclge_vport *vport, 922 const unsigned char *addr); 923 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 924 const unsigned char *addr); 925 926 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 927 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 928 int vector_id, bool en, 929 struct hnae3_ring_chain_node *ring_chain); 930 931 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 932 { 933 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 934 935 return tqp->index; 936 } 937 938 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 939 { 940 return !!hdev->reset_pending; 941 } 942 943 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 944 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 945 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 946 u16 vlan_id, bool is_kill); 947 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 948 949 int hclge_buffer_alloc(struct hclge_dev *hdev); 950 int hclge_rss_init_hw(struct hclge_dev *hdev); 951 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 952 953 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 954 void hclge_mbx_handler(struct hclge_dev *hdev); 955 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 956 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 957 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 958 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 959 int hclge_vport_start(struct hclge_vport *vport); 960 void hclge_vport_stop(struct hclge_vport *vport); 961 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 962 int hclge_dbg_run_cmd(struct hnae3_handle *handle, char *cmd_buf); 963 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 964 int hclge_notify_client(struct hclge_dev *hdev, 965 enum hnae3_reset_notify_type type); 966 void hclge_add_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 967 enum HCLGE_MAC_ADDR_TYPE mac_type); 968 void hclge_rm_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 969 bool is_write_tbl, 970 enum HCLGE_MAC_ADDR_TYPE mac_type); 971 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 972 enum HCLGE_MAC_ADDR_TYPE mac_type); 973 void hclge_uninit_vport_mac_table(struct hclge_dev *hdev); 974 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 975 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 976 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 977 struct hclge_vlan_info *vlan_info); 978 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 979 u16 state, u16 vlan_tag, u16 qos, 980 u16 vlan_proto); 981 #endif 982