1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 /* after init the max rss_size and tqps, adjust the default tqp numbers 415 * and rss size with the actual vector numbers 416 */ 417 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 418 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 419 kinfo->rss_size); 420 421 return 0; 422 } 423 424 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 425 { 426 int status; 427 u8 resp_msg; 428 429 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 430 0, false, &resp_msg, sizeof(resp_msg)); 431 if (status) 432 dev_err(&hdev->pdev->dev, 433 "VF failed to fetch link status(%d) from PF", status); 434 } 435 436 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 437 { 438 struct hnae3_handle *rhandle = &hdev->roce; 439 struct hnae3_handle *handle = &hdev->nic; 440 struct hnae3_client *rclient; 441 struct hnae3_client *client; 442 443 client = handle->client; 444 rclient = hdev->roce_client; 445 446 link_state = 447 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 448 449 if (link_state != hdev->hw.mac.link) { 450 client->ops->link_status_change(handle, !!link_state); 451 if (rclient && rclient->ops->link_status_change) 452 rclient->ops->link_status_change(rhandle, !!link_state); 453 hdev->hw.mac.link = link_state; 454 } 455 } 456 457 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 458 { 459 #define HCLGEVF_ADVERTISING 0 460 #define HCLGEVF_SUPPORTED 1 461 u8 send_msg; 462 u8 resp_msg; 463 464 send_msg = HCLGEVF_ADVERTISING; 465 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 466 &send_msg, sizeof(send_msg), false, 467 &resp_msg, sizeof(resp_msg)); 468 send_msg = HCLGEVF_SUPPORTED; 469 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 470 &send_msg, sizeof(send_msg), false, 471 &resp_msg, sizeof(resp_msg)); 472 } 473 474 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 475 { 476 struct hnae3_handle *nic = &hdev->nic; 477 int ret; 478 479 nic->ae_algo = &ae_algovf; 480 nic->pdev = hdev->pdev; 481 nic->numa_node_mask = hdev->numa_node_mask; 482 nic->flags |= HNAE3_SUPPORT_VF; 483 484 ret = hclgevf_knic_setup(hdev); 485 if (ret) 486 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 487 ret); 488 return ret; 489 } 490 491 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 492 { 493 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 494 dev_warn(&hdev->pdev->dev, 495 "vector(vector_id %d) has been freed.\n", vector_id); 496 return; 497 } 498 499 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 500 hdev->num_msi_left += 1; 501 hdev->num_msi_used -= 1; 502 } 503 504 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 505 struct hnae3_vector_info *vector_info) 506 { 507 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 508 struct hnae3_vector_info *vector = vector_info; 509 int alloc = 0; 510 int i, j; 511 512 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 513 vector_num = min(hdev->num_msi_left, vector_num); 514 515 for (j = 0; j < vector_num; j++) { 516 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 517 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 518 vector->vector = pci_irq_vector(hdev->pdev, i); 519 vector->io_addr = hdev->hw.io_base + 520 HCLGEVF_VECTOR_REG_BASE + 521 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 522 hdev->vector_status[i] = 0; 523 hdev->vector_irq[i] = vector->vector; 524 525 vector++; 526 alloc++; 527 528 break; 529 } 530 } 531 } 532 hdev->num_msi_left -= alloc; 533 hdev->num_msi_used += alloc; 534 535 return alloc; 536 } 537 538 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 539 { 540 int i; 541 542 for (i = 0; i < hdev->num_msi; i++) 543 if (vector == hdev->vector_irq[i]) 544 return i; 545 546 return -EINVAL; 547 } 548 549 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 550 const u8 hfunc, const u8 *key) 551 { 552 struct hclgevf_rss_config_cmd *req; 553 unsigned int key_offset = 0; 554 struct hclgevf_desc desc; 555 int key_counts; 556 int key_size; 557 int ret; 558 559 key_counts = HCLGEVF_RSS_KEY_SIZE; 560 req = (struct hclgevf_rss_config_cmd *)desc.data; 561 562 while (key_counts) { 563 hclgevf_cmd_setup_basic_desc(&desc, 564 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 565 false); 566 567 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 568 req->hash_config |= 569 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 570 571 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 572 memcpy(req->hash_key, 573 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 574 575 key_counts -= key_size; 576 key_offset++; 577 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 578 if (ret) { 579 dev_err(&hdev->pdev->dev, 580 "Configure RSS config fail, status = %d\n", 581 ret); 582 return ret; 583 } 584 } 585 586 return 0; 587 } 588 589 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 590 { 591 return HCLGEVF_RSS_KEY_SIZE; 592 } 593 594 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 595 { 596 return HCLGEVF_RSS_IND_TBL_SIZE; 597 } 598 599 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 600 { 601 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 602 struct hclgevf_rss_indirection_table_cmd *req; 603 struct hclgevf_desc desc; 604 int status; 605 int i, j; 606 607 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 608 609 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 610 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 611 false); 612 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 613 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 614 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 615 req->rss_result[j] = 616 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 617 618 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 619 if (status) { 620 dev_err(&hdev->pdev->dev, 621 "VF failed(=%d) to set RSS indirection table\n", 622 status); 623 return status; 624 } 625 } 626 627 return 0; 628 } 629 630 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 631 { 632 struct hclgevf_rss_tc_mode_cmd *req; 633 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 634 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 635 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 636 struct hclgevf_desc desc; 637 u16 roundup_size; 638 int status; 639 unsigned int i; 640 641 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 642 643 roundup_size = roundup_pow_of_two(rss_size); 644 roundup_size = ilog2(roundup_size); 645 646 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 647 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 648 tc_size[i] = roundup_size; 649 tc_offset[i] = rss_size * i; 650 } 651 652 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 653 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 654 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 655 (tc_valid[i] & 0x1)); 656 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 657 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 658 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 659 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 660 } 661 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 662 if (status) 663 dev_err(&hdev->pdev->dev, 664 "VF failed(=%d) to set rss tc mode\n", status); 665 666 return status; 667 } 668 669 /* for revision 0x20, vf shared the same rss config with pf */ 670 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 671 { 672 #define HCLGEVF_RSS_MBX_RESP_LEN 8 673 674 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 675 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 676 u16 msg_num, hash_key_index; 677 u8 index; 678 int ret; 679 680 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 681 HCLGEVF_RSS_MBX_RESP_LEN; 682 for (index = 0; index < msg_num; index++) { 683 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 684 &index, sizeof(index), 685 true, resp_msg, 686 HCLGEVF_RSS_MBX_RESP_LEN); 687 if (ret) { 688 dev_err(&hdev->pdev->dev, 689 "VF get rss hash key from PF failed, ret=%d", 690 ret); 691 return ret; 692 } 693 694 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 695 if (index == msg_num - 1) 696 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 697 &resp_msg[0], 698 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 699 else 700 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 701 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 702 } 703 704 return 0; 705 } 706 707 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 708 u8 *hfunc) 709 { 710 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 711 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 712 int i, ret; 713 714 if (handle->pdev->revision >= 0x21) { 715 /* Get hash algorithm */ 716 if (hfunc) { 717 switch (rss_cfg->hash_algo) { 718 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 719 *hfunc = ETH_RSS_HASH_TOP; 720 break; 721 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 722 *hfunc = ETH_RSS_HASH_XOR; 723 break; 724 default: 725 *hfunc = ETH_RSS_HASH_UNKNOWN; 726 break; 727 } 728 } 729 730 /* Get the RSS Key required by the user */ 731 if (key) 732 memcpy(key, rss_cfg->rss_hash_key, 733 HCLGEVF_RSS_KEY_SIZE); 734 } else { 735 if (hfunc) 736 *hfunc = ETH_RSS_HASH_TOP; 737 if (key) { 738 ret = hclgevf_get_rss_hash_key(hdev); 739 if (ret) 740 return ret; 741 memcpy(key, rss_cfg->rss_hash_key, 742 HCLGEVF_RSS_KEY_SIZE); 743 } 744 } 745 746 if (indir) 747 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 748 indir[i] = rss_cfg->rss_indirection_tbl[i]; 749 750 return 0; 751 } 752 753 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 754 const u8 *key, const u8 hfunc) 755 { 756 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 757 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 758 int ret, i; 759 760 if (handle->pdev->revision >= 0x21) { 761 /* Set the RSS Hash Key if specififed by the user */ 762 if (key) { 763 switch (hfunc) { 764 case ETH_RSS_HASH_TOP: 765 rss_cfg->hash_algo = 766 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 767 break; 768 case ETH_RSS_HASH_XOR: 769 rss_cfg->hash_algo = 770 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 771 break; 772 case ETH_RSS_HASH_NO_CHANGE: 773 break; 774 default: 775 return -EINVAL; 776 } 777 778 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 779 key); 780 if (ret) 781 return ret; 782 783 /* Update the shadow RSS key with user specified qids */ 784 memcpy(rss_cfg->rss_hash_key, key, 785 HCLGEVF_RSS_KEY_SIZE); 786 } 787 } 788 789 /* update the shadow RSS table with user specified qids */ 790 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 791 rss_cfg->rss_indirection_tbl[i] = indir[i]; 792 793 /* update the hardware */ 794 return hclgevf_set_rss_indir_table(hdev); 795 } 796 797 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 798 { 799 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 800 801 if (nfc->data & RXH_L4_B_2_3) 802 hash_sets |= HCLGEVF_D_PORT_BIT; 803 else 804 hash_sets &= ~HCLGEVF_D_PORT_BIT; 805 806 if (nfc->data & RXH_IP_SRC) 807 hash_sets |= HCLGEVF_S_IP_BIT; 808 else 809 hash_sets &= ~HCLGEVF_S_IP_BIT; 810 811 if (nfc->data & RXH_IP_DST) 812 hash_sets |= HCLGEVF_D_IP_BIT; 813 else 814 hash_sets &= ~HCLGEVF_D_IP_BIT; 815 816 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 817 hash_sets |= HCLGEVF_V_TAG_BIT; 818 819 return hash_sets; 820 } 821 822 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 823 struct ethtool_rxnfc *nfc) 824 { 825 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 826 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 827 struct hclgevf_rss_input_tuple_cmd *req; 828 struct hclgevf_desc desc; 829 u8 tuple_sets; 830 int ret; 831 832 if (handle->pdev->revision == 0x20) 833 return -EOPNOTSUPP; 834 835 if (nfc->data & 836 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 837 return -EINVAL; 838 839 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 840 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 841 842 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 843 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 844 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 845 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 846 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 847 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 848 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 849 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 850 851 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 852 switch (nfc->flow_type) { 853 case TCP_V4_FLOW: 854 req->ipv4_tcp_en = tuple_sets; 855 break; 856 case TCP_V6_FLOW: 857 req->ipv6_tcp_en = tuple_sets; 858 break; 859 case UDP_V4_FLOW: 860 req->ipv4_udp_en = tuple_sets; 861 break; 862 case UDP_V6_FLOW: 863 req->ipv6_udp_en = tuple_sets; 864 break; 865 case SCTP_V4_FLOW: 866 req->ipv4_sctp_en = tuple_sets; 867 break; 868 case SCTP_V6_FLOW: 869 if ((nfc->data & RXH_L4_B_0_1) || 870 (nfc->data & RXH_L4_B_2_3)) 871 return -EINVAL; 872 873 req->ipv6_sctp_en = tuple_sets; 874 break; 875 case IPV4_FLOW: 876 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 877 break; 878 case IPV6_FLOW: 879 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 880 break; 881 default: 882 return -EINVAL; 883 } 884 885 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 886 if (ret) { 887 dev_err(&hdev->pdev->dev, 888 "Set rss tuple fail, status = %d\n", ret); 889 return ret; 890 } 891 892 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 893 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 894 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 895 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 896 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 897 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 898 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 899 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 900 return 0; 901 } 902 903 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 904 struct ethtool_rxnfc *nfc) 905 { 906 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 907 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 908 u8 tuple_sets; 909 910 if (handle->pdev->revision == 0x20) 911 return -EOPNOTSUPP; 912 913 nfc->data = 0; 914 915 switch (nfc->flow_type) { 916 case TCP_V4_FLOW: 917 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 918 break; 919 case UDP_V4_FLOW: 920 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 921 break; 922 case TCP_V6_FLOW: 923 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 924 break; 925 case UDP_V6_FLOW: 926 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 927 break; 928 case SCTP_V4_FLOW: 929 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 930 break; 931 case SCTP_V6_FLOW: 932 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 933 break; 934 case IPV4_FLOW: 935 case IPV6_FLOW: 936 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 937 break; 938 default: 939 return -EINVAL; 940 } 941 942 if (!tuple_sets) 943 return 0; 944 945 if (tuple_sets & HCLGEVF_D_PORT_BIT) 946 nfc->data |= RXH_L4_B_2_3; 947 if (tuple_sets & HCLGEVF_S_PORT_BIT) 948 nfc->data |= RXH_L4_B_0_1; 949 if (tuple_sets & HCLGEVF_D_IP_BIT) 950 nfc->data |= RXH_IP_DST; 951 if (tuple_sets & HCLGEVF_S_IP_BIT) 952 nfc->data |= RXH_IP_SRC; 953 954 return 0; 955 } 956 957 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 958 struct hclgevf_rss_cfg *rss_cfg) 959 { 960 struct hclgevf_rss_input_tuple_cmd *req; 961 struct hclgevf_desc desc; 962 int ret; 963 964 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 965 966 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 967 968 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 969 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 970 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 971 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 972 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 973 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 974 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 975 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 976 977 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 978 if (ret) 979 dev_err(&hdev->pdev->dev, 980 "Configure rss input fail, status = %d\n", ret); 981 return ret; 982 } 983 984 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 985 { 986 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 987 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 988 989 return rss_cfg->rss_size; 990 } 991 992 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 993 int vector_id, 994 struct hnae3_ring_chain_node *ring_chain) 995 { 996 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 997 struct hnae3_ring_chain_node *node; 998 struct hclge_mbx_vf_to_pf_cmd *req; 999 struct hclgevf_desc desc; 1000 int i = 0; 1001 int status; 1002 u8 type; 1003 1004 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1005 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1006 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1007 1008 for (node = ring_chain; node; node = node->next) { 1009 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1010 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1011 1012 if (i == 0) { 1013 hclgevf_cmd_setup_basic_desc(&desc, 1014 HCLGEVF_OPC_MBX_VF_TO_PF, 1015 false); 1016 req->msg[0] = type; 1017 req->msg[1] = vector_id; 1018 } 1019 1020 req->msg[idx_offset] = 1021 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1022 req->msg[idx_offset + 1] = node->tqp_index; 1023 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1024 HNAE3_RING_GL_IDX_M, 1025 HNAE3_RING_GL_IDX_S); 1026 1027 i++; 1028 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1029 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1030 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1031 !node->next) { 1032 req->msg[2] = i; 1033 1034 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1035 if (status) { 1036 dev_err(&hdev->pdev->dev, 1037 "Map TQP fail, status is %d.\n", 1038 status); 1039 return status; 1040 } 1041 i = 0; 1042 hclgevf_cmd_setup_basic_desc(&desc, 1043 HCLGEVF_OPC_MBX_VF_TO_PF, 1044 false); 1045 req->msg[0] = type; 1046 req->msg[1] = vector_id; 1047 } 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1054 struct hnae3_ring_chain_node *ring_chain) 1055 { 1056 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1057 int vector_id; 1058 1059 vector_id = hclgevf_get_vector_index(hdev, vector); 1060 if (vector_id < 0) { 1061 dev_err(&handle->pdev->dev, 1062 "Get vector index fail. ret =%d\n", vector_id); 1063 return vector_id; 1064 } 1065 1066 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1067 } 1068 1069 static int hclgevf_unmap_ring_from_vector( 1070 struct hnae3_handle *handle, 1071 int vector, 1072 struct hnae3_ring_chain_node *ring_chain) 1073 { 1074 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1075 int ret, vector_id; 1076 1077 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1078 return 0; 1079 1080 vector_id = hclgevf_get_vector_index(hdev, vector); 1081 if (vector_id < 0) { 1082 dev_err(&handle->pdev->dev, 1083 "Get vector index fail. ret =%d\n", vector_id); 1084 return vector_id; 1085 } 1086 1087 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1088 if (ret) 1089 dev_err(&handle->pdev->dev, 1090 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1091 vector_id, 1092 ret); 1093 1094 return ret; 1095 } 1096 1097 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1098 { 1099 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1100 int vector_id; 1101 1102 vector_id = hclgevf_get_vector_index(hdev, vector); 1103 if (vector_id < 0) { 1104 dev_err(&handle->pdev->dev, 1105 "hclgevf_put_vector get vector index fail. ret =%d\n", 1106 vector_id); 1107 return vector_id; 1108 } 1109 1110 hclgevf_free_vector(hdev, vector_id); 1111 1112 return 0; 1113 } 1114 1115 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1116 bool en_bc_pmc) 1117 { 1118 struct hclge_mbx_vf_to_pf_cmd *req; 1119 struct hclgevf_desc desc; 1120 int ret; 1121 1122 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1123 1124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1125 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1126 req->msg[1] = en_bc_pmc ? 1 : 0; 1127 1128 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1129 if (ret) 1130 dev_err(&hdev->pdev->dev, 1131 "Set promisc mode fail, status is %d.\n", ret); 1132 1133 return ret; 1134 } 1135 1136 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1137 { 1138 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1139 } 1140 1141 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1142 int stream_id, bool enable) 1143 { 1144 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1145 struct hclgevf_desc desc; 1146 int status; 1147 1148 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1149 1150 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1151 false); 1152 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1153 req->stream_id = cpu_to_le16(stream_id); 1154 if (enable) 1155 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1156 1157 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1158 if (status) 1159 dev_err(&hdev->pdev->dev, 1160 "TQP enable fail, status =%d.\n", status); 1161 1162 return status; 1163 } 1164 1165 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1166 { 1167 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1168 struct hclgevf_tqp *tqp; 1169 int i; 1170 1171 for (i = 0; i < kinfo->num_tqps; i++) { 1172 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1173 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1174 } 1175 } 1176 1177 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1178 { 1179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180 1181 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1182 } 1183 1184 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1185 bool is_first) 1186 { 1187 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1188 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1189 u8 *new_mac_addr = (u8 *)p; 1190 u8 msg_data[ETH_ALEN * 2]; 1191 u16 subcode; 1192 int status; 1193 1194 ether_addr_copy(msg_data, new_mac_addr); 1195 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1196 1197 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1198 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1199 1200 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1201 subcode, msg_data, sizeof(msg_data), 1202 true, NULL, 0); 1203 if (!status) 1204 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1205 1206 return status; 1207 } 1208 1209 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1210 const unsigned char *addr) 1211 { 1212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1213 1214 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1215 HCLGE_MBX_MAC_VLAN_UC_ADD, 1216 addr, ETH_ALEN, false, NULL, 0); 1217 } 1218 1219 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1220 const unsigned char *addr) 1221 { 1222 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1223 1224 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1225 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1226 addr, ETH_ALEN, false, NULL, 0); 1227 } 1228 1229 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1230 const unsigned char *addr) 1231 { 1232 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1233 1234 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1235 HCLGE_MBX_MAC_VLAN_MC_ADD, 1236 addr, ETH_ALEN, false, NULL, 0); 1237 } 1238 1239 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1240 const unsigned char *addr) 1241 { 1242 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1243 1244 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1245 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1246 addr, ETH_ALEN, false, NULL, 0); 1247 } 1248 1249 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1250 __be16 proto, u16 vlan_id, 1251 bool is_kill) 1252 { 1253 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1254 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1255 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1256 int ret; 1257 1258 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1259 return -EINVAL; 1260 1261 if (proto != htons(ETH_P_8021Q)) 1262 return -EPROTONOSUPPORT; 1263 1264 /* When device is resetting, firmware is unable to handle 1265 * mailbox. Just record the vlan id, and remove it after 1266 * reset finished. 1267 */ 1268 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1269 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1270 return -EBUSY; 1271 } 1272 1273 msg_data[0] = is_kill; 1274 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1275 memcpy(&msg_data[3], &proto, sizeof(proto)); 1276 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1277 HCLGE_MBX_VLAN_FILTER, msg_data, 1278 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1279 1280 /* when remove hw vlan filter failed, record the vlan id, 1281 * and try to remove it from hw later, to be consistence 1282 * with stack. 1283 */ 1284 if (is_kill && ret) 1285 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1286 1287 return ret; 1288 } 1289 1290 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1291 { 1292 #define HCLGEVF_MAX_SYNC_COUNT 60 1293 struct hnae3_handle *handle = &hdev->nic; 1294 int ret, sync_cnt = 0; 1295 u16 vlan_id; 1296 1297 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1298 while (vlan_id != VLAN_N_VID) { 1299 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1300 vlan_id, true); 1301 if (ret) 1302 return; 1303 1304 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1305 sync_cnt++; 1306 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1307 return; 1308 1309 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1310 } 1311 } 1312 1313 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1314 { 1315 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1316 u8 msg_data; 1317 1318 msg_data = enable ? 1 : 0; 1319 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1320 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1321 1, false, NULL, 0); 1322 } 1323 1324 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1325 { 1326 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1327 u8 msg_data[2]; 1328 int ret; 1329 1330 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1331 1332 /* disable vf queue before send queue reset msg to PF */ 1333 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1334 if (ret) 1335 return ret; 1336 1337 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1338 sizeof(msg_data), true, NULL, 0); 1339 } 1340 1341 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1342 { 1343 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1344 1345 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1346 sizeof(new_mtu), true, NULL, 0); 1347 } 1348 1349 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1350 enum hnae3_reset_notify_type type) 1351 { 1352 struct hnae3_client *client = hdev->nic_client; 1353 struct hnae3_handle *handle = &hdev->nic; 1354 int ret; 1355 1356 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1357 !client) 1358 return 0; 1359 1360 if (!client->ops->reset_notify) 1361 return -EOPNOTSUPP; 1362 1363 ret = client->ops->reset_notify(handle, type); 1364 if (ret) 1365 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1366 type, ret); 1367 1368 return ret; 1369 } 1370 1371 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1372 { 1373 struct hclgevf_dev *hdev = ae_dev->priv; 1374 1375 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1376 } 1377 1378 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1379 unsigned long delay_us, 1380 unsigned long wait_cnt) 1381 { 1382 unsigned long cnt = 0; 1383 1384 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1385 cnt++ < wait_cnt) 1386 usleep_range(delay_us, delay_us * 2); 1387 1388 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1389 dev_err(&hdev->pdev->dev, 1390 "flr wait timeout\n"); 1391 return -ETIMEDOUT; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1398 { 1399 #define HCLGEVF_RESET_WAIT_US 20000 1400 #define HCLGEVF_RESET_WAIT_CNT 2000 1401 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1402 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1403 1404 u32 val; 1405 int ret; 1406 1407 if (hdev->reset_type == HNAE3_FLR_RESET) 1408 return hclgevf_flr_poll_timeout(hdev, 1409 HCLGEVF_RESET_WAIT_US, 1410 HCLGEVF_RESET_WAIT_CNT); 1411 else if (hdev->reset_type == HNAE3_VF_RESET) 1412 ret = readl_poll_timeout(hdev->hw.io_base + 1413 HCLGEVF_VF_RST_ING, val, 1414 !(val & HCLGEVF_VF_RST_ING_BIT), 1415 HCLGEVF_RESET_WAIT_US, 1416 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1417 else 1418 ret = readl_poll_timeout(hdev->hw.io_base + 1419 HCLGEVF_RST_ING, val, 1420 !(val & HCLGEVF_RST_ING_BITS), 1421 HCLGEVF_RESET_WAIT_US, 1422 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1423 1424 /* hardware completion status should be available by this time */ 1425 if (ret) { 1426 dev_err(&hdev->pdev->dev, 1427 "could'nt get reset done status from h/w, timeout!\n"); 1428 return ret; 1429 } 1430 1431 /* we will wait a bit more to let reset of the stack to complete. This 1432 * might happen in case reset assertion was made by PF. Yes, this also 1433 * means we might end up waiting bit more even for VF reset. 1434 */ 1435 msleep(5000); 1436 1437 return 0; 1438 } 1439 1440 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1441 { 1442 u32 reg_val; 1443 1444 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1445 if (enable) 1446 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1447 else 1448 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1449 1450 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1451 reg_val); 1452 } 1453 1454 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1455 { 1456 int ret; 1457 1458 /* uninitialize the nic client */ 1459 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1460 if (ret) 1461 return ret; 1462 1463 /* re-initialize the hclge device */ 1464 ret = hclgevf_reset_hdev(hdev); 1465 if (ret) { 1466 dev_err(&hdev->pdev->dev, 1467 "hclge device re-init failed, VF is disabled!\n"); 1468 return ret; 1469 } 1470 1471 /* bring up the nic client again */ 1472 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1473 if (ret) 1474 return ret; 1475 1476 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1477 if (ret) 1478 return ret; 1479 1480 /* clear handshake status with IMP */ 1481 hclgevf_reset_handshake(hdev, false); 1482 1483 return 0; 1484 } 1485 1486 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1487 { 1488 #define HCLGEVF_RESET_SYNC_TIME 100 1489 1490 int ret = 0; 1491 1492 switch (hdev->reset_type) { 1493 case HNAE3_VF_FUNC_RESET: 1494 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1495 0, true, NULL, sizeof(u8)); 1496 hdev->rst_stats.vf_func_rst_cnt++; 1497 break; 1498 case HNAE3_FLR_RESET: 1499 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1500 hdev->rst_stats.flr_rst_cnt++; 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1507 /* inform hardware that preparatory work is done */ 1508 msleep(HCLGEVF_RESET_SYNC_TIME); 1509 hclgevf_reset_handshake(hdev, true); 1510 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1511 hdev->reset_type, ret); 1512 1513 return ret; 1514 } 1515 1516 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1517 { 1518 /* recover handshake status with IMP when reset fail */ 1519 hclgevf_reset_handshake(hdev, true); 1520 hdev->rst_stats.rst_fail_cnt++; 1521 dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1522 hdev->rst_stats.rst_fail_cnt); 1523 1524 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1525 set_bit(hdev->reset_type, &hdev->reset_pending); 1526 1527 if (hclgevf_is_reset_pending(hdev)) { 1528 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1529 hclgevf_reset_task_schedule(hdev); 1530 } 1531 } 1532 1533 static int hclgevf_reset(struct hclgevf_dev *hdev) 1534 { 1535 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1536 int ret; 1537 1538 /* Initialize ae_dev reset status as well, in case enet layer wants to 1539 * know if device is undergoing reset 1540 */ 1541 ae_dev->reset_type = hdev->reset_type; 1542 hdev->rst_stats.rst_cnt++; 1543 rtnl_lock(); 1544 1545 /* bring down the nic to stop any ongoing TX/RX */ 1546 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1547 if (ret) 1548 goto err_reset_lock; 1549 1550 rtnl_unlock(); 1551 1552 ret = hclgevf_reset_prepare_wait(hdev); 1553 if (ret) 1554 goto err_reset; 1555 1556 /* check if VF could successfully fetch the hardware reset completion 1557 * status from the hardware 1558 */ 1559 ret = hclgevf_reset_wait(hdev); 1560 if (ret) { 1561 /* can't do much in this situation, will disable VF */ 1562 dev_err(&hdev->pdev->dev, 1563 "VF failed(=%d) to fetch H/W reset completion status\n", 1564 ret); 1565 goto err_reset; 1566 } 1567 1568 hdev->rst_stats.hw_rst_done_cnt++; 1569 1570 rtnl_lock(); 1571 1572 /* now, re-initialize the nic client and ae device */ 1573 ret = hclgevf_reset_stack(hdev); 1574 if (ret) { 1575 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1576 goto err_reset_lock; 1577 } 1578 1579 /* bring up the nic to enable TX/RX again */ 1580 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1581 if (ret) 1582 goto err_reset_lock; 1583 1584 rtnl_unlock(); 1585 1586 hdev->last_reset_time = jiffies; 1587 ae_dev->reset_type = HNAE3_NONE_RESET; 1588 hdev->rst_stats.rst_done_cnt++; 1589 hdev->rst_stats.rst_fail_cnt = 0; 1590 1591 return ret; 1592 err_reset_lock: 1593 rtnl_unlock(); 1594 err_reset: 1595 hclgevf_reset_err_handle(hdev); 1596 1597 return ret; 1598 } 1599 1600 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1601 unsigned long *addr) 1602 { 1603 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1604 1605 /* return the highest priority reset level amongst all */ 1606 if (test_bit(HNAE3_VF_RESET, addr)) { 1607 rst_level = HNAE3_VF_RESET; 1608 clear_bit(HNAE3_VF_RESET, addr); 1609 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1610 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1611 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1612 rst_level = HNAE3_VF_FULL_RESET; 1613 clear_bit(HNAE3_VF_FULL_RESET, addr); 1614 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1615 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1616 rst_level = HNAE3_VF_PF_FUNC_RESET; 1617 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1618 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1619 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1620 rst_level = HNAE3_VF_FUNC_RESET; 1621 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1622 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1623 rst_level = HNAE3_FLR_RESET; 1624 clear_bit(HNAE3_FLR_RESET, addr); 1625 } 1626 1627 return rst_level; 1628 } 1629 1630 static void hclgevf_reset_event(struct pci_dev *pdev, 1631 struct hnae3_handle *handle) 1632 { 1633 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1634 struct hclgevf_dev *hdev = ae_dev->priv; 1635 1636 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1637 1638 if (hdev->default_reset_request) 1639 hdev->reset_level = 1640 hclgevf_get_reset_level(hdev, 1641 &hdev->default_reset_request); 1642 else 1643 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1644 1645 /* reset of this VF requested */ 1646 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1647 hclgevf_reset_task_schedule(hdev); 1648 1649 hdev->last_reset_time = jiffies; 1650 } 1651 1652 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1653 enum hnae3_reset_type rst_type) 1654 { 1655 struct hclgevf_dev *hdev = ae_dev->priv; 1656 1657 set_bit(rst_type, &hdev->default_reset_request); 1658 } 1659 1660 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1661 { 1662 #define HCLGEVF_FLR_WAIT_MS 100 1663 #define HCLGEVF_FLR_WAIT_CNT 50 1664 struct hclgevf_dev *hdev = ae_dev->priv; 1665 int cnt = 0; 1666 1667 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1668 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1669 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1670 hclgevf_reset_event(hdev->pdev, NULL); 1671 1672 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1673 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1674 msleep(HCLGEVF_FLR_WAIT_MS); 1675 1676 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1677 dev_err(&hdev->pdev->dev, 1678 "flr wait down timeout: %d\n", cnt); 1679 } 1680 1681 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1682 { 1683 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1684 1685 return hdev->fw_version; 1686 } 1687 1688 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1689 { 1690 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1691 1692 vector->vector_irq = pci_irq_vector(hdev->pdev, 1693 HCLGEVF_MISC_VECTOR_NUM); 1694 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1695 /* vector status always valid for Vector 0 */ 1696 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1697 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1698 1699 hdev->num_msi_left -= 1; 1700 hdev->num_msi_used += 1; 1701 } 1702 1703 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1704 { 1705 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1706 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1707 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1708 schedule_work(&hdev->rst_service_task); 1709 } 1710 } 1711 1712 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1713 { 1714 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1715 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1716 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1717 schedule_work(&hdev->mbx_service_task); 1718 } 1719 } 1720 1721 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1722 { 1723 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1724 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1725 schedule_work(&hdev->service_task); 1726 } 1727 1728 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1729 { 1730 /* if we have any pending mailbox event then schedule the mbx task */ 1731 if (hdev->mbx_event_pending) 1732 hclgevf_mbx_task_schedule(hdev); 1733 1734 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1735 hclgevf_reset_task_schedule(hdev); 1736 } 1737 1738 static void hclgevf_service_timer(struct timer_list *t) 1739 { 1740 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1741 1742 mod_timer(&hdev->service_timer, jiffies + 1743 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1744 1745 hdev->stats_timer++; 1746 hclgevf_task_schedule(hdev); 1747 } 1748 1749 static void hclgevf_reset_service_task(struct work_struct *work) 1750 { 1751 struct hclgevf_dev *hdev = 1752 container_of(work, struct hclgevf_dev, rst_service_task); 1753 int ret; 1754 1755 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1756 return; 1757 1758 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1759 1760 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1761 &hdev->reset_state)) { 1762 /* PF has initmated that it is about to reset the hardware. 1763 * We now have to poll & check if hardware has actually 1764 * completed the reset sequence. On hardware reset completion, 1765 * VF needs to reset the client and ae device. 1766 */ 1767 hdev->reset_attempts = 0; 1768 1769 hdev->last_reset_time = jiffies; 1770 while ((hdev->reset_type = 1771 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1772 != HNAE3_NONE_RESET) { 1773 ret = hclgevf_reset(hdev); 1774 if (ret) 1775 dev_err(&hdev->pdev->dev, 1776 "VF stack reset failed %d.\n", ret); 1777 } 1778 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1779 &hdev->reset_state)) { 1780 /* we could be here when either of below happens: 1781 * 1. reset was initiated due to watchdog timeout caused by 1782 * a. IMP was earlier reset and our TX got choked down and 1783 * which resulted in watchdog reacting and inducing VF 1784 * reset. This also means our cmdq would be unreliable. 1785 * b. problem in TX due to other lower layer(example link 1786 * layer not functioning properly etc.) 1787 * 2. VF reset might have been initiated due to some config 1788 * change. 1789 * 1790 * NOTE: Theres no clear way to detect above cases than to react 1791 * to the response of PF for this reset request. PF will ack the 1792 * 1b and 2. cases but we will not get any intimation about 1a 1793 * from PF as cmdq would be in unreliable state i.e. mailbox 1794 * communication between PF and VF would be broken. 1795 * 1796 * if we are never geting into pending state it means either: 1797 * 1. PF is not receiving our request which could be due to IMP 1798 * reset 1799 * 2. PF is screwed 1800 * We cannot do much for 2. but to check first we can try reset 1801 * our PCIe + stack and see if it alleviates the problem. 1802 */ 1803 if (hdev->reset_attempts > 3) { 1804 /* prepare for full reset of stack + pcie interface */ 1805 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1806 1807 /* "defer" schedule the reset task again */ 1808 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1809 } else { 1810 hdev->reset_attempts++; 1811 1812 set_bit(hdev->reset_level, &hdev->reset_pending); 1813 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1814 } 1815 hclgevf_reset_task_schedule(hdev); 1816 } 1817 1818 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1819 } 1820 1821 static void hclgevf_mailbox_service_task(struct work_struct *work) 1822 { 1823 struct hclgevf_dev *hdev; 1824 1825 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1826 1827 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1828 return; 1829 1830 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1831 1832 hclgevf_mbx_async_handler(hdev); 1833 1834 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1835 } 1836 1837 static void hclgevf_keep_alive_timer(struct timer_list *t) 1838 { 1839 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1840 1841 schedule_work(&hdev->keep_alive_task); 1842 mod_timer(&hdev->keep_alive_timer, jiffies + 1843 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1844 } 1845 1846 static void hclgevf_keep_alive_task(struct work_struct *work) 1847 { 1848 struct hclgevf_dev *hdev; 1849 u8 respmsg; 1850 int ret; 1851 1852 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1853 1854 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1855 return; 1856 1857 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1858 0, false, &respmsg, sizeof(respmsg)); 1859 if (ret) 1860 dev_err(&hdev->pdev->dev, 1861 "VF sends keep alive cmd failed(=%d)\n", ret); 1862 } 1863 1864 static void hclgevf_service_task(struct work_struct *work) 1865 { 1866 struct hnae3_handle *handle; 1867 struct hclgevf_dev *hdev; 1868 1869 hdev = container_of(work, struct hclgevf_dev, service_task); 1870 handle = &hdev->nic; 1871 1872 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1873 hclgevf_tqps_update_stats(handle); 1874 hdev->stats_timer = 0; 1875 } 1876 1877 /* request the link status from the PF. PF would be able to tell VF 1878 * about such updates in future so we might remove this later 1879 */ 1880 hclgevf_request_link_info(hdev); 1881 1882 hclgevf_update_link_mode(hdev); 1883 1884 hclgevf_sync_vlan_filter(hdev); 1885 1886 hclgevf_deferred_task_schedule(hdev); 1887 1888 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1889 } 1890 1891 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1892 { 1893 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1894 } 1895 1896 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1897 u32 *clearval) 1898 { 1899 u32 val, cmdq_stat_reg, rst_ing_reg; 1900 1901 /* fetch the events from their corresponding regs */ 1902 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1903 HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1904 1905 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1906 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1907 dev_info(&hdev->pdev->dev, 1908 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1909 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1910 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1911 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1912 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1913 hdev->rst_stats.vf_rst_cnt++; 1914 /* set up VF hardware reset status, its PF will clear 1915 * this status when PF has initialized done. 1916 */ 1917 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1918 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1919 val | HCLGEVF_VF_RST_ING_BIT); 1920 return HCLGEVF_VECTOR0_EVENT_RST; 1921 } 1922 1923 /* check for vector0 mailbox(=CMDQ RX) event source */ 1924 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1925 /* for revision 0x21, clearing interrupt is writing bit 0 1926 * to the clear register, writing bit 1 means to keep the 1927 * old value. 1928 * for revision 0x20, the clear register is a read & write 1929 * register, so we should just write 0 to the bit we are 1930 * handling, and keep other bits as cmdq_stat_reg. 1931 */ 1932 if (hdev->pdev->revision >= 0x21) 1933 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1934 else 1935 *clearval = cmdq_stat_reg & 1936 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1937 1938 return HCLGEVF_VECTOR0_EVENT_MBX; 1939 } 1940 1941 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1942 1943 return HCLGEVF_VECTOR0_EVENT_OTHER; 1944 } 1945 1946 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1947 { 1948 writel(en ? 1 : 0, vector->addr); 1949 } 1950 1951 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1952 { 1953 enum hclgevf_evt_cause event_cause; 1954 struct hclgevf_dev *hdev = data; 1955 u32 clearval; 1956 1957 hclgevf_enable_vector(&hdev->misc_vector, false); 1958 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1959 1960 switch (event_cause) { 1961 case HCLGEVF_VECTOR0_EVENT_RST: 1962 hclgevf_reset_task_schedule(hdev); 1963 break; 1964 case HCLGEVF_VECTOR0_EVENT_MBX: 1965 hclgevf_mbx_handler(hdev); 1966 break; 1967 default: 1968 break; 1969 } 1970 1971 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1972 hclgevf_clear_event_cause(hdev, clearval); 1973 hclgevf_enable_vector(&hdev->misc_vector, true); 1974 } 1975 1976 return IRQ_HANDLED; 1977 } 1978 1979 static int hclgevf_configure(struct hclgevf_dev *hdev) 1980 { 1981 int ret; 1982 1983 /* get current port based vlan state from PF */ 1984 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1985 if (ret) 1986 return ret; 1987 1988 /* get queue configuration from PF */ 1989 ret = hclgevf_get_queue_info(hdev); 1990 if (ret) 1991 return ret; 1992 1993 /* get queue depth info from PF */ 1994 ret = hclgevf_get_queue_depth(hdev); 1995 if (ret) 1996 return ret; 1997 1998 ret = hclgevf_get_pf_media_type(hdev); 1999 if (ret) 2000 return ret; 2001 2002 /* get tc configuration from PF */ 2003 return hclgevf_get_tc_info(hdev); 2004 } 2005 2006 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2007 { 2008 struct pci_dev *pdev = ae_dev->pdev; 2009 struct hclgevf_dev *hdev; 2010 2011 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2012 if (!hdev) 2013 return -ENOMEM; 2014 2015 hdev->pdev = pdev; 2016 hdev->ae_dev = ae_dev; 2017 ae_dev->priv = hdev; 2018 2019 return 0; 2020 } 2021 2022 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2023 { 2024 struct hnae3_handle *roce = &hdev->roce; 2025 struct hnae3_handle *nic = &hdev->nic; 2026 2027 roce->rinfo.num_vectors = hdev->num_roce_msix; 2028 2029 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2030 hdev->num_msi_left == 0) 2031 return -EINVAL; 2032 2033 roce->rinfo.base_vector = hdev->roce_base_vector; 2034 2035 roce->rinfo.netdev = nic->kinfo.netdev; 2036 roce->rinfo.roce_io_base = hdev->hw.io_base; 2037 2038 roce->pdev = nic->pdev; 2039 roce->ae_algo = nic->ae_algo; 2040 roce->numa_node_mask = nic->numa_node_mask; 2041 2042 return 0; 2043 } 2044 2045 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2046 { 2047 struct hclgevf_cfg_gro_status_cmd *req; 2048 struct hclgevf_desc desc; 2049 int ret; 2050 2051 if (!hnae3_dev_gro_supported(hdev)) 2052 return 0; 2053 2054 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2055 false); 2056 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2057 2058 req->gro_en = cpu_to_le16(en ? 1 : 0); 2059 2060 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2061 if (ret) 2062 dev_err(&hdev->pdev->dev, 2063 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2064 2065 return ret; 2066 } 2067 2068 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2069 { 2070 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2071 int ret; 2072 u32 i; 2073 2074 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2075 2076 if (hdev->pdev->revision >= 0x21) { 2077 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2078 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2079 HCLGEVF_RSS_KEY_SIZE); 2080 2081 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2082 rss_cfg->rss_hash_key); 2083 if (ret) 2084 return ret; 2085 2086 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2087 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2088 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2089 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2090 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2091 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2092 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2093 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2094 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2095 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2096 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2097 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2098 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2099 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2100 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2101 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2102 2103 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2104 if (ret) 2105 return ret; 2106 2107 } 2108 2109 /* Initialize RSS indirect table */ 2110 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2111 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2112 2113 ret = hclgevf_set_rss_indir_table(hdev); 2114 if (ret) 2115 return ret; 2116 2117 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2118 } 2119 2120 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2121 { 2122 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2123 false); 2124 } 2125 2126 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2127 { 2128 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2129 2130 if (enable) { 2131 mod_timer(&hdev->service_timer, jiffies + HZ); 2132 } else { 2133 del_timer_sync(&hdev->service_timer); 2134 cancel_work_sync(&hdev->service_task); 2135 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2136 } 2137 } 2138 2139 static int hclgevf_ae_start(struct hnae3_handle *handle) 2140 { 2141 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2142 2143 hclgevf_reset_tqp_stats(handle); 2144 2145 hclgevf_request_link_info(hdev); 2146 2147 hclgevf_update_link_mode(hdev); 2148 2149 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2150 2151 return 0; 2152 } 2153 2154 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2155 { 2156 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2157 int i; 2158 2159 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2160 2161 if (hdev->reset_type != HNAE3_VF_RESET) 2162 for (i = 0; i < handle->kinfo.num_tqps; i++) 2163 if (hclgevf_reset_tqp(handle, i)) 2164 break; 2165 2166 hclgevf_reset_tqp_stats(handle); 2167 hclgevf_update_link_status(hdev, 0); 2168 } 2169 2170 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2171 { 2172 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2173 u8 msg_data; 2174 2175 msg_data = alive ? 1 : 0; 2176 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2177 0, &msg_data, 1, false, NULL, 0); 2178 } 2179 2180 static int hclgevf_client_start(struct hnae3_handle *handle) 2181 { 2182 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2183 int ret; 2184 2185 ret = hclgevf_set_alive(handle, true); 2186 if (ret) 2187 return ret; 2188 2189 mod_timer(&hdev->keep_alive_timer, jiffies + 2190 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2191 2192 return 0; 2193 } 2194 2195 static void hclgevf_client_stop(struct hnae3_handle *handle) 2196 { 2197 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2198 int ret; 2199 2200 ret = hclgevf_set_alive(handle, false); 2201 if (ret) 2202 dev_warn(&hdev->pdev->dev, 2203 "%s failed %d\n", __func__, ret); 2204 2205 del_timer_sync(&hdev->keep_alive_timer); 2206 cancel_work_sync(&hdev->keep_alive_task); 2207 } 2208 2209 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2210 { 2211 /* setup tasks for the MBX */ 2212 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2213 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2214 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2215 2216 /* setup tasks for service timer */ 2217 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2218 2219 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2220 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2221 2222 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2223 2224 mutex_init(&hdev->mbx_resp.mbx_mutex); 2225 2226 /* bring the device down */ 2227 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2228 } 2229 2230 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2231 { 2232 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2233 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2234 2235 if (hdev->keep_alive_timer.function) 2236 del_timer_sync(&hdev->keep_alive_timer); 2237 if (hdev->keep_alive_task.func) 2238 cancel_work_sync(&hdev->keep_alive_task); 2239 if (hdev->service_timer.function) 2240 del_timer_sync(&hdev->service_timer); 2241 if (hdev->service_task.func) 2242 cancel_work_sync(&hdev->service_task); 2243 if (hdev->mbx_service_task.func) 2244 cancel_work_sync(&hdev->mbx_service_task); 2245 if (hdev->rst_service_task.func) 2246 cancel_work_sync(&hdev->rst_service_task); 2247 2248 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2249 } 2250 2251 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2252 { 2253 struct pci_dev *pdev = hdev->pdev; 2254 int vectors; 2255 int i; 2256 2257 if (hnae3_dev_roce_supported(hdev)) 2258 vectors = pci_alloc_irq_vectors(pdev, 2259 hdev->roce_base_msix_offset + 1, 2260 hdev->num_msi, 2261 PCI_IRQ_MSIX); 2262 else 2263 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2264 hdev->num_msi, 2265 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2266 2267 if (vectors < 0) { 2268 dev_err(&pdev->dev, 2269 "failed(%d) to allocate MSI/MSI-X vectors\n", 2270 vectors); 2271 return vectors; 2272 } 2273 if (vectors < hdev->num_msi) 2274 dev_warn(&hdev->pdev->dev, 2275 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2276 hdev->num_msi, vectors); 2277 2278 hdev->num_msi = vectors; 2279 hdev->num_msi_left = vectors; 2280 2281 hdev->base_msi_vector = pdev->irq; 2282 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2283 2284 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2285 sizeof(u16), GFP_KERNEL); 2286 if (!hdev->vector_status) { 2287 pci_free_irq_vectors(pdev); 2288 return -ENOMEM; 2289 } 2290 2291 for (i = 0; i < hdev->num_msi; i++) 2292 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2293 2294 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2295 sizeof(int), GFP_KERNEL); 2296 if (!hdev->vector_irq) { 2297 devm_kfree(&pdev->dev, hdev->vector_status); 2298 pci_free_irq_vectors(pdev); 2299 return -ENOMEM; 2300 } 2301 2302 return 0; 2303 } 2304 2305 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2306 { 2307 struct pci_dev *pdev = hdev->pdev; 2308 2309 devm_kfree(&pdev->dev, hdev->vector_status); 2310 devm_kfree(&pdev->dev, hdev->vector_irq); 2311 pci_free_irq_vectors(pdev); 2312 } 2313 2314 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2315 { 2316 int ret; 2317 2318 hclgevf_get_misc_vector(hdev); 2319 2320 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2321 0, "hclgevf_cmd", hdev); 2322 if (ret) { 2323 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2324 hdev->misc_vector.vector_irq); 2325 return ret; 2326 } 2327 2328 hclgevf_clear_event_cause(hdev, 0); 2329 2330 /* enable misc. vector(vector 0) */ 2331 hclgevf_enable_vector(&hdev->misc_vector, true); 2332 2333 return ret; 2334 } 2335 2336 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2337 { 2338 /* disable misc vector(vector 0) */ 2339 hclgevf_enable_vector(&hdev->misc_vector, false); 2340 synchronize_irq(hdev->misc_vector.vector_irq); 2341 free_irq(hdev->misc_vector.vector_irq, hdev); 2342 hclgevf_free_vector(hdev, 0); 2343 } 2344 2345 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2346 { 2347 struct device *dev = &hdev->pdev->dev; 2348 2349 dev_info(dev, "VF info begin:\n"); 2350 2351 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2352 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2353 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2354 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2355 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2356 dev_info(dev, "PF media type of this VF: %d\n", 2357 hdev->hw.mac.media_type); 2358 2359 dev_info(dev, "VF info end.\n"); 2360 } 2361 2362 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2363 struct hnae3_client *client) 2364 { 2365 struct hclgevf_dev *hdev = ae_dev->priv; 2366 int ret; 2367 2368 ret = client->ops->init_instance(&hdev->nic); 2369 if (ret) 2370 return ret; 2371 2372 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2373 hnae3_set_client_init_flag(client, ae_dev, 1); 2374 2375 if (netif_msg_drv(&hdev->nic)) 2376 hclgevf_info_show(hdev); 2377 2378 return 0; 2379 } 2380 2381 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2382 struct hnae3_client *client) 2383 { 2384 struct hclgevf_dev *hdev = ae_dev->priv; 2385 int ret; 2386 2387 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2388 !hdev->nic_client) 2389 return 0; 2390 2391 ret = hclgevf_init_roce_base_info(hdev); 2392 if (ret) 2393 return ret; 2394 2395 ret = client->ops->init_instance(&hdev->roce); 2396 if (ret) 2397 return ret; 2398 2399 hnae3_set_client_init_flag(client, ae_dev, 1); 2400 2401 return 0; 2402 } 2403 2404 static int hclgevf_init_client_instance(struct hnae3_client *client, 2405 struct hnae3_ae_dev *ae_dev) 2406 { 2407 struct hclgevf_dev *hdev = ae_dev->priv; 2408 int ret; 2409 2410 switch (client->type) { 2411 case HNAE3_CLIENT_KNIC: 2412 hdev->nic_client = client; 2413 hdev->nic.client = client; 2414 2415 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2416 if (ret) 2417 goto clear_nic; 2418 2419 ret = hclgevf_init_roce_client_instance(ae_dev, 2420 hdev->roce_client); 2421 if (ret) 2422 goto clear_roce; 2423 2424 break; 2425 case HNAE3_CLIENT_ROCE: 2426 if (hnae3_dev_roce_supported(hdev)) { 2427 hdev->roce_client = client; 2428 hdev->roce.client = client; 2429 } 2430 2431 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2432 if (ret) 2433 goto clear_roce; 2434 2435 break; 2436 default: 2437 return -EINVAL; 2438 } 2439 2440 return 0; 2441 2442 clear_nic: 2443 hdev->nic_client = NULL; 2444 hdev->nic.client = NULL; 2445 return ret; 2446 clear_roce: 2447 hdev->roce_client = NULL; 2448 hdev->roce.client = NULL; 2449 return ret; 2450 } 2451 2452 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2453 struct hnae3_ae_dev *ae_dev) 2454 { 2455 struct hclgevf_dev *hdev = ae_dev->priv; 2456 2457 /* un-init roce, if it exists */ 2458 if (hdev->roce_client) { 2459 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2460 hdev->roce_client = NULL; 2461 hdev->roce.client = NULL; 2462 } 2463 2464 /* un-init nic/unic, if this was not called by roce client */ 2465 if (client->ops->uninit_instance && hdev->nic_client && 2466 client->type != HNAE3_CLIENT_ROCE) { 2467 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2468 2469 client->ops->uninit_instance(&hdev->nic, 0); 2470 hdev->nic_client = NULL; 2471 hdev->nic.client = NULL; 2472 } 2473 } 2474 2475 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2476 { 2477 struct pci_dev *pdev = hdev->pdev; 2478 struct hclgevf_hw *hw; 2479 int ret; 2480 2481 ret = pci_enable_device(pdev); 2482 if (ret) { 2483 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2484 return ret; 2485 } 2486 2487 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2488 if (ret) { 2489 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2490 goto err_disable_device; 2491 } 2492 2493 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2494 if (ret) { 2495 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2496 goto err_disable_device; 2497 } 2498 2499 pci_set_master(pdev); 2500 hw = &hdev->hw; 2501 hw->hdev = hdev; 2502 hw->io_base = pci_iomap(pdev, 2, 0); 2503 if (!hw->io_base) { 2504 dev_err(&pdev->dev, "can't map configuration register space\n"); 2505 ret = -ENOMEM; 2506 goto err_clr_master; 2507 } 2508 2509 return 0; 2510 2511 err_clr_master: 2512 pci_clear_master(pdev); 2513 pci_release_regions(pdev); 2514 err_disable_device: 2515 pci_disable_device(pdev); 2516 2517 return ret; 2518 } 2519 2520 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2521 { 2522 struct pci_dev *pdev = hdev->pdev; 2523 2524 pci_iounmap(pdev, hdev->hw.io_base); 2525 pci_clear_master(pdev); 2526 pci_release_regions(pdev); 2527 pci_disable_device(pdev); 2528 } 2529 2530 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2531 { 2532 struct hclgevf_query_res_cmd *req; 2533 struct hclgevf_desc desc; 2534 int ret; 2535 2536 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2537 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2538 if (ret) { 2539 dev_err(&hdev->pdev->dev, 2540 "query vf resource failed, ret = %d.\n", ret); 2541 return ret; 2542 } 2543 2544 req = (struct hclgevf_query_res_cmd *)desc.data; 2545 2546 if (hnae3_dev_roce_supported(hdev)) { 2547 hdev->roce_base_msix_offset = 2548 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2549 HCLGEVF_MSIX_OFT_ROCEE_M, 2550 HCLGEVF_MSIX_OFT_ROCEE_S); 2551 hdev->num_roce_msix = 2552 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2553 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2554 2555 /* nic's msix numbers is always equals to the roce's. */ 2556 hdev->num_nic_msix = hdev->num_roce_msix; 2557 2558 /* VF should have NIC vectors and Roce vectors, NIC vectors 2559 * are queued before Roce vectors. The offset is fixed to 64. 2560 */ 2561 hdev->num_msi = hdev->num_roce_msix + 2562 hdev->roce_base_msix_offset; 2563 } else { 2564 hdev->num_msi = 2565 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2566 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2567 2568 hdev->num_nic_msix = hdev->num_msi; 2569 } 2570 2571 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2572 dev_err(&hdev->pdev->dev, 2573 "Just %u msi resources, not enough for vf(min:2).\n", 2574 hdev->num_nic_msix); 2575 return -EINVAL; 2576 } 2577 2578 return 0; 2579 } 2580 2581 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2582 { 2583 struct pci_dev *pdev = hdev->pdev; 2584 int ret = 0; 2585 2586 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2587 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2588 hclgevf_misc_irq_uninit(hdev); 2589 hclgevf_uninit_msi(hdev); 2590 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2591 } 2592 2593 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2594 pci_set_master(pdev); 2595 ret = hclgevf_init_msi(hdev); 2596 if (ret) { 2597 dev_err(&pdev->dev, 2598 "failed(%d) to init MSI/MSI-X\n", ret); 2599 return ret; 2600 } 2601 2602 ret = hclgevf_misc_irq_init(hdev); 2603 if (ret) { 2604 hclgevf_uninit_msi(hdev); 2605 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2606 ret); 2607 return ret; 2608 } 2609 2610 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2611 } 2612 2613 return ret; 2614 } 2615 2616 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2617 { 2618 struct pci_dev *pdev = hdev->pdev; 2619 int ret; 2620 2621 ret = hclgevf_pci_reset(hdev); 2622 if (ret) { 2623 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2624 return ret; 2625 } 2626 2627 ret = hclgevf_cmd_init(hdev); 2628 if (ret) { 2629 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2630 return ret; 2631 } 2632 2633 ret = hclgevf_rss_init_hw(hdev); 2634 if (ret) { 2635 dev_err(&hdev->pdev->dev, 2636 "failed(%d) to initialize RSS\n", ret); 2637 return ret; 2638 } 2639 2640 ret = hclgevf_config_gro(hdev, true); 2641 if (ret) 2642 return ret; 2643 2644 ret = hclgevf_init_vlan_config(hdev); 2645 if (ret) { 2646 dev_err(&hdev->pdev->dev, 2647 "failed(%d) to initialize VLAN config\n", ret); 2648 return ret; 2649 } 2650 2651 if (pdev->revision >= 0x21) { 2652 ret = hclgevf_set_promisc_mode(hdev, true); 2653 if (ret) 2654 return ret; 2655 } 2656 2657 dev_info(&hdev->pdev->dev, "Reset done\n"); 2658 2659 return 0; 2660 } 2661 2662 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2663 { 2664 struct pci_dev *pdev = hdev->pdev; 2665 int ret; 2666 2667 ret = hclgevf_pci_init(hdev); 2668 if (ret) { 2669 dev_err(&pdev->dev, "PCI initialization failed\n"); 2670 return ret; 2671 } 2672 2673 ret = hclgevf_cmd_queue_init(hdev); 2674 if (ret) { 2675 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2676 goto err_cmd_queue_init; 2677 } 2678 2679 ret = hclgevf_cmd_init(hdev); 2680 if (ret) 2681 goto err_cmd_init; 2682 2683 /* Get vf resource */ 2684 ret = hclgevf_query_vf_resource(hdev); 2685 if (ret) { 2686 dev_err(&hdev->pdev->dev, 2687 "Query vf status error, ret = %d.\n", ret); 2688 goto err_cmd_init; 2689 } 2690 2691 ret = hclgevf_init_msi(hdev); 2692 if (ret) { 2693 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2694 goto err_cmd_init; 2695 } 2696 2697 hclgevf_state_init(hdev); 2698 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2699 2700 ret = hclgevf_misc_irq_init(hdev); 2701 if (ret) { 2702 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2703 ret); 2704 goto err_misc_irq_init; 2705 } 2706 2707 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2708 2709 ret = hclgevf_configure(hdev); 2710 if (ret) { 2711 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2712 goto err_config; 2713 } 2714 2715 ret = hclgevf_alloc_tqps(hdev); 2716 if (ret) { 2717 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2718 goto err_config; 2719 } 2720 2721 ret = hclgevf_set_handle_info(hdev); 2722 if (ret) { 2723 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2724 goto err_config; 2725 } 2726 2727 ret = hclgevf_config_gro(hdev, true); 2728 if (ret) 2729 goto err_config; 2730 2731 /* vf is not allowed to enable unicast/multicast promisc mode. 2732 * For revision 0x20, default to disable broadcast promisc mode, 2733 * firmware makes sure broadcast packets can be accepted. 2734 * For revision 0x21, default to enable broadcast promisc mode. 2735 */ 2736 if (pdev->revision >= 0x21) { 2737 ret = hclgevf_set_promisc_mode(hdev, true); 2738 if (ret) 2739 goto err_config; 2740 } 2741 2742 /* Initialize RSS for this VF */ 2743 ret = hclgevf_rss_init_hw(hdev); 2744 if (ret) { 2745 dev_err(&hdev->pdev->dev, 2746 "failed(%d) to initialize RSS\n", ret); 2747 goto err_config; 2748 } 2749 2750 ret = hclgevf_init_vlan_config(hdev); 2751 if (ret) { 2752 dev_err(&hdev->pdev->dev, 2753 "failed(%d) to initialize VLAN config\n", ret); 2754 goto err_config; 2755 } 2756 2757 hdev->last_reset_time = jiffies; 2758 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2759 HCLGEVF_DRIVER_NAME); 2760 2761 return 0; 2762 2763 err_config: 2764 hclgevf_misc_irq_uninit(hdev); 2765 err_misc_irq_init: 2766 hclgevf_state_uninit(hdev); 2767 hclgevf_uninit_msi(hdev); 2768 err_cmd_init: 2769 hclgevf_cmd_uninit(hdev); 2770 err_cmd_queue_init: 2771 hclgevf_pci_uninit(hdev); 2772 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2773 return ret; 2774 } 2775 2776 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2777 { 2778 hclgevf_state_uninit(hdev); 2779 2780 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2781 hclgevf_misc_irq_uninit(hdev); 2782 hclgevf_uninit_msi(hdev); 2783 } 2784 2785 hclgevf_pci_uninit(hdev); 2786 hclgevf_cmd_uninit(hdev); 2787 } 2788 2789 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2790 { 2791 struct pci_dev *pdev = ae_dev->pdev; 2792 struct hclgevf_dev *hdev; 2793 int ret; 2794 2795 ret = hclgevf_alloc_hdev(ae_dev); 2796 if (ret) { 2797 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2798 return ret; 2799 } 2800 2801 ret = hclgevf_init_hdev(ae_dev->priv); 2802 if (ret) { 2803 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2804 return ret; 2805 } 2806 2807 hdev = ae_dev->priv; 2808 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2809 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2810 2811 return 0; 2812 } 2813 2814 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2815 { 2816 struct hclgevf_dev *hdev = ae_dev->priv; 2817 2818 hclgevf_uninit_hdev(hdev); 2819 ae_dev->priv = NULL; 2820 } 2821 2822 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2823 { 2824 struct hnae3_handle *nic = &hdev->nic; 2825 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2826 2827 return min_t(u32, hdev->rss_size_max, 2828 hdev->num_tqps / kinfo->num_tc); 2829 } 2830 2831 /** 2832 * hclgevf_get_channels - Get the current channels enabled and max supported. 2833 * @handle: hardware information for network interface 2834 * @ch: ethtool channels structure 2835 * 2836 * We don't support separate tx and rx queues as channels. The other count 2837 * represents how many queues are being used for control. max_combined counts 2838 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2839 * q_vectors since we support a lot more queue pairs than q_vectors. 2840 **/ 2841 static void hclgevf_get_channels(struct hnae3_handle *handle, 2842 struct ethtool_channels *ch) 2843 { 2844 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2845 2846 ch->max_combined = hclgevf_get_max_channels(hdev); 2847 ch->other_count = 0; 2848 ch->max_other = 0; 2849 ch->combined_count = handle->kinfo.rss_size; 2850 } 2851 2852 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2853 u16 *alloc_tqps, u16 *max_rss_size) 2854 { 2855 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2856 2857 *alloc_tqps = hdev->num_tqps; 2858 *max_rss_size = hdev->rss_size_max; 2859 } 2860 2861 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 2862 u32 new_tqps_num) 2863 { 2864 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2865 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2866 u16 max_rss_size; 2867 2868 kinfo->req_rss_size = new_tqps_num; 2869 2870 max_rss_size = min_t(u16, hdev->rss_size_max, 2871 hdev->num_tqps / kinfo->num_tc); 2872 2873 /* Use the user's configuration when it is not larger than 2874 * max_rss_size, otherwise, use the maximum specification value. 2875 */ 2876 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 2877 kinfo->req_rss_size <= max_rss_size) 2878 kinfo->rss_size = kinfo->req_rss_size; 2879 else if (kinfo->rss_size > max_rss_size || 2880 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 2881 kinfo->rss_size = max_rss_size; 2882 2883 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 2884 } 2885 2886 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 2887 bool rxfh_configured) 2888 { 2889 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2890 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2891 u16 cur_rss_size = kinfo->rss_size; 2892 u16 cur_tqps = kinfo->num_tqps; 2893 u32 *rss_indir; 2894 unsigned int i; 2895 int ret; 2896 2897 hclgevf_update_rss_size(handle, new_tqps_num); 2898 2899 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 2900 if (ret) 2901 return ret; 2902 2903 /* RSS indirection table has been configuared by user */ 2904 if (rxfh_configured) 2905 goto out; 2906 2907 /* Reinitializes the rss indirect table according to the new RSS size */ 2908 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 2909 if (!rss_indir) 2910 return -ENOMEM; 2911 2912 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2913 rss_indir[i] = i % kinfo->rss_size; 2914 2915 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 2916 if (ret) 2917 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 2918 ret); 2919 2920 kfree(rss_indir); 2921 2922 out: 2923 if (!ret) 2924 dev_info(&hdev->pdev->dev, 2925 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 2926 cur_rss_size, kinfo->rss_size, 2927 cur_tqps, kinfo->rss_size * kinfo->num_tc); 2928 2929 return ret; 2930 } 2931 2932 static int hclgevf_get_status(struct hnae3_handle *handle) 2933 { 2934 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2935 2936 return hdev->hw.mac.link; 2937 } 2938 2939 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2940 u8 *auto_neg, u32 *speed, 2941 u8 *duplex) 2942 { 2943 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2944 2945 if (speed) 2946 *speed = hdev->hw.mac.speed; 2947 if (duplex) 2948 *duplex = hdev->hw.mac.duplex; 2949 if (auto_neg) 2950 *auto_neg = AUTONEG_DISABLE; 2951 } 2952 2953 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2954 u8 duplex) 2955 { 2956 hdev->hw.mac.speed = speed; 2957 hdev->hw.mac.duplex = duplex; 2958 } 2959 2960 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2961 { 2962 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2963 2964 return hclgevf_config_gro(hdev, enable); 2965 } 2966 2967 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2968 u8 *module_type) 2969 { 2970 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2971 2972 if (media_type) 2973 *media_type = hdev->hw.mac.media_type; 2974 2975 if (module_type) 2976 *module_type = hdev->hw.mac.module_type; 2977 } 2978 2979 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2980 { 2981 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2982 2983 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2984 } 2985 2986 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2987 { 2988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2989 2990 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2991 } 2992 2993 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2994 { 2995 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2996 2997 return hdev->rst_stats.hw_rst_done_cnt; 2998 } 2999 3000 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3001 unsigned long *supported, 3002 unsigned long *advertising) 3003 { 3004 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3005 3006 *supported = hdev->hw.mac.supported; 3007 *advertising = hdev->hw.mac.advertising; 3008 } 3009 3010 #define MAX_SEPARATE_NUM 4 3011 #define SEPARATOR_VALUE 0xFFFFFFFF 3012 #define REG_NUM_PER_LINE 4 3013 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3014 3015 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3016 { 3017 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3018 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3019 3020 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3021 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3022 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3023 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3024 3025 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3026 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3027 } 3028 3029 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3030 void *data) 3031 { 3032 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3033 int i, j, reg_um, separator_num; 3034 u32 *reg = data; 3035 3036 *version = hdev->fw_version; 3037 3038 /* fetching per-VF registers values from VF PCIe register space */ 3039 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3040 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3041 for (i = 0; i < reg_um; i++) 3042 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3043 for (i = 0; i < separator_num; i++) 3044 *reg++ = SEPARATOR_VALUE; 3045 3046 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3047 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3048 for (i = 0; i < reg_um; i++) 3049 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3050 for (i = 0; i < separator_num; i++) 3051 *reg++ = SEPARATOR_VALUE; 3052 3053 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3054 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3055 for (j = 0; j < hdev->num_tqps; j++) { 3056 for (i = 0; i < reg_um; i++) 3057 *reg++ = hclgevf_read_dev(&hdev->hw, 3058 ring_reg_addr_list[i] + 3059 0x200 * j); 3060 for (i = 0; i < separator_num; i++) 3061 *reg++ = SEPARATOR_VALUE; 3062 } 3063 3064 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3065 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3066 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3067 for (i = 0; i < reg_um; i++) 3068 *reg++ = hclgevf_read_dev(&hdev->hw, 3069 tqp_intr_reg_addr_list[i] + 3070 4 * j); 3071 for (i = 0; i < separator_num; i++) 3072 *reg++ = SEPARATOR_VALUE; 3073 } 3074 } 3075 3076 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3077 u8 *port_base_vlan_info, u8 data_size) 3078 { 3079 struct hnae3_handle *nic = &hdev->nic; 3080 3081 rtnl_lock(); 3082 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3083 rtnl_unlock(); 3084 3085 /* send msg to PF and wait update port based vlan info */ 3086 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 3087 HCLGE_MBX_PORT_BASE_VLAN_CFG, 3088 port_base_vlan_info, data_size, 3089 false, NULL, 0); 3090 3091 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3092 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 3093 else 3094 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3095 3096 rtnl_lock(); 3097 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3098 rtnl_unlock(); 3099 } 3100 3101 static const struct hnae3_ae_ops hclgevf_ops = { 3102 .init_ae_dev = hclgevf_init_ae_dev, 3103 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3104 .flr_prepare = hclgevf_flr_prepare, 3105 .flr_done = hclgevf_flr_done, 3106 .init_client_instance = hclgevf_init_client_instance, 3107 .uninit_client_instance = hclgevf_uninit_client_instance, 3108 .start = hclgevf_ae_start, 3109 .stop = hclgevf_ae_stop, 3110 .client_start = hclgevf_client_start, 3111 .client_stop = hclgevf_client_stop, 3112 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3113 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3114 .get_vector = hclgevf_get_vector, 3115 .put_vector = hclgevf_put_vector, 3116 .reset_queue = hclgevf_reset_tqp, 3117 .get_mac_addr = hclgevf_get_mac_addr, 3118 .set_mac_addr = hclgevf_set_mac_addr, 3119 .add_uc_addr = hclgevf_add_uc_addr, 3120 .rm_uc_addr = hclgevf_rm_uc_addr, 3121 .add_mc_addr = hclgevf_add_mc_addr, 3122 .rm_mc_addr = hclgevf_rm_mc_addr, 3123 .get_stats = hclgevf_get_stats, 3124 .update_stats = hclgevf_update_stats, 3125 .get_strings = hclgevf_get_strings, 3126 .get_sset_count = hclgevf_get_sset_count, 3127 .get_rss_key_size = hclgevf_get_rss_key_size, 3128 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3129 .get_rss = hclgevf_get_rss, 3130 .set_rss = hclgevf_set_rss, 3131 .get_rss_tuple = hclgevf_get_rss_tuple, 3132 .set_rss_tuple = hclgevf_set_rss_tuple, 3133 .get_tc_size = hclgevf_get_tc_size, 3134 .get_fw_version = hclgevf_get_fw_version, 3135 .set_vlan_filter = hclgevf_set_vlan_filter, 3136 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3137 .reset_event = hclgevf_reset_event, 3138 .set_default_reset_request = hclgevf_set_def_reset_request, 3139 .set_channels = hclgevf_set_channels, 3140 .get_channels = hclgevf_get_channels, 3141 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3142 .get_regs_len = hclgevf_get_regs_len, 3143 .get_regs = hclgevf_get_regs, 3144 .get_status = hclgevf_get_status, 3145 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3146 .get_media_type = hclgevf_get_media_type, 3147 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3148 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3149 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3150 .set_gro_en = hclgevf_gro_en, 3151 .set_mtu = hclgevf_set_mtu, 3152 .get_global_queue_id = hclgevf_get_qid_global, 3153 .set_timer_task = hclgevf_set_timer_task, 3154 .get_link_mode = hclgevf_get_link_mode, 3155 }; 3156 3157 static struct hnae3_ae_algo ae_algovf = { 3158 .ops = &hclgevf_ops, 3159 .pdev_id_table = ae_algovf_pci_tbl, 3160 }; 3161 3162 static int hclgevf_init(void) 3163 { 3164 pr_info("%s is initializing\n", HCLGEVF_NAME); 3165 3166 hnae3_register_ae_algo(&ae_algovf); 3167 3168 return 0; 3169 } 3170 3171 static void hclgevf_exit(void) 3172 { 3173 hnae3_unregister_ae_algo(&ae_algovf); 3174 } 3175 module_init(hclgevf_init); 3176 module_exit(hclgevf_exit); 3177 3178 MODULE_LICENSE("GPL"); 3179 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3180 MODULE_DESCRIPTION("HCLGEVF Driver"); 3181 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3182