1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_IF_H 8 #define HINIC_HW_IF_H 9 10 #include <linux/pci.h> 11 #include <linux/io.h> 12 #include <linux/types.h> 13 #include <asm/byteorder.h> 14 15 #define HINIC_DMA_ATTR_ST_SHIFT 0 16 #define HINIC_DMA_ATTR_AT_SHIFT 8 17 #define HINIC_DMA_ATTR_PH_SHIFT 10 18 #define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12 19 #define HINIC_DMA_ATTR_TPH_EN_SHIFT 13 20 21 #define HINIC_DMA_ATTR_ST_MASK 0xFF 22 #define HINIC_DMA_ATTR_AT_MASK 0x3 23 #define HINIC_DMA_ATTR_PH_MASK 0x3 24 #define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1 25 #define HINIC_DMA_ATTR_TPH_EN_MASK 0x1 26 27 #define HINIC_DMA_ATTR_SET(val, member) \ 28 (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \ 29 HINIC_DMA_ATTR_##member##_SHIFT) 30 31 #define HINIC_DMA_ATTR_CLEAR(val, member) \ 32 ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \ 33 << HINIC_DMA_ATTR_##member##_SHIFT))) 34 35 #define HINIC_FA0_FUNC_IDX_SHIFT 0 36 #define HINIC_FA0_PF_IDX_SHIFT 10 37 #define HINIC_FA0_PCI_INTF_IDX_SHIFT 14 38 /* reserved members - off 16 */ 39 #define HINIC_FA0_FUNC_TYPE_SHIFT 24 40 41 #define HINIC_FA0_FUNC_IDX_MASK 0x3FF 42 #define HINIC_FA0_PF_IDX_MASK 0xF 43 #define HINIC_FA0_PCI_INTF_IDX_MASK 0x3 44 #define HINIC_FA0_FUNC_TYPE_MASK 0x1 45 46 #define HINIC_FA0_GET(val, member) \ 47 (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK) 48 49 #define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8 50 /* reserved members - off 10 */ 51 #define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12 52 /* reserved members - off 15 */ 53 #define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20 54 #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24 55 /* reserved members - off 27 */ 56 #define HINIC_FA1_INIT_STATUS_SHIFT 30 57 58 #define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3 59 #define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7 60 #define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF 61 #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7 62 #define HINIC_FA1_INIT_STATUS_MASK 0x1 63 64 #define HINIC_FA1_GET(val, member) \ 65 (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK) 66 67 #define HINIC_FA4_OUTBOUND_STATE_SHIFT 0 68 #define HINIC_FA4_DB_STATE_SHIFT 1 69 70 #define HINIC_FA4_OUTBOUND_STATE_MASK 0x1 71 #define HINIC_FA4_DB_STATE_MASK 0x1 72 73 #define HINIC_FA4_GET(val, member) \ 74 (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK) 75 76 #define HINIC_FA4_SET(val, member) \ 77 ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT) 78 79 #define HINIC_FA4_CLEAR(val, member) \ 80 ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT))) 81 82 #define HINIC_FA5_PF_ACTION_SHIFT 0 83 #define HINIC_FA5_PF_ACTION_MASK 0xFFFF 84 85 #define HINIC_FA5_SET(val, member) \ 86 (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT) 87 88 #define HINIC_FA5_CLEAR(val, member) \ 89 ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT))) 90 91 #define HINIC_PPF_ELECTION_IDX_SHIFT 0 92 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F 93 94 #define HINIC_PPF_ELECTION_SET(val, member) \ 95 (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \ 96 HINIC_PPF_ELECTION_##member##_SHIFT) 97 98 #define HINIC_PPF_ELECTION_GET(val, member) \ 99 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \ 100 HINIC_PPF_ELECTION_##member##_MASK) 101 102 #define HINIC_PPF_ELECTION_CLEAR(val, member) \ 103 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ 104 << HINIC_PPF_ELECTION_##member##_SHIFT))) 105 106 #define HINIC_MSIX_PENDING_LIMIT_SHIFT 0 107 #define HINIC_MSIX_COALESC_TIMER_SHIFT 8 108 #define HINIC_MSIX_LLI_TIMER_SHIFT 16 109 #define HINIC_MSIX_LLI_CREDIT_SHIFT 24 110 #define HINIC_MSIX_RESEND_TIMER_SHIFT 29 111 112 #define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF 113 #define HINIC_MSIX_COALESC_TIMER_MASK 0xFF 114 #define HINIC_MSIX_LLI_TIMER_MASK 0xFF 115 #define HINIC_MSIX_LLI_CREDIT_MASK 0x1F 116 #define HINIC_MSIX_RESEND_TIMER_MASK 0x7 117 118 #define HINIC_MSIX_ATTR_SET(val, member) \ 119 (((u32)(val) & HINIC_MSIX_##member##_MASK) << \ 120 HINIC_MSIX_##member##_SHIFT) 121 122 #define HINIC_MSIX_ATTR_GET(val, member) \ 123 (((val) >> HINIC_MSIX_##member##_SHIFT) & \ 124 HINIC_MSIX_##member##_MASK) 125 126 #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29 127 128 #define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1 129 130 #define HINIC_MSIX_CNT_SET(val, member) \ 131 (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \ 132 HINIC_MSIX_CNT_##member##_SHIFT) 133 134 #define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs) 135 #define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs) 136 #define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs) 137 #define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx) 138 #define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx) 139 #define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx) 140 141 #define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type) 142 #define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF) 143 #define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF) 144 145 #define HINIC_PCI_CFG_REGS_BAR 0 146 #define HINIC_PCI_INTR_REGS_BAR 2 147 #define HINIC_PCI_DB_BAR 4 148 149 #define HINIC_PCIE_ST_DISABLE 0 150 #define HINIC_PCIE_AT_DISABLE 0 151 #define HINIC_PCIE_PH_DISABLE 0 152 153 #define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */ 154 #define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */ 155 #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */ 156 #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */ 157 #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */ 158 159 #define HINIC_PCI_MSIX_ENTRY_SIZE 16 160 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12 161 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1 162 163 enum hinic_pcie_nosnoop { 164 HINIC_PCIE_SNOOP = 0, 165 HINIC_PCIE_NO_SNOOP = 1, 166 }; 167 168 enum hinic_pcie_tph { 169 HINIC_PCIE_TPH_DISABLE = 0, 170 HINIC_PCIE_TPH_ENABLE = 1, 171 }; 172 173 enum hinic_func_type { 174 HINIC_PF = 0, 175 HINIC_PPF = 2, 176 }; 177 178 enum hinic_mod_type { 179 HINIC_MOD_COMM = 0, /* HW communication module */ 180 HINIC_MOD_L2NIC = 1, /* L2NIC module */ 181 HINIC_MOD_CFGM = 7, /* Configuration module */ 182 183 HINIC_MOD_MAX = 15 184 }; 185 186 enum hinic_node_id { 187 HINIC_NODE_ID_MGMT = 21, 188 }; 189 190 enum hinic_pf_action { 191 HINIC_PF_MGMT_INIT = 0x0, 192 193 HINIC_PF_MGMT_ACTIVE = 0x11, 194 }; 195 196 enum hinic_outbound_state { 197 HINIC_OUTBOUND_ENABLE = 0, 198 HINIC_OUTBOUND_DISABLE = 1, 199 }; 200 201 enum hinic_db_state { 202 HINIC_DB_ENABLE = 0, 203 HINIC_DB_DISABLE = 1, 204 }; 205 206 enum hinic_msix_state { 207 HINIC_MSIX_ENABLE, 208 HINIC_MSIX_DISABLE, 209 }; 210 211 struct hinic_func_attr { 212 u16 func_idx; 213 u8 pf_idx; 214 u8 pci_intf_idx; 215 216 enum hinic_func_type func_type; 217 218 u8 ppf_idx; 219 220 u16 num_irqs; 221 u8 num_aeqs; 222 u8 num_ceqs; 223 224 u8 num_dma_attr; 225 }; 226 227 struct hinic_hwif { 228 struct pci_dev *pdev; 229 void __iomem *cfg_regs_bar; 230 void __iomem *intr_regs_base; 231 232 struct hinic_func_attr attr; 233 }; 234 235 static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg) 236 { 237 return be32_to_cpu(readl(hwif->cfg_regs_bar + reg)); 238 } 239 240 static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, 241 u32 val) 242 { 243 writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg); 244 } 245 246 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 247 u8 pending_limit, u8 coalesc_timer, 248 u8 lli_timer_cfg, u8 lli_credit_limit, 249 u8 resend_timer); 250 251 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 252 u8 *pending_limit, u8 *coalesc_timer_cfg, 253 u8 *lli_timer, u8 *lli_credit_limit, 254 u8 *resend_timer); 255 256 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 257 enum hinic_msix_state flag); 258 259 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index); 260 261 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action); 262 263 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif); 264 265 void hinic_outbound_state_set(struct hinic_hwif *hwif, 266 enum hinic_outbound_state outbound_state); 267 268 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif); 269 270 void hinic_db_state_set(struct hinic_hwif *hwif, 271 enum hinic_db_state db_state); 272 273 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev); 274 275 void hinic_free_hwif(struct hinic_hwif *hwif); 276 277 #endif 278