1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 #include <linux/suspend.h> 29 30 #include "e1000.h" 31 32 char e1000e_driver_name[] = "e1000e"; 33 34 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 35 static int debug = -1; 36 module_param(debug, int, 0); 37 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 38 39 static const struct e1000_info *e1000_info_tbl[] = { 40 [board_82571] = &e1000_82571_info, 41 [board_82572] = &e1000_82572_info, 42 [board_82573] = &e1000_82573_info, 43 [board_82574] = &e1000_82574_info, 44 [board_82583] = &e1000_82583_info, 45 [board_80003es2lan] = &e1000_es2_info, 46 [board_ich8lan] = &e1000_ich8_info, 47 [board_ich9lan] = &e1000_ich9_info, 48 [board_ich10lan] = &e1000_ich10_info, 49 [board_pchlan] = &e1000_pch_info, 50 [board_pch2lan] = &e1000_pch2_info, 51 [board_pch_lpt] = &e1000_pch_lpt_info, 52 [board_pch_spt] = &e1000_pch_spt_info, 53 [board_pch_cnp] = &e1000_pch_cnp_info, 54 [board_pch_tgp] = &e1000_pch_tgp_info, 55 [board_pch_adp] = &e1000_pch_adp_info, 56 }; 57 58 struct e1000_reg_info { 59 u32 ofs; 60 char *name; 61 }; 62 63 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 64 /* General Registers */ 65 {E1000_CTRL, "CTRL"}, 66 {E1000_STATUS, "STATUS"}, 67 {E1000_CTRL_EXT, "CTRL_EXT"}, 68 69 /* Interrupt Registers */ 70 {E1000_ICR, "ICR"}, 71 72 /* Rx Registers */ 73 {E1000_RCTL, "RCTL"}, 74 {E1000_RDLEN(0), "RDLEN"}, 75 {E1000_RDH(0), "RDH"}, 76 {E1000_RDT(0), "RDT"}, 77 {E1000_RDTR, "RDTR"}, 78 {E1000_RXDCTL(0), "RXDCTL"}, 79 {E1000_ERT, "ERT"}, 80 {E1000_RDBAL(0), "RDBAL"}, 81 {E1000_RDBAH(0), "RDBAH"}, 82 {E1000_RDFH, "RDFH"}, 83 {E1000_RDFT, "RDFT"}, 84 {E1000_RDFHS, "RDFHS"}, 85 {E1000_RDFTS, "RDFTS"}, 86 {E1000_RDFPC, "RDFPC"}, 87 88 /* Tx Registers */ 89 {E1000_TCTL, "TCTL"}, 90 {E1000_TDBAL(0), "TDBAL"}, 91 {E1000_TDBAH(0), "TDBAH"}, 92 {E1000_TDLEN(0), "TDLEN"}, 93 {E1000_TDH(0), "TDH"}, 94 {E1000_TDT(0), "TDT"}, 95 {E1000_TIDV, "TIDV"}, 96 {E1000_TXDCTL(0), "TXDCTL"}, 97 {E1000_TADV, "TADV"}, 98 {E1000_TARC(0), "TARC"}, 99 {E1000_TDFH, "TDFH"}, 100 {E1000_TDFT, "TDFT"}, 101 {E1000_TDFHS, "TDFHS"}, 102 {E1000_TDFTS, "TDFTS"}, 103 {E1000_TDFPC, "TDFPC"}, 104 105 /* List Terminator */ 106 {0, NULL} 107 }; 108 109 /** 110 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 111 * @hw: pointer to the HW structure 112 * 113 * When updating the MAC CSR registers, the Manageability Engine (ME) could 114 * be accessing the registers at the same time. Normally, this is handled in 115 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 116 * accesses later than it should which could result in the register to have 117 * an incorrect value. Workaround this by checking the FWSM register which 118 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 119 * and try again a number of times. 120 **/ 121 static void __ew32_prepare(struct e1000_hw *hw) 122 { 123 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 124 125 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 126 udelay(50); 127 } 128 129 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 130 { 131 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 132 __ew32_prepare(hw); 133 134 writel(val, hw->hw_addr + reg); 135 } 136 137 /** 138 * e1000_regdump - register printout routine 139 * @hw: pointer to the HW structure 140 * @reginfo: pointer to the register info table 141 **/ 142 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 143 { 144 int n = 0; 145 char rname[16]; 146 u32 regs[8]; 147 148 switch (reginfo->ofs) { 149 case E1000_RXDCTL(0): 150 for (n = 0; n < 2; n++) 151 regs[n] = __er32(hw, E1000_RXDCTL(n)); 152 break; 153 case E1000_TXDCTL(0): 154 for (n = 0; n < 2; n++) 155 regs[n] = __er32(hw, E1000_TXDCTL(n)); 156 break; 157 case E1000_TARC(0): 158 for (n = 0; n < 2; n++) 159 regs[n] = __er32(hw, E1000_TARC(n)); 160 break; 161 default: 162 pr_info("%-15s %08x\n", 163 reginfo->name, __er32(hw, reginfo->ofs)); 164 return; 165 } 166 167 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 168 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 169 } 170 171 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 172 struct e1000_buffer *bi) 173 { 174 int i; 175 struct e1000_ps_page *ps_page; 176 177 for (i = 0; i < adapter->rx_ps_pages; i++) { 178 ps_page = &bi->ps_pages[i]; 179 180 if (ps_page->page) { 181 pr_info("packet dump for ps_page %d:\n", i); 182 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 183 16, 1, page_address(ps_page->page), 184 PAGE_SIZE, true); 185 } 186 } 187 } 188 189 /** 190 * e1000e_dump - Print registers, Tx-ring and Rx-ring 191 * @adapter: board private structure 192 **/ 193 static void e1000e_dump(struct e1000_adapter *adapter) 194 { 195 struct net_device *netdev = adapter->netdev; 196 struct e1000_hw *hw = &adapter->hw; 197 struct e1000_reg_info *reginfo; 198 struct e1000_ring *tx_ring = adapter->tx_ring; 199 struct e1000_tx_desc *tx_desc; 200 struct my_u0 { 201 __le64 a; 202 __le64 b; 203 } *u0; 204 struct e1000_buffer *buffer_info; 205 struct e1000_ring *rx_ring = adapter->rx_ring; 206 union e1000_rx_desc_packet_split *rx_desc_ps; 207 union e1000_rx_desc_extended *rx_desc; 208 struct my_u1 { 209 __le64 a; 210 __le64 b; 211 __le64 c; 212 __le64 d; 213 } *u1; 214 u32 staterr; 215 int i = 0; 216 217 if (!netif_msg_hw(adapter)) 218 return; 219 220 /* Print netdevice Info */ 221 if (netdev) { 222 dev_info(&adapter->pdev->dev, "Net device Info\n"); 223 pr_info("Device Name state trans_start\n"); 224 pr_info("%-15s %016lX %016lX\n", netdev->name, 225 netdev->state, dev_trans_start(netdev)); 226 } 227 228 /* Print Registers */ 229 dev_info(&adapter->pdev->dev, "Register Dump\n"); 230 pr_info(" Register Name Value\n"); 231 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 232 reginfo->name; reginfo++) { 233 e1000_regdump(hw, reginfo); 234 } 235 236 /* Print Tx Ring Summary */ 237 if (!netdev || !netif_running(netdev)) 238 return; 239 240 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 241 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 242 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 243 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 244 0, tx_ring->next_to_use, tx_ring->next_to_clean, 245 (unsigned long long)buffer_info->dma, 246 buffer_info->length, 247 buffer_info->next_to_watch, 248 (unsigned long long)buffer_info->time_stamp); 249 250 /* Print Tx Ring */ 251 if (!netif_msg_tx_done(adapter)) 252 goto rx_ring_summary; 253 254 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 255 256 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 257 * 258 * Legacy Transmit Descriptor 259 * +--------------------------------------------------------------+ 260 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 261 * +--------------------------------------------------------------+ 262 * 8 | Special | CSS | Status | CMD | CSO | Length | 263 * +--------------------------------------------------------------+ 264 * 63 48 47 36 35 32 31 24 23 16 15 0 265 * 266 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 267 * 63 48 47 40 39 32 31 16 15 8 7 0 268 * +----------------------------------------------------------------+ 269 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 270 * +----------------------------------------------------------------+ 271 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 272 * +----------------------------------------------------------------+ 273 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 274 * 275 * Extended Data Descriptor (DTYP=0x1) 276 * +----------------------------------------------------------------+ 277 * 0 | Buffer Address [63:0] | 278 * +----------------------------------------------------------------+ 279 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 280 * +----------------------------------------------------------------+ 281 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 282 */ 283 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 284 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 285 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 286 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 287 const char *next_desc; 288 tx_desc = E1000_TX_DESC(*tx_ring, i); 289 buffer_info = &tx_ring->buffer_info[i]; 290 u0 = (struct my_u0 *)tx_desc; 291 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 292 next_desc = " NTC/U"; 293 else if (i == tx_ring->next_to_use) 294 next_desc = " NTU"; 295 else if (i == tx_ring->next_to_clean) 296 next_desc = " NTC"; 297 else 298 next_desc = ""; 299 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 300 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 301 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 302 i, 303 (unsigned long long)le64_to_cpu(u0->a), 304 (unsigned long long)le64_to_cpu(u0->b), 305 (unsigned long long)buffer_info->dma, 306 buffer_info->length, buffer_info->next_to_watch, 307 (unsigned long long)buffer_info->time_stamp, 308 buffer_info->skb, next_desc); 309 310 if (netif_msg_pktdata(adapter) && buffer_info->skb) 311 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 312 16, 1, buffer_info->skb->data, 313 buffer_info->skb->len, true); 314 } 315 316 /* Print Rx Ring Summary */ 317 rx_ring_summary: 318 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 319 pr_info("Queue [NTU] [NTC]\n"); 320 pr_info(" %5d %5X %5X\n", 321 0, rx_ring->next_to_use, rx_ring->next_to_clean); 322 323 /* Print Rx Ring */ 324 if (!netif_msg_rx_status(adapter)) 325 return; 326 327 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 328 switch (adapter->rx_ps_pages) { 329 case 1: 330 case 2: 331 case 3: 332 /* [Extended] Packet Split Receive Descriptor Format 333 * 334 * +-----------------------------------------------------+ 335 * 0 | Buffer Address 0 [63:0] | 336 * +-----------------------------------------------------+ 337 * 8 | Buffer Address 1 [63:0] | 338 * +-----------------------------------------------------+ 339 * 16 | Buffer Address 2 [63:0] | 340 * +-----------------------------------------------------+ 341 * 24 | Buffer Address 3 [63:0] | 342 * +-----------------------------------------------------+ 343 */ 344 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 345 /* [Extended] Receive Descriptor (Write-Back) Format 346 * 347 * 63 48 47 32 31 13 12 8 7 4 3 0 348 * +------------------------------------------------------+ 349 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 350 * | Checksum | Ident | | Queue | | Type | 351 * +------------------------------------------------------+ 352 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 353 * +------------------------------------------------------+ 354 * 63 48 47 32 31 20 19 0 355 */ 356 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 357 for (i = 0; i < rx_ring->count; i++) { 358 const char *next_desc; 359 buffer_info = &rx_ring->buffer_info[i]; 360 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 361 u1 = (struct my_u1 *)rx_desc_ps; 362 staterr = 363 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 364 365 if (i == rx_ring->next_to_use) 366 next_desc = " NTU"; 367 else if (i == rx_ring->next_to_clean) 368 next_desc = " NTC"; 369 else 370 next_desc = ""; 371 372 if (staterr & E1000_RXD_STAT_DD) { 373 /* Descriptor Done */ 374 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 375 "RWB", i, 376 (unsigned long long)le64_to_cpu(u1->a), 377 (unsigned long long)le64_to_cpu(u1->b), 378 (unsigned long long)le64_to_cpu(u1->c), 379 (unsigned long long)le64_to_cpu(u1->d), 380 buffer_info->skb, next_desc); 381 } else { 382 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 383 "R ", i, 384 (unsigned long long)le64_to_cpu(u1->a), 385 (unsigned long long)le64_to_cpu(u1->b), 386 (unsigned long long)le64_to_cpu(u1->c), 387 (unsigned long long)le64_to_cpu(u1->d), 388 (unsigned long long)buffer_info->dma, 389 buffer_info->skb, next_desc); 390 391 if (netif_msg_pktdata(adapter)) 392 e1000e_dump_ps_pages(adapter, 393 buffer_info); 394 } 395 } 396 break; 397 default: 398 case 0: 399 /* Extended Receive Descriptor (Read) Format 400 * 401 * +-----------------------------------------------------+ 402 * 0 | Buffer Address [63:0] | 403 * +-----------------------------------------------------+ 404 * 8 | Reserved | 405 * +-----------------------------------------------------+ 406 */ 407 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 408 /* Extended Receive Descriptor (Write-Back) Format 409 * 410 * 63 48 47 32 31 24 23 4 3 0 411 * +------------------------------------------------------+ 412 * | RSS Hash | | | | 413 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 414 * | Packet | IP | | | Type | 415 * | Checksum | Ident | | | | 416 * +------------------------------------------------------+ 417 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 418 * +------------------------------------------------------+ 419 * 63 48 47 32 31 20 19 0 420 */ 421 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 422 423 for (i = 0; i < rx_ring->count; i++) { 424 const char *next_desc; 425 426 buffer_info = &rx_ring->buffer_info[i]; 427 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 428 u1 = (struct my_u1 *)rx_desc; 429 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 430 431 if (i == rx_ring->next_to_use) 432 next_desc = " NTU"; 433 else if (i == rx_ring->next_to_clean) 434 next_desc = " NTC"; 435 else 436 next_desc = ""; 437 438 if (staterr & E1000_RXD_STAT_DD) { 439 /* Descriptor Done */ 440 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 441 "RWB", i, 442 (unsigned long long)le64_to_cpu(u1->a), 443 (unsigned long long)le64_to_cpu(u1->b), 444 buffer_info->skb, next_desc); 445 } else { 446 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 447 "R ", i, 448 (unsigned long long)le64_to_cpu(u1->a), 449 (unsigned long long)le64_to_cpu(u1->b), 450 (unsigned long long)buffer_info->dma, 451 buffer_info->skb, next_desc); 452 453 if (netif_msg_pktdata(adapter) && 454 buffer_info->skb) 455 print_hex_dump(KERN_INFO, "", 456 DUMP_PREFIX_ADDRESS, 16, 457 1, 458 buffer_info->skb->data, 459 adapter->rx_buffer_len, 460 true); 461 } 462 } 463 } 464 } 465 466 /** 467 * e1000_desc_unused - calculate if we have unused descriptors 468 * @ring: pointer to ring struct to perform calculation on 469 **/ 470 static int e1000_desc_unused(struct e1000_ring *ring) 471 { 472 if (ring->next_to_clean > ring->next_to_use) 473 return ring->next_to_clean - ring->next_to_use - 1; 474 475 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 476 } 477 478 /** 479 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 480 * @adapter: board private structure 481 * @hwtstamps: time stamp structure to update 482 * @systim: unsigned 64bit system time value. 483 * 484 * Convert the system time value stored in the RX/TXSTMP registers into a 485 * hwtstamp which can be used by the upper level time stamping functions. 486 * 487 * The 'systim_lock' spinlock is used to protect the consistency of the 488 * system time value. This is needed because reading the 64 bit time 489 * value involves reading two 32 bit registers. The first read latches the 490 * value. 491 **/ 492 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 493 struct skb_shared_hwtstamps *hwtstamps, 494 u64 systim) 495 { 496 u64 ns; 497 unsigned long flags; 498 499 spin_lock_irqsave(&adapter->systim_lock, flags); 500 ns = timecounter_cyc2time(&adapter->tc, systim); 501 spin_unlock_irqrestore(&adapter->systim_lock, flags); 502 503 memset(hwtstamps, 0, sizeof(*hwtstamps)); 504 hwtstamps->hwtstamp = ns_to_ktime(ns); 505 } 506 507 /** 508 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 509 * @adapter: board private structure 510 * @status: descriptor extended error and status field 511 * @skb: particular skb to include time stamp 512 * 513 * If the time stamp is valid, convert it into the timecounter ns value 514 * and store that result into the shhwtstamps structure which is passed 515 * up the network stack. 516 **/ 517 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 518 struct sk_buff *skb) 519 { 520 struct e1000_hw *hw = &adapter->hw; 521 u64 rxstmp; 522 523 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 524 !(status & E1000_RXDEXT_STATERR_TST) || 525 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 526 return; 527 528 /* The Rx time stamp registers contain the time stamp. No other 529 * received packet will be time stamped until the Rx time stamp 530 * registers are read. Because only one packet can be time stamped 531 * at a time, the register values must belong to this packet and 532 * therefore none of the other additional attributes need to be 533 * compared. 534 */ 535 rxstmp = (u64)er32(RXSTMPL); 536 rxstmp |= (u64)er32(RXSTMPH) << 32; 537 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 538 539 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 540 } 541 542 /** 543 * e1000_receive_skb - helper function to handle Rx indications 544 * @adapter: board private structure 545 * @netdev: pointer to netdev struct 546 * @staterr: descriptor extended error and status field as written by hardware 547 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 548 * @skb: pointer to sk_buff to be indicated to stack 549 **/ 550 static void e1000_receive_skb(struct e1000_adapter *adapter, 551 struct net_device *netdev, struct sk_buff *skb, 552 u32 staterr, __le16 vlan) 553 { 554 u16 tag = le16_to_cpu(vlan); 555 556 e1000e_rx_hwtstamp(adapter, staterr, skb); 557 558 skb->protocol = eth_type_trans(skb, netdev); 559 560 if (staterr & E1000_RXD_STAT_VP) 561 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 562 563 napi_gro_receive(&adapter->napi, skb); 564 } 565 566 /** 567 * e1000_rx_checksum - Receive Checksum Offload 568 * @adapter: board private structure 569 * @status_err: receive descriptor status and error fields 570 * @skb: socket buffer with received data 571 **/ 572 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 573 struct sk_buff *skb) 574 { 575 u16 status = (u16)status_err; 576 u8 errors = (u8)(status_err >> 24); 577 578 skb_checksum_none_assert(skb); 579 580 /* Rx checksum disabled */ 581 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 582 return; 583 584 /* Ignore Checksum bit is set */ 585 if (status & E1000_RXD_STAT_IXSM) 586 return; 587 588 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 589 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 590 /* let the stack verify checksum errors */ 591 adapter->hw_csum_err++; 592 return; 593 } 594 595 /* TCP/UDP Checksum has not been calculated */ 596 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 597 return; 598 599 /* It must be a TCP or UDP packet with a valid checksum */ 600 skb->ip_summed = CHECKSUM_UNNECESSARY; 601 adapter->hw_csum_good++; 602 } 603 604 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 605 { 606 struct e1000_adapter *adapter = rx_ring->adapter; 607 struct e1000_hw *hw = &adapter->hw; 608 609 __ew32_prepare(hw); 610 writel(i, rx_ring->tail); 611 612 if (unlikely(i != readl(rx_ring->tail))) { 613 u32 rctl = er32(RCTL); 614 615 ew32(RCTL, rctl & ~E1000_RCTL_EN); 616 e_err("ME firmware caused invalid RDT - resetting\n"); 617 schedule_work(&adapter->reset_task); 618 } 619 } 620 621 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 622 { 623 struct e1000_adapter *adapter = tx_ring->adapter; 624 struct e1000_hw *hw = &adapter->hw; 625 626 __ew32_prepare(hw); 627 writel(i, tx_ring->tail); 628 629 if (unlikely(i != readl(tx_ring->tail))) { 630 u32 tctl = er32(TCTL); 631 632 ew32(TCTL, tctl & ~E1000_TCTL_EN); 633 e_err("ME firmware caused invalid TDT - resetting\n"); 634 schedule_work(&adapter->reset_task); 635 } 636 } 637 638 /** 639 * e1000_alloc_rx_buffers - Replace used receive buffers 640 * @rx_ring: Rx descriptor ring 641 * @cleaned_count: number to reallocate 642 * @gfp: flags for allocation 643 **/ 644 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 645 int cleaned_count, gfp_t gfp) 646 { 647 struct e1000_adapter *adapter = rx_ring->adapter; 648 struct net_device *netdev = adapter->netdev; 649 struct pci_dev *pdev = adapter->pdev; 650 union e1000_rx_desc_extended *rx_desc; 651 struct e1000_buffer *buffer_info; 652 struct sk_buff *skb; 653 unsigned int i; 654 unsigned int bufsz = adapter->rx_buffer_len; 655 656 i = rx_ring->next_to_use; 657 buffer_info = &rx_ring->buffer_info[i]; 658 659 while (cleaned_count--) { 660 skb = buffer_info->skb; 661 if (skb) { 662 skb_trim(skb, 0); 663 goto map_skb; 664 } 665 666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 667 if (!skb) { 668 /* Better luck next round */ 669 adapter->alloc_rx_buff_failed++; 670 break; 671 } 672 673 buffer_info->skb = skb; 674 map_skb: 675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 676 adapter->rx_buffer_len, 677 DMA_FROM_DEVICE); 678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 679 dev_err(&pdev->dev, "Rx DMA map failed\n"); 680 adapter->rx_dma_failed++; 681 break; 682 } 683 684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 686 687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 688 /* Force memory writes to complete before letting h/w 689 * know there are new descriptors to fetch. (Only 690 * applicable for weak-ordered memory model archs, 691 * such as IA-64). 692 */ 693 wmb(); 694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 695 e1000e_update_rdt_wa(rx_ring, i); 696 else 697 writel(i, rx_ring->tail); 698 } 699 i++; 700 if (i == rx_ring->count) 701 i = 0; 702 buffer_info = &rx_ring->buffer_info[i]; 703 } 704 705 rx_ring->next_to_use = i; 706 } 707 708 /** 709 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 710 * @rx_ring: Rx descriptor ring 711 * @cleaned_count: number to reallocate 712 * @gfp: flags for allocation 713 **/ 714 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 715 int cleaned_count, gfp_t gfp) 716 { 717 struct e1000_adapter *adapter = rx_ring->adapter; 718 struct net_device *netdev = adapter->netdev; 719 struct pci_dev *pdev = adapter->pdev; 720 union e1000_rx_desc_packet_split *rx_desc; 721 struct e1000_buffer *buffer_info; 722 struct e1000_ps_page *ps_page; 723 struct sk_buff *skb; 724 unsigned int i, j; 725 726 i = rx_ring->next_to_use; 727 buffer_info = &rx_ring->buffer_info[i]; 728 729 while (cleaned_count--) { 730 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 731 732 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 733 ps_page = &buffer_info->ps_pages[j]; 734 if (j >= adapter->rx_ps_pages) { 735 /* all unused desc entries get hw null ptr */ 736 rx_desc->read.buffer_addr[j + 1] = 737 ~cpu_to_le64(0); 738 continue; 739 } 740 if (!ps_page->page) { 741 ps_page->page = alloc_page(gfp); 742 if (!ps_page->page) { 743 adapter->alloc_rx_buff_failed++; 744 goto no_buffers; 745 } 746 ps_page->dma = dma_map_page(&pdev->dev, 747 ps_page->page, 748 0, PAGE_SIZE, 749 DMA_FROM_DEVICE); 750 if (dma_mapping_error(&pdev->dev, 751 ps_page->dma)) { 752 dev_err(&adapter->pdev->dev, 753 "Rx DMA page map failed\n"); 754 adapter->rx_dma_failed++; 755 goto no_buffers; 756 } 757 } 758 /* Refresh the desc even if buffer_addrs 759 * didn't change because each write-back 760 * erases this info. 761 */ 762 rx_desc->read.buffer_addr[j + 1] = 763 cpu_to_le64(ps_page->dma); 764 } 765 766 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 767 gfp); 768 769 if (!skb) { 770 adapter->alloc_rx_buff_failed++; 771 break; 772 } 773 774 buffer_info->skb = skb; 775 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 776 adapter->rx_ps_bsize0, 777 DMA_FROM_DEVICE); 778 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 779 dev_err(&pdev->dev, "Rx DMA map failed\n"); 780 adapter->rx_dma_failed++; 781 /* cleanup skb */ 782 dev_kfree_skb_any(skb); 783 buffer_info->skb = NULL; 784 break; 785 } 786 787 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 788 789 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 790 /* Force memory writes to complete before letting h/w 791 * know there are new descriptors to fetch. (Only 792 * applicable for weak-ordered memory model archs, 793 * such as IA-64). 794 */ 795 wmb(); 796 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 797 e1000e_update_rdt_wa(rx_ring, i << 1); 798 else 799 writel(i << 1, rx_ring->tail); 800 } 801 802 i++; 803 if (i == rx_ring->count) 804 i = 0; 805 buffer_info = &rx_ring->buffer_info[i]; 806 } 807 808 no_buffers: 809 rx_ring->next_to_use = i; 810 } 811 812 /** 813 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 814 * @rx_ring: Rx descriptor ring 815 * @cleaned_count: number of buffers to allocate this pass 816 * @gfp: flags for allocation 817 **/ 818 819 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 820 int cleaned_count, gfp_t gfp) 821 { 822 struct e1000_adapter *adapter = rx_ring->adapter; 823 struct net_device *netdev = adapter->netdev; 824 struct pci_dev *pdev = adapter->pdev; 825 union e1000_rx_desc_extended *rx_desc; 826 struct e1000_buffer *buffer_info; 827 struct sk_buff *skb; 828 unsigned int i; 829 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 830 831 i = rx_ring->next_to_use; 832 buffer_info = &rx_ring->buffer_info[i]; 833 834 while (cleaned_count--) { 835 skb = buffer_info->skb; 836 if (skb) { 837 skb_trim(skb, 0); 838 goto check_page; 839 } 840 841 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 842 if (unlikely(!skb)) { 843 /* Better luck next round */ 844 adapter->alloc_rx_buff_failed++; 845 break; 846 } 847 848 buffer_info->skb = skb; 849 check_page: 850 /* allocate a new page if necessary */ 851 if (!buffer_info->page) { 852 buffer_info->page = alloc_page(gfp); 853 if (unlikely(!buffer_info->page)) { 854 adapter->alloc_rx_buff_failed++; 855 break; 856 } 857 } 858 859 if (!buffer_info->dma) { 860 buffer_info->dma = dma_map_page(&pdev->dev, 861 buffer_info->page, 0, 862 PAGE_SIZE, 863 DMA_FROM_DEVICE); 864 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 865 adapter->alloc_rx_buff_failed++; 866 break; 867 } 868 } 869 870 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 871 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 872 873 if (unlikely(++i == rx_ring->count)) 874 i = 0; 875 buffer_info = &rx_ring->buffer_info[i]; 876 } 877 878 if (likely(rx_ring->next_to_use != i)) { 879 rx_ring->next_to_use = i; 880 if (unlikely(i-- == 0)) 881 i = (rx_ring->count - 1); 882 883 /* Force memory writes to complete before letting h/w 884 * know there are new descriptors to fetch. (Only 885 * applicable for weak-ordered memory model archs, 886 * such as IA-64). 887 */ 888 wmb(); 889 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 890 e1000e_update_rdt_wa(rx_ring, i); 891 else 892 writel(i, rx_ring->tail); 893 } 894 } 895 896 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 897 struct sk_buff *skb) 898 { 899 if (netdev->features & NETIF_F_RXHASH) 900 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 901 } 902 903 /** 904 * e1000_clean_rx_irq - Send received data up the network stack 905 * @rx_ring: Rx descriptor ring 906 * @work_done: output parameter for indicating completed work 907 * @work_to_do: how many packets we can clean 908 * 909 * the return value indicates whether actual cleaning was done, there 910 * is no guarantee that everything was cleaned 911 **/ 912 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 913 int work_to_do) 914 { 915 struct e1000_adapter *adapter = rx_ring->adapter; 916 struct net_device *netdev = adapter->netdev; 917 struct pci_dev *pdev = adapter->pdev; 918 struct e1000_hw *hw = &adapter->hw; 919 union e1000_rx_desc_extended *rx_desc, *next_rxd; 920 struct e1000_buffer *buffer_info, *next_buffer; 921 u32 length, staterr; 922 unsigned int i; 923 int cleaned_count = 0; 924 bool cleaned = false; 925 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 926 927 i = rx_ring->next_to_clean; 928 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 929 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 930 buffer_info = &rx_ring->buffer_info[i]; 931 932 while (staterr & E1000_RXD_STAT_DD) { 933 struct sk_buff *skb; 934 935 if (*work_done >= work_to_do) 936 break; 937 (*work_done)++; 938 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 939 940 skb = buffer_info->skb; 941 buffer_info->skb = NULL; 942 943 prefetch(skb->data - NET_IP_ALIGN); 944 945 i++; 946 if (i == rx_ring->count) 947 i = 0; 948 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 949 prefetch(next_rxd); 950 951 next_buffer = &rx_ring->buffer_info[i]; 952 953 cleaned = true; 954 cleaned_count++; 955 dma_unmap_single(&pdev->dev, buffer_info->dma, 956 adapter->rx_buffer_len, DMA_FROM_DEVICE); 957 buffer_info->dma = 0; 958 959 length = le16_to_cpu(rx_desc->wb.upper.length); 960 961 /* !EOP means multiple descriptors were used to store a single 962 * packet, if that's the case we need to toss it. In fact, we 963 * need to toss every packet with the EOP bit clear and the 964 * next frame that _does_ have the EOP bit set, as it is by 965 * definition only a frame fragment 966 */ 967 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 968 adapter->flags2 |= FLAG2_IS_DISCARDING; 969 970 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 971 /* All receives must fit into a single buffer */ 972 e_dbg("Receive packet consumed multiple buffers\n"); 973 /* recycle */ 974 buffer_info->skb = skb; 975 if (staterr & E1000_RXD_STAT_EOP) 976 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 977 goto next_desc; 978 } 979 980 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 981 !(netdev->features & NETIF_F_RXALL))) { 982 /* recycle */ 983 buffer_info->skb = skb; 984 goto next_desc; 985 } 986 987 /* adjust length to remove Ethernet CRC */ 988 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 989 /* If configured to store CRC, don't subtract FCS, 990 * but keep the FCS bytes out of the total_rx_bytes 991 * counter 992 */ 993 if (netdev->features & NETIF_F_RXFCS) 994 total_rx_bytes -= 4; 995 else 996 length -= 4; 997 } 998 999 total_rx_bytes += length; 1000 total_rx_packets++; 1001 1002 /* code added for copybreak, this should improve 1003 * performance for small packets with large amounts 1004 * of reassembly being done in the stack 1005 */ 1006 if (length < copybreak) { 1007 struct sk_buff *new_skb = 1008 napi_alloc_skb(&adapter->napi, length); 1009 if (new_skb) { 1010 skb_copy_to_linear_data_offset(new_skb, 1011 -NET_IP_ALIGN, 1012 (skb->data - 1013 NET_IP_ALIGN), 1014 (length + 1015 NET_IP_ALIGN)); 1016 /* save the skb in buffer_info as good */ 1017 buffer_info->skb = skb; 1018 skb = new_skb; 1019 } 1020 /* else just continue with the old one */ 1021 } 1022 /* end copybreak code */ 1023 skb_put(skb, length); 1024 1025 /* Receive Checksum Offload */ 1026 e1000_rx_checksum(adapter, staterr, skb); 1027 1028 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1029 1030 e1000_receive_skb(adapter, netdev, skb, staterr, 1031 rx_desc->wb.upper.vlan); 1032 1033 next_desc: 1034 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1035 1036 /* return some buffers to hardware, one at a time is too slow */ 1037 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1038 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1039 GFP_ATOMIC); 1040 cleaned_count = 0; 1041 } 1042 1043 /* use prefetched values */ 1044 rx_desc = next_rxd; 1045 buffer_info = next_buffer; 1046 1047 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1048 } 1049 rx_ring->next_to_clean = i; 1050 1051 cleaned_count = e1000_desc_unused(rx_ring); 1052 if (cleaned_count) 1053 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1054 1055 adapter->total_rx_bytes += total_rx_bytes; 1056 adapter->total_rx_packets += total_rx_packets; 1057 return cleaned; 1058 } 1059 1060 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1061 struct e1000_buffer *buffer_info, 1062 bool drop) 1063 { 1064 struct e1000_adapter *adapter = tx_ring->adapter; 1065 1066 if (buffer_info->dma) { 1067 if (buffer_info->mapped_as_page) 1068 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1069 buffer_info->length, DMA_TO_DEVICE); 1070 else 1071 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1072 buffer_info->length, DMA_TO_DEVICE); 1073 buffer_info->dma = 0; 1074 } 1075 if (buffer_info->skb) { 1076 if (drop) 1077 dev_kfree_skb_any(buffer_info->skb); 1078 else 1079 dev_consume_skb_any(buffer_info->skb); 1080 buffer_info->skb = NULL; 1081 } 1082 buffer_info->time_stamp = 0; 1083 } 1084 1085 static void e1000_print_hw_hang(struct work_struct *work) 1086 { 1087 struct e1000_adapter *adapter = container_of(work, 1088 struct e1000_adapter, 1089 print_hang_task); 1090 struct net_device *netdev = adapter->netdev; 1091 struct e1000_ring *tx_ring = adapter->tx_ring; 1092 unsigned int i = tx_ring->next_to_clean; 1093 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1094 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1095 struct e1000_hw *hw = &adapter->hw; 1096 u16 phy_status, phy_1000t_status, phy_ext_status; 1097 u16 pci_status; 1098 1099 if (test_bit(__E1000_DOWN, &adapter->state)) 1100 return; 1101 1102 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1103 /* May be block on write-back, flush and detect again 1104 * flush pending descriptor writebacks to memory 1105 */ 1106 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1107 /* execute the writes immediately */ 1108 e1e_flush(); 1109 /* Due to rare timing issues, write to TIDV again to ensure 1110 * the write is successful 1111 */ 1112 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1113 /* execute the writes immediately */ 1114 e1e_flush(); 1115 adapter->tx_hang_recheck = true; 1116 return; 1117 } 1118 adapter->tx_hang_recheck = false; 1119 1120 if (er32(TDH(0)) == er32(TDT(0))) { 1121 e_dbg("false hang detected, ignoring\n"); 1122 return; 1123 } 1124 1125 /* Real hang detected */ 1126 netif_stop_queue(netdev); 1127 1128 e1e_rphy(hw, MII_BMSR, &phy_status); 1129 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1130 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1131 1132 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1133 1134 /* detected Hardware unit hang */ 1135 e_err("Detected Hardware Unit Hang:\n" 1136 " TDH <%x>\n" 1137 " TDT <%x>\n" 1138 " next_to_use <%x>\n" 1139 " next_to_clean <%x>\n" 1140 "buffer_info[next_to_clean]:\n" 1141 " time_stamp <%lx>\n" 1142 " next_to_watch <%x>\n" 1143 " jiffies <%lx>\n" 1144 " next_to_watch.status <%x>\n" 1145 "MAC Status <%x>\n" 1146 "PHY Status <%x>\n" 1147 "PHY 1000BASE-T Status <%x>\n" 1148 "PHY Extended Status <%x>\n" 1149 "PCI Status <%x>\n", 1150 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1151 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1152 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1153 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1154 1155 e1000e_dump(adapter); 1156 1157 /* Suggest workaround for known h/w issue */ 1158 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1159 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1160 } 1161 1162 /** 1163 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1164 * @work: pointer to work struct 1165 * 1166 * This work function polls the TSYNCTXCTL valid bit to determine when a 1167 * timestamp has been taken for the current stored skb. The timestamp must 1168 * be for this skb because only one such packet is allowed in the queue. 1169 */ 1170 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1171 { 1172 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1173 tx_hwtstamp_work); 1174 struct e1000_hw *hw = &adapter->hw; 1175 1176 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1177 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1178 struct skb_shared_hwtstamps shhwtstamps; 1179 u64 txstmp; 1180 1181 txstmp = er32(TXSTMPL); 1182 txstmp |= (u64)er32(TXSTMPH) << 32; 1183 1184 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1185 1186 /* Clear the global tx_hwtstamp_skb pointer and force writes 1187 * prior to notifying the stack of a Tx timestamp. 1188 */ 1189 adapter->tx_hwtstamp_skb = NULL; 1190 wmb(); /* force write prior to skb_tstamp_tx */ 1191 1192 skb_tstamp_tx(skb, &shhwtstamps); 1193 dev_consume_skb_any(skb); 1194 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1195 + adapter->tx_timeout_factor * HZ)) { 1196 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1197 adapter->tx_hwtstamp_skb = NULL; 1198 adapter->tx_hwtstamp_timeouts++; 1199 e_warn("clearing Tx timestamp hang\n"); 1200 } else { 1201 /* reschedule to check later */ 1202 schedule_work(&adapter->tx_hwtstamp_work); 1203 } 1204 } 1205 1206 /** 1207 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1208 * @tx_ring: Tx descriptor ring 1209 * 1210 * the return value indicates whether actual cleaning was done, there 1211 * is no guarantee that everything was cleaned 1212 **/ 1213 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1214 { 1215 struct e1000_adapter *adapter = tx_ring->adapter; 1216 struct net_device *netdev = adapter->netdev; 1217 struct e1000_hw *hw = &adapter->hw; 1218 struct e1000_tx_desc *tx_desc, *eop_desc; 1219 struct e1000_buffer *buffer_info; 1220 unsigned int i, eop; 1221 unsigned int count = 0; 1222 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1223 unsigned int bytes_compl = 0, pkts_compl = 0; 1224 1225 i = tx_ring->next_to_clean; 1226 eop = tx_ring->buffer_info[i].next_to_watch; 1227 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1228 1229 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1230 (count < tx_ring->count)) { 1231 bool cleaned = false; 1232 1233 dma_rmb(); /* read buffer_info after eop_desc */ 1234 for (; !cleaned; count++) { 1235 tx_desc = E1000_TX_DESC(*tx_ring, i); 1236 buffer_info = &tx_ring->buffer_info[i]; 1237 cleaned = (i == eop); 1238 1239 if (cleaned) { 1240 total_tx_packets += buffer_info->segs; 1241 total_tx_bytes += buffer_info->bytecount; 1242 if (buffer_info->skb) { 1243 bytes_compl += buffer_info->skb->len; 1244 pkts_compl++; 1245 } 1246 } 1247 1248 e1000_put_txbuf(tx_ring, buffer_info, false); 1249 tx_desc->upper.data = 0; 1250 1251 i++; 1252 if (i == tx_ring->count) 1253 i = 0; 1254 } 1255 1256 if (i == tx_ring->next_to_use) 1257 break; 1258 eop = tx_ring->buffer_info[i].next_to_watch; 1259 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1260 } 1261 1262 tx_ring->next_to_clean = i; 1263 1264 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1265 1266 #define TX_WAKE_THRESHOLD 32 1267 if (count && netif_carrier_ok(netdev) && 1268 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1269 /* Make sure that anybody stopping the queue after this 1270 * sees the new next_to_clean. 1271 */ 1272 smp_mb(); 1273 1274 if (netif_queue_stopped(netdev) && 1275 !(test_bit(__E1000_DOWN, &adapter->state))) { 1276 netif_wake_queue(netdev); 1277 ++adapter->restart_queue; 1278 } 1279 } 1280 1281 if (adapter->detect_tx_hung) { 1282 /* Detect a transmit hang in hardware, this serializes the 1283 * check with the clearing of time_stamp and movement of i 1284 */ 1285 adapter->detect_tx_hung = false; 1286 if (tx_ring->buffer_info[i].time_stamp && 1287 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1288 + (adapter->tx_timeout_factor * HZ)) && 1289 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1290 schedule_work(&adapter->print_hang_task); 1291 else 1292 adapter->tx_hang_recheck = false; 1293 } 1294 adapter->total_tx_bytes += total_tx_bytes; 1295 adapter->total_tx_packets += total_tx_packets; 1296 return count < tx_ring->count; 1297 } 1298 1299 /** 1300 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1301 * @rx_ring: Rx descriptor ring 1302 * @work_done: output parameter for indicating completed work 1303 * @work_to_do: how many packets we can clean 1304 * 1305 * the return value indicates whether actual cleaning was done, there 1306 * is no guarantee that everything was cleaned 1307 **/ 1308 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1309 int work_to_do) 1310 { 1311 struct e1000_adapter *adapter = rx_ring->adapter; 1312 struct e1000_hw *hw = &adapter->hw; 1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1314 struct net_device *netdev = adapter->netdev; 1315 struct pci_dev *pdev = adapter->pdev; 1316 struct e1000_buffer *buffer_info, *next_buffer; 1317 struct e1000_ps_page *ps_page; 1318 struct sk_buff *skb; 1319 unsigned int i, j; 1320 u32 length, staterr; 1321 int cleaned_count = 0; 1322 bool cleaned = false; 1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1324 1325 i = rx_ring->next_to_clean; 1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1328 buffer_info = &rx_ring->buffer_info[i]; 1329 1330 while (staterr & E1000_RXD_STAT_DD) { 1331 if (*work_done >= work_to_do) 1332 break; 1333 (*work_done)++; 1334 skb = buffer_info->skb; 1335 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1336 1337 /* in the packet split case this is header only */ 1338 prefetch(skb->data - NET_IP_ALIGN); 1339 1340 i++; 1341 if (i == rx_ring->count) 1342 i = 0; 1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1344 prefetch(next_rxd); 1345 1346 next_buffer = &rx_ring->buffer_info[i]; 1347 1348 cleaned = true; 1349 cleaned_count++; 1350 dma_unmap_single(&pdev->dev, buffer_info->dma, 1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1352 buffer_info->dma = 0; 1353 1354 /* see !EOP comment in other Rx routine */ 1355 if (!(staterr & E1000_RXD_STAT_EOP)) 1356 adapter->flags2 |= FLAG2_IS_DISCARDING; 1357 1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1359 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1360 dev_kfree_skb_irq(skb); 1361 if (staterr & E1000_RXD_STAT_EOP) 1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1363 goto next_desc; 1364 } 1365 1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1367 !(netdev->features & NETIF_F_RXALL))) { 1368 dev_kfree_skb_irq(skb); 1369 goto next_desc; 1370 } 1371 1372 length = le16_to_cpu(rx_desc->wb.middle.length0); 1373 1374 if (!length) { 1375 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1376 dev_kfree_skb_irq(skb); 1377 goto next_desc; 1378 } 1379 1380 /* Good Receive */ 1381 skb_put(skb, length); 1382 1383 { 1384 /* this looks ugly, but it seems compiler issues make 1385 * it more efficient than reusing j 1386 */ 1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1388 1389 /* page alloc/put takes too long and effects small 1390 * packet throughput, so unsplit small packets and 1391 * save the alloc/put only valid in softirq (napi) 1392 * context to call kmap_* 1393 */ 1394 if (l1 && (l1 <= copybreak) && 1395 ((length + l1) <= adapter->rx_ps_bsize0)) { 1396 u8 *vaddr; 1397 1398 ps_page = &buffer_info->ps_pages[0]; 1399 1400 /* there is no documentation about how to call 1401 * kmap_atomic, so we can't hold the mapping 1402 * very long 1403 */ 1404 dma_sync_single_for_cpu(&pdev->dev, 1405 ps_page->dma, 1406 PAGE_SIZE, 1407 DMA_FROM_DEVICE); 1408 vaddr = kmap_atomic(ps_page->page); 1409 memcpy(skb_tail_pointer(skb), vaddr, l1); 1410 kunmap_atomic(vaddr); 1411 dma_sync_single_for_device(&pdev->dev, 1412 ps_page->dma, 1413 PAGE_SIZE, 1414 DMA_FROM_DEVICE); 1415 1416 /* remove the CRC */ 1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1418 if (!(netdev->features & NETIF_F_RXFCS)) 1419 l1 -= 4; 1420 } 1421 1422 skb_put(skb, l1); 1423 goto copydone; 1424 } /* if */ 1425 } 1426 1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1429 if (!length) 1430 break; 1431 1432 ps_page = &buffer_info->ps_pages[j]; 1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1434 DMA_FROM_DEVICE); 1435 ps_page->dma = 0; 1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1437 ps_page->page = NULL; 1438 skb->len += length; 1439 skb->data_len += length; 1440 skb->truesize += PAGE_SIZE; 1441 } 1442 1443 /* strip the ethernet crc, problem is we're using pages now so 1444 * this whole operation can get a little cpu intensive 1445 */ 1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1447 if (!(netdev->features & NETIF_F_RXFCS)) 1448 pskb_trim(skb, skb->len - 4); 1449 } 1450 1451 copydone: 1452 total_rx_bytes += skb->len; 1453 total_rx_packets++; 1454 1455 e1000_rx_checksum(adapter, staterr, skb); 1456 1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1458 1459 if (rx_desc->wb.upper.header_status & 1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1461 adapter->rx_hdr_split++; 1462 1463 e1000_receive_skb(adapter, netdev, skb, staterr, 1464 rx_desc->wb.middle.vlan); 1465 1466 next_desc: 1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1468 buffer_info->skb = NULL; 1469 1470 /* return some buffers to hardware, one at a time is too slow */ 1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1472 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1473 GFP_ATOMIC); 1474 cleaned_count = 0; 1475 } 1476 1477 /* use prefetched values */ 1478 rx_desc = next_rxd; 1479 buffer_info = next_buffer; 1480 1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1482 } 1483 rx_ring->next_to_clean = i; 1484 1485 cleaned_count = e1000_desc_unused(rx_ring); 1486 if (cleaned_count) 1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1488 1489 adapter->total_rx_bytes += total_rx_bytes; 1490 adapter->total_rx_packets += total_rx_packets; 1491 return cleaned; 1492 } 1493 1494 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1495 u16 length) 1496 { 1497 bi->page = NULL; 1498 skb->len += length; 1499 skb->data_len += length; 1500 skb->truesize += PAGE_SIZE; 1501 } 1502 1503 /** 1504 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1505 * @rx_ring: Rx descriptor ring 1506 * @work_done: output parameter for indicating completed work 1507 * @work_to_do: how many packets we can clean 1508 * 1509 * the return value indicates whether actual cleaning was done, there 1510 * is no guarantee that everything was cleaned 1511 **/ 1512 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1513 int work_to_do) 1514 { 1515 struct e1000_adapter *adapter = rx_ring->adapter; 1516 struct net_device *netdev = adapter->netdev; 1517 struct pci_dev *pdev = adapter->pdev; 1518 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1519 struct e1000_buffer *buffer_info, *next_buffer; 1520 u32 length, staterr; 1521 unsigned int i; 1522 int cleaned_count = 0; 1523 bool cleaned = false; 1524 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1525 struct skb_shared_info *shinfo; 1526 1527 i = rx_ring->next_to_clean; 1528 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1529 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1530 buffer_info = &rx_ring->buffer_info[i]; 1531 1532 while (staterr & E1000_RXD_STAT_DD) { 1533 struct sk_buff *skb; 1534 1535 if (*work_done >= work_to_do) 1536 break; 1537 (*work_done)++; 1538 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1539 1540 skb = buffer_info->skb; 1541 buffer_info->skb = NULL; 1542 1543 ++i; 1544 if (i == rx_ring->count) 1545 i = 0; 1546 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1547 prefetch(next_rxd); 1548 1549 next_buffer = &rx_ring->buffer_info[i]; 1550 1551 cleaned = true; 1552 cleaned_count++; 1553 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1554 DMA_FROM_DEVICE); 1555 buffer_info->dma = 0; 1556 1557 length = le16_to_cpu(rx_desc->wb.upper.length); 1558 1559 /* errors is only valid for DD + EOP descriptors */ 1560 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1561 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1562 !(netdev->features & NETIF_F_RXALL)))) { 1563 /* recycle both page and skb */ 1564 buffer_info->skb = skb; 1565 /* an error means any chain goes out the window too */ 1566 if (rx_ring->rx_skb_top) 1567 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1568 rx_ring->rx_skb_top = NULL; 1569 goto next_desc; 1570 } 1571 #define rxtop (rx_ring->rx_skb_top) 1572 if (!(staterr & E1000_RXD_STAT_EOP)) { 1573 /* this descriptor is only the beginning (or middle) */ 1574 if (!rxtop) { 1575 /* this is the beginning of a chain */ 1576 rxtop = skb; 1577 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1578 0, length); 1579 } else { 1580 /* this is the middle of a chain */ 1581 shinfo = skb_shinfo(rxtop); 1582 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1583 buffer_info->page, 0, 1584 length); 1585 /* re-use the skb, only consumed the page */ 1586 buffer_info->skb = skb; 1587 } 1588 e1000_consume_page(buffer_info, rxtop, length); 1589 goto next_desc; 1590 } else { 1591 if (rxtop) { 1592 /* end of the chain */ 1593 shinfo = skb_shinfo(rxtop); 1594 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1595 buffer_info->page, 0, 1596 length); 1597 /* re-use the current skb, we only consumed the 1598 * page 1599 */ 1600 buffer_info->skb = skb; 1601 skb = rxtop; 1602 rxtop = NULL; 1603 e1000_consume_page(buffer_info, skb, length); 1604 } else { 1605 /* no chain, got EOP, this buf is the packet 1606 * copybreak to save the put_page/alloc_page 1607 */ 1608 if (length <= copybreak && 1609 skb_tailroom(skb) >= length) { 1610 u8 *vaddr; 1611 vaddr = kmap_atomic(buffer_info->page); 1612 memcpy(skb_tail_pointer(skb), vaddr, 1613 length); 1614 kunmap_atomic(vaddr); 1615 /* re-use the page, so don't erase 1616 * buffer_info->page 1617 */ 1618 skb_put(skb, length); 1619 } else { 1620 skb_fill_page_desc(skb, 0, 1621 buffer_info->page, 0, 1622 length); 1623 e1000_consume_page(buffer_info, skb, 1624 length); 1625 } 1626 } 1627 } 1628 1629 /* Receive Checksum Offload */ 1630 e1000_rx_checksum(adapter, staterr, skb); 1631 1632 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1633 1634 /* probably a little skewed due to removing CRC */ 1635 total_rx_bytes += skb->len; 1636 total_rx_packets++; 1637 1638 /* eth type trans needs skb->data to point to something */ 1639 if (!pskb_may_pull(skb, ETH_HLEN)) { 1640 e_err("pskb_may_pull failed.\n"); 1641 dev_kfree_skb_irq(skb); 1642 goto next_desc; 1643 } 1644 1645 e1000_receive_skb(adapter, netdev, skb, staterr, 1646 rx_desc->wb.upper.vlan); 1647 1648 next_desc: 1649 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1650 1651 /* return some buffers to hardware, one at a time is too slow */ 1652 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1653 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1654 GFP_ATOMIC); 1655 cleaned_count = 0; 1656 } 1657 1658 /* use prefetched values */ 1659 rx_desc = next_rxd; 1660 buffer_info = next_buffer; 1661 1662 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1663 } 1664 rx_ring->next_to_clean = i; 1665 1666 cleaned_count = e1000_desc_unused(rx_ring); 1667 if (cleaned_count) 1668 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1669 1670 adapter->total_rx_bytes += total_rx_bytes; 1671 adapter->total_rx_packets += total_rx_packets; 1672 return cleaned; 1673 } 1674 1675 /** 1676 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1677 * @rx_ring: Rx descriptor ring 1678 **/ 1679 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1680 { 1681 struct e1000_adapter *adapter = rx_ring->adapter; 1682 struct e1000_buffer *buffer_info; 1683 struct e1000_ps_page *ps_page; 1684 struct pci_dev *pdev = adapter->pdev; 1685 unsigned int i, j; 1686 1687 /* Free all the Rx ring sk_buffs */ 1688 for (i = 0; i < rx_ring->count; i++) { 1689 buffer_info = &rx_ring->buffer_info[i]; 1690 if (buffer_info->dma) { 1691 if (adapter->clean_rx == e1000_clean_rx_irq) 1692 dma_unmap_single(&pdev->dev, buffer_info->dma, 1693 adapter->rx_buffer_len, 1694 DMA_FROM_DEVICE); 1695 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1696 dma_unmap_page(&pdev->dev, buffer_info->dma, 1697 PAGE_SIZE, DMA_FROM_DEVICE); 1698 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1699 dma_unmap_single(&pdev->dev, buffer_info->dma, 1700 adapter->rx_ps_bsize0, 1701 DMA_FROM_DEVICE); 1702 buffer_info->dma = 0; 1703 } 1704 1705 if (buffer_info->page) { 1706 put_page(buffer_info->page); 1707 buffer_info->page = NULL; 1708 } 1709 1710 if (buffer_info->skb) { 1711 dev_kfree_skb(buffer_info->skb); 1712 buffer_info->skb = NULL; 1713 } 1714 1715 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1716 ps_page = &buffer_info->ps_pages[j]; 1717 if (!ps_page->page) 1718 break; 1719 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1720 DMA_FROM_DEVICE); 1721 ps_page->dma = 0; 1722 put_page(ps_page->page); 1723 ps_page->page = NULL; 1724 } 1725 } 1726 1727 /* there also may be some cached data from a chained receive */ 1728 if (rx_ring->rx_skb_top) { 1729 dev_kfree_skb(rx_ring->rx_skb_top); 1730 rx_ring->rx_skb_top = NULL; 1731 } 1732 1733 /* Zero out the descriptor ring */ 1734 memset(rx_ring->desc, 0, rx_ring->size); 1735 1736 rx_ring->next_to_clean = 0; 1737 rx_ring->next_to_use = 0; 1738 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1739 } 1740 1741 static void e1000e_downshift_workaround(struct work_struct *work) 1742 { 1743 struct e1000_adapter *adapter = container_of(work, 1744 struct e1000_adapter, 1745 downshift_task); 1746 1747 if (test_bit(__E1000_DOWN, &adapter->state)) 1748 return; 1749 1750 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1751 } 1752 1753 /** 1754 * e1000_intr_msi - Interrupt Handler 1755 * @irq: interrupt number 1756 * @data: pointer to a network interface device structure 1757 **/ 1758 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1759 { 1760 struct net_device *netdev = data; 1761 struct e1000_adapter *adapter = netdev_priv(netdev); 1762 struct e1000_hw *hw = &adapter->hw; 1763 u32 icr = er32(ICR); 1764 1765 /* read ICR disables interrupts using IAM */ 1766 if (icr & E1000_ICR_LSC) { 1767 hw->mac.get_link_status = true; 1768 /* ICH8 workaround-- Call gig speed drop workaround on cable 1769 * disconnect (LSC) before accessing any PHY registers 1770 */ 1771 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1772 (!(er32(STATUS) & E1000_STATUS_LU))) 1773 schedule_work(&adapter->downshift_task); 1774 1775 /* 80003ES2LAN workaround-- For packet buffer work-around on 1776 * link down event; disable receives here in the ISR and reset 1777 * adapter in watchdog 1778 */ 1779 if (netif_carrier_ok(netdev) && 1780 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1781 /* disable receives */ 1782 u32 rctl = er32(RCTL); 1783 1784 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1785 adapter->flags |= FLAG_RESTART_NOW; 1786 } 1787 /* guard against interrupt when we're going down */ 1788 if (!test_bit(__E1000_DOWN, &adapter->state)) 1789 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1790 } 1791 1792 /* Reset on uncorrectable ECC error */ 1793 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1794 u32 pbeccsts = er32(PBECCSTS); 1795 1796 adapter->corr_errors += 1797 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1798 adapter->uncorr_errors += 1799 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1800 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1801 1802 /* Do the reset outside of interrupt context */ 1803 schedule_work(&adapter->reset_task); 1804 1805 /* return immediately since reset is imminent */ 1806 return IRQ_HANDLED; 1807 } 1808 1809 if (napi_schedule_prep(&adapter->napi)) { 1810 adapter->total_tx_bytes = 0; 1811 adapter->total_tx_packets = 0; 1812 adapter->total_rx_bytes = 0; 1813 adapter->total_rx_packets = 0; 1814 __napi_schedule(&adapter->napi); 1815 } 1816 1817 return IRQ_HANDLED; 1818 } 1819 1820 /** 1821 * e1000_intr - Interrupt Handler 1822 * @irq: interrupt number 1823 * @data: pointer to a network interface device structure 1824 **/ 1825 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1826 { 1827 struct net_device *netdev = data; 1828 struct e1000_adapter *adapter = netdev_priv(netdev); 1829 struct e1000_hw *hw = &adapter->hw; 1830 u32 rctl, icr = er32(ICR); 1831 1832 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1833 return IRQ_NONE; /* Not our interrupt */ 1834 1835 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1836 * not set, then the adapter didn't send an interrupt 1837 */ 1838 if (!(icr & E1000_ICR_INT_ASSERTED)) 1839 return IRQ_NONE; 1840 1841 /* Interrupt Auto-Mask...upon reading ICR, 1842 * interrupts are masked. No need for the 1843 * IMC write 1844 */ 1845 1846 if (icr & E1000_ICR_LSC) { 1847 hw->mac.get_link_status = true; 1848 /* ICH8 workaround-- Call gig speed drop workaround on cable 1849 * disconnect (LSC) before accessing any PHY registers 1850 */ 1851 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1852 (!(er32(STATUS) & E1000_STATUS_LU))) 1853 schedule_work(&adapter->downshift_task); 1854 1855 /* 80003ES2LAN workaround-- 1856 * For packet buffer work-around on link down event; 1857 * disable receives here in the ISR and 1858 * reset adapter in watchdog 1859 */ 1860 if (netif_carrier_ok(netdev) && 1861 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1862 /* disable receives */ 1863 rctl = er32(RCTL); 1864 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1865 adapter->flags |= FLAG_RESTART_NOW; 1866 } 1867 /* guard against interrupt when we're going down */ 1868 if (!test_bit(__E1000_DOWN, &adapter->state)) 1869 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1870 } 1871 1872 /* Reset on uncorrectable ECC error */ 1873 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1874 u32 pbeccsts = er32(PBECCSTS); 1875 1876 adapter->corr_errors += 1877 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1878 adapter->uncorr_errors += 1879 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1880 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1881 1882 /* Do the reset outside of interrupt context */ 1883 schedule_work(&adapter->reset_task); 1884 1885 /* return immediately since reset is imminent */ 1886 return IRQ_HANDLED; 1887 } 1888 1889 if (napi_schedule_prep(&adapter->napi)) { 1890 adapter->total_tx_bytes = 0; 1891 adapter->total_tx_packets = 0; 1892 adapter->total_rx_bytes = 0; 1893 adapter->total_rx_packets = 0; 1894 __napi_schedule(&adapter->napi); 1895 } 1896 1897 return IRQ_HANDLED; 1898 } 1899 1900 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1901 { 1902 struct net_device *netdev = data; 1903 struct e1000_adapter *adapter = netdev_priv(netdev); 1904 struct e1000_hw *hw = &adapter->hw; 1905 u32 icr = er32(ICR); 1906 1907 if (icr & adapter->eiac_mask) 1908 ew32(ICS, (icr & adapter->eiac_mask)); 1909 1910 if (icr & E1000_ICR_LSC) { 1911 hw->mac.get_link_status = true; 1912 /* guard against interrupt when we're going down */ 1913 if (!test_bit(__E1000_DOWN, &adapter->state)) 1914 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1915 } 1916 1917 if (!test_bit(__E1000_DOWN, &adapter->state)) 1918 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1919 1920 return IRQ_HANDLED; 1921 } 1922 1923 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1924 { 1925 struct net_device *netdev = data; 1926 struct e1000_adapter *adapter = netdev_priv(netdev); 1927 struct e1000_hw *hw = &adapter->hw; 1928 struct e1000_ring *tx_ring = adapter->tx_ring; 1929 1930 adapter->total_tx_bytes = 0; 1931 adapter->total_tx_packets = 0; 1932 1933 if (!e1000_clean_tx_irq(tx_ring)) 1934 /* Ring was not completely cleaned, so fire another interrupt */ 1935 ew32(ICS, tx_ring->ims_val); 1936 1937 if (!test_bit(__E1000_DOWN, &adapter->state)) 1938 ew32(IMS, adapter->tx_ring->ims_val); 1939 1940 return IRQ_HANDLED; 1941 } 1942 1943 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1944 { 1945 struct net_device *netdev = data; 1946 struct e1000_adapter *adapter = netdev_priv(netdev); 1947 struct e1000_ring *rx_ring = adapter->rx_ring; 1948 1949 /* Write the ITR value calculated at the end of the 1950 * previous interrupt. 1951 */ 1952 if (rx_ring->set_itr) { 1953 u32 itr = rx_ring->itr_val ? 1954 1000000000 / (rx_ring->itr_val * 256) : 0; 1955 1956 writel(itr, rx_ring->itr_register); 1957 rx_ring->set_itr = 0; 1958 } 1959 1960 if (napi_schedule_prep(&adapter->napi)) { 1961 adapter->total_rx_bytes = 0; 1962 adapter->total_rx_packets = 0; 1963 __napi_schedule(&adapter->napi); 1964 } 1965 return IRQ_HANDLED; 1966 } 1967 1968 /** 1969 * e1000_configure_msix - Configure MSI-X hardware 1970 * @adapter: board private structure 1971 * 1972 * e1000_configure_msix sets up the hardware to properly 1973 * generate MSI-X interrupts. 1974 **/ 1975 static void e1000_configure_msix(struct e1000_adapter *adapter) 1976 { 1977 struct e1000_hw *hw = &adapter->hw; 1978 struct e1000_ring *rx_ring = adapter->rx_ring; 1979 struct e1000_ring *tx_ring = adapter->tx_ring; 1980 int vector = 0; 1981 u32 ctrl_ext, ivar = 0; 1982 1983 adapter->eiac_mask = 0; 1984 1985 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1986 if (hw->mac.type == e1000_82574) { 1987 u32 rfctl = er32(RFCTL); 1988 1989 rfctl |= E1000_RFCTL_ACK_DIS; 1990 ew32(RFCTL, rfctl); 1991 } 1992 1993 /* Configure Rx vector */ 1994 rx_ring->ims_val = E1000_IMS_RXQ0; 1995 adapter->eiac_mask |= rx_ring->ims_val; 1996 if (rx_ring->itr_val) 1997 writel(1000000000 / (rx_ring->itr_val * 256), 1998 rx_ring->itr_register); 1999 else 2000 writel(1, rx_ring->itr_register); 2001 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2002 2003 /* Configure Tx vector */ 2004 tx_ring->ims_val = E1000_IMS_TXQ0; 2005 vector++; 2006 if (tx_ring->itr_val) 2007 writel(1000000000 / (tx_ring->itr_val * 256), 2008 tx_ring->itr_register); 2009 else 2010 writel(1, tx_ring->itr_register); 2011 adapter->eiac_mask |= tx_ring->ims_val; 2012 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2013 2014 /* set vector for Other Causes, e.g. link changes */ 2015 vector++; 2016 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2017 if (rx_ring->itr_val) 2018 writel(1000000000 / (rx_ring->itr_val * 256), 2019 hw->hw_addr + E1000_EITR_82574(vector)); 2020 else 2021 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2022 2023 /* Cause Tx interrupts on every write back */ 2024 ivar |= BIT(31); 2025 2026 ew32(IVAR, ivar); 2027 2028 /* enable MSI-X PBA support */ 2029 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2030 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2031 ew32(CTRL_EXT, ctrl_ext); 2032 e1e_flush(); 2033 } 2034 2035 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2036 { 2037 if (adapter->msix_entries) { 2038 pci_disable_msix(adapter->pdev); 2039 kfree(adapter->msix_entries); 2040 adapter->msix_entries = NULL; 2041 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2042 pci_disable_msi(adapter->pdev); 2043 adapter->flags &= ~FLAG_MSI_ENABLED; 2044 } 2045 } 2046 2047 /** 2048 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2049 * @adapter: board private structure 2050 * 2051 * Attempt to configure interrupts using the best available 2052 * capabilities of the hardware and kernel. 2053 **/ 2054 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2055 { 2056 int err; 2057 int i; 2058 2059 switch (adapter->int_mode) { 2060 case E1000E_INT_MODE_MSIX: 2061 if (adapter->flags & FLAG_HAS_MSIX) { 2062 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2063 adapter->msix_entries = kcalloc(adapter->num_vectors, 2064 sizeof(struct 2065 msix_entry), 2066 GFP_KERNEL); 2067 if (adapter->msix_entries) { 2068 struct e1000_adapter *a = adapter; 2069 2070 for (i = 0; i < adapter->num_vectors; i++) 2071 adapter->msix_entries[i].entry = i; 2072 2073 err = pci_enable_msix_range(a->pdev, 2074 a->msix_entries, 2075 a->num_vectors, 2076 a->num_vectors); 2077 if (err > 0) 2078 return; 2079 } 2080 /* MSI-X failed, so fall through and try MSI */ 2081 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2082 e1000e_reset_interrupt_capability(adapter); 2083 } 2084 adapter->int_mode = E1000E_INT_MODE_MSI; 2085 fallthrough; 2086 case E1000E_INT_MODE_MSI: 2087 if (!pci_enable_msi(adapter->pdev)) { 2088 adapter->flags |= FLAG_MSI_ENABLED; 2089 } else { 2090 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2091 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2092 } 2093 fallthrough; 2094 case E1000E_INT_MODE_LEGACY: 2095 /* Don't do anything; this is the system default */ 2096 break; 2097 } 2098 2099 /* store the number of vectors being used */ 2100 adapter->num_vectors = 1; 2101 } 2102 2103 /** 2104 * e1000_request_msix - Initialize MSI-X interrupts 2105 * @adapter: board private structure 2106 * 2107 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2108 * kernel. 2109 **/ 2110 static int e1000_request_msix(struct e1000_adapter *adapter) 2111 { 2112 struct net_device *netdev = adapter->netdev; 2113 int err = 0, vector = 0; 2114 2115 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2116 snprintf(adapter->rx_ring->name, 2117 sizeof(adapter->rx_ring->name) - 1, 2118 "%.14s-rx-0", netdev->name); 2119 else 2120 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2121 err = request_irq(adapter->msix_entries[vector].vector, 2122 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2123 netdev); 2124 if (err) 2125 return err; 2126 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2127 E1000_EITR_82574(vector); 2128 adapter->rx_ring->itr_val = adapter->itr; 2129 vector++; 2130 2131 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2132 snprintf(adapter->tx_ring->name, 2133 sizeof(adapter->tx_ring->name) - 1, 2134 "%.14s-tx-0", netdev->name); 2135 else 2136 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2137 err = request_irq(adapter->msix_entries[vector].vector, 2138 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2139 netdev); 2140 if (err) 2141 return err; 2142 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2143 E1000_EITR_82574(vector); 2144 adapter->tx_ring->itr_val = adapter->itr; 2145 vector++; 2146 2147 err = request_irq(adapter->msix_entries[vector].vector, 2148 e1000_msix_other, 0, netdev->name, netdev); 2149 if (err) 2150 return err; 2151 2152 e1000_configure_msix(adapter); 2153 2154 return 0; 2155 } 2156 2157 /** 2158 * e1000_request_irq - initialize interrupts 2159 * @adapter: board private structure 2160 * 2161 * Attempts to configure interrupts using the best available 2162 * capabilities of the hardware and kernel. 2163 **/ 2164 static int e1000_request_irq(struct e1000_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 int err; 2168 2169 if (adapter->msix_entries) { 2170 err = e1000_request_msix(adapter); 2171 if (!err) 2172 return err; 2173 /* fall back to MSI */ 2174 e1000e_reset_interrupt_capability(adapter); 2175 adapter->int_mode = E1000E_INT_MODE_MSI; 2176 e1000e_set_interrupt_capability(adapter); 2177 } 2178 if (adapter->flags & FLAG_MSI_ENABLED) { 2179 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2180 netdev->name, netdev); 2181 if (!err) 2182 return err; 2183 2184 /* fall back to legacy interrupt */ 2185 e1000e_reset_interrupt_capability(adapter); 2186 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2187 } 2188 2189 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2190 netdev->name, netdev); 2191 if (err) 2192 e_err("Unable to allocate interrupt, Error: %d\n", err); 2193 2194 return err; 2195 } 2196 2197 static void e1000_free_irq(struct e1000_adapter *adapter) 2198 { 2199 struct net_device *netdev = adapter->netdev; 2200 2201 if (adapter->msix_entries) { 2202 int vector = 0; 2203 2204 free_irq(adapter->msix_entries[vector].vector, netdev); 2205 vector++; 2206 2207 free_irq(adapter->msix_entries[vector].vector, netdev); 2208 vector++; 2209 2210 /* Other Causes interrupt vector */ 2211 free_irq(adapter->msix_entries[vector].vector, netdev); 2212 return; 2213 } 2214 2215 free_irq(adapter->pdev->irq, netdev); 2216 } 2217 2218 /** 2219 * e1000_irq_disable - Mask off interrupt generation on the NIC 2220 * @adapter: board private structure 2221 **/ 2222 static void e1000_irq_disable(struct e1000_adapter *adapter) 2223 { 2224 struct e1000_hw *hw = &adapter->hw; 2225 2226 ew32(IMC, ~0); 2227 if (adapter->msix_entries) 2228 ew32(EIAC_82574, 0); 2229 e1e_flush(); 2230 2231 if (adapter->msix_entries) { 2232 int i; 2233 2234 for (i = 0; i < adapter->num_vectors; i++) 2235 synchronize_irq(adapter->msix_entries[i].vector); 2236 } else { 2237 synchronize_irq(adapter->pdev->irq); 2238 } 2239 } 2240 2241 /** 2242 * e1000_irq_enable - Enable default interrupt generation settings 2243 * @adapter: board private structure 2244 **/ 2245 static void e1000_irq_enable(struct e1000_adapter *adapter) 2246 { 2247 struct e1000_hw *hw = &adapter->hw; 2248 2249 if (adapter->msix_entries) { 2250 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2251 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2252 IMS_OTHER_MASK); 2253 } else if (hw->mac.type >= e1000_pch_lpt) { 2254 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2255 } else { 2256 ew32(IMS, IMS_ENABLE_MASK); 2257 } 2258 e1e_flush(); 2259 } 2260 2261 /** 2262 * e1000e_get_hw_control - get control of the h/w from f/w 2263 * @adapter: address of board private structure 2264 * 2265 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2266 * For ASF and Pass Through versions of f/w this means that 2267 * the driver is loaded. For AMT version (only with 82573) 2268 * of the f/w this means that the network i/f is open. 2269 **/ 2270 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2271 { 2272 struct e1000_hw *hw = &adapter->hw; 2273 u32 ctrl_ext; 2274 u32 swsm; 2275 2276 /* Let firmware know the driver has taken over */ 2277 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2278 swsm = er32(SWSM); 2279 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2280 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2281 ctrl_ext = er32(CTRL_EXT); 2282 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2283 } 2284 } 2285 2286 /** 2287 * e1000e_release_hw_control - release control of the h/w to f/w 2288 * @adapter: address of board private structure 2289 * 2290 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2291 * For ASF and Pass Through versions of f/w this means that the 2292 * driver is no longer loaded. For AMT version (only with 82573) i 2293 * of the f/w this means that the network i/f is closed. 2294 * 2295 **/ 2296 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2297 { 2298 struct e1000_hw *hw = &adapter->hw; 2299 u32 ctrl_ext; 2300 u32 swsm; 2301 2302 /* Let firmware taken over control of h/w */ 2303 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2304 swsm = er32(SWSM); 2305 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2306 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2307 ctrl_ext = er32(CTRL_EXT); 2308 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2309 } 2310 } 2311 2312 /** 2313 * e1000_alloc_ring_dma - allocate memory for a ring structure 2314 * @adapter: board private structure 2315 * @ring: ring struct for which to allocate dma 2316 **/ 2317 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2318 struct e1000_ring *ring) 2319 { 2320 struct pci_dev *pdev = adapter->pdev; 2321 2322 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2323 GFP_KERNEL); 2324 if (!ring->desc) 2325 return -ENOMEM; 2326 2327 return 0; 2328 } 2329 2330 /** 2331 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2332 * @tx_ring: Tx descriptor ring 2333 * 2334 * Return 0 on success, negative on failure 2335 **/ 2336 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2337 { 2338 struct e1000_adapter *adapter = tx_ring->adapter; 2339 int err = -ENOMEM, size; 2340 2341 size = sizeof(struct e1000_buffer) * tx_ring->count; 2342 tx_ring->buffer_info = vzalloc(size); 2343 if (!tx_ring->buffer_info) 2344 goto err; 2345 2346 /* round up to nearest 4K */ 2347 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2348 tx_ring->size = ALIGN(tx_ring->size, 4096); 2349 2350 err = e1000_alloc_ring_dma(adapter, tx_ring); 2351 if (err) 2352 goto err; 2353 2354 tx_ring->next_to_use = 0; 2355 tx_ring->next_to_clean = 0; 2356 2357 return 0; 2358 err: 2359 vfree(tx_ring->buffer_info); 2360 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2361 return err; 2362 } 2363 2364 /** 2365 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2366 * @rx_ring: Rx descriptor ring 2367 * 2368 * Returns 0 on success, negative on failure 2369 **/ 2370 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2371 { 2372 struct e1000_adapter *adapter = rx_ring->adapter; 2373 struct e1000_buffer *buffer_info; 2374 int i, size, desc_len, err = -ENOMEM; 2375 2376 size = sizeof(struct e1000_buffer) * rx_ring->count; 2377 rx_ring->buffer_info = vzalloc(size); 2378 if (!rx_ring->buffer_info) 2379 goto err; 2380 2381 for (i = 0; i < rx_ring->count; i++) { 2382 buffer_info = &rx_ring->buffer_info[i]; 2383 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2384 sizeof(struct e1000_ps_page), 2385 GFP_KERNEL); 2386 if (!buffer_info->ps_pages) 2387 goto err_pages; 2388 } 2389 2390 desc_len = sizeof(union e1000_rx_desc_packet_split); 2391 2392 /* Round up to nearest 4K */ 2393 rx_ring->size = rx_ring->count * desc_len; 2394 rx_ring->size = ALIGN(rx_ring->size, 4096); 2395 2396 err = e1000_alloc_ring_dma(adapter, rx_ring); 2397 if (err) 2398 goto err_pages; 2399 2400 rx_ring->next_to_clean = 0; 2401 rx_ring->next_to_use = 0; 2402 rx_ring->rx_skb_top = NULL; 2403 2404 return 0; 2405 2406 err_pages: 2407 for (i = 0; i < rx_ring->count; i++) { 2408 buffer_info = &rx_ring->buffer_info[i]; 2409 kfree(buffer_info->ps_pages); 2410 } 2411 err: 2412 vfree(rx_ring->buffer_info); 2413 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2414 return err; 2415 } 2416 2417 /** 2418 * e1000_clean_tx_ring - Free Tx Buffers 2419 * @tx_ring: Tx descriptor ring 2420 **/ 2421 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2422 { 2423 struct e1000_adapter *adapter = tx_ring->adapter; 2424 struct e1000_buffer *buffer_info; 2425 unsigned long size; 2426 unsigned int i; 2427 2428 for (i = 0; i < tx_ring->count; i++) { 2429 buffer_info = &tx_ring->buffer_info[i]; 2430 e1000_put_txbuf(tx_ring, buffer_info, false); 2431 } 2432 2433 netdev_reset_queue(adapter->netdev); 2434 size = sizeof(struct e1000_buffer) * tx_ring->count; 2435 memset(tx_ring->buffer_info, 0, size); 2436 2437 memset(tx_ring->desc, 0, tx_ring->size); 2438 2439 tx_ring->next_to_use = 0; 2440 tx_ring->next_to_clean = 0; 2441 } 2442 2443 /** 2444 * e1000e_free_tx_resources - Free Tx Resources per Queue 2445 * @tx_ring: Tx descriptor ring 2446 * 2447 * Free all transmit software resources 2448 **/ 2449 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2450 { 2451 struct e1000_adapter *adapter = tx_ring->adapter; 2452 struct pci_dev *pdev = adapter->pdev; 2453 2454 e1000_clean_tx_ring(tx_ring); 2455 2456 vfree(tx_ring->buffer_info); 2457 tx_ring->buffer_info = NULL; 2458 2459 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2460 tx_ring->dma); 2461 tx_ring->desc = NULL; 2462 } 2463 2464 /** 2465 * e1000e_free_rx_resources - Free Rx Resources 2466 * @rx_ring: Rx descriptor ring 2467 * 2468 * Free all receive software resources 2469 **/ 2470 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2471 { 2472 struct e1000_adapter *adapter = rx_ring->adapter; 2473 struct pci_dev *pdev = adapter->pdev; 2474 int i; 2475 2476 e1000_clean_rx_ring(rx_ring); 2477 2478 for (i = 0; i < rx_ring->count; i++) 2479 kfree(rx_ring->buffer_info[i].ps_pages); 2480 2481 vfree(rx_ring->buffer_info); 2482 rx_ring->buffer_info = NULL; 2483 2484 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2485 rx_ring->dma); 2486 rx_ring->desc = NULL; 2487 } 2488 2489 /** 2490 * e1000_update_itr - update the dynamic ITR value based on statistics 2491 * @itr_setting: current adapter->itr 2492 * @packets: the number of packets during this measurement interval 2493 * @bytes: the number of bytes during this measurement interval 2494 * 2495 * Stores a new ITR value based on packets and byte 2496 * counts during the last interrupt. The advantage of per interrupt 2497 * computation is faster updates and more accurate ITR for the current 2498 * traffic pattern. Constants in this function were computed 2499 * based on theoretical maximum wire speed and thresholds were set based 2500 * on testing data as well as attempting to minimize response time 2501 * while increasing bulk throughput. This functionality is controlled 2502 * by the InterruptThrottleRate module parameter. 2503 **/ 2504 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2505 { 2506 unsigned int retval = itr_setting; 2507 2508 if (packets == 0) 2509 return itr_setting; 2510 2511 switch (itr_setting) { 2512 case lowest_latency: 2513 /* handle TSO and jumbo frames */ 2514 if (bytes / packets > 8000) 2515 retval = bulk_latency; 2516 else if ((packets < 5) && (bytes > 512)) 2517 retval = low_latency; 2518 break; 2519 case low_latency: /* 50 usec aka 20000 ints/s */ 2520 if (bytes > 10000) { 2521 /* this if handles the TSO accounting */ 2522 if (bytes / packets > 8000) 2523 retval = bulk_latency; 2524 else if ((packets < 10) || ((bytes / packets) > 1200)) 2525 retval = bulk_latency; 2526 else if ((packets > 35)) 2527 retval = lowest_latency; 2528 } else if (bytes / packets > 2000) { 2529 retval = bulk_latency; 2530 } else if (packets <= 2 && bytes < 512) { 2531 retval = lowest_latency; 2532 } 2533 break; 2534 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2535 if (bytes > 25000) { 2536 if (packets > 35) 2537 retval = low_latency; 2538 } else if (bytes < 6000) { 2539 retval = low_latency; 2540 } 2541 break; 2542 } 2543 2544 return retval; 2545 } 2546 2547 static void e1000_set_itr(struct e1000_adapter *adapter) 2548 { 2549 u16 current_itr; 2550 u32 new_itr = adapter->itr; 2551 2552 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2553 if (adapter->link_speed != SPEED_1000) { 2554 new_itr = 4000; 2555 goto set_itr_now; 2556 } 2557 2558 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2559 new_itr = 0; 2560 goto set_itr_now; 2561 } 2562 2563 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2564 adapter->total_tx_packets, 2565 adapter->total_tx_bytes); 2566 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2567 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2568 adapter->tx_itr = low_latency; 2569 2570 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2571 adapter->total_rx_packets, 2572 adapter->total_rx_bytes); 2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2574 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2575 adapter->rx_itr = low_latency; 2576 2577 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2578 2579 /* counts and packets in update_itr are dependent on these numbers */ 2580 switch (current_itr) { 2581 case lowest_latency: 2582 new_itr = 70000; 2583 break; 2584 case low_latency: 2585 new_itr = 20000; /* aka hwitr = ~200 */ 2586 break; 2587 case bulk_latency: 2588 new_itr = 4000; 2589 break; 2590 default: 2591 break; 2592 } 2593 2594 set_itr_now: 2595 if (new_itr != adapter->itr) { 2596 /* this attempts to bias the interrupt rate towards Bulk 2597 * by adding intermediate steps when interrupt rate is 2598 * increasing 2599 */ 2600 new_itr = new_itr > adapter->itr ? 2601 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2602 adapter->itr = new_itr; 2603 adapter->rx_ring->itr_val = new_itr; 2604 if (adapter->msix_entries) 2605 adapter->rx_ring->set_itr = 1; 2606 else 2607 e1000e_write_itr(adapter, new_itr); 2608 } 2609 } 2610 2611 /** 2612 * e1000e_write_itr - write the ITR value to the appropriate registers 2613 * @adapter: address of board private structure 2614 * @itr: new ITR value to program 2615 * 2616 * e1000e_write_itr determines if the adapter is in MSI-X mode 2617 * and, if so, writes the EITR registers with the ITR value. 2618 * Otherwise, it writes the ITR value into the ITR register. 2619 **/ 2620 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2621 { 2622 struct e1000_hw *hw = &adapter->hw; 2623 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2624 2625 if (adapter->msix_entries) { 2626 int vector; 2627 2628 for (vector = 0; vector < adapter->num_vectors; vector++) 2629 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2630 } else { 2631 ew32(ITR, new_itr); 2632 } 2633 } 2634 2635 /** 2636 * e1000_alloc_queues - Allocate memory for all rings 2637 * @adapter: board private structure to initialize 2638 **/ 2639 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2640 { 2641 int size = sizeof(struct e1000_ring); 2642 2643 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2644 if (!adapter->tx_ring) 2645 goto err; 2646 adapter->tx_ring->count = adapter->tx_ring_count; 2647 adapter->tx_ring->adapter = adapter; 2648 2649 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2650 if (!adapter->rx_ring) 2651 goto err; 2652 adapter->rx_ring->count = adapter->rx_ring_count; 2653 adapter->rx_ring->adapter = adapter; 2654 2655 return 0; 2656 err: 2657 e_err("Unable to allocate memory for queues\n"); 2658 kfree(adapter->rx_ring); 2659 kfree(adapter->tx_ring); 2660 return -ENOMEM; 2661 } 2662 2663 /** 2664 * e1000e_poll - NAPI Rx polling callback 2665 * @napi: struct associated with this polling callback 2666 * @budget: number of packets driver is allowed to process this poll 2667 **/ 2668 static int e1000e_poll(struct napi_struct *napi, int budget) 2669 { 2670 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2671 napi); 2672 struct e1000_hw *hw = &adapter->hw; 2673 struct net_device *poll_dev = adapter->netdev; 2674 int tx_cleaned = 1, work_done = 0; 2675 2676 adapter = netdev_priv(poll_dev); 2677 2678 if (!adapter->msix_entries || 2679 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2680 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2681 2682 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2683 2684 if (!tx_cleaned || work_done == budget) 2685 return budget; 2686 2687 /* Exit the polling mode, but don't re-enable interrupts if stack might 2688 * poll us due to busy-polling 2689 */ 2690 if (likely(napi_complete_done(napi, work_done))) { 2691 if (adapter->itr_setting & 3) 2692 e1000_set_itr(adapter); 2693 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2694 if (adapter->msix_entries) 2695 ew32(IMS, adapter->rx_ring->ims_val); 2696 else 2697 e1000_irq_enable(adapter); 2698 } 2699 } 2700 2701 return work_done; 2702 } 2703 2704 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2705 __always_unused __be16 proto, u16 vid) 2706 { 2707 struct e1000_adapter *adapter = netdev_priv(netdev); 2708 struct e1000_hw *hw = &adapter->hw; 2709 u32 vfta, index; 2710 2711 /* don't update vlan cookie if already programmed */ 2712 if ((adapter->hw.mng_cookie.status & 2713 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2714 (vid == adapter->mng_vlan_id)) 2715 return 0; 2716 2717 /* add VID to filter table */ 2718 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2719 index = (vid >> 5) & 0x7F; 2720 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2721 vfta |= BIT((vid & 0x1F)); 2722 hw->mac.ops.write_vfta(hw, index, vfta); 2723 } 2724 2725 set_bit(vid, adapter->active_vlans); 2726 2727 return 0; 2728 } 2729 2730 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2731 __always_unused __be16 proto, u16 vid) 2732 { 2733 struct e1000_adapter *adapter = netdev_priv(netdev); 2734 struct e1000_hw *hw = &adapter->hw; 2735 u32 vfta, index; 2736 2737 if ((adapter->hw.mng_cookie.status & 2738 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2739 (vid == adapter->mng_vlan_id)) { 2740 /* release control to f/w */ 2741 e1000e_release_hw_control(adapter); 2742 return 0; 2743 } 2744 2745 /* remove VID from filter table */ 2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2747 index = (vid >> 5) & 0x7F; 2748 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2749 vfta &= ~BIT((vid & 0x1F)); 2750 hw->mac.ops.write_vfta(hw, index, vfta); 2751 } 2752 2753 clear_bit(vid, adapter->active_vlans); 2754 2755 return 0; 2756 } 2757 2758 /** 2759 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2760 * @adapter: board private structure to initialize 2761 **/ 2762 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2763 { 2764 struct net_device *netdev = adapter->netdev; 2765 struct e1000_hw *hw = &adapter->hw; 2766 u32 rctl; 2767 2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2769 /* disable VLAN receive filtering */ 2770 rctl = er32(RCTL); 2771 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2772 ew32(RCTL, rctl); 2773 2774 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2775 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2776 adapter->mng_vlan_id); 2777 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2778 } 2779 } 2780 } 2781 2782 /** 2783 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2784 * @adapter: board private structure to initialize 2785 **/ 2786 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2787 { 2788 struct e1000_hw *hw = &adapter->hw; 2789 u32 rctl; 2790 2791 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2792 /* enable VLAN receive filtering */ 2793 rctl = er32(RCTL); 2794 rctl |= E1000_RCTL_VFE; 2795 rctl &= ~E1000_RCTL_CFIEN; 2796 ew32(RCTL, rctl); 2797 } 2798 } 2799 2800 /** 2801 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2802 * @adapter: board private structure to initialize 2803 **/ 2804 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2805 { 2806 struct e1000_hw *hw = &adapter->hw; 2807 u32 ctrl; 2808 2809 /* disable VLAN tag insert/strip */ 2810 ctrl = er32(CTRL); 2811 ctrl &= ~E1000_CTRL_VME; 2812 ew32(CTRL, ctrl); 2813 } 2814 2815 /** 2816 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2817 * @adapter: board private structure to initialize 2818 **/ 2819 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2820 { 2821 struct e1000_hw *hw = &adapter->hw; 2822 u32 ctrl; 2823 2824 /* enable VLAN tag insert/strip */ 2825 ctrl = er32(CTRL); 2826 ctrl |= E1000_CTRL_VME; 2827 ew32(CTRL, ctrl); 2828 } 2829 2830 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2831 { 2832 struct net_device *netdev = adapter->netdev; 2833 u16 vid = adapter->hw.mng_cookie.vlan_id; 2834 u16 old_vid = adapter->mng_vlan_id; 2835 2836 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2837 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2838 adapter->mng_vlan_id = vid; 2839 } 2840 2841 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2842 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2843 } 2844 2845 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2846 { 2847 u16 vid; 2848 2849 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2850 2851 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2852 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2853 } 2854 2855 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2856 { 2857 struct e1000_hw *hw = &adapter->hw; 2858 u32 manc, manc2h, mdef, i, j; 2859 2860 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2861 return; 2862 2863 manc = er32(MANC); 2864 2865 /* enable receiving management packets to the host. this will probably 2866 * generate destination unreachable messages from the host OS, but 2867 * the packets will be handled on SMBUS 2868 */ 2869 manc |= E1000_MANC_EN_MNG2HOST; 2870 manc2h = er32(MANC2H); 2871 2872 switch (hw->mac.type) { 2873 default: 2874 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2875 break; 2876 case e1000_82574: 2877 case e1000_82583: 2878 /* Check if IPMI pass-through decision filter already exists; 2879 * if so, enable it. 2880 */ 2881 for (i = 0, j = 0; i < 8; i++) { 2882 mdef = er32(MDEF(i)); 2883 2884 /* Ignore filters with anything other than IPMI ports */ 2885 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2886 continue; 2887 2888 /* Enable this decision filter in MANC2H */ 2889 if (mdef) 2890 manc2h |= BIT(i); 2891 2892 j |= mdef; 2893 } 2894 2895 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2896 break; 2897 2898 /* Create new decision filter in an empty filter */ 2899 for (i = 0, j = 0; i < 8; i++) 2900 if (er32(MDEF(i)) == 0) { 2901 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2902 E1000_MDEF_PORT_664)); 2903 manc2h |= BIT(1); 2904 j++; 2905 break; 2906 } 2907 2908 if (!j) 2909 e_warn("Unable to create IPMI pass-through filter\n"); 2910 break; 2911 } 2912 2913 ew32(MANC2H, manc2h); 2914 ew32(MANC, manc); 2915 } 2916 2917 /** 2918 * e1000_configure_tx - Configure Transmit Unit after Reset 2919 * @adapter: board private structure 2920 * 2921 * Configure the Tx unit of the MAC after a reset. 2922 **/ 2923 static void e1000_configure_tx(struct e1000_adapter *adapter) 2924 { 2925 struct e1000_hw *hw = &adapter->hw; 2926 struct e1000_ring *tx_ring = adapter->tx_ring; 2927 u64 tdba; 2928 u32 tdlen, tctl, tarc; 2929 2930 /* Setup the HW Tx Head and Tail descriptor pointers */ 2931 tdba = tx_ring->dma; 2932 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2933 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2934 ew32(TDBAH(0), (tdba >> 32)); 2935 ew32(TDLEN(0), tdlen); 2936 ew32(TDH(0), 0); 2937 ew32(TDT(0), 0); 2938 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2939 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2940 2941 writel(0, tx_ring->head); 2942 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2943 e1000e_update_tdt_wa(tx_ring, 0); 2944 else 2945 writel(0, tx_ring->tail); 2946 2947 /* Set the Tx Interrupt Delay register */ 2948 ew32(TIDV, adapter->tx_int_delay); 2949 /* Tx irq moderation */ 2950 ew32(TADV, adapter->tx_abs_int_delay); 2951 2952 if (adapter->flags2 & FLAG2_DMA_BURST) { 2953 u32 txdctl = er32(TXDCTL(0)); 2954 2955 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2956 E1000_TXDCTL_WTHRESH); 2957 /* set up some performance related parameters to encourage the 2958 * hardware to use the bus more efficiently in bursts, depends 2959 * on the tx_int_delay to be enabled, 2960 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2961 * hthresh = 1 ==> prefetch when one or more available 2962 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2963 * BEWARE: this seems to work but should be considered first if 2964 * there are Tx hangs or other Tx related bugs 2965 */ 2966 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2967 ew32(TXDCTL(0), txdctl); 2968 } 2969 /* erratum work around: set txdctl the same for both queues */ 2970 ew32(TXDCTL(1), er32(TXDCTL(0))); 2971 2972 /* Program the Transmit Control Register */ 2973 tctl = er32(TCTL); 2974 tctl &= ~E1000_TCTL_CT; 2975 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2976 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2977 2978 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2979 tarc = er32(TARC(0)); 2980 /* set the speed mode bit, we'll clear it if we're not at 2981 * gigabit link later 2982 */ 2983 #define SPEED_MODE_BIT BIT(21) 2984 tarc |= SPEED_MODE_BIT; 2985 ew32(TARC(0), tarc); 2986 } 2987 2988 /* errata: program both queues to unweighted RR */ 2989 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2990 tarc = er32(TARC(0)); 2991 tarc |= 1; 2992 ew32(TARC(0), tarc); 2993 tarc = er32(TARC(1)); 2994 tarc |= 1; 2995 ew32(TARC(1), tarc); 2996 } 2997 2998 /* Setup Transmit Descriptor Settings for eop descriptor */ 2999 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3000 3001 /* only set IDE if we are delaying interrupts using the timers */ 3002 if (adapter->tx_int_delay) 3003 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3004 3005 /* enable Report Status bit */ 3006 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3007 3008 ew32(TCTL, tctl); 3009 3010 hw->mac.ops.config_collision_dist(hw); 3011 3012 /* SPT and KBL Si errata workaround to avoid data corruption */ 3013 if (hw->mac.type == e1000_pch_spt) { 3014 u32 reg_val; 3015 3016 reg_val = er32(IOSFPC); 3017 reg_val |= E1000_RCTL_RDMTS_HEX; 3018 ew32(IOSFPC, reg_val); 3019 3020 reg_val = er32(TARC(0)); 3021 /* SPT and KBL Si errata workaround to avoid Tx hang. 3022 * Dropping the number of outstanding requests from 3023 * 3 to 2 in order to avoid a buffer overrun. 3024 */ 3025 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3026 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3027 ew32(TARC(0), reg_val); 3028 } 3029 } 3030 3031 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3032 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3033 3034 /** 3035 * e1000_setup_rctl - configure the receive control registers 3036 * @adapter: Board private structure 3037 **/ 3038 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3039 { 3040 struct e1000_hw *hw = &adapter->hw; 3041 u32 rctl, rfctl; 3042 u32 pages = 0; 3043 3044 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3045 * If jumbo frames not set, program related MAC/PHY registers 3046 * to h/w defaults 3047 */ 3048 if (hw->mac.type >= e1000_pch2lan) { 3049 s32 ret_val; 3050 3051 if (adapter->netdev->mtu > ETH_DATA_LEN) 3052 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3053 else 3054 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3055 3056 if (ret_val) 3057 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3058 } 3059 3060 /* Program MC offset vector base */ 3061 rctl = er32(RCTL); 3062 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3063 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3064 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3065 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3066 3067 /* Do not Store bad packets */ 3068 rctl &= ~E1000_RCTL_SBP; 3069 3070 /* Enable Long Packet receive */ 3071 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3072 rctl &= ~E1000_RCTL_LPE; 3073 else 3074 rctl |= E1000_RCTL_LPE; 3075 3076 /* Some systems expect that the CRC is included in SMBUS traffic. The 3077 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3078 * host memory when this is enabled 3079 */ 3080 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3081 rctl |= E1000_RCTL_SECRC; 3082 3083 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3084 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3085 u16 phy_data; 3086 3087 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3088 phy_data &= 0xfff8; 3089 phy_data |= BIT(2); 3090 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3091 3092 e1e_rphy(hw, 22, &phy_data); 3093 phy_data &= 0x0fff; 3094 phy_data |= BIT(14); 3095 e1e_wphy(hw, 0x10, 0x2823); 3096 e1e_wphy(hw, 0x11, 0x0003); 3097 e1e_wphy(hw, 22, phy_data); 3098 } 3099 3100 /* Setup buffer sizes */ 3101 rctl &= ~E1000_RCTL_SZ_4096; 3102 rctl |= E1000_RCTL_BSEX; 3103 switch (adapter->rx_buffer_len) { 3104 case 2048: 3105 default: 3106 rctl |= E1000_RCTL_SZ_2048; 3107 rctl &= ~E1000_RCTL_BSEX; 3108 break; 3109 case 4096: 3110 rctl |= E1000_RCTL_SZ_4096; 3111 break; 3112 case 8192: 3113 rctl |= E1000_RCTL_SZ_8192; 3114 break; 3115 case 16384: 3116 rctl |= E1000_RCTL_SZ_16384; 3117 break; 3118 } 3119 3120 /* Enable Extended Status in all Receive Descriptors */ 3121 rfctl = er32(RFCTL); 3122 rfctl |= E1000_RFCTL_EXTEN; 3123 ew32(RFCTL, rfctl); 3124 3125 /* 82571 and greater support packet-split where the protocol 3126 * header is placed in skb->data and the packet data is 3127 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3128 * In the case of a non-split, skb->data is linearly filled, 3129 * followed by the page buffers. Therefore, skb->data is 3130 * sized to hold the largest protocol header. 3131 * 3132 * allocations using alloc_page take too long for regular MTU 3133 * so only enable packet split for jumbo frames 3134 * 3135 * Using pages when the page size is greater than 16k wastes 3136 * a lot of memory, since we allocate 3 pages at all times 3137 * per packet. 3138 */ 3139 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3140 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3141 adapter->rx_ps_pages = pages; 3142 else 3143 adapter->rx_ps_pages = 0; 3144 3145 if (adapter->rx_ps_pages) { 3146 u32 psrctl = 0; 3147 3148 /* Enable Packet split descriptors */ 3149 rctl |= E1000_RCTL_DTYP_PS; 3150 3151 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3152 3153 switch (adapter->rx_ps_pages) { 3154 case 3: 3155 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3156 fallthrough; 3157 case 2: 3158 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3159 fallthrough; 3160 case 1: 3161 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3162 break; 3163 } 3164 3165 ew32(PSRCTL, psrctl); 3166 } 3167 3168 /* This is useful for sniffing bad packets. */ 3169 if (adapter->netdev->features & NETIF_F_RXALL) { 3170 /* UPE and MPE will be handled by normal PROMISC logic 3171 * in e1000e_set_rx_mode 3172 */ 3173 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3174 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3175 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3176 3177 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3178 E1000_RCTL_DPF | /* Allow filtered pause */ 3179 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3180 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3181 * and that breaks VLANs. 3182 */ 3183 } 3184 3185 ew32(RCTL, rctl); 3186 /* just started the receive unit, no need to restart */ 3187 adapter->flags &= ~FLAG_RESTART_NOW; 3188 } 3189 3190 /** 3191 * e1000_configure_rx - Configure Receive Unit after Reset 3192 * @adapter: board private structure 3193 * 3194 * Configure the Rx unit of the MAC after a reset. 3195 **/ 3196 static void e1000_configure_rx(struct e1000_adapter *adapter) 3197 { 3198 struct e1000_hw *hw = &adapter->hw; 3199 struct e1000_ring *rx_ring = adapter->rx_ring; 3200 u64 rdba; 3201 u32 rdlen, rctl, rxcsum, ctrl_ext; 3202 3203 if (adapter->rx_ps_pages) { 3204 /* this is a 32 byte descriptor */ 3205 rdlen = rx_ring->count * 3206 sizeof(union e1000_rx_desc_packet_split); 3207 adapter->clean_rx = e1000_clean_rx_irq_ps; 3208 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3209 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3210 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3211 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3212 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3213 } else { 3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3215 adapter->clean_rx = e1000_clean_rx_irq; 3216 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3217 } 3218 3219 /* disable receives while setting up the descriptors */ 3220 rctl = er32(RCTL); 3221 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3222 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3223 e1e_flush(); 3224 usleep_range(10000, 11000); 3225 3226 if (adapter->flags2 & FLAG2_DMA_BURST) { 3227 /* set the writeback threshold (only takes effect if the RDTR 3228 * is set). set GRAN=1 and write back up to 0x4 worth, and 3229 * enable prefetching of 0x20 Rx descriptors 3230 * granularity = 01 3231 * wthresh = 04, 3232 * hthresh = 04, 3233 * pthresh = 0x20 3234 */ 3235 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3236 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3237 } 3238 3239 /* set the Receive Delay Timer Register */ 3240 ew32(RDTR, adapter->rx_int_delay); 3241 3242 /* irq moderation */ 3243 ew32(RADV, adapter->rx_abs_int_delay); 3244 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3245 e1000e_write_itr(adapter, adapter->itr); 3246 3247 ctrl_ext = er32(CTRL_EXT); 3248 /* Auto-Mask interrupts upon ICR access */ 3249 ctrl_ext |= E1000_CTRL_EXT_IAME; 3250 ew32(IAM, 0xffffffff); 3251 ew32(CTRL_EXT, ctrl_ext); 3252 e1e_flush(); 3253 3254 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3255 * the Base and Length of the Rx Descriptor Ring 3256 */ 3257 rdba = rx_ring->dma; 3258 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3259 ew32(RDBAH(0), (rdba >> 32)); 3260 ew32(RDLEN(0), rdlen); 3261 ew32(RDH(0), 0); 3262 ew32(RDT(0), 0); 3263 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3264 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3265 3266 writel(0, rx_ring->head); 3267 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3268 e1000e_update_rdt_wa(rx_ring, 0); 3269 else 3270 writel(0, rx_ring->tail); 3271 3272 /* Enable Receive Checksum Offload for TCP and UDP */ 3273 rxcsum = er32(RXCSUM); 3274 if (adapter->netdev->features & NETIF_F_RXCSUM) 3275 rxcsum |= E1000_RXCSUM_TUOFL; 3276 else 3277 rxcsum &= ~E1000_RXCSUM_TUOFL; 3278 ew32(RXCSUM, rxcsum); 3279 3280 /* With jumbo frames, excessive C-state transition latencies result 3281 * in dropped transactions. 3282 */ 3283 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3284 u32 lat = 3285 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3286 adapter->max_frame_size) * 8 / 1000; 3287 3288 if (adapter->flags & FLAG_IS_ICH) { 3289 u32 rxdctl = er32(RXDCTL(0)); 3290 3291 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3292 } 3293 3294 dev_info(&adapter->pdev->dev, 3295 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3296 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3297 } else { 3298 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3299 PM_QOS_DEFAULT_VALUE); 3300 } 3301 3302 /* Enable Receives */ 3303 ew32(RCTL, rctl); 3304 } 3305 3306 /** 3307 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3308 * @netdev: network interface device structure 3309 * 3310 * Writes multicast address list to the MTA hash table. 3311 * Returns: -ENOMEM on failure 3312 * 0 on no addresses written 3313 * X on writing X addresses to MTA 3314 */ 3315 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3316 { 3317 struct e1000_adapter *adapter = netdev_priv(netdev); 3318 struct e1000_hw *hw = &adapter->hw; 3319 struct netdev_hw_addr *ha; 3320 u8 *mta_list; 3321 int i; 3322 3323 if (netdev_mc_empty(netdev)) { 3324 /* nothing to program, so clear mc list */ 3325 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3326 return 0; 3327 } 3328 3329 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3330 if (!mta_list) 3331 return -ENOMEM; 3332 3333 /* update_mc_addr_list expects a packed array of only addresses. */ 3334 i = 0; 3335 netdev_for_each_mc_addr(ha, netdev) 3336 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3337 3338 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3339 kfree(mta_list); 3340 3341 return netdev_mc_count(netdev); 3342 } 3343 3344 /** 3345 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3346 * @netdev: network interface device structure 3347 * 3348 * Writes unicast address list to the RAR table. 3349 * Returns: -ENOMEM on failure/insufficient address space 3350 * 0 on no addresses written 3351 * X on writing X addresses to the RAR table 3352 **/ 3353 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3354 { 3355 struct e1000_adapter *adapter = netdev_priv(netdev); 3356 struct e1000_hw *hw = &adapter->hw; 3357 unsigned int rar_entries; 3358 int count = 0; 3359 3360 rar_entries = hw->mac.ops.rar_get_count(hw); 3361 3362 /* save a rar entry for our hardware address */ 3363 rar_entries--; 3364 3365 /* save a rar entry for the LAA workaround */ 3366 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3367 rar_entries--; 3368 3369 /* return ENOMEM indicating insufficient memory for addresses */ 3370 if (netdev_uc_count(netdev) > rar_entries) 3371 return -ENOMEM; 3372 3373 if (!netdev_uc_empty(netdev) && rar_entries) { 3374 struct netdev_hw_addr *ha; 3375 3376 /* write the addresses in reverse order to avoid write 3377 * combining 3378 */ 3379 netdev_for_each_uc_addr(ha, netdev) { 3380 int ret_val; 3381 3382 if (!rar_entries) 3383 break; 3384 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3385 if (ret_val < 0) 3386 return -ENOMEM; 3387 count++; 3388 } 3389 } 3390 3391 /* zero out the remaining RAR entries not used above */ 3392 for (; rar_entries > 0; rar_entries--) { 3393 ew32(RAH(rar_entries), 0); 3394 ew32(RAL(rar_entries), 0); 3395 } 3396 e1e_flush(); 3397 3398 return count; 3399 } 3400 3401 /** 3402 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3403 * @netdev: network interface device structure 3404 * 3405 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3406 * address list or the network interface flags are updated. This routine is 3407 * responsible for configuring the hardware for proper unicast, multicast, 3408 * promiscuous mode, and all-multi behavior. 3409 **/ 3410 static void e1000e_set_rx_mode(struct net_device *netdev) 3411 { 3412 struct e1000_adapter *adapter = netdev_priv(netdev); 3413 struct e1000_hw *hw = &adapter->hw; 3414 u32 rctl; 3415 3416 if (pm_runtime_suspended(netdev->dev.parent)) 3417 return; 3418 3419 /* Check for Promiscuous and All Multicast modes */ 3420 rctl = er32(RCTL); 3421 3422 /* clear the affected bits */ 3423 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3424 3425 if (netdev->flags & IFF_PROMISC) { 3426 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3427 /* Do not hardware filter VLANs in promisc mode */ 3428 e1000e_vlan_filter_disable(adapter); 3429 } else { 3430 int count; 3431 3432 if (netdev->flags & IFF_ALLMULTI) { 3433 rctl |= E1000_RCTL_MPE; 3434 } else { 3435 /* Write addresses to the MTA, if the attempt fails 3436 * then we should just turn on promiscuous mode so 3437 * that we can at least receive multicast traffic 3438 */ 3439 count = e1000e_write_mc_addr_list(netdev); 3440 if (count < 0) 3441 rctl |= E1000_RCTL_MPE; 3442 } 3443 e1000e_vlan_filter_enable(adapter); 3444 /* Write addresses to available RAR registers, if there is not 3445 * sufficient space to store all the addresses then enable 3446 * unicast promiscuous mode 3447 */ 3448 count = e1000e_write_uc_addr_list(netdev); 3449 if (count < 0) 3450 rctl |= E1000_RCTL_UPE; 3451 } 3452 3453 ew32(RCTL, rctl); 3454 3455 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3456 e1000e_vlan_strip_enable(adapter); 3457 else 3458 e1000e_vlan_strip_disable(adapter); 3459 } 3460 3461 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3462 { 3463 struct e1000_hw *hw = &adapter->hw; 3464 u32 mrqc, rxcsum; 3465 u32 rss_key[10]; 3466 int i; 3467 3468 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3469 for (i = 0; i < 10; i++) 3470 ew32(RSSRK(i), rss_key[i]); 3471 3472 /* Direct all traffic to queue 0 */ 3473 for (i = 0; i < 32; i++) 3474 ew32(RETA(i), 0); 3475 3476 /* Disable raw packet checksumming so that RSS hash is placed in 3477 * descriptor on writeback. 3478 */ 3479 rxcsum = er32(RXCSUM); 3480 rxcsum |= E1000_RXCSUM_PCSD; 3481 3482 ew32(RXCSUM, rxcsum); 3483 3484 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3485 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3486 E1000_MRQC_RSS_FIELD_IPV6 | 3487 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3488 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3489 3490 ew32(MRQC, mrqc); 3491 } 3492 3493 /** 3494 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3495 * @adapter: board private structure 3496 * @timinca: pointer to returned time increment attributes 3497 * 3498 * Get attributes for incrementing the System Time Register SYSTIML/H at 3499 * the default base frequency, and set the cyclecounter shift value. 3500 **/ 3501 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3502 { 3503 struct e1000_hw *hw = &adapter->hw; 3504 u32 incvalue, incperiod, shift; 3505 3506 /* Make sure clock is enabled on I217/I218/I219 before checking 3507 * the frequency 3508 */ 3509 if ((hw->mac.type >= e1000_pch_lpt) && 3510 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3511 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3512 u32 fextnvm7 = er32(FEXTNVM7); 3513 3514 if (!(fextnvm7 & BIT(0))) { 3515 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3516 e1e_flush(); 3517 } 3518 } 3519 3520 switch (hw->mac.type) { 3521 case e1000_pch2lan: 3522 /* Stable 96MHz frequency */ 3523 incperiod = INCPERIOD_96MHZ; 3524 incvalue = INCVALUE_96MHZ; 3525 shift = INCVALUE_SHIFT_96MHZ; 3526 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3527 break; 3528 case e1000_pch_lpt: 3529 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3530 /* Stable 96MHz frequency */ 3531 incperiod = INCPERIOD_96MHZ; 3532 incvalue = INCVALUE_96MHZ; 3533 shift = INCVALUE_SHIFT_96MHZ; 3534 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3535 } else { 3536 /* Stable 25MHz frequency */ 3537 incperiod = INCPERIOD_25MHZ; 3538 incvalue = INCVALUE_25MHZ; 3539 shift = INCVALUE_SHIFT_25MHZ; 3540 adapter->cc.shift = shift; 3541 } 3542 break; 3543 case e1000_pch_spt: 3544 /* Stable 24MHz frequency */ 3545 incperiod = INCPERIOD_24MHZ; 3546 incvalue = INCVALUE_24MHZ; 3547 shift = INCVALUE_SHIFT_24MHZ; 3548 adapter->cc.shift = shift; 3549 break; 3550 case e1000_pch_cnp: 3551 case e1000_pch_tgp: 3552 case e1000_pch_adp: 3553 case e1000_pch_mtp: 3554 case e1000_pch_lnp: 3555 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3556 /* Stable 24MHz frequency */ 3557 incperiod = INCPERIOD_24MHZ; 3558 incvalue = INCVALUE_24MHZ; 3559 shift = INCVALUE_SHIFT_24MHZ; 3560 adapter->cc.shift = shift; 3561 } else { 3562 /* Stable 38400KHz frequency */ 3563 incperiod = INCPERIOD_38400KHZ; 3564 incvalue = INCVALUE_38400KHZ; 3565 shift = INCVALUE_SHIFT_38400KHZ; 3566 adapter->cc.shift = shift; 3567 } 3568 break; 3569 case e1000_82574: 3570 case e1000_82583: 3571 /* Stable 25MHz frequency */ 3572 incperiod = INCPERIOD_25MHZ; 3573 incvalue = INCVALUE_25MHZ; 3574 shift = INCVALUE_SHIFT_25MHZ; 3575 adapter->cc.shift = shift; 3576 break; 3577 default: 3578 return -EINVAL; 3579 } 3580 3581 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3582 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3583 3584 return 0; 3585 } 3586 3587 /** 3588 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3589 * @adapter: board private structure 3590 * @config: timestamp configuration 3591 * 3592 * Outgoing time stamping can be enabled and disabled. Play nice and 3593 * disable it when requested, although it shouldn't cause any overhead 3594 * when no packet needs it. At most one packet in the queue may be 3595 * marked for time stamping, otherwise it would be impossible to tell 3596 * for sure to which packet the hardware time stamp belongs. 3597 * 3598 * Incoming time stamping has to be configured via the hardware filters. 3599 * Not all combinations are supported, in particular event type has to be 3600 * specified. Matching the kind of event packet is not supported, with the 3601 * exception of "all V2 events regardless of level 2 or 4". 3602 **/ 3603 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3604 struct hwtstamp_config *config) 3605 { 3606 struct e1000_hw *hw = &adapter->hw; 3607 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3608 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3609 u32 rxmtrl = 0; 3610 u16 rxudp = 0; 3611 bool is_l4 = false; 3612 bool is_l2 = false; 3613 u32 regval; 3614 3615 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3616 return -EINVAL; 3617 3618 switch (config->tx_type) { 3619 case HWTSTAMP_TX_OFF: 3620 tsync_tx_ctl = 0; 3621 break; 3622 case HWTSTAMP_TX_ON: 3623 break; 3624 default: 3625 return -ERANGE; 3626 } 3627 3628 switch (config->rx_filter) { 3629 case HWTSTAMP_FILTER_NONE: 3630 tsync_rx_ctl = 0; 3631 break; 3632 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3633 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3634 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3635 is_l4 = true; 3636 break; 3637 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3639 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3640 is_l4 = true; 3641 break; 3642 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3643 /* Also time stamps V2 L2 Path Delay Request/Response */ 3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3645 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3646 is_l2 = true; 3647 break; 3648 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3649 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3651 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3652 is_l2 = true; 3653 break; 3654 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3655 /* Hardware cannot filter just V2 L4 Sync messages */ 3656 fallthrough; 3657 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3658 /* Also time stamps V2 Path Delay Request/Response. */ 3659 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3660 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3661 is_l2 = true; 3662 is_l4 = true; 3663 break; 3664 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3665 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3666 fallthrough; 3667 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3668 /* Also time stamps V2 Path Delay Request/Response. */ 3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3670 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3671 is_l2 = true; 3672 is_l4 = true; 3673 break; 3674 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3675 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3676 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3677 fallthrough; 3678 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3679 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3680 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3681 is_l2 = true; 3682 is_l4 = true; 3683 break; 3684 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3685 /* For V1, the hardware can only filter Sync messages or 3686 * Delay Request messages but not both so fall-through to 3687 * time stamp all packets. 3688 */ 3689 fallthrough; 3690 case HWTSTAMP_FILTER_NTP_ALL: 3691 case HWTSTAMP_FILTER_ALL: 3692 is_l2 = true; 3693 is_l4 = true; 3694 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3695 config->rx_filter = HWTSTAMP_FILTER_ALL; 3696 break; 3697 default: 3698 return -ERANGE; 3699 } 3700 3701 adapter->hwtstamp_config = *config; 3702 3703 /* enable/disable Tx h/w time stamping */ 3704 regval = er32(TSYNCTXCTL); 3705 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3706 regval |= tsync_tx_ctl; 3707 ew32(TSYNCTXCTL, regval); 3708 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3709 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3710 e_err("Timesync Tx Control register not set as expected\n"); 3711 return -EAGAIN; 3712 } 3713 3714 /* enable/disable Rx h/w time stamping */ 3715 regval = er32(TSYNCRXCTL); 3716 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3717 regval |= tsync_rx_ctl; 3718 ew32(TSYNCRXCTL, regval); 3719 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3720 E1000_TSYNCRXCTL_TYPE_MASK)) != 3721 (regval & (E1000_TSYNCRXCTL_ENABLED | 3722 E1000_TSYNCRXCTL_TYPE_MASK))) { 3723 e_err("Timesync Rx Control register not set as expected\n"); 3724 return -EAGAIN; 3725 } 3726 3727 /* L2: define ethertype filter for time stamped packets */ 3728 if (is_l2) 3729 rxmtrl |= ETH_P_1588; 3730 3731 /* define which PTP packets get time stamped */ 3732 ew32(RXMTRL, rxmtrl); 3733 3734 /* Filter by destination port */ 3735 if (is_l4) { 3736 rxudp = PTP_EV_PORT; 3737 cpu_to_be16s(&rxudp); 3738 } 3739 ew32(RXUDP, rxudp); 3740 3741 e1e_flush(); 3742 3743 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3744 er32(RXSTMPH); 3745 er32(TXSTMPH); 3746 3747 return 0; 3748 } 3749 3750 /** 3751 * e1000_configure - configure the hardware for Rx and Tx 3752 * @adapter: private board structure 3753 **/ 3754 static void e1000_configure(struct e1000_adapter *adapter) 3755 { 3756 struct e1000_ring *rx_ring = adapter->rx_ring; 3757 3758 e1000e_set_rx_mode(adapter->netdev); 3759 3760 e1000_restore_vlan(adapter); 3761 e1000_init_manageability_pt(adapter); 3762 3763 e1000_configure_tx(adapter); 3764 3765 if (adapter->netdev->features & NETIF_F_RXHASH) 3766 e1000e_setup_rss_hash(adapter); 3767 e1000_setup_rctl(adapter); 3768 e1000_configure_rx(adapter); 3769 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3770 } 3771 3772 /** 3773 * e1000e_power_up_phy - restore link in case the phy was powered down 3774 * @adapter: address of board private structure 3775 * 3776 * The phy may be powered down to save power and turn off link when the 3777 * driver is unloaded and wake on lan is not enabled (among others) 3778 * *** this routine MUST be followed by a call to e1000e_reset *** 3779 **/ 3780 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3781 { 3782 if (adapter->hw.phy.ops.power_up) 3783 adapter->hw.phy.ops.power_up(&adapter->hw); 3784 3785 adapter->hw.mac.ops.setup_link(&adapter->hw); 3786 } 3787 3788 /** 3789 * e1000_power_down_phy - Power down the PHY 3790 * @adapter: board private structure 3791 * 3792 * Power down the PHY so no link is implied when interface is down. 3793 * The PHY cannot be powered down if management or WoL is active. 3794 */ 3795 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3796 { 3797 if (adapter->hw.phy.ops.power_down) 3798 adapter->hw.phy.ops.power_down(&adapter->hw); 3799 } 3800 3801 /** 3802 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3803 * @adapter: board private structure 3804 * 3805 * We want to clear all pending descriptors from the TX ring. 3806 * zeroing happens when the HW reads the regs. We assign the ring itself as 3807 * the data of the next descriptor. We don't care about the data we are about 3808 * to reset the HW. 3809 */ 3810 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3811 { 3812 struct e1000_hw *hw = &adapter->hw; 3813 struct e1000_ring *tx_ring = adapter->tx_ring; 3814 struct e1000_tx_desc *tx_desc = NULL; 3815 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3816 u16 size = 512; 3817 3818 tctl = er32(TCTL); 3819 ew32(TCTL, tctl | E1000_TCTL_EN); 3820 tdt = er32(TDT(0)); 3821 BUG_ON(tdt != tx_ring->next_to_use); 3822 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3823 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3824 3825 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3826 tx_desc->upper.data = 0; 3827 /* flush descriptors to memory before notifying the HW */ 3828 wmb(); 3829 tx_ring->next_to_use++; 3830 if (tx_ring->next_to_use == tx_ring->count) 3831 tx_ring->next_to_use = 0; 3832 ew32(TDT(0), tx_ring->next_to_use); 3833 usleep_range(200, 250); 3834 } 3835 3836 /** 3837 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3838 * @adapter: board private structure 3839 * 3840 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3841 */ 3842 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3843 { 3844 u32 rctl, rxdctl; 3845 struct e1000_hw *hw = &adapter->hw; 3846 3847 rctl = er32(RCTL); 3848 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3849 e1e_flush(); 3850 usleep_range(100, 150); 3851 3852 rxdctl = er32(RXDCTL(0)); 3853 /* zero the lower 14 bits (prefetch and host thresholds) */ 3854 rxdctl &= 0xffffc000; 3855 3856 /* update thresholds: prefetch threshold to 31, host threshold to 1 3857 * and make sure the granularity is "descriptors" and not "cache lines" 3858 */ 3859 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3860 3861 ew32(RXDCTL(0), rxdctl); 3862 /* momentarily enable the RX ring for the changes to take effect */ 3863 ew32(RCTL, rctl | E1000_RCTL_EN); 3864 e1e_flush(); 3865 usleep_range(100, 150); 3866 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3867 } 3868 3869 /** 3870 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3871 * @adapter: board private structure 3872 * 3873 * In i219, the descriptor rings must be emptied before resetting the HW 3874 * or before changing the device state to D3 during runtime (runtime PM). 3875 * 3876 * Failure to do this will cause the HW to enter a unit hang state which can 3877 * only be released by PCI reset on the device 3878 * 3879 */ 3880 3881 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3882 { 3883 u16 hang_state; 3884 u32 fext_nvm11, tdlen; 3885 struct e1000_hw *hw = &adapter->hw; 3886 3887 /* First, disable MULR fix in FEXTNVM11 */ 3888 fext_nvm11 = er32(FEXTNVM11); 3889 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3890 ew32(FEXTNVM11, fext_nvm11); 3891 /* do nothing if we're not in faulty state, or if the queue is empty */ 3892 tdlen = er32(TDLEN(0)); 3893 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3894 &hang_state); 3895 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3896 return; 3897 e1000_flush_tx_ring(adapter); 3898 /* recheck, maybe the fault is caused by the rx ring */ 3899 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3900 &hang_state); 3901 if (hang_state & FLUSH_DESC_REQUIRED) 3902 e1000_flush_rx_ring(adapter); 3903 } 3904 3905 /** 3906 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3907 * @adapter: board private structure 3908 * 3909 * When the MAC is reset, all hardware bits for timesync will be reset to the 3910 * default values. This function will restore the settings last in place. 3911 * Since the clock SYSTIME registers are reset, we will simply restore the 3912 * cyclecounter to the kernel real clock time. 3913 **/ 3914 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3915 { 3916 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3917 struct e1000_hw *hw = &adapter->hw; 3918 unsigned long flags; 3919 u32 timinca; 3920 s32 ret_val; 3921 3922 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3923 return; 3924 3925 if (info->adjfreq) { 3926 /* restore the previous ptp frequency delta */ 3927 ret_val = info->adjfreq(info, adapter->ptp_delta); 3928 } else { 3929 /* set the default base frequency if no adjustment possible */ 3930 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3931 if (!ret_val) 3932 ew32(TIMINCA, timinca); 3933 } 3934 3935 if (ret_val) { 3936 dev_warn(&adapter->pdev->dev, 3937 "Failed to restore TIMINCA clock rate delta: %d\n", 3938 ret_val); 3939 return; 3940 } 3941 3942 /* reset the systim ns time counter */ 3943 spin_lock_irqsave(&adapter->systim_lock, flags); 3944 timecounter_init(&adapter->tc, &adapter->cc, 3945 ktime_to_ns(ktime_get_real())); 3946 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3947 3948 /* restore the previous hwtstamp configuration settings */ 3949 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3950 } 3951 3952 /** 3953 * e1000e_reset - bring the hardware into a known good state 3954 * @adapter: board private structure 3955 * 3956 * This function boots the hardware and enables some settings that 3957 * require a configuration cycle of the hardware - those cannot be 3958 * set/changed during runtime. After reset the device needs to be 3959 * properly configured for Rx, Tx etc. 3960 */ 3961 void e1000e_reset(struct e1000_adapter *adapter) 3962 { 3963 struct e1000_mac_info *mac = &adapter->hw.mac; 3964 struct e1000_fc_info *fc = &adapter->hw.fc; 3965 struct e1000_hw *hw = &adapter->hw; 3966 u32 tx_space, min_tx_space, min_rx_space; 3967 u32 pba = adapter->pba; 3968 u16 hwm; 3969 3970 /* reset Packet Buffer Allocation to default */ 3971 ew32(PBA, pba); 3972 3973 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3974 /* To maintain wire speed transmits, the Tx FIFO should be 3975 * large enough to accommodate two full transmit packets, 3976 * rounded up to the next 1KB and expressed in KB. Likewise, 3977 * the Rx FIFO should be large enough to accommodate at least 3978 * one full receive packet and is similarly rounded up and 3979 * expressed in KB. 3980 */ 3981 pba = er32(PBA); 3982 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3983 tx_space = pba >> 16; 3984 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3985 pba &= 0xffff; 3986 /* the Tx fifo also stores 16 bytes of information about the Tx 3987 * but don't include ethernet FCS because hardware appends it 3988 */ 3989 min_tx_space = (adapter->max_frame_size + 3990 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3991 min_tx_space = ALIGN(min_tx_space, 1024); 3992 min_tx_space >>= 10; 3993 /* software strips receive CRC, so leave room for it */ 3994 min_rx_space = adapter->max_frame_size; 3995 min_rx_space = ALIGN(min_rx_space, 1024); 3996 min_rx_space >>= 10; 3997 3998 /* If current Tx allocation is less than the min Tx FIFO size, 3999 * and the min Tx FIFO size is less than the current Rx FIFO 4000 * allocation, take space away from current Rx allocation 4001 */ 4002 if ((tx_space < min_tx_space) && 4003 ((min_tx_space - tx_space) < pba)) { 4004 pba -= min_tx_space - tx_space; 4005 4006 /* if short on Rx space, Rx wins and must trump Tx 4007 * adjustment 4008 */ 4009 if (pba < min_rx_space) 4010 pba = min_rx_space; 4011 } 4012 4013 ew32(PBA, pba); 4014 } 4015 4016 /* flow control settings 4017 * 4018 * The high water mark must be low enough to fit one full frame 4019 * (or the size used for early receive) above it in the Rx FIFO. 4020 * Set it to the lower of: 4021 * - 90% of the Rx FIFO size, and 4022 * - the full Rx FIFO size minus one full frame 4023 */ 4024 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4025 fc->pause_time = 0xFFFF; 4026 else 4027 fc->pause_time = E1000_FC_PAUSE_TIME; 4028 fc->send_xon = true; 4029 fc->current_mode = fc->requested_mode; 4030 4031 switch (hw->mac.type) { 4032 case e1000_ich9lan: 4033 case e1000_ich10lan: 4034 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4035 pba = 14; 4036 ew32(PBA, pba); 4037 fc->high_water = 0x2800; 4038 fc->low_water = fc->high_water - 8; 4039 break; 4040 } 4041 fallthrough; 4042 default: 4043 hwm = min(((pba << 10) * 9 / 10), 4044 ((pba << 10) - adapter->max_frame_size)); 4045 4046 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4047 fc->low_water = fc->high_water - 8; 4048 break; 4049 case e1000_pchlan: 4050 /* Workaround PCH LOM adapter hangs with certain network 4051 * loads. If hangs persist, try disabling Tx flow control. 4052 */ 4053 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4054 fc->high_water = 0x3500; 4055 fc->low_water = 0x1500; 4056 } else { 4057 fc->high_water = 0x5000; 4058 fc->low_water = 0x3000; 4059 } 4060 fc->refresh_time = 0x1000; 4061 break; 4062 case e1000_pch2lan: 4063 case e1000_pch_lpt: 4064 case e1000_pch_spt: 4065 case e1000_pch_cnp: 4066 case e1000_pch_tgp: 4067 case e1000_pch_adp: 4068 case e1000_pch_mtp: 4069 case e1000_pch_lnp: 4070 fc->refresh_time = 0xFFFF; 4071 fc->pause_time = 0xFFFF; 4072 4073 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4074 fc->high_water = 0x05C20; 4075 fc->low_water = 0x05048; 4076 break; 4077 } 4078 4079 pba = 14; 4080 ew32(PBA, pba); 4081 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4082 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4083 break; 4084 } 4085 4086 /* Alignment of Tx data is on an arbitrary byte boundary with the 4087 * maximum size per Tx descriptor limited only to the transmit 4088 * allocation of the packet buffer minus 96 bytes with an upper 4089 * limit of 24KB due to receive synchronization limitations. 4090 */ 4091 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4092 24 << 10); 4093 4094 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4095 * fit in receive buffer. 4096 */ 4097 if (adapter->itr_setting & 0x3) { 4098 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4099 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4100 dev_info(&adapter->pdev->dev, 4101 "Interrupt Throttle Rate off\n"); 4102 adapter->flags2 |= FLAG2_DISABLE_AIM; 4103 e1000e_write_itr(adapter, 0); 4104 } 4105 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4106 dev_info(&adapter->pdev->dev, 4107 "Interrupt Throttle Rate on\n"); 4108 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4109 adapter->itr = 20000; 4110 e1000e_write_itr(adapter, adapter->itr); 4111 } 4112 } 4113 4114 if (hw->mac.type >= e1000_pch_spt) 4115 e1000_flush_desc_rings(adapter); 4116 /* Allow time for pending master requests to run */ 4117 mac->ops.reset_hw(hw); 4118 4119 /* For parts with AMT enabled, let the firmware know 4120 * that the network interface is in control 4121 */ 4122 if (adapter->flags & FLAG_HAS_AMT) 4123 e1000e_get_hw_control(adapter); 4124 4125 ew32(WUC, 0); 4126 4127 if (mac->ops.init_hw(hw)) 4128 e_err("Hardware Error\n"); 4129 4130 e1000_update_mng_vlan(adapter); 4131 4132 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4133 ew32(VET, ETH_P_8021Q); 4134 4135 e1000e_reset_adaptive(hw); 4136 4137 /* restore systim and hwtstamp settings */ 4138 e1000e_systim_reset(adapter); 4139 4140 /* Set EEE advertisement as appropriate */ 4141 if (adapter->flags2 & FLAG2_HAS_EEE) { 4142 s32 ret_val; 4143 u16 adv_addr; 4144 4145 switch (hw->phy.type) { 4146 case e1000_phy_82579: 4147 adv_addr = I82579_EEE_ADVERTISEMENT; 4148 break; 4149 case e1000_phy_i217: 4150 adv_addr = I217_EEE_ADVERTISEMENT; 4151 break; 4152 default: 4153 dev_err(&adapter->pdev->dev, 4154 "Invalid PHY type setting EEE advertisement\n"); 4155 return; 4156 } 4157 4158 ret_val = hw->phy.ops.acquire(hw); 4159 if (ret_val) { 4160 dev_err(&adapter->pdev->dev, 4161 "EEE advertisement - unable to acquire PHY\n"); 4162 return; 4163 } 4164 4165 e1000_write_emi_reg_locked(hw, adv_addr, 4166 hw->dev_spec.ich8lan.eee_disable ? 4167 0 : adapter->eee_advert); 4168 4169 hw->phy.ops.release(hw); 4170 } 4171 4172 if (!netif_running(adapter->netdev) && 4173 !test_bit(__E1000_TESTING, &adapter->state)) 4174 e1000_power_down_phy(adapter); 4175 4176 e1000_get_phy_info(hw); 4177 4178 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4179 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4180 u16 phy_data = 0; 4181 /* speed up time to link by disabling smart power down, ignore 4182 * the return value of this function because there is nothing 4183 * different we would do if it failed 4184 */ 4185 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4186 phy_data &= ~IGP02E1000_PM_SPD; 4187 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4188 } 4189 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4190 u32 reg; 4191 4192 /* Fextnvm7 @ 0xe4[2] = 1 */ 4193 reg = er32(FEXTNVM7); 4194 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4195 ew32(FEXTNVM7, reg); 4196 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4197 reg = er32(FEXTNVM9); 4198 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4199 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4200 ew32(FEXTNVM9, reg); 4201 } 4202 4203 } 4204 4205 /** 4206 * e1000e_trigger_lsc - trigger an LSC interrupt 4207 * @adapter: 4208 * 4209 * Fire a link status change interrupt to start the watchdog. 4210 **/ 4211 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4212 { 4213 struct e1000_hw *hw = &adapter->hw; 4214 4215 if (adapter->msix_entries) 4216 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4217 else 4218 ew32(ICS, E1000_ICS_LSC); 4219 } 4220 4221 void e1000e_up(struct e1000_adapter *adapter) 4222 { 4223 /* hardware has been reset, we need to reload some things */ 4224 e1000_configure(adapter); 4225 4226 clear_bit(__E1000_DOWN, &adapter->state); 4227 4228 if (adapter->msix_entries) 4229 e1000_configure_msix(adapter); 4230 e1000_irq_enable(adapter); 4231 4232 /* Tx queue started by watchdog timer when link is up */ 4233 4234 e1000e_trigger_lsc(adapter); 4235 } 4236 4237 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4238 { 4239 struct e1000_hw *hw = &adapter->hw; 4240 4241 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4242 return; 4243 4244 /* flush pending descriptor writebacks to memory */ 4245 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4246 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4247 4248 /* execute the writes immediately */ 4249 e1e_flush(); 4250 4251 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4252 * write is successful 4253 */ 4254 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4255 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4256 4257 /* execute the writes immediately */ 4258 e1e_flush(); 4259 } 4260 4261 static void e1000e_update_stats(struct e1000_adapter *adapter); 4262 4263 /** 4264 * e1000e_down - quiesce the device and optionally reset the hardware 4265 * @adapter: board private structure 4266 * @reset: boolean flag to reset the hardware or not 4267 */ 4268 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4269 { 4270 struct net_device *netdev = adapter->netdev; 4271 struct e1000_hw *hw = &adapter->hw; 4272 u32 tctl, rctl; 4273 4274 /* signal that we're down so the interrupt handler does not 4275 * reschedule our watchdog timer 4276 */ 4277 set_bit(__E1000_DOWN, &adapter->state); 4278 4279 netif_carrier_off(netdev); 4280 4281 /* disable receives in the hardware */ 4282 rctl = er32(RCTL); 4283 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4284 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4285 /* flush and sleep below */ 4286 4287 netif_stop_queue(netdev); 4288 4289 /* disable transmits in the hardware */ 4290 tctl = er32(TCTL); 4291 tctl &= ~E1000_TCTL_EN; 4292 ew32(TCTL, tctl); 4293 4294 /* flush both disables and wait for them to finish */ 4295 e1e_flush(); 4296 usleep_range(10000, 11000); 4297 4298 e1000_irq_disable(adapter); 4299 4300 napi_synchronize(&adapter->napi); 4301 4302 del_timer_sync(&adapter->watchdog_timer); 4303 del_timer_sync(&adapter->phy_info_timer); 4304 4305 spin_lock(&adapter->stats64_lock); 4306 e1000e_update_stats(adapter); 4307 spin_unlock(&adapter->stats64_lock); 4308 4309 e1000e_flush_descriptors(adapter); 4310 4311 adapter->link_speed = 0; 4312 adapter->link_duplex = 0; 4313 4314 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4315 if ((hw->mac.type >= e1000_pch2lan) && 4316 (adapter->netdev->mtu > ETH_DATA_LEN) && 4317 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4318 e_dbg("failed to disable jumbo frame workaround mode\n"); 4319 4320 if (!pci_channel_offline(adapter->pdev)) { 4321 if (reset) 4322 e1000e_reset(adapter); 4323 else if (hw->mac.type >= e1000_pch_spt) 4324 e1000_flush_desc_rings(adapter); 4325 } 4326 e1000_clean_tx_ring(adapter->tx_ring); 4327 e1000_clean_rx_ring(adapter->rx_ring); 4328 } 4329 4330 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4331 { 4332 might_sleep(); 4333 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4334 usleep_range(1000, 1100); 4335 e1000e_down(adapter, true); 4336 e1000e_up(adapter); 4337 clear_bit(__E1000_RESETTING, &adapter->state); 4338 } 4339 4340 /** 4341 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4342 * @hw: pointer to the HW structure 4343 * @systim: PHC time value read, sanitized and returned 4344 * @sts: structure to hold system time before and after reading SYSTIML, 4345 * may be NULL 4346 * 4347 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4348 * check to see that the time is incrementing at a reasonable 4349 * rate and is a multiple of incvalue. 4350 **/ 4351 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4352 struct ptp_system_timestamp *sts) 4353 { 4354 u64 time_delta, rem, temp; 4355 u64 systim_next; 4356 u32 incvalue; 4357 int i; 4358 4359 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4360 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4361 /* latch SYSTIMH on read of SYSTIML */ 4362 ptp_read_system_prets(sts); 4363 systim_next = (u64)er32(SYSTIML); 4364 ptp_read_system_postts(sts); 4365 systim_next |= (u64)er32(SYSTIMH) << 32; 4366 4367 time_delta = systim_next - systim; 4368 temp = time_delta; 4369 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4370 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4371 4372 systim = systim_next; 4373 4374 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4375 break; 4376 } 4377 4378 return systim; 4379 } 4380 4381 /** 4382 * e1000e_read_systim - read SYSTIM register 4383 * @adapter: board private structure 4384 * @sts: structure which will contain system time before and after reading 4385 * SYSTIML, may be NULL 4386 **/ 4387 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4388 struct ptp_system_timestamp *sts) 4389 { 4390 struct e1000_hw *hw = &adapter->hw; 4391 u32 systimel, systimel_2, systimeh; 4392 u64 systim; 4393 /* SYSTIMH latching upon SYSTIML read does not work well. 4394 * This means that if SYSTIML overflows after we read it but before 4395 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4396 * will experience a huge non linear increment in the systime value 4397 * to fix that we test for overflow and if true, we re-read systime. 4398 */ 4399 ptp_read_system_prets(sts); 4400 systimel = er32(SYSTIML); 4401 ptp_read_system_postts(sts); 4402 systimeh = er32(SYSTIMH); 4403 /* Is systimel is so large that overflow is possible? */ 4404 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4405 ptp_read_system_prets(sts); 4406 systimel_2 = er32(SYSTIML); 4407 ptp_read_system_postts(sts); 4408 if (systimel > systimel_2) { 4409 /* There was an overflow, read again SYSTIMH, and use 4410 * systimel_2 4411 */ 4412 systimeh = er32(SYSTIMH); 4413 systimel = systimel_2; 4414 } 4415 } 4416 systim = (u64)systimel; 4417 systim |= (u64)systimeh << 32; 4418 4419 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4420 systim = e1000e_sanitize_systim(hw, systim, sts); 4421 4422 return systim; 4423 } 4424 4425 /** 4426 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4427 * @cc: cyclecounter structure 4428 **/ 4429 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4430 { 4431 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4432 cc); 4433 4434 return e1000e_read_systim(adapter, NULL); 4435 } 4436 4437 /** 4438 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4439 * @adapter: board private structure to initialize 4440 * 4441 * e1000_sw_init initializes the Adapter private data structure. 4442 * Fields are initialized based on PCI device information and 4443 * OS network device settings (MTU size). 4444 **/ 4445 static int e1000_sw_init(struct e1000_adapter *adapter) 4446 { 4447 struct net_device *netdev = adapter->netdev; 4448 4449 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4450 adapter->rx_ps_bsize0 = 128; 4451 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4452 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4453 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4454 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4455 4456 spin_lock_init(&adapter->stats64_lock); 4457 4458 e1000e_set_interrupt_capability(adapter); 4459 4460 if (e1000_alloc_queues(adapter)) 4461 return -ENOMEM; 4462 4463 /* Setup hardware time stamping cyclecounter */ 4464 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4465 adapter->cc.read = e1000e_cyclecounter_read; 4466 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4467 adapter->cc.mult = 1; 4468 /* cc.shift set in e1000e_get_base_tininca() */ 4469 4470 spin_lock_init(&adapter->systim_lock); 4471 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4472 } 4473 4474 /* Explicitly disable IRQ since the NIC can be in any state. */ 4475 e1000_irq_disable(adapter); 4476 4477 set_bit(__E1000_DOWN, &adapter->state); 4478 return 0; 4479 } 4480 4481 /** 4482 * e1000_intr_msi_test - Interrupt Handler 4483 * @irq: interrupt number 4484 * @data: pointer to a network interface device structure 4485 **/ 4486 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4487 { 4488 struct net_device *netdev = data; 4489 struct e1000_adapter *adapter = netdev_priv(netdev); 4490 struct e1000_hw *hw = &adapter->hw; 4491 u32 icr = er32(ICR); 4492 4493 e_dbg("icr is %08X\n", icr); 4494 if (icr & E1000_ICR_RXSEQ) { 4495 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4496 /* Force memory writes to complete before acknowledging the 4497 * interrupt is handled. 4498 */ 4499 wmb(); 4500 } 4501 4502 return IRQ_HANDLED; 4503 } 4504 4505 /** 4506 * e1000_test_msi_interrupt - Returns 0 for successful test 4507 * @adapter: board private struct 4508 * 4509 * code flow taken from tg3.c 4510 **/ 4511 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4512 { 4513 struct net_device *netdev = adapter->netdev; 4514 struct e1000_hw *hw = &adapter->hw; 4515 int err; 4516 4517 /* poll_enable hasn't been called yet, so don't need disable */ 4518 /* clear any pending events */ 4519 er32(ICR); 4520 4521 /* free the real vector and request a test handler */ 4522 e1000_free_irq(adapter); 4523 e1000e_reset_interrupt_capability(adapter); 4524 4525 /* Assume that the test fails, if it succeeds then the test 4526 * MSI irq handler will unset this flag 4527 */ 4528 adapter->flags |= FLAG_MSI_TEST_FAILED; 4529 4530 err = pci_enable_msi(adapter->pdev); 4531 if (err) 4532 goto msi_test_failed; 4533 4534 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4535 netdev->name, netdev); 4536 if (err) { 4537 pci_disable_msi(adapter->pdev); 4538 goto msi_test_failed; 4539 } 4540 4541 /* Force memory writes to complete before enabling and firing an 4542 * interrupt. 4543 */ 4544 wmb(); 4545 4546 e1000_irq_enable(adapter); 4547 4548 /* fire an unusual interrupt on the test handler */ 4549 ew32(ICS, E1000_ICS_RXSEQ); 4550 e1e_flush(); 4551 msleep(100); 4552 4553 e1000_irq_disable(adapter); 4554 4555 rmb(); /* read flags after interrupt has been fired */ 4556 4557 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4558 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4559 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4560 } else { 4561 e_dbg("MSI interrupt test succeeded!\n"); 4562 } 4563 4564 free_irq(adapter->pdev->irq, netdev); 4565 pci_disable_msi(adapter->pdev); 4566 4567 msi_test_failed: 4568 e1000e_set_interrupt_capability(adapter); 4569 return e1000_request_irq(adapter); 4570 } 4571 4572 /** 4573 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4574 * @adapter: board private struct 4575 * 4576 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4577 **/ 4578 static int e1000_test_msi(struct e1000_adapter *adapter) 4579 { 4580 int err; 4581 u16 pci_cmd; 4582 4583 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4584 return 0; 4585 4586 /* disable SERR in case the MSI write causes a master abort */ 4587 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4588 if (pci_cmd & PCI_COMMAND_SERR) 4589 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4590 pci_cmd & ~PCI_COMMAND_SERR); 4591 4592 err = e1000_test_msi_interrupt(adapter); 4593 4594 /* re-enable SERR */ 4595 if (pci_cmd & PCI_COMMAND_SERR) { 4596 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4597 pci_cmd |= PCI_COMMAND_SERR; 4598 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4599 } 4600 4601 return err; 4602 } 4603 4604 /** 4605 * e1000e_open - Called when a network interface is made active 4606 * @netdev: network interface device structure 4607 * 4608 * Returns 0 on success, negative value on failure 4609 * 4610 * The open entry point is called when a network interface is made 4611 * active by the system (IFF_UP). At this point all resources needed 4612 * for transmit and receive operations are allocated, the interrupt 4613 * handler is registered with the OS, the watchdog timer is started, 4614 * and the stack is notified that the interface is ready. 4615 **/ 4616 int e1000e_open(struct net_device *netdev) 4617 { 4618 struct e1000_adapter *adapter = netdev_priv(netdev); 4619 struct e1000_hw *hw = &adapter->hw; 4620 struct pci_dev *pdev = adapter->pdev; 4621 int err; 4622 4623 /* disallow open during test */ 4624 if (test_bit(__E1000_TESTING, &adapter->state)) 4625 return -EBUSY; 4626 4627 pm_runtime_get_sync(&pdev->dev); 4628 4629 netif_carrier_off(netdev); 4630 netif_stop_queue(netdev); 4631 4632 /* allocate transmit descriptors */ 4633 err = e1000e_setup_tx_resources(adapter->tx_ring); 4634 if (err) 4635 goto err_setup_tx; 4636 4637 /* allocate receive descriptors */ 4638 err = e1000e_setup_rx_resources(adapter->rx_ring); 4639 if (err) 4640 goto err_setup_rx; 4641 4642 /* If AMT is enabled, let the firmware know that the network 4643 * interface is now open and reset the part to a known state. 4644 */ 4645 if (adapter->flags & FLAG_HAS_AMT) { 4646 e1000e_get_hw_control(adapter); 4647 e1000e_reset(adapter); 4648 } 4649 4650 e1000e_power_up_phy(adapter); 4651 4652 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4653 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4654 e1000_update_mng_vlan(adapter); 4655 4656 /* DMA latency requirement to workaround jumbo issue */ 4657 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4658 4659 /* before we allocate an interrupt, we must be ready to handle it. 4660 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4661 * as soon as we call pci_request_irq, so we have to setup our 4662 * clean_rx handler before we do so. 4663 */ 4664 e1000_configure(adapter); 4665 4666 err = e1000_request_irq(adapter); 4667 if (err) 4668 goto err_req_irq; 4669 4670 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4671 * ignore e1000e MSI messages, which means we need to test our MSI 4672 * interrupt now 4673 */ 4674 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4675 err = e1000_test_msi(adapter); 4676 if (err) { 4677 e_err("Interrupt allocation failed\n"); 4678 goto err_req_irq; 4679 } 4680 } 4681 4682 /* From here on the code is the same as e1000e_up() */ 4683 clear_bit(__E1000_DOWN, &adapter->state); 4684 4685 napi_enable(&adapter->napi); 4686 4687 e1000_irq_enable(adapter); 4688 4689 adapter->tx_hang_recheck = false; 4690 4691 hw->mac.get_link_status = true; 4692 pm_runtime_put(&pdev->dev); 4693 4694 e1000e_trigger_lsc(adapter); 4695 4696 return 0; 4697 4698 err_req_irq: 4699 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4700 e1000e_release_hw_control(adapter); 4701 e1000_power_down_phy(adapter); 4702 e1000e_free_rx_resources(adapter->rx_ring); 4703 err_setup_rx: 4704 e1000e_free_tx_resources(adapter->tx_ring); 4705 err_setup_tx: 4706 e1000e_reset(adapter); 4707 pm_runtime_put_sync(&pdev->dev); 4708 4709 return err; 4710 } 4711 4712 /** 4713 * e1000e_close - Disables a network interface 4714 * @netdev: network interface device structure 4715 * 4716 * Returns 0, this is not allowed to fail 4717 * 4718 * The close entry point is called when an interface is de-activated 4719 * by the OS. The hardware is still under the drivers control, but 4720 * needs to be disabled. A global MAC reset is issued to stop the 4721 * hardware, and all transmit and receive resources are freed. 4722 **/ 4723 int e1000e_close(struct net_device *netdev) 4724 { 4725 struct e1000_adapter *adapter = netdev_priv(netdev); 4726 struct pci_dev *pdev = adapter->pdev; 4727 int count = E1000_CHECK_RESET_COUNT; 4728 4729 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4730 usleep_range(10000, 11000); 4731 4732 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4733 4734 pm_runtime_get_sync(&pdev->dev); 4735 4736 if (netif_device_present(netdev)) { 4737 e1000e_down(adapter, true); 4738 e1000_free_irq(adapter); 4739 4740 /* Link status message must follow this format */ 4741 netdev_info(netdev, "NIC Link is Down\n"); 4742 } 4743 4744 napi_disable(&adapter->napi); 4745 4746 e1000e_free_tx_resources(adapter->tx_ring); 4747 e1000e_free_rx_resources(adapter->rx_ring); 4748 4749 /* kill manageability vlan ID if supported, but not if a vlan with 4750 * the same ID is registered on the host OS (let 8021q kill it) 4751 */ 4752 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4753 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4754 adapter->mng_vlan_id); 4755 4756 /* If AMT is enabled, let the firmware know that the network 4757 * interface is now closed 4758 */ 4759 if ((adapter->flags & FLAG_HAS_AMT) && 4760 !test_bit(__E1000_TESTING, &adapter->state)) 4761 e1000e_release_hw_control(adapter); 4762 4763 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4764 4765 pm_runtime_put_sync(&pdev->dev); 4766 4767 return 0; 4768 } 4769 4770 /** 4771 * e1000_set_mac - Change the Ethernet Address of the NIC 4772 * @netdev: network interface device structure 4773 * @p: pointer to an address structure 4774 * 4775 * Returns 0 on success, negative on failure 4776 **/ 4777 static int e1000_set_mac(struct net_device *netdev, void *p) 4778 { 4779 struct e1000_adapter *adapter = netdev_priv(netdev); 4780 struct e1000_hw *hw = &adapter->hw; 4781 struct sockaddr *addr = p; 4782 4783 if (!is_valid_ether_addr(addr->sa_data)) 4784 return -EADDRNOTAVAIL; 4785 4786 eth_hw_addr_set(netdev, addr->sa_data); 4787 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4788 4789 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4790 4791 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4792 /* activate the work around */ 4793 e1000e_set_laa_state_82571(&adapter->hw, 1); 4794 4795 /* Hold a copy of the LAA in RAR[14] This is done so that 4796 * between the time RAR[0] gets clobbered and the time it 4797 * gets fixed (in e1000_watchdog), the actual LAA is in one 4798 * of the RARs and no incoming packets directed to this port 4799 * are dropped. Eventually the LAA will be in RAR[0] and 4800 * RAR[14] 4801 */ 4802 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4803 adapter->hw.mac.rar_entry_count - 1); 4804 } 4805 4806 return 0; 4807 } 4808 4809 /** 4810 * e1000e_update_phy_task - work thread to update phy 4811 * @work: pointer to our work struct 4812 * 4813 * this worker thread exists because we must acquire a 4814 * semaphore to read the phy, which we could msleep while 4815 * waiting for it, and we can't msleep in a timer. 4816 **/ 4817 static void e1000e_update_phy_task(struct work_struct *work) 4818 { 4819 struct e1000_adapter *adapter = container_of(work, 4820 struct e1000_adapter, 4821 update_phy_task); 4822 struct e1000_hw *hw = &adapter->hw; 4823 4824 if (test_bit(__E1000_DOWN, &adapter->state)) 4825 return; 4826 4827 e1000_get_phy_info(hw); 4828 4829 /* Enable EEE on 82579 after link up */ 4830 if (hw->phy.type >= e1000_phy_82579) 4831 e1000_set_eee_pchlan(hw); 4832 } 4833 4834 /** 4835 * e1000_update_phy_info - timre call-back to update PHY info 4836 * @t: pointer to timer_list containing private info adapter 4837 * 4838 * Need to wait a few seconds after link up to get diagnostic information from 4839 * the phy 4840 **/ 4841 static void e1000_update_phy_info(struct timer_list *t) 4842 { 4843 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4844 4845 if (test_bit(__E1000_DOWN, &adapter->state)) 4846 return; 4847 4848 schedule_work(&adapter->update_phy_task); 4849 } 4850 4851 /** 4852 * e1000e_update_phy_stats - Update the PHY statistics counters 4853 * @adapter: board private structure 4854 * 4855 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4856 **/ 4857 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4858 { 4859 struct e1000_hw *hw = &adapter->hw; 4860 s32 ret_val; 4861 u16 phy_data; 4862 4863 ret_val = hw->phy.ops.acquire(hw); 4864 if (ret_val) 4865 return; 4866 4867 /* A page set is expensive so check if already on desired page. 4868 * If not, set to the page with the PHY status registers. 4869 */ 4870 hw->phy.addr = 1; 4871 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4872 &phy_data); 4873 if (ret_val) 4874 goto release; 4875 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4876 ret_val = hw->phy.ops.set_page(hw, 4877 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4878 if (ret_val) 4879 goto release; 4880 } 4881 4882 /* Single Collision Count */ 4883 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4884 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4885 if (!ret_val) 4886 adapter->stats.scc += phy_data; 4887 4888 /* Excessive Collision Count */ 4889 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4890 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4891 if (!ret_val) 4892 adapter->stats.ecol += phy_data; 4893 4894 /* Multiple Collision Count */ 4895 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4896 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4897 if (!ret_val) 4898 adapter->stats.mcc += phy_data; 4899 4900 /* Late Collision Count */ 4901 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4902 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4903 if (!ret_val) 4904 adapter->stats.latecol += phy_data; 4905 4906 /* Collision Count - also used for adaptive IFS */ 4907 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4908 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4909 if (!ret_val) 4910 hw->mac.collision_delta = phy_data; 4911 4912 /* Defer Count */ 4913 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4914 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4915 if (!ret_val) 4916 adapter->stats.dc += phy_data; 4917 4918 /* Transmit with no CRS */ 4919 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4920 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4921 if (!ret_val) 4922 adapter->stats.tncrs += phy_data; 4923 4924 release: 4925 hw->phy.ops.release(hw); 4926 } 4927 4928 /** 4929 * e1000e_update_stats - Update the board statistics counters 4930 * @adapter: board private structure 4931 **/ 4932 static void e1000e_update_stats(struct e1000_adapter *adapter) 4933 { 4934 struct net_device *netdev = adapter->netdev; 4935 struct e1000_hw *hw = &adapter->hw; 4936 struct pci_dev *pdev = adapter->pdev; 4937 4938 /* Prevent stats update while adapter is being reset, or if the pci 4939 * connection is down. 4940 */ 4941 if (adapter->link_speed == 0) 4942 return; 4943 if (pci_channel_offline(pdev)) 4944 return; 4945 4946 adapter->stats.crcerrs += er32(CRCERRS); 4947 adapter->stats.gprc += er32(GPRC); 4948 adapter->stats.gorc += er32(GORCL); 4949 er32(GORCH); /* Clear gorc */ 4950 adapter->stats.bprc += er32(BPRC); 4951 adapter->stats.mprc += er32(MPRC); 4952 adapter->stats.roc += er32(ROC); 4953 4954 adapter->stats.mpc += er32(MPC); 4955 4956 /* Half-duplex statistics */ 4957 if (adapter->link_duplex == HALF_DUPLEX) { 4958 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4959 e1000e_update_phy_stats(adapter); 4960 } else { 4961 adapter->stats.scc += er32(SCC); 4962 adapter->stats.ecol += er32(ECOL); 4963 adapter->stats.mcc += er32(MCC); 4964 adapter->stats.latecol += er32(LATECOL); 4965 adapter->stats.dc += er32(DC); 4966 4967 hw->mac.collision_delta = er32(COLC); 4968 4969 if ((hw->mac.type != e1000_82574) && 4970 (hw->mac.type != e1000_82583)) 4971 adapter->stats.tncrs += er32(TNCRS); 4972 } 4973 adapter->stats.colc += hw->mac.collision_delta; 4974 } 4975 4976 adapter->stats.xonrxc += er32(XONRXC); 4977 adapter->stats.xontxc += er32(XONTXC); 4978 adapter->stats.xoffrxc += er32(XOFFRXC); 4979 adapter->stats.xofftxc += er32(XOFFTXC); 4980 adapter->stats.gptc += er32(GPTC); 4981 adapter->stats.gotc += er32(GOTCL); 4982 er32(GOTCH); /* Clear gotc */ 4983 adapter->stats.rnbc += er32(RNBC); 4984 adapter->stats.ruc += er32(RUC); 4985 4986 adapter->stats.mptc += er32(MPTC); 4987 adapter->stats.bptc += er32(BPTC); 4988 4989 /* used for adaptive IFS */ 4990 4991 hw->mac.tx_packet_delta = er32(TPT); 4992 adapter->stats.tpt += hw->mac.tx_packet_delta; 4993 4994 adapter->stats.algnerrc += er32(ALGNERRC); 4995 adapter->stats.rxerrc += er32(RXERRC); 4996 adapter->stats.cexterr += er32(CEXTERR); 4997 adapter->stats.tsctc += er32(TSCTC); 4998 adapter->stats.tsctfc += er32(TSCTFC); 4999 5000 /* Fill out the OS statistics structure */ 5001 netdev->stats.multicast = adapter->stats.mprc; 5002 netdev->stats.collisions = adapter->stats.colc; 5003 5004 /* Rx Errors */ 5005 5006 /* RLEC on some newer hardware can be incorrect so build 5007 * our own version based on RUC and ROC 5008 */ 5009 netdev->stats.rx_errors = adapter->stats.rxerrc + 5010 adapter->stats.crcerrs + adapter->stats.algnerrc + 5011 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5012 netdev->stats.rx_length_errors = adapter->stats.ruc + 5013 adapter->stats.roc; 5014 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5015 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5016 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5017 5018 /* Tx Errors */ 5019 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5020 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5021 netdev->stats.tx_window_errors = adapter->stats.latecol; 5022 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5023 5024 /* Tx Dropped needs to be maintained elsewhere */ 5025 5026 /* Management Stats */ 5027 adapter->stats.mgptc += er32(MGTPTC); 5028 adapter->stats.mgprc += er32(MGTPRC); 5029 adapter->stats.mgpdc += er32(MGTPDC); 5030 5031 /* Correctable ECC Errors */ 5032 if (hw->mac.type >= e1000_pch_lpt) { 5033 u32 pbeccsts = er32(PBECCSTS); 5034 5035 adapter->corr_errors += 5036 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5037 adapter->uncorr_errors += 5038 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5039 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5040 } 5041 } 5042 5043 /** 5044 * e1000_phy_read_status - Update the PHY register status snapshot 5045 * @adapter: board private structure 5046 **/ 5047 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5048 { 5049 struct e1000_hw *hw = &adapter->hw; 5050 struct e1000_phy_regs *phy = &adapter->phy_regs; 5051 5052 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5053 (er32(STATUS) & E1000_STATUS_LU) && 5054 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5055 int ret_val; 5056 5057 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5058 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5059 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5060 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5061 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5062 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5063 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5064 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5065 if (ret_val) 5066 e_warn("Error reading PHY register\n"); 5067 } else { 5068 /* Do not read PHY registers if link is not up 5069 * Set values to typical power-on defaults 5070 */ 5071 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5072 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5073 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5074 BMSR_ERCAP); 5075 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5076 ADVERTISE_ALL | ADVERTISE_CSMA); 5077 phy->lpa = 0; 5078 phy->expansion = EXPANSION_ENABLENPAGE; 5079 phy->ctrl1000 = ADVERTISE_1000FULL; 5080 phy->stat1000 = 0; 5081 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5082 } 5083 } 5084 5085 static void e1000_print_link_info(struct e1000_adapter *adapter) 5086 { 5087 struct e1000_hw *hw = &adapter->hw; 5088 u32 ctrl = er32(CTRL); 5089 5090 /* Link status message must follow this format for user tools */ 5091 netdev_info(adapter->netdev, 5092 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5093 adapter->link_speed, 5094 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5095 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5096 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5097 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5098 } 5099 5100 static bool e1000e_has_link(struct e1000_adapter *adapter) 5101 { 5102 struct e1000_hw *hw = &adapter->hw; 5103 bool link_active = false; 5104 s32 ret_val = 0; 5105 5106 /* get_link_status is set on LSC (link status) interrupt or 5107 * Rx sequence error interrupt. get_link_status will stay 5108 * true until the check_for_link establishes link 5109 * for copper adapters ONLY 5110 */ 5111 switch (hw->phy.media_type) { 5112 case e1000_media_type_copper: 5113 if (hw->mac.get_link_status) { 5114 ret_val = hw->mac.ops.check_for_link(hw); 5115 link_active = !hw->mac.get_link_status; 5116 } else { 5117 link_active = true; 5118 } 5119 break; 5120 case e1000_media_type_fiber: 5121 ret_val = hw->mac.ops.check_for_link(hw); 5122 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5123 break; 5124 case e1000_media_type_internal_serdes: 5125 ret_val = hw->mac.ops.check_for_link(hw); 5126 link_active = hw->mac.serdes_has_link; 5127 break; 5128 default: 5129 case e1000_media_type_unknown: 5130 break; 5131 } 5132 5133 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5134 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5135 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5136 e_info("Gigabit has been disabled, downgrading speed\n"); 5137 } 5138 5139 return link_active; 5140 } 5141 5142 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5143 { 5144 /* make sure the receive unit is started */ 5145 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5146 (adapter->flags & FLAG_RESTART_NOW)) { 5147 struct e1000_hw *hw = &adapter->hw; 5148 u32 rctl = er32(RCTL); 5149 5150 ew32(RCTL, rctl | E1000_RCTL_EN); 5151 adapter->flags &= ~FLAG_RESTART_NOW; 5152 } 5153 } 5154 5155 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5156 { 5157 struct e1000_hw *hw = &adapter->hw; 5158 5159 /* With 82574 controllers, PHY needs to be checked periodically 5160 * for hung state and reset, if two calls return true 5161 */ 5162 if (e1000_check_phy_82574(hw)) 5163 adapter->phy_hang_count++; 5164 else 5165 adapter->phy_hang_count = 0; 5166 5167 if (adapter->phy_hang_count > 1) { 5168 adapter->phy_hang_count = 0; 5169 e_dbg("PHY appears hung - resetting\n"); 5170 schedule_work(&adapter->reset_task); 5171 } 5172 } 5173 5174 /** 5175 * e1000_watchdog - Timer Call-back 5176 * @t: pointer to timer_list containing private info adapter 5177 **/ 5178 static void e1000_watchdog(struct timer_list *t) 5179 { 5180 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5181 5182 /* Do the rest outside of interrupt context */ 5183 schedule_work(&adapter->watchdog_task); 5184 5185 /* TODO: make this use queue_delayed_work() */ 5186 } 5187 5188 static void e1000_watchdog_task(struct work_struct *work) 5189 { 5190 struct e1000_adapter *adapter = container_of(work, 5191 struct e1000_adapter, 5192 watchdog_task); 5193 struct net_device *netdev = adapter->netdev; 5194 struct e1000_mac_info *mac = &adapter->hw.mac; 5195 struct e1000_phy_info *phy = &adapter->hw.phy; 5196 struct e1000_ring *tx_ring = adapter->tx_ring; 5197 u32 dmoff_exit_timeout = 100, tries = 0; 5198 struct e1000_hw *hw = &adapter->hw; 5199 u32 link, tctl, pcim_state; 5200 5201 if (test_bit(__E1000_DOWN, &adapter->state)) 5202 return; 5203 5204 link = e1000e_has_link(adapter); 5205 if ((netif_carrier_ok(netdev)) && link) { 5206 /* Cancel scheduled suspend requests. */ 5207 pm_runtime_resume(netdev->dev.parent); 5208 5209 e1000e_enable_receives(adapter); 5210 goto link_up; 5211 } 5212 5213 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5214 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5215 e1000_update_mng_vlan(adapter); 5216 5217 if (link) { 5218 if (!netif_carrier_ok(netdev)) { 5219 bool txb2b = true; 5220 5221 /* Cancel scheduled suspend requests. */ 5222 pm_runtime_resume(netdev->dev.parent); 5223 5224 /* Checking if MAC is in DMoff state*/ 5225 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 5226 pcim_state = er32(STATUS); 5227 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5228 if (tries++ == dmoff_exit_timeout) { 5229 e_dbg("Error in exiting dmoff\n"); 5230 break; 5231 } 5232 usleep_range(10000, 20000); 5233 pcim_state = er32(STATUS); 5234 5235 /* Checking if MAC exited DMoff state */ 5236 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5237 e1000_phy_hw_reset(&adapter->hw); 5238 } 5239 } 5240 5241 /* update snapshot of PHY registers on LSC */ 5242 e1000_phy_read_status(adapter); 5243 mac->ops.get_link_up_info(&adapter->hw, 5244 &adapter->link_speed, 5245 &adapter->link_duplex); 5246 e1000_print_link_info(adapter); 5247 5248 /* check if SmartSpeed worked */ 5249 e1000e_check_downshift(hw); 5250 if (phy->speed_downgraded) 5251 netdev_warn(netdev, 5252 "Link Speed was downgraded by SmartSpeed\n"); 5253 5254 /* On supported PHYs, check for duplex mismatch only 5255 * if link has autonegotiated at 10/100 half 5256 */ 5257 if ((hw->phy.type == e1000_phy_igp_3 || 5258 hw->phy.type == e1000_phy_bm) && 5259 hw->mac.autoneg && 5260 (adapter->link_speed == SPEED_10 || 5261 adapter->link_speed == SPEED_100) && 5262 (adapter->link_duplex == HALF_DUPLEX)) { 5263 u16 autoneg_exp; 5264 5265 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5266 5267 if (!(autoneg_exp & EXPANSION_NWAY)) 5268 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5269 } 5270 5271 /* adjust timeout factor according to speed/duplex */ 5272 adapter->tx_timeout_factor = 1; 5273 switch (adapter->link_speed) { 5274 case SPEED_10: 5275 txb2b = false; 5276 adapter->tx_timeout_factor = 16; 5277 break; 5278 case SPEED_100: 5279 txb2b = false; 5280 adapter->tx_timeout_factor = 10; 5281 break; 5282 } 5283 5284 /* workaround: re-program speed mode bit after 5285 * link-up event 5286 */ 5287 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5288 !txb2b) { 5289 u32 tarc0; 5290 5291 tarc0 = er32(TARC(0)); 5292 tarc0 &= ~SPEED_MODE_BIT; 5293 ew32(TARC(0), tarc0); 5294 } 5295 5296 /* disable TSO for pcie and 10/100 speeds, to avoid 5297 * some hardware issues 5298 */ 5299 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5300 switch (adapter->link_speed) { 5301 case SPEED_10: 5302 case SPEED_100: 5303 e_info("10/100 speed: disabling TSO\n"); 5304 netdev->features &= ~NETIF_F_TSO; 5305 netdev->features &= ~NETIF_F_TSO6; 5306 break; 5307 case SPEED_1000: 5308 netdev->features |= NETIF_F_TSO; 5309 netdev->features |= NETIF_F_TSO6; 5310 break; 5311 default: 5312 /* oops */ 5313 break; 5314 } 5315 if (hw->mac.type == e1000_pch_spt) { 5316 netdev->features &= ~NETIF_F_TSO; 5317 netdev->features &= ~NETIF_F_TSO6; 5318 } 5319 } 5320 5321 /* enable transmits in the hardware, need to do this 5322 * after setting TARC(0) 5323 */ 5324 tctl = er32(TCTL); 5325 tctl |= E1000_TCTL_EN; 5326 ew32(TCTL, tctl); 5327 5328 /* Perform any post-link-up configuration before 5329 * reporting link up. 5330 */ 5331 if (phy->ops.cfg_on_link_up) 5332 phy->ops.cfg_on_link_up(hw); 5333 5334 netif_wake_queue(netdev); 5335 netif_carrier_on(netdev); 5336 5337 if (!test_bit(__E1000_DOWN, &adapter->state)) 5338 mod_timer(&adapter->phy_info_timer, 5339 round_jiffies(jiffies + 2 * HZ)); 5340 } 5341 } else { 5342 if (netif_carrier_ok(netdev)) { 5343 adapter->link_speed = 0; 5344 adapter->link_duplex = 0; 5345 /* Link status message must follow this format */ 5346 netdev_info(netdev, "NIC Link is Down\n"); 5347 netif_carrier_off(netdev); 5348 netif_stop_queue(netdev); 5349 if (!test_bit(__E1000_DOWN, &adapter->state)) 5350 mod_timer(&adapter->phy_info_timer, 5351 round_jiffies(jiffies + 2 * HZ)); 5352 5353 /* 8000ES2LAN requires a Rx packet buffer work-around 5354 * on link down event; reset the controller to flush 5355 * the Rx packet buffer. 5356 */ 5357 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5358 adapter->flags |= FLAG_RESTART_NOW; 5359 else 5360 pm_schedule_suspend(netdev->dev.parent, 5361 LINK_TIMEOUT); 5362 } 5363 } 5364 5365 link_up: 5366 spin_lock(&adapter->stats64_lock); 5367 e1000e_update_stats(adapter); 5368 5369 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5370 adapter->tpt_old = adapter->stats.tpt; 5371 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5372 adapter->colc_old = adapter->stats.colc; 5373 5374 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5375 adapter->gorc_old = adapter->stats.gorc; 5376 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5377 adapter->gotc_old = adapter->stats.gotc; 5378 spin_unlock(&adapter->stats64_lock); 5379 5380 /* If the link is lost the controller stops DMA, but 5381 * if there is queued Tx work it cannot be done. So 5382 * reset the controller to flush the Tx packet buffers. 5383 */ 5384 if (!netif_carrier_ok(netdev) && 5385 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5386 adapter->flags |= FLAG_RESTART_NOW; 5387 5388 /* If reset is necessary, do it outside of interrupt context. */ 5389 if (adapter->flags & FLAG_RESTART_NOW) { 5390 schedule_work(&adapter->reset_task); 5391 /* return immediately since reset is imminent */ 5392 return; 5393 } 5394 5395 e1000e_update_adaptive(&adapter->hw); 5396 5397 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5398 if (adapter->itr_setting == 4) { 5399 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5400 * Total asymmetrical Tx or Rx gets ITR=8000; 5401 * everyone else is between 2000-8000. 5402 */ 5403 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5404 u32 dif = (adapter->gotc > adapter->gorc ? 5405 adapter->gotc - adapter->gorc : 5406 adapter->gorc - adapter->gotc) / 10000; 5407 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5408 5409 e1000e_write_itr(adapter, itr); 5410 } 5411 5412 /* Cause software interrupt to ensure Rx ring is cleaned */ 5413 if (adapter->msix_entries) 5414 ew32(ICS, adapter->rx_ring->ims_val); 5415 else 5416 ew32(ICS, E1000_ICS_RXDMT0); 5417 5418 /* flush pending descriptors to memory before detecting Tx hang */ 5419 e1000e_flush_descriptors(adapter); 5420 5421 /* Force detection of hung controller every watchdog period */ 5422 adapter->detect_tx_hung = true; 5423 5424 /* With 82571 controllers, LAA may be overwritten due to controller 5425 * reset from the other port. Set the appropriate LAA in RAR[0] 5426 */ 5427 if (e1000e_get_laa_state_82571(hw)) 5428 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5429 5430 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5431 e1000e_check_82574_phy_workaround(adapter); 5432 5433 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5434 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5435 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5436 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5437 er32(RXSTMPH); 5438 adapter->rx_hwtstamp_cleared++; 5439 } else { 5440 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5441 } 5442 } 5443 5444 /* Reset the timer */ 5445 if (!test_bit(__E1000_DOWN, &adapter->state)) 5446 mod_timer(&adapter->watchdog_timer, 5447 round_jiffies(jiffies + 2 * HZ)); 5448 } 5449 5450 #define E1000_TX_FLAGS_CSUM 0x00000001 5451 #define E1000_TX_FLAGS_VLAN 0x00000002 5452 #define E1000_TX_FLAGS_TSO 0x00000004 5453 #define E1000_TX_FLAGS_IPV4 0x00000008 5454 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5455 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5456 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5457 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5458 5459 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5460 __be16 protocol) 5461 { 5462 struct e1000_context_desc *context_desc; 5463 struct e1000_buffer *buffer_info; 5464 unsigned int i; 5465 u32 cmd_length = 0; 5466 u16 ipcse = 0, mss; 5467 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5468 int err; 5469 5470 if (!skb_is_gso(skb)) 5471 return 0; 5472 5473 err = skb_cow_head(skb, 0); 5474 if (err < 0) 5475 return err; 5476 5477 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5478 mss = skb_shinfo(skb)->gso_size; 5479 if (protocol == htons(ETH_P_IP)) { 5480 struct iphdr *iph = ip_hdr(skb); 5481 iph->tot_len = 0; 5482 iph->check = 0; 5483 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5484 0, IPPROTO_TCP, 0); 5485 cmd_length = E1000_TXD_CMD_IP; 5486 ipcse = skb_transport_offset(skb) - 1; 5487 } else if (skb_is_gso_v6(skb)) { 5488 tcp_v6_gso_csum_prep(skb); 5489 ipcse = 0; 5490 } 5491 ipcss = skb_network_offset(skb); 5492 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5493 tucss = skb_transport_offset(skb); 5494 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5495 5496 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5497 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5498 5499 i = tx_ring->next_to_use; 5500 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5501 buffer_info = &tx_ring->buffer_info[i]; 5502 5503 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5504 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5505 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5506 context_desc->upper_setup.tcp_fields.tucss = tucss; 5507 context_desc->upper_setup.tcp_fields.tucso = tucso; 5508 context_desc->upper_setup.tcp_fields.tucse = 0; 5509 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5510 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5511 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5512 5513 buffer_info->time_stamp = jiffies; 5514 buffer_info->next_to_watch = i; 5515 5516 i++; 5517 if (i == tx_ring->count) 5518 i = 0; 5519 tx_ring->next_to_use = i; 5520 5521 return 1; 5522 } 5523 5524 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5525 __be16 protocol) 5526 { 5527 struct e1000_adapter *adapter = tx_ring->adapter; 5528 struct e1000_context_desc *context_desc; 5529 struct e1000_buffer *buffer_info; 5530 unsigned int i; 5531 u8 css; 5532 u32 cmd_len = E1000_TXD_CMD_DEXT; 5533 5534 if (skb->ip_summed != CHECKSUM_PARTIAL) 5535 return false; 5536 5537 switch (protocol) { 5538 case cpu_to_be16(ETH_P_IP): 5539 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5540 cmd_len |= E1000_TXD_CMD_TCP; 5541 break; 5542 case cpu_to_be16(ETH_P_IPV6): 5543 /* XXX not handling all IPV6 headers */ 5544 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5545 cmd_len |= E1000_TXD_CMD_TCP; 5546 break; 5547 default: 5548 if (unlikely(net_ratelimit())) 5549 e_warn("checksum_partial proto=%x!\n", 5550 be16_to_cpu(protocol)); 5551 break; 5552 } 5553 5554 css = skb_checksum_start_offset(skb); 5555 5556 i = tx_ring->next_to_use; 5557 buffer_info = &tx_ring->buffer_info[i]; 5558 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5559 5560 context_desc->lower_setup.ip_config = 0; 5561 context_desc->upper_setup.tcp_fields.tucss = css; 5562 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5563 context_desc->upper_setup.tcp_fields.tucse = 0; 5564 context_desc->tcp_seg_setup.data = 0; 5565 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5566 5567 buffer_info->time_stamp = jiffies; 5568 buffer_info->next_to_watch = i; 5569 5570 i++; 5571 if (i == tx_ring->count) 5572 i = 0; 5573 tx_ring->next_to_use = i; 5574 5575 return true; 5576 } 5577 5578 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5579 unsigned int first, unsigned int max_per_txd, 5580 unsigned int nr_frags) 5581 { 5582 struct e1000_adapter *adapter = tx_ring->adapter; 5583 struct pci_dev *pdev = adapter->pdev; 5584 struct e1000_buffer *buffer_info; 5585 unsigned int len = skb_headlen(skb); 5586 unsigned int offset = 0, size, count = 0, i; 5587 unsigned int f, bytecount, segs; 5588 5589 i = tx_ring->next_to_use; 5590 5591 while (len) { 5592 buffer_info = &tx_ring->buffer_info[i]; 5593 size = min(len, max_per_txd); 5594 5595 buffer_info->length = size; 5596 buffer_info->time_stamp = jiffies; 5597 buffer_info->next_to_watch = i; 5598 buffer_info->dma = dma_map_single(&pdev->dev, 5599 skb->data + offset, 5600 size, DMA_TO_DEVICE); 5601 buffer_info->mapped_as_page = false; 5602 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5603 goto dma_error; 5604 5605 len -= size; 5606 offset += size; 5607 count++; 5608 5609 if (len) { 5610 i++; 5611 if (i == tx_ring->count) 5612 i = 0; 5613 } 5614 } 5615 5616 for (f = 0; f < nr_frags; f++) { 5617 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5618 5619 len = skb_frag_size(frag); 5620 offset = 0; 5621 5622 while (len) { 5623 i++; 5624 if (i == tx_ring->count) 5625 i = 0; 5626 5627 buffer_info = &tx_ring->buffer_info[i]; 5628 size = min(len, max_per_txd); 5629 5630 buffer_info->length = size; 5631 buffer_info->time_stamp = jiffies; 5632 buffer_info->next_to_watch = i; 5633 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5634 offset, size, 5635 DMA_TO_DEVICE); 5636 buffer_info->mapped_as_page = true; 5637 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5638 goto dma_error; 5639 5640 len -= size; 5641 offset += size; 5642 count++; 5643 } 5644 } 5645 5646 segs = skb_shinfo(skb)->gso_segs ? : 1; 5647 /* multiply data chunks by size of headers */ 5648 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5649 5650 tx_ring->buffer_info[i].skb = skb; 5651 tx_ring->buffer_info[i].segs = segs; 5652 tx_ring->buffer_info[i].bytecount = bytecount; 5653 tx_ring->buffer_info[first].next_to_watch = i; 5654 5655 return count; 5656 5657 dma_error: 5658 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5659 buffer_info->dma = 0; 5660 if (count) 5661 count--; 5662 5663 while (count--) { 5664 if (i == 0) 5665 i += tx_ring->count; 5666 i--; 5667 buffer_info = &tx_ring->buffer_info[i]; 5668 e1000_put_txbuf(tx_ring, buffer_info, true); 5669 } 5670 5671 return 0; 5672 } 5673 5674 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5675 { 5676 struct e1000_adapter *adapter = tx_ring->adapter; 5677 struct e1000_tx_desc *tx_desc = NULL; 5678 struct e1000_buffer *buffer_info; 5679 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5680 unsigned int i; 5681 5682 if (tx_flags & E1000_TX_FLAGS_TSO) { 5683 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5684 E1000_TXD_CMD_TSE; 5685 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5686 5687 if (tx_flags & E1000_TX_FLAGS_IPV4) 5688 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5689 } 5690 5691 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5692 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5693 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5694 } 5695 5696 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5697 txd_lower |= E1000_TXD_CMD_VLE; 5698 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5699 } 5700 5701 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5702 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5703 5704 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5705 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5706 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5707 } 5708 5709 i = tx_ring->next_to_use; 5710 5711 do { 5712 buffer_info = &tx_ring->buffer_info[i]; 5713 tx_desc = E1000_TX_DESC(*tx_ring, i); 5714 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5715 tx_desc->lower.data = cpu_to_le32(txd_lower | 5716 buffer_info->length); 5717 tx_desc->upper.data = cpu_to_le32(txd_upper); 5718 5719 i++; 5720 if (i == tx_ring->count) 5721 i = 0; 5722 } while (--count > 0); 5723 5724 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5725 5726 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5727 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5728 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5729 5730 /* Force memory writes to complete before letting h/w 5731 * know there are new descriptors to fetch. (Only 5732 * applicable for weak-ordered memory model archs, 5733 * such as IA-64). 5734 */ 5735 wmb(); 5736 5737 tx_ring->next_to_use = i; 5738 } 5739 5740 #define MINIMUM_DHCP_PACKET_SIZE 282 5741 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5742 struct sk_buff *skb) 5743 { 5744 struct e1000_hw *hw = &adapter->hw; 5745 u16 length, offset; 5746 5747 if (skb_vlan_tag_present(skb) && 5748 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5749 (adapter->hw.mng_cookie.status & 5750 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5751 return 0; 5752 5753 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5754 return 0; 5755 5756 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5757 return 0; 5758 5759 { 5760 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5761 struct udphdr *udp; 5762 5763 if (ip->protocol != IPPROTO_UDP) 5764 return 0; 5765 5766 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5767 if (ntohs(udp->dest) != 67) 5768 return 0; 5769 5770 offset = (u8 *)udp + 8 - skb->data; 5771 length = skb->len - offset; 5772 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5773 } 5774 5775 return 0; 5776 } 5777 5778 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5779 { 5780 struct e1000_adapter *adapter = tx_ring->adapter; 5781 5782 netif_stop_queue(adapter->netdev); 5783 /* Herbert's original patch had: 5784 * smp_mb__after_netif_stop_queue(); 5785 * but since that doesn't exist yet, just open code it. 5786 */ 5787 smp_mb(); 5788 5789 /* We need to check again in a case another CPU has just 5790 * made room available. 5791 */ 5792 if (e1000_desc_unused(tx_ring) < size) 5793 return -EBUSY; 5794 5795 /* A reprieve! */ 5796 netif_start_queue(adapter->netdev); 5797 ++adapter->restart_queue; 5798 return 0; 5799 } 5800 5801 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5802 { 5803 BUG_ON(size > tx_ring->count); 5804 5805 if (e1000_desc_unused(tx_ring) >= size) 5806 return 0; 5807 return __e1000_maybe_stop_tx(tx_ring, size); 5808 } 5809 5810 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5811 struct net_device *netdev) 5812 { 5813 struct e1000_adapter *adapter = netdev_priv(netdev); 5814 struct e1000_ring *tx_ring = adapter->tx_ring; 5815 unsigned int first; 5816 unsigned int tx_flags = 0; 5817 unsigned int len = skb_headlen(skb); 5818 unsigned int nr_frags; 5819 unsigned int mss; 5820 int count = 0; 5821 int tso; 5822 unsigned int f; 5823 __be16 protocol = vlan_get_protocol(skb); 5824 5825 if (test_bit(__E1000_DOWN, &adapter->state)) { 5826 dev_kfree_skb_any(skb); 5827 return NETDEV_TX_OK; 5828 } 5829 5830 if (skb->len <= 0) { 5831 dev_kfree_skb_any(skb); 5832 return NETDEV_TX_OK; 5833 } 5834 5835 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5836 * pad skb in order to meet this minimum size requirement 5837 */ 5838 if (skb_put_padto(skb, 17)) 5839 return NETDEV_TX_OK; 5840 5841 mss = skb_shinfo(skb)->gso_size; 5842 if (mss) { 5843 u8 hdr_len; 5844 5845 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5846 * points to just header, pull a few bytes of payload from 5847 * frags into skb->data 5848 */ 5849 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5850 /* we do this workaround for ES2LAN, but it is un-necessary, 5851 * avoiding it could save a lot of cycles 5852 */ 5853 if (skb->data_len && (hdr_len == len)) { 5854 unsigned int pull_size; 5855 5856 pull_size = min_t(unsigned int, 4, skb->data_len); 5857 if (!__pskb_pull_tail(skb, pull_size)) { 5858 e_err("__pskb_pull_tail failed.\n"); 5859 dev_kfree_skb_any(skb); 5860 return NETDEV_TX_OK; 5861 } 5862 len = skb_headlen(skb); 5863 } 5864 } 5865 5866 /* reserve a descriptor for the offload context */ 5867 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5868 count++; 5869 count++; 5870 5871 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5872 5873 nr_frags = skb_shinfo(skb)->nr_frags; 5874 for (f = 0; f < nr_frags; f++) 5875 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5876 adapter->tx_fifo_limit); 5877 5878 if (adapter->hw.mac.tx_pkt_filtering) 5879 e1000_transfer_dhcp_info(adapter, skb); 5880 5881 /* need: count + 2 desc gap to keep tail from touching 5882 * head, otherwise try next time 5883 */ 5884 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5885 return NETDEV_TX_BUSY; 5886 5887 if (skb_vlan_tag_present(skb)) { 5888 tx_flags |= E1000_TX_FLAGS_VLAN; 5889 tx_flags |= (skb_vlan_tag_get(skb) << 5890 E1000_TX_FLAGS_VLAN_SHIFT); 5891 } 5892 5893 first = tx_ring->next_to_use; 5894 5895 tso = e1000_tso(tx_ring, skb, protocol); 5896 if (tso < 0) { 5897 dev_kfree_skb_any(skb); 5898 return NETDEV_TX_OK; 5899 } 5900 5901 if (tso) 5902 tx_flags |= E1000_TX_FLAGS_TSO; 5903 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5904 tx_flags |= E1000_TX_FLAGS_CSUM; 5905 5906 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5907 * 82571 hardware supports TSO capabilities for IPv6 as well... 5908 * no longer assume, we must. 5909 */ 5910 if (protocol == htons(ETH_P_IP)) 5911 tx_flags |= E1000_TX_FLAGS_IPV4; 5912 5913 if (unlikely(skb->no_fcs)) 5914 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5915 5916 /* if count is 0 then mapping error has occurred */ 5917 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5918 nr_frags); 5919 if (count) { 5920 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5921 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5922 if (!adapter->tx_hwtstamp_skb) { 5923 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5924 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5925 adapter->tx_hwtstamp_skb = skb_get(skb); 5926 adapter->tx_hwtstamp_start = jiffies; 5927 schedule_work(&adapter->tx_hwtstamp_work); 5928 } else { 5929 adapter->tx_hwtstamp_skipped++; 5930 } 5931 } 5932 5933 skb_tx_timestamp(skb); 5934 5935 netdev_sent_queue(netdev, skb->len); 5936 e1000_tx_queue(tx_ring, tx_flags, count); 5937 /* Make sure there is space in the ring for the next send. */ 5938 e1000_maybe_stop_tx(tx_ring, 5939 (MAX_SKB_FRAGS * 5940 DIV_ROUND_UP(PAGE_SIZE, 5941 adapter->tx_fifo_limit) + 2)); 5942 5943 if (!netdev_xmit_more() || 5944 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5945 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5946 e1000e_update_tdt_wa(tx_ring, 5947 tx_ring->next_to_use); 5948 else 5949 writel(tx_ring->next_to_use, tx_ring->tail); 5950 } 5951 } else { 5952 dev_kfree_skb_any(skb); 5953 tx_ring->buffer_info[first].time_stamp = 0; 5954 tx_ring->next_to_use = first; 5955 } 5956 5957 return NETDEV_TX_OK; 5958 } 5959 5960 /** 5961 * e1000_tx_timeout - Respond to a Tx Hang 5962 * @netdev: network interface device structure 5963 * @txqueue: index of the hung queue (unused) 5964 **/ 5965 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 5966 { 5967 struct e1000_adapter *adapter = netdev_priv(netdev); 5968 5969 /* Do the reset outside of interrupt context */ 5970 adapter->tx_timeout_count++; 5971 schedule_work(&adapter->reset_task); 5972 } 5973 5974 static void e1000_reset_task(struct work_struct *work) 5975 { 5976 struct e1000_adapter *adapter; 5977 adapter = container_of(work, struct e1000_adapter, reset_task); 5978 5979 rtnl_lock(); 5980 /* don't run the task if already down */ 5981 if (test_bit(__E1000_DOWN, &adapter->state)) { 5982 rtnl_unlock(); 5983 return; 5984 } 5985 5986 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5987 e1000e_dump(adapter); 5988 e_err("Reset adapter unexpectedly\n"); 5989 } 5990 e1000e_reinit_locked(adapter); 5991 rtnl_unlock(); 5992 } 5993 5994 /** 5995 * e1000e_get_stats64 - Get System Network Statistics 5996 * @netdev: network interface device structure 5997 * @stats: rtnl_link_stats64 pointer 5998 * 5999 * Returns the address of the device statistics structure. 6000 **/ 6001 void e1000e_get_stats64(struct net_device *netdev, 6002 struct rtnl_link_stats64 *stats) 6003 { 6004 struct e1000_adapter *adapter = netdev_priv(netdev); 6005 6006 spin_lock(&adapter->stats64_lock); 6007 e1000e_update_stats(adapter); 6008 /* Fill out the OS statistics structure */ 6009 stats->rx_bytes = adapter->stats.gorc; 6010 stats->rx_packets = adapter->stats.gprc; 6011 stats->tx_bytes = adapter->stats.gotc; 6012 stats->tx_packets = adapter->stats.gptc; 6013 stats->multicast = adapter->stats.mprc; 6014 stats->collisions = adapter->stats.colc; 6015 6016 /* Rx Errors */ 6017 6018 /* RLEC on some newer hardware can be incorrect so build 6019 * our own version based on RUC and ROC 6020 */ 6021 stats->rx_errors = adapter->stats.rxerrc + 6022 adapter->stats.crcerrs + adapter->stats.algnerrc + 6023 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6024 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6025 stats->rx_crc_errors = adapter->stats.crcerrs; 6026 stats->rx_frame_errors = adapter->stats.algnerrc; 6027 stats->rx_missed_errors = adapter->stats.mpc; 6028 6029 /* Tx Errors */ 6030 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6031 stats->tx_aborted_errors = adapter->stats.ecol; 6032 stats->tx_window_errors = adapter->stats.latecol; 6033 stats->tx_carrier_errors = adapter->stats.tncrs; 6034 6035 /* Tx Dropped needs to be maintained elsewhere */ 6036 6037 spin_unlock(&adapter->stats64_lock); 6038 } 6039 6040 /** 6041 * e1000_change_mtu - Change the Maximum Transfer Unit 6042 * @netdev: network interface device structure 6043 * @new_mtu: new value for maximum frame size 6044 * 6045 * Returns 0 on success, negative on failure 6046 **/ 6047 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6048 { 6049 struct e1000_adapter *adapter = netdev_priv(netdev); 6050 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6051 6052 /* Jumbo frame support */ 6053 if ((new_mtu > ETH_DATA_LEN) && 6054 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6055 e_err("Jumbo Frames not supported.\n"); 6056 return -EINVAL; 6057 } 6058 6059 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6060 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6061 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6062 (new_mtu > ETH_DATA_LEN)) { 6063 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6064 return -EINVAL; 6065 } 6066 6067 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6068 usleep_range(1000, 1100); 6069 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6070 adapter->max_frame_size = max_frame; 6071 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6072 netdev->mtu, new_mtu); 6073 netdev->mtu = new_mtu; 6074 6075 pm_runtime_get_sync(netdev->dev.parent); 6076 6077 if (netif_running(netdev)) 6078 e1000e_down(adapter, true); 6079 6080 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6081 * means we reserve 2 more, this pushes us to allocate from the next 6082 * larger slab size. 6083 * i.e. RXBUFFER_2048 --> size-4096 slab 6084 * However with the new *_jumbo_rx* routines, jumbo receives will use 6085 * fragmented skbs 6086 */ 6087 6088 if (max_frame <= 2048) 6089 adapter->rx_buffer_len = 2048; 6090 else 6091 adapter->rx_buffer_len = 4096; 6092 6093 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6094 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6095 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6096 6097 if (netif_running(netdev)) 6098 e1000e_up(adapter); 6099 else 6100 e1000e_reset(adapter); 6101 6102 pm_runtime_put_sync(netdev->dev.parent); 6103 6104 clear_bit(__E1000_RESETTING, &adapter->state); 6105 6106 return 0; 6107 } 6108 6109 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6110 int cmd) 6111 { 6112 struct e1000_adapter *adapter = netdev_priv(netdev); 6113 struct mii_ioctl_data *data = if_mii(ifr); 6114 6115 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6116 return -EOPNOTSUPP; 6117 6118 switch (cmd) { 6119 case SIOCGMIIPHY: 6120 data->phy_id = adapter->hw.phy.addr; 6121 break; 6122 case SIOCGMIIREG: 6123 e1000_phy_read_status(adapter); 6124 6125 switch (data->reg_num & 0x1F) { 6126 case MII_BMCR: 6127 data->val_out = adapter->phy_regs.bmcr; 6128 break; 6129 case MII_BMSR: 6130 data->val_out = adapter->phy_regs.bmsr; 6131 break; 6132 case MII_PHYSID1: 6133 data->val_out = (adapter->hw.phy.id >> 16); 6134 break; 6135 case MII_PHYSID2: 6136 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6137 break; 6138 case MII_ADVERTISE: 6139 data->val_out = adapter->phy_regs.advertise; 6140 break; 6141 case MII_LPA: 6142 data->val_out = adapter->phy_regs.lpa; 6143 break; 6144 case MII_EXPANSION: 6145 data->val_out = adapter->phy_regs.expansion; 6146 break; 6147 case MII_CTRL1000: 6148 data->val_out = adapter->phy_regs.ctrl1000; 6149 break; 6150 case MII_STAT1000: 6151 data->val_out = adapter->phy_regs.stat1000; 6152 break; 6153 case MII_ESTATUS: 6154 data->val_out = adapter->phy_regs.estatus; 6155 break; 6156 default: 6157 return -EIO; 6158 } 6159 break; 6160 case SIOCSMIIREG: 6161 default: 6162 return -EOPNOTSUPP; 6163 } 6164 return 0; 6165 } 6166 6167 /** 6168 * e1000e_hwtstamp_set - control hardware time stamping 6169 * @netdev: network interface device structure 6170 * @ifr: interface request 6171 * 6172 * Outgoing time stamping can be enabled and disabled. Play nice and 6173 * disable it when requested, although it shouldn't cause any overhead 6174 * when no packet needs it. At most one packet in the queue may be 6175 * marked for time stamping, otherwise it would be impossible to tell 6176 * for sure to which packet the hardware time stamp belongs. 6177 * 6178 * Incoming time stamping has to be configured via the hardware filters. 6179 * Not all combinations are supported, in particular event type has to be 6180 * specified. Matching the kind of event packet is not supported, with the 6181 * exception of "all V2 events regardless of level 2 or 4". 6182 **/ 6183 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6184 { 6185 struct e1000_adapter *adapter = netdev_priv(netdev); 6186 struct hwtstamp_config config; 6187 int ret_val; 6188 6189 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6190 return -EFAULT; 6191 6192 ret_val = e1000e_config_hwtstamp(adapter, &config); 6193 if (ret_val) 6194 return ret_val; 6195 6196 switch (config.rx_filter) { 6197 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6198 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6199 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6200 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6201 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6202 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6203 /* With V2 type filters which specify a Sync or Delay Request, 6204 * Path Delay Request/Response messages are also time stamped 6205 * by hardware so notify the caller the requested packets plus 6206 * some others are time stamped. 6207 */ 6208 config.rx_filter = HWTSTAMP_FILTER_SOME; 6209 break; 6210 default: 6211 break; 6212 } 6213 6214 return copy_to_user(ifr->ifr_data, &config, 6215 sizeof(config)) ? -EFAULT : 0; 6216 } 6217 6218 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6219 { 6220 struct e1000_adapter *adapter = netdev_priv(netdev); 6221 6222 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6223 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6224 } 6225 6226 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6227 { 6228 switch (cmd) { 6229 case SIOCGMIIPHY: 6230 case SIOCGMIIREG: 6231 case SIOCSMIIREG: 6232 return e1000_mii_ioctl(netdev, ifr, cmd); 6233 case SIOCSHWTSTAMP: 6234 return e1000e_hwtstamp_set(netdev, ifr); 6235 case SIOCGHWTSTAMP: 6236 return e1000e_hwtstamp_get(netdev, ifr); 6237 default: 6238 return -EOPNOTSUPP; 6239 } 6240 } 6241 6242 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6243 { 6244 struct e1000_hw *hw = &adapter->hw; 6245 u32 i, mac_reg, wuc; 6246 u16 phy_reg, wuc_enable; 6247 int retval; 6248 6249 /* copy MAC RARs to PHY RARs */ 6250 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6251 6252 retval = hw->phy.ops.acquire(hw); 6253 if (retval) { 6254 e_err("Could not acquire PHY\n"); 6255 return retval; 6256 } 6257 6258 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6259 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6260 if (retval) 6261 goto release; 6262 6263 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6264 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6265 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6266 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6267 (u16)(mac_reg & 0xFFFF)); 6268 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6269 (u16)((mac_reg >> 16) & 0xFFFF)); 6270 } 6271 6272 /* configure PHY Rx Control register */ 6273 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6274 mac_reg = er32(RCTL); 6275 if (mac_reg & E1000_RCTL_UPE) 6276 phy_reg |= BM_RCTL_UPE; 6277 if (mac_reg & E1000_RCTL_MPE) 6278 phy_reg |= BM_RCTL_MPE; 6279 phy_reg &= ~(BM_RCTL_MO_MASK); 6280 if (mac_reg & E1000_RCTL_MO_3) 6281 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6282 << BM_RCTL_MO_SHIFT); 6283 if (mac_reg & E1000_RCTL_BAM) 6284 phy_reg |= BM_RCTL_BAM; 6285 if (mac_reg & E1000_RCTL_PMCF) 6286 phy_reg |= BM_RCTL_PMCF; 6287 mac_reg = er32(CTRL); 6288 if (mac_reg & E1000_CTRL_RFCE) 6289 phy_reg |= BM_RCTL_RFCE; 6290 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6291 6292 wuc = E1000_WUC_PME_EN; 6293 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6294 wuc |= E1000_WUC_APME; 6295 6296 /* enable PHY wakeup in MAC register */ 6297 ew32(WUFC, wufc); 6298 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6299 E1000_WUC_PME_STATUS | wuc)); 6300 6301 /* configure and enable PHY wakeup in PHY registers */ 6302 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6303 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6304 6305 /* activate PHY wakeup */ 6306 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6307 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6308 if (retval) 6309 e_err("Could not set PHY Host Wakeup bit\n"); 6310 release: 6311 hw->phy.ops.release(hw); 6312 6313 return retval; 6314 } 6315 6316 static void e1000e_flush_lpic(struct pci_dev *pdev) 6317 { 6318 struct net_device *netdev = pci_get_drvdata(pdev); 6319 struct e1000_adapter *adapter = netdev_priv(netdev); 6320 struct e1000_hw *hw = &adapter->hw; 6321 u32 ret_val; 6322 6323 pm_runtime_get_sync(netdev->dev.parent); 6324 6325 ret_val = hw->phy.ops.acquire(hw); 6326 if (ret_val) 6327 goto fl_out; 6328 6329 pr_info("EEE TX LPI TIMER: %08X\n", 6330 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6331 6332 hw->phy.ops.release(hw); 6333 6334 fl_out: 6335 pm_runtime_put_sync(netdev->dev.parent); 6336 } 6337 6338 /* S0ix implementation */ 6339 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6340 { 6341 struct e1000_hw *hw = &adapter->hw; 6342 u32 mac_data; 6343 u16 phy_data; 6344 6345 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6346 hw->mac.type >= e1000_pch_adp) { 6347 /* Request ME configure the device for S0ix */ 6348 mac_data = er32(H2ME); 6349 mac_data |= E1000_H2ME_START_DPG; 6350 mac_data &= ~E1000_H2ME_EXIT_DPG; 6351 ew32(H2ME, mac_data); 6352 } else { 6353 /* Request driver configure the device to S0ix */ 6354 /* Disable the periodic inband message, 6355 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6356 */ 6357 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6358 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6359 phy_data |= BIT(10); 6360 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6361 6362 /* Make sure we don't exit K1 every time a new packet arrives 6363 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6364 */ 6365 e1e_rphy(hw, I217_CGFREG, &phy_data); 6366 phy_data |= BIT(5); 6367 e1e_wphy(hw, I217_CGFREG, phy_data); 6368 6369 /* Change the MAC/PHY interface to SMBus 6370 * Force the SMBus in PHY page769_23[0] = 1 6371 * Force the SMBus in MAC CTRL_EXT[11] = 1 6372 */ 6373 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6374 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6375 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6376 mac_data = er32(CTRL_EXT); 6377 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6378 ew32(CTRL_EXT, mac_data); 6379 6380 /* DFT control: PHY bit: page769_20[0] = 1 6381 * page769_20[7] - PHY PLL stop 6382 * page769_20[8] - PHY go to the electrical idle 6383 * page769_20[9] - PHY serdes disable 6384 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6385 */ 6386 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6387 phy_data |= BIT(0); 6388 phy_data |= BIT(7); 6389 phy_data |= BIT(8); 6390 phy_data |= BIT(9); 6391 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6392 6393 mac_data = er32(EXTCNF_CTRL); 6394 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6395 ew32(EXTCNF_CTRL, mac_data); 6396 6397 /* Enable the Dynamic Power Gating in the MAC */ 6398 mac_data = er32(FEXTNVM7); 6399 mac_data |= BIT(22); 6400 ew32(FEXTNVM7, mac_data); 6401 6402 /* Disable disconnected cable conditioning for Power Gating */ 6403 mac_data = er32(DPGFR); 6404 mac_data |= BIT(2); 6405 ew32(DPGFR, mac_data); 6406 6407 /* Don't wake from dynamic Power Gating with clock request */ 6408 mac_data = er32(FEXTNVM12); 6409 mac_data |= BIT(12); 6410 ew32(FEXTNVM12, mac_data); 6411 6412 /* Ungate PGCB clock */ 6413 mac_data = er32(FEXTNVM9); 6414 mac_data &= ~BIT(28); 6415 ew32(FEXTNVM9, mac_data); 6416 6417 /* Enable K1 off to enable mPHY Power Gating */ 6418 mac_data = er32(FEXTNVM6); 6419 mac_data |= BIT(31); 6420 ew32(FEXTNVM6, mac_data); 6421 6422 /* Enable mPHY power gating for any link and speed */ 6423 mac_data = er32(FEXTNVM8); 6424 mac_data |= BIT(9); 6425 ew32(FEXTNVM8, mac_data); 6426 6427 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6428 mac_data = er32(CTRL_EXT); 6429 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6430 ew32(CTRL_EXT, mac_data); 6431 6432 /* No MAC DPG gating SLP_S0 in modern standby 6433 * Switch the logic of the lanphypc to use PMC counter 6434 */ 6435 mac_data = er32(FEXTNVM5); 6436 mac_data |= BIT(7); 6437 ew32(FEXTNVM5, mac_data); 6438 } 6439 6440 /* Disable the time synchronization clock */ 6441 mac_data = er32(FEXTNVM7); 6442 mac_data |= BIT(31); 6443 mac_data &= ~BIT(0); 6444 ew32(FEXTNVM7, mac_data); 6445 6446 /* Dynamic Power Gating Enable */ 6447 mac_data = er32(CTRL_EXT); 6448 mac_data |= BIT(3); 6449 ew32(CTRL_EXT, mac_data); 6450 6451 /* Check MAC Tx/Rx packet buffer pointers. 6452 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6453 * pending traffic indication that would prevent power gating. 6454 */ 6455 mac_data = er32(TDFH); 6456 if (mac_data) 6457 ew32(TDFH, 0); 6458 mac_data = er32(TDFT); 6459 if (mac_data) 6460 ew32(TDFT, 0); 6461 mac_data = er32(TDFHS); 6462 if (mac_data) 6463 ew32(TDFHS, 0); 6464 mac_data = er32(TDFTS); 6465 if (mac_data) 6466 ew32(TDFTS, 0); 6467 mac_data = er32(TDFPC); 6468 if (mac_data) 6469 ew32(TDFPC, 0); 6470 mac_data = er32(RDFH); 6471 if (mac_data) 6472 ew32(RDFH, 0); 6473 mac_data = er32(RDFT); 6474 if (mac_data) 6475 ew32(RDFT, 0); 6476 mac_data = er32(RDFHS); 6477 if (mac_data) 6478 ew32(RDFHS, 0); 6479 mac_data = er32(RDFTS); 6480 if (mac_data) 6481 ew32(RDFTS, 0); 6482 mac_data = er32(RDFPC); 6483 if (mac_data) 6484 ew32(RDFPC, 0); 6485 } 6486 6487 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6488 { 6489 struct e1000_hw *hw = &adapter->hw; 6490 bool firmware_bug = false; 6491 u32 mac_data; 6492 u16 phy_data; 6493 u32 i = 0; 6494 6495 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6496 hw->mac.type >= e1000_pch_adp) { 6497 /* Request ME unconfigure the device from S0ix */ 6498 mac_data = er32(H2ME); 6499 mac_data &= ~E1000_H2ME_START_DPG; 6500 mac_data |= E1000_H2ME_EXIT_DPG; 6501 ew32(H2ME, mac_data); 6502 6503 /* Poll up to 2.5 seconds for ME to unconfigure DPG. 6504 * If this takes more than 1 second, show a warning indicating a 6505 * firmware bug 6506 */ 6507 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { 6508 if (i > 100 && !firmware_bug) 6509 firmware_bug = true; 6510 6511 if (i++ == 250) { 6512 e_dbg("Timeout (firmware bug): %d msec\n", 6513 i * 10); 6514 break; 6515 } 6516 6517 usleep_range(10000, 11000); 6518 } 6519 if (firmware_bug) 6520 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n", 6521 i * 10); 6522 else 6523 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10); 6524 } else { 6525 /* Request driver unconfigure the device from S0ix */ 6526 6527 /* Disable the Dynamic Power Gating in the MAC */ 6528 mac_data = er32(FEXTNVM7); 6529 mac_data &= 0xFFBFFFFF; 6530 ew32(FEXTNVM7, mac_data); 6531 6532 /* Disable mPHY power gating for any link and speed */ 6533 mac_data = er32(FEXTNVM8); 6534 mac_data &= ~BIT(9); 6535 ew32(FEXTNVM8, mac_data); 6536 6537 /* Disable K1 off */ 6538 mac_data = er32(FEXTNVM6); 6539 mac_data &= ~BIT(31); 6540 ew32(FEXTNVM6, mac_data); 6541 6542 /* Disable Ungate PGCB clock */ 6543 mac_data = er32(FEXTNVM9); 6544 mac_data |= BIT(28); 6545 ew32(FEXTNVM9, mac_data); 6546 6547 /* Cancel not waking from dynamic 6548 * Power Gating with clock request 6549 */ 6550 mac_data = er32(FEXTNVM12); 6551 mac_data &= ~BIT(12); 6552 ew32(FEXTNVM12, mac_data); 6553 6554 /* Cancel disable disconnected cable conditioning 6555 * for Power Gating 6556 */ 6557 mac_data = er32(DPGFR); 6558 mac_data &= ~BIT(2); 6559 ew32(DPGFR, mac_data); 6560 6561 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6562 mac_data = er32(CTRL_EXT); 6563 mac_data &= 0xFFF7FFFF; 6564 ew32(CTRL_EXT, mac_data); 6565 6566 /* Revert the lanphypc logic to use the internal Gbe counter 6567 * and not the PMC counter 6568 */ 6569 mac_data = er32(FEXTNVM5); 6570 mac_data &= 0xFFFFFF7F; 6571 ew32(FEXTNVM5, mac_data); 6572 6573 /* Enable the periodic inband message, 6574 * Request PCIe clock in K1 page770_17[10:9] =01b 6575 */ 6576 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6577 phy_data &= 0xFBFF; 6578 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6579 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6580 6581 /* Return back configuration 6582 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6583 */ 6584 e1e_rphy(hw, I217_CGFREG, &phy_data); 6585 phy_data &= 0xFFDF; 6586 e1e_wphy(hw, I217_CGFREG, phy_data); 6587 6588 /* Change the MAC/PHY interface to Kumeran 6589 * Unforce the SMBus in PHY page769_23[0] = 0 6590 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6591 */ 6592 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6593 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6594 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6595 mac_data = er32(CTRL_EXT); 6596 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6597 ew32(CTRL_EXT, mac_data); 6598 } 6599 6600 /* Disable Dynamic Power Gating */ 6601 mac_data = er32(CTRL_EXT); 6602 mac_data &= 0xFFFFFFF7; 6603 ew32(CTRL_EXT, mac_data); 6604 6605 /* Enable the time synchronization clock */ 6606 mac_data = er32(FEXTNVM7); 6607 mac_data &= ~BIT(31); 6608 mac_data |= BIT(0); 6609 ew32(FEXTNVM7, mac_data); 6610 } 6611 6612 static int e1000e_pm_freeze(struct device *dev) 6613 { 6614 struct net_device *netdev = dev_get_drvdata(dev); 6615 struct e1000_adapter *adapter = netdev_priv(netdev); 6616 bool present; 6617 6618 rtnl_lock(); 6619 6620 present = netif_device_present(netdev); 6621 netif_device_detach(netdev); 6622 6623 if (present && netif_running(netdev)) { 6624 int count = E1000_CHECK_RESET_COUNT; 6625 6626 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6627 usleep_range(10000, 11000); 6628 6629 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6630 6631 /* Quiesce the device without resetting the hardware */ 6632 e1000e_down(adapter, false); 6633 e1000_free_irq(adapter); 6634 } 6635 rtnl_unlock(); 6636 6637 e1000e_reset_interrupt_capability(adapter); 6638 6639 /* Allow time for pending master requests to run */ 6640 e1000e_disable_pcie_master(&adapter->hw); 6641 6642 return 0; 6643 } 6644 6645 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6646 { 6647 struct net_device *netdev = pci_get_drvdata(pdev); 6648 struct e1000_adapter *adapter = netdev_priv(netdev); 6649 struct e1000_hw *hw = &adapter->hw; 6650 u32 ctrl, ctrl_ext, rctl, status, wufc; 6651 int retval = 0; 6652 6653 /* Runtime suspend should only enable wakeup for link changes */ 6654 if (runtime) 6655 wufc = E1000_WUFC_LNKC; 6656 else if (device_may_wakeup(&pdev->dev)) 6657 wufc = adapter->wol; 6658 else 6659 wufc = 0; 6660 6661 status = er32(STATUS); 6662 if (status & E1000_STATUS_LU) 6663 wufc &= ~E1000_WUFC_LNKC; 6664 6665 if (wufc) { 6666 e1000_setup_rctl(adapter); 6667 e1000e_set_rx_mode(netdev); 6668 6669 /* turn on all-multi mode if wake on multicast is enabled */ 6670 if (wufc & E1000_WUFC_MC) { 6671 rctl = er32(RCTL); 6672 rctl |= E1000_RCTL_MPE; 6673 ew32(RCTL, rctl); 6674 } 6675 6676 ctrl = er32(CTRL); 6677 ctrl |= E1000_CTRL_ADVD3WUC; 6678 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6679 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6680 ew32(CTRL, ctrl); 6681 6682 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6683 adapter->hw.phy.media_type == 6684 e1000_media_type_internal_serdes) { 6685 /* keep the laser running in D3 */ 6686 ctrl_ext = er32(CTRL_EXT); 6687 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6688 ew32(CTRL_EXT, ctrl_ext); 6689 } 6690 6691 if (!runtime) 6692 e1000e_power_up_phy(adapter); 6693 6694 if (adapter->flags & FLAG_IS_ICH) 6695 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6696 6697 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6698 /* enable wakeup by the PHY */ 6699 retval = e1000_init_phy_wakeup(adapter, wufc); 6700 if (retval) 6701 return retval; 6702 } else { 6703 /* enable wakeup by the MAC */ 6704 ew32(WUFC, wufc); 6705 ew32(WUC, E1000_WUC_PME_EN); 6706 } 6707 } else { 6708 ew32(WUC, 0); 6709 ew32(WUFC, 0); 6710 6711 e1000_power_down_phy(adapter); 6712 } 6713 6714 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6715 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6716 } else if (hw->mac.type >= e1000_pch_lpt) { 6717 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6718 /* ULP does not support wake from unicast, multicast 6719 * or broadcast. 6720 */ 6721 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6722 6723 if (retval) 6724 return retval; 6725 } 6726 6727 /* Ensure that the appropriate bits are set in LPI_CTRL 6728 * for EEE in Sx 6729 */ 6730 if ((hw->phy.type >= e1000_phy_i217) && 6731 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6732 u16 lpi_ctrl = 0; 6733 6734 retval = hw->phy.ops.acquire(hw); 6735 if (!retval) { 6736 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6737 &lpi_ctrl); 6738 if (!retval) { 6739 if (adapter->eee_advert & 6740 hw->dev_spec.ich8lan.eee_lp_ability & 6741 I82579_EEE_100_SUPPORTED) 6742 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6743 if (adapter->eee_advert & 6744 hw->dev_spec.ich8lan.eee_lp_ability & 6745 I82579_EEE_1000_SUPPORTED) 6746 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6747 6748 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6749 lpi_ctrl); 6750 } 6751 } 6752 hw->phy.ops.release(hw); 6753 } 6754 6755 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6756 * would have already happened in close and is redundant. 6757 */ 6758 e1000e_release_hw_control(adapter); 6759 6760 pci_clear_master(pdev); 6761 6762 /* The pci-e switch on some quad port adapters will report a 6763 * correctable error when the MAC transitions from D0 to D3. To 6764 * prevent this we need to mask off the correctable errors on the 6765 * downstream port of the pci-e switch. 6766 * 6767 * We don't have the associated upstream bridge while assigning 6768 * the PCI device into guest. For example, the KVM on power is 6769 * one of the cases. 6770 */ 6771 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6772 struct pci_dev *us_dev = pdev->bus->self; 6773 u16 devctl; 6774 6775 if (!us_dev) 6776 return 0; 6777 6778 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6779 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6780 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6781 6782 pci_save_state(pdev); 6783 pci_prepare_to_sleep(pdev); 6784 6785 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6786 } 6787 6788 return 0; 6789 } 6790 6791 /** 6792 * __e1000e_disable_aspm - Disable ASPM states 6793 * @pdev: pointer to PCI device struct 6794 * @state: bit-mask of ASPM states to disable 6795 * @locked: indication if this context holds pci_bus_sem locked. 6796 * 6797 * Some devices *must* have certain ASPM states disabled per hardware errata. 6798 **/ 6799 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6800 { 6801 struct pci_dev *parent = pdev->bus->self; 6802 u16 aspm_dis_mask = 0; 6803 u16 pdev_aspmc, parent_aspmc; 6804 6805 switch (state) { 6806 case PCIE_LINK_STATE_L0S: 6807 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6808 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6809 fallthrough; /* can't have L1 without L0s */ 6810 case PCIE_LINK_STATE_L1: 6811 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6812 break; 6813 default: 6814 return; 6815 } 6816 6817 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6818 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6819 6820 if (parent) { 6821 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6822 &parent_aspmc); 6823 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6824 } 6825 6826 /* Nothing to do if the ASPM states to be disabled already are */ 6827 if (!(pdev_aspmc & aspm_dis_mask) && 6828 (!parent || !(parent_aspmc & aspm_dis_mask))) 6829 return; 6830 6831 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6832 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6833 "L0s" : "", 6834 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6835 "L1" : ""); 6836 6837 #ifdef CONFIG_PCIEASPM 6838 if (locked) 6839 pci_disable_link_state_locked(pdev, state); 6840 else 6841 pci_disable_link_state(pdev, state); 6842 6843 /* Double-check ASPM control. If not disabled by the above, the 6844 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6845 * not enabled); override by writing PCI config space directly. 6846 */ 6847 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6848 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6849 6850 if (!(aspm_dis_mask & pdev_aspmc)) 6851 return; 6852 #endif 6853 6854 /* Both device and parent should have the same ASPM setting. 6855 * Disable ASPM in downstream component first and then upstream. 6856 */ 6857 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6858 6859 if (parent) 6860 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6861 aspm_dis_mask); 6862 } 6863 6864 /** 6865 * e1000e_disable_aspm - Disable ASPM states. 6866 * @pdev: pointer to PCI device struct 6867 * @state: bit-mask of ASPM states to disable 6868 * 6869 * This function acquires the pci_bus_sem! 6870 * Some devices *must* have certain ASPM states disabled per hardware errata. 6871 **/ 6872 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6873 { 6874 __e1000e_disable_aspm(pdev, state, 0); 6875 } 6876 6877 /** 6878 * e1000e_disable_aspm_locked - Disable ASPM states. 6879 * @pdev: pointer to PCI device struct 6880 * @state: bit-mask of ASPM states to disable 6881 * 6882 * This function must be called with pci_bus_sem acquired! 6883 * Some devices *must* have certain ASPM states disabled per hardware errata. 6884 **/ 6885 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6886 { 6887 __e1000e_disable_aspm(pdev, state, 1); 6888 } 6889 6890 static int e1000e_pm_thaw(struct device *dev) 6891 { 6892 struct net_device *netdev = dev_get_drvdata(dev); 6893 struct e1000_adapter *adapter = netdev_priv(netdev); 6894 int rc = 0; 6895 6896 e1000e_set_interrupt_capability(adapter); 6897 6898 rtnl_lock(); 6899 if (netif_running(netdev)) { 6900 rc = e1000_request_irq(adapter); 6901 if (rc) 6902 goto err_irq; 6903 6904 e1000e_up(adapter); 6905 } 6906 6907 netif_device_attach(netdev); 6908 err_irq: 6909 rtnl_unlock(); 6910 6911 return rc; 6912 } 6913 6914 static int __e1000_resume(struct pci_dev *pdev) 6915 { 6916 struct net_device *netdev = pci_get_drvdata(pdev); 6917 struct e1000_adapter *adapter = netdev_priv(netdev); 6918 struct e1000_hw *hw = &adapter->hw; 6919 u16 aspm_disable_flag = 0; 6920 6921 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6922 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6923 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6924 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6925 if (aspm_disable_flag) 6926 e1000e_disable_aspm(pdev, aspm_disable_flag); 6927 6928 pci_set_master(pdev); 6929 6930 if (hw->mac.type >= e1000_pch2lan) 6931 e1000_resume_workarounds_pchlan(&adapter->hw); 6932 6933 e1000e_power_up_phy(adapter); 6934 6935 /* report the system wakeup cause from S3/S4 */ 6936 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6937 u16 phy_data; 6938 6939 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6940 if (phy_data) { 6941 e_info("PHY Wakeup cause - %s\n", 6942 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6943 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6944 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6945 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6946 phy_data & E1000_WUS_LNKC ? 6947 "Link Status Change" : "other"); 6948 } 6949 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6950 } else { 6951 u32 wus = er32(WUS); 6952 6953 if (wus) { 6954 e_info("MAC Wakeup cause - %s\n", 6955 wus & E1000_WUS_EX ? "Unicast Packet" : 6956 wus & E1000_WUS_MC ? "Multicast Packet" : 6957 wus & E1000_WUS_BC ? "Broadcast Packet" : 6958 wus & E1000_WUS_MAG ? "Magic Packet" : 6959 wus & E1000_WUS_LNKC ? "Link Status Change" : 6960 "other"); 6961 } 6962 ew32(WUS, ~0); 6963 } 6964 6965 e1000e_reset(adapter); 6966 6967 e1000_init_manageability_pt(adapter); 6968 6969 /* If the controller has AMT, do not set DRV_LOAD until the interface 6970 * is up. For all other cases, let the f/w know that the h/w is now 6971 * under the control of the driver. 6972 */ 6973 if (!(adapter->flags & FLAG_HAS_AMT)) 6974 e1000e_get_hw_control(adapter); 6975 6976 return 0; 6977 } 6978 6979 static __maybe_unused int e1000e_pm_prepare(struct device *dev) 6980 { 6981 return pm_runtime_suspended(dev) && 6982 pm_suspend_via_firmware(); 6983 } 6984 6985 static __maybe_unused int e1000e_pm_suspend(struct device *dev) 6986 { 6987 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6988 struct e1000_adapter *adapter = netdev_priv(netdev); 6989 struct pci_dev *pdev = to_pci_dev(dev); 6990 struct e1000_hw *hw = &adapter->hw; 6991 u16 phy_data; 6992 int rc; 6993 6994 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 6995 hw->mac.type >= e1000_pch_adp) { 6996 /* Mask OEM Bits / Gig Disable / Restart AN (772_26[12] = 1) */ 6997 e1e_rphy(hw, I217_MEMPWR, &phy_data); 6998 phy_data |= I217_MEMPWR_MOEM; 6999 e1e_wphy(hw, I217_MEMPWR, phy_data); 7000 7001 /* Disable LCD reset */ 7002 hw->phy.reset_disable = true; 7003 } 7004 7005 e1000e_flush_lpic(pdev); 7006 7007 e1000e_pm_freeze(dev); 7008 7009 rc = __e1000_shutdown(pdev, false); 7010 if (rc) { 7011 e1000e_pm_thaw(dev); 7012 } else { 7013 /* Introduce S0ix implementation */ 7014 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7015 e1000e_s0ix_entry_flow(adapter); 7016 } 7017 7018 return rc; 7019 } 7020 7021 static __maybe_unused int e1000e_pm_resume(struct device *dev) 7022 { 7023 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 7024 struct e1000_adapter *adapter = netdev_priv(netdev); 7025 struct pci_dev *pdev = to_pci_dev(dev); 7026 struct e1000_hw *hw = &adapter->hw; 7027 u16 phy_data; 7028 int rc; 7029 7030 /* Introduce S0ix implementation */ 7031 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS) 7032 e1000e_s0ix_exit_flow(adapter); 7033 7034 rc = __e1000_resume(pdev); 7035 if (rc) 7036 return rc; 7037 7038 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID && 7039 hw->mac.type >= e1000_pch_adp) { 7040 /* Unmask OEM Bits / Gig Disable / Restart AN 772_26[12] = 0 */ 7041 e1e_rphy(hw, I217_MEMPWR, &phy_data); 7042 phy_data &= ~I217_MEMPWR_MOEM; 7043 e1e_wphy(hw, I217_MEMPWR, phy_data); 7044 7045 /* Enable LCD reset */ 7046 hw->phy.reset_disable = false; 7047 } 7048 7049 return e1000e_pm_thaw(dev); 7050 } 7051 7052 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 7053 { 7054 struct net_device *netdev = dev_get_drvdata(dev); 7055 struct e1000_adapter *adapter = netdev_priv(netdev); 7056 u16 eee_lp; 7057 7058 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 7059 7060 if (!e1000e_has_link(adapter)) { 7061 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 7062 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 7063 } 7064 7065 return -EBUSY; 7066 } 7067 7068 static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev) 7069 { 7070 struct pci_dev *pdev = to_pci_dev(dev); 7071 struct net_device *netdev = pci_get_drvdata(pdev); 7072 struct e1000_adapter *adapter = netdev_priv(netdev); 7073 int rc; 7074 7075 rc = __e1000_resume(pdev); 7076 if (rc) 7077 return rc; 7078 7079 if (netdev->flags & IFF_UP) 7080 e1000e_up(adapter); 7081 7082 return rc; 7083 } 7084 7085 static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev) 7086 { 7087 struct pci_dev *pdev = to_pci_dev(dev); 7088 struct net_device *netdev = pci_get_drvdata(pdev); 7089 struct e1000_adapter *adapter = netdev_priv(netdev); 7090 7091 if (netdev->flags & IFF_UP) { 7092 int count = E1000_CHECK_RESET_COUNT; 7093 7094 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7095 usleep_range(10000, 11000); 7096 7097 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7098 7099 /* Down the device without resetting the hardware */ 7100 e1000e_down(adapter, false); 7101 } 7102 7103 if (__e1000_shutdown(pdev, true)) { 7104 e1000e_pm_runtime_resume(dev); 7105 return -EBUSY; 7106 } 7107 7108 return 0; 7109 } 7110 7111 static void e1000_shutdown(struct pci_dev *pdev) 7112 { 7113 e1000e_flush_lpic(pdev); 7114 7115 e1000e_pm_freeze(&pdev->dev); 7116 7117 __e1000_shutdown(pdev, false); 7118 } 7119 7120 #ifdef CONFIG_NET_POLL_CONTROLLER 7121 7122 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7123 { 7124 struct net_device *netdev = data; 7125 struct e1000_adapter *adapter = netdev_priv(netdev); 7126 7127 if (adapter->msix_entries) { 7128 int vector, msix_irq; 7129 7130 vector = 0; 7131 msix_irq = adapter->msix_entries[vector].vector; 7132 if (disable_hardirq(msix_irq)) 7133 e1000_intr_msix_rx(msix_irq, netdev); 7134 enable_irq(msix_irq); 7135 7136 vector++; 7137 msix_irq = adapter->msix_entries[vector].vector; 7138 if (disable_hardirq(msix_irq)) 7139 e1000_intr_msix_tx(msix_irq, netdev); 7140 enable_irq(msix_irq); 7141 7142 vector++; 7143 msix_irq = adapter->msix_entries[vector].vector; 7144 if (disable_hardirq(msix_irq)) 7145 e1000_msix_other(msix_irq, netdev); 7146 enable_irq(msix_irq); 7147 } 7148 7149 return IRQ_HANDLED; 7150 } 7151 7152 /** 7153 * e1000_netpoll 7154 * @netdev: network interface device structure 7155 * 7156 * Polling 'interrupt' - used by things like netconsole to send skbs 7157 * without having to re-enable interrupts. It's not called while 7158 * the interrupt routine is executing. 7159 */ 7160 static void e1000_netpoll(struct net_device *netdev) 7161 { 7162 struct e1000_adapter *adapter = netdev_priv(netdev); 7163 7164 switch (adapter->int_mode) { 7165 case E1000E_INT_MODE_MSIX: 7166 e1000_intr_msix(adapter->pdev->irq, netdev); 7167 break; 7168 case E1000E_INT_MODE_MSI: 7169 if (disable_hardirq(adapter->pdev->irq)) 7170 e1000_intr_msi(adapter->pdev->irq, netdev); 7171 enable_irq(adapter->pdev->irq); 7172 break; 7173 default: /* E1000E_INT_MODE_LEGACY */ 7174 if (disable_hardirq(adapter->pdev->irq)) 7175 e1000_intr(adapter->pdev->irq, netdev); 7176 enable_irq(adapter->pdev->irq); 7177 break; 7178 } 7179 } 7180 #endif 7181 7182 /** 7183 * e1000_io_error_detected - called when PCI error is detected 7184 * @pdev: Pointer to PCI device 7185 * @state: The current pci connection state 7186 * 7187 * This function is called after a PCI bus error affecting 7188 * this device has been detected. 7189 */ 7190 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7191 pci_channel_state_t state) 7192 { 7193 e1000e_pm_freeze(&pdev->dev); 7194 7195 if (state == pci_channel_io_perm_failure) 7196 return PCI_ERS_RESULT_DISCONNECT; 7197 7198 pci_disable_device(pdev); 7199 7200 /* Request a slot reset. */ 7201 return PCI_ERS_RESULT_NEED_RESET; 7202 } 7203 7204 /** 7205 * e1000_io_slot_reset - called after the pci bus has been reset. 7206 * @pdev: Pointer to PCI device 7207 * 7208 * Restart the card from scratch, as if from a cold-boot. Implementation 7209 * resembles the first-half of the e1000e_pm_resume routine. 7210 */ 7211 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7212 { 7213 struct net_device *netdev = pci_get_drvdata(pdev); 7214 struct e1000_adapter *adapter = netdev_priv(netdev); 7215 struct e1000_hw *hw = &adapter->hw; 7216 u16 aspm_disable_flag = 0; 7217 int err; 7218 pci_ers_result_t result; 7219 7220 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7221 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7222 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7223 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7224 if (aspm_disable_flag) 7225 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7226 7227 err = pci_enable_device_mem(pdev); 7228 if (err) { 7229 dev_err(&pdev->dev, 7230 "Cannot re-enable PCI device after reset.\n"); 7231 result = PCI_ERS_RESULT_DISCONNECT; 7232 } else { 7233 pdev->state_saved = true; 7234 pci_restore_state(pdev); 7235 pci_set_master(pdev); 7236 7237 pci_enable_wake(pdev, PCI_D3hot, 0); 7238 pci_enable_wake(pdev, PCI_D3cold, 0); 7239 7240 e1000e_reset(adapter); 7241 ew32(WUS, ~0); 7242 result = PCI_ERS_RESULT_RECOVERED; 7243 } 7244 7245 return result; 7246 } 7247 7248 /** 7249 * e1000_io_resume - called when traffic can start flowing again. 7250 * @pdev: Pointer to PCI device 7251 * 7252 * This callback is called when the error recovery driver tells us that 7253 * its OK to resume normal operation. Implementation resembles the 7254 * second-half of the e1000e_pm_resume routine. 7255 */ 7256 static void e1000_io_resume(struct pci_dev *pdev) 7257 { 7258 struct net_device *netdev = pci_get_drvdata(pdev); 7259 struct e1000_adapter *adapter = netdev_priv(netdev); 7260 7261 e1000_init_manageability_pt(adapter); 7262 7263 e1000e_pm_thaw(&pdev->dev); 7264 7265 /* If the controller has AMT, do not set DRV_LOAD until the interface 7266 * is up. For all other cases, let the f/w know that the h/w is now 7267 * under the control of the driver. 7268 */ 7269 if (!(adapter->flags & FLAG_HAS_AMT)) 7270 e1000e_get_hw_control(adapter); 7271 } 7272 7273 static void e1000_print_device_info(struct e1000_adapter *adapter) 7274 { 7275 struct e1000_hw *hw = &adapter->hw; 7276 struct net_device *netdev = adapter->netdev; 7277 u32 ret_val; 7278 u8 pba_str[E1000_PBANUM_LENGTH]; 7279 7280 /* print bus type/speed/width info */ 7281 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7282 /* bus width */ 7283 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7284 "Width x1"), 7285 /* MAC address */ 7286 netdev->dev_addr); 7287 e_info("Intel(R) PRO/%s Network Connection\n", 7288 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7289 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7290 E1000_PBANUM_LENGTH); 7291 if (ret_val) 7292 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7293 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7294 hw->mac.type, hw->phy.type, pba_str); 7295 } 7296 7297 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7298 { 7299 struct e1000_hw *hw = &adapter->hw; 7300 int ret_val; 7301 u16 buf = 0; 7302 7303 if (hw->mac.type != e1000_82573) 7304 return; 7305 7306 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7307 le16_to_cpus(&buf); 7308 if (!ret_val && (!(buf & BIT(0)))) { 7309 /* Deep Smart Power Down (DSPD) */ 7310 dev_warn(&adapter->pdev->dev, 7311 "Warning: detected DSPD enabled in EEPROM\n"); 7312 } 7313 } 7314 7315 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7316 netdev_features_t features) 7317 { 7318 struct e1000_adapter *adapter = netdev_priv(netdev); 7319 struct e1000_hw *hw = &adapter->hw; 7320 7321 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7322 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7323 features &= ~NETIF_F_RXFCS; 7324 7325 /* Since there is no support for separate Rx/Tx vlan accel 7326 * enable/disable make sure Tx flag is always in same state as Rx. 7327 */ 7328 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7329 features |= NETIF_F_HW_VLAN_CTAG_TX; 7330 else 7331 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7332 7333 return features; 7334 } 7335 7336 static int e1000_set_features(struct net_device *netdev, 7337 netdev_features_t features) 7338 { 7339 struct e1000_adapter *adapter = netdev_priv(netdev); 7340 netdev_features_t changed = features ^ netdev->features; 7341 7342 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7343 adapter->flags |= FLAG_TSO_FORCE; 7344 7345 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7346 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7347 NETIF_F_RXALL))) 7348 return 0; 7349 7350 if (changed & NETIF_F_RXFCS) { 7351 if (features & NETIF_F_RXFCS) { 7352 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7353 } else { 7354 /* We need to take it back to defaults, which might mean 7355 * stripping is still disabled at the adapter level. 7356 */ 7357 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7358 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7359 else 7360 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7361 } 7362 } 7363 7364 netdev->features = features; 7365 7366 if (netif_running(netdev)) 7367 e1000e_reinit_locked(adapter); 7368 else 7369 e1000e_reset(adapter); 7370 7371 return 1; 7372 } 7373 7374 static const struct net_device_ops e1000e_netdev_ops = { 7375 .ndo_open = e1000e_open, 7376 .ndo_stop = e1000e_close, 7377 .ndo_start_xmit = e1000_xmit_frame, 7378 .ndo_get_stats64 = e1000e_get_stats64, 7379 .ndo_set_rx_mode = e1000e_set_rx_mode, 7380 .ndo_set_mac_address = e1000_set_mac, 7381 .ndo_change_mtu = e1000_change_mtu, 7382 .ndo_eth_ioctl = e1000_ioctl, 7383 .ndo_tx_timeout = e1000_tx_timeout, 7384 .ndo_validate_addr = eth_validate_addr, 7385 7386 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7387 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7388 #ifdef CONFIG_NET_POLL_CONTROLLER 7389 .ndo_poll_controller = e1000_netpoll, 7390 #endif 7391 .ndo_set_features = e1000_set_features, 7392 .ndo_fix_features = e1000_fix_features, 7393 .ndo_features_check = passthru_features_check, 7394 }; 7395 7396 /** 7397 * e1000_probe - Device Initialization Routine 7398 * @pdev: PCI device information struct 7399 * @ent: entry in e1000_pci_tbl 7400 * 7401 * Returns 0 on success, negative on failure 7402 * 7403 * e1000_probe initializes an adapter identified by a pci_dev structure. 7404 * The OS initialization, configuring of the adapter private structure, 7405 * and a hardware reset occur. 7406 **/ 7407 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7408 { 7409 struct net_device *netdev; 7410 struct e1000_adapter *adapter; 7411 struct e1000_hw *hw; 7412 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7413 resource_size_t mmio_start, mmio_len; 7414 resource_size_t flash_start, flash_len; 7415 static int cards_found; 7416 u16 aspm_disable_flag = 0; 7417 u16 eeprom_data = 0; 7418 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7419 int bars, i, err; 7420 s32 ret_val = 0; 7421 7422 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7423 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7424 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7425 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7426 if (aspm_disable_flag) 7427 e1000e_disable_aspm(pdev, aspm_disable_flag); 7428 7429 err = pci_enable_device_mem(pdev); 7430 if (err) 7431 return err; 7432 7433 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7434 if (err) { 7435 dev_err(&pdev->dev, 7436 "No usable DMA configuration, aborting\n"); 7437 goto err_dma; 7438 } 7439 7440 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7441 err = pci_request_selected_regions_exclusive(pdev, bars, 7442 e1000e_driver_name); 7443 if (err) 7444 goto err_pci_reg; 7445 7446 /* AER (Advanced Error Reporting) hooks */ 7447 pci_enable_pcie_error_reporting(pdev); 7448 7449 pci_set_master(pdev); 7450 /* PCI config space info */ 7451 err = pci_save_state(pdev); 7452 if (err) 7453 goto err_alloc_etherdev; 7454 7455 err = -ENOMEM; 7456 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7457 if (!netdev) 7458 goto err_alloc_etherdev; 7459 7460 SET_NETDEV_DEV(netdev, &pdev->dev); 7461 7462 netdev->irq = pdev->irq; 7463 7464 pci_set_drvdata(pdev, netdev); 7465 adapter = netdev_priv(netdev); 7466 hw = &adapter->hw; 7467 adapter->netdev = netdev; 7468 adapter->pdev = pdev; 7469 adapter->ei = ei; 7470 adapter->pba = ei->pba; 7471 adapter->flags = ei->flags; 7472 adapter->flags2 = ei->flags2; 7473 adapter->hw.adapter = adapter; 7474 adapter->hw.mac.type = ei->mac; 7475 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7476 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7477 7478 mmio_start = pci_resource_start(pdev, 0); 7479 mmio_len = pci_resource_len(pdev, 0); 7480 7481 err = -EIO; 7482 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7483 if (!adapter->hw.hw_addr) 7484 goto err_ioremap; 7485 7486 if ((adapter->flags & FLAG_HAS_FLASH) && 7487 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7488 (hw->mac.type < e1000_pch_spt)) { 7489 flash_start = pci_resource_start(pdev, 1); 7490 flash_len = pci_resource_len(pdev, 1); 7491 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7492 if (!adapter->hw.flash_address) 7493 goto err_flashmap; 7494 } 7495 7496 /* Set default EEE advertisement */ 7497 if (adapter->flags2 & FLAG2_HAS_EEE) 7498 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7499 7500 /* construct the net_device struct */ 7501 netdev->netdev_ops = &e1000e_netdev_ops; 7502 e1000e_set_ethtool_ops(netdev); 7503 netdev->watchdog_timeo = 5 * HZ; 7504 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7505 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7506 7507 netdev->mem_start = mmio_start; 7508 netdev->mem_end = mmio_start + mmio_len; 7509 7510 adapter->bd_number = cards_found++; 7511 7512 e1000e_check_options(adapter); 7513 7514 /* setup adapter struct */ 7515 err = e1000_sw_init(adapter); 7516 if (err) 7517 goto err_sw_init; 7518 7519 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7520 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7521 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7522 7523 err = ei->get_variants(adapter); 7524 if (err) 7525 goto err_hw_init; 7526 7527 if ((adapter->flags & FLAG_IS_ICH) && 7528 (adapter->flags & FLAG_READ_ONLY_NVM) && 7529 (hw->mac.type < e1000_pch_spt)) 7530 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7531 7532 hw->mac.ops.get_bus_info(&adapter->hw); 7533 7534 adapter->hw.phy.autoneg_wait_to_complete = 0; 7535 7536 /* Copper options */ 7537 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7538 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7539 adapter->hw.phy.disable_polarity_correction = 0; 7540 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7541 } 7542 7543 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7544 dev_info(&pdev->dev, 7545 "PHY reset is blocked due to SOL/IDER session.\n"); 7546 7547 /* Set initial default active device features */ 7548 netdev->features = (NETIF_F_SG | 7549 NETIF_F_HW_VLAN_CTAG_RX | 7550 NETIF_F_HW_VLAN_CTAG_TX | 7551 NETIF_F_TSO | 7552 NETIF_F_TSO6 | 7553 NETIF_F_RXHASH | 7554 NETIF_F_RXCSUM | 7555 NETIF_F_HW_CSUM); 7556 7557 /* Set user-changeable features (subset of all device features) */ 7558 netdev->hw_features = netdev->features; 7559 netdev->hw_features |= NETIF_F_RXFCS; 7560 netdev->priv_flags |= IFF_SUPP_NOFCS; 7561 netdev->hw_features |= NETIF_F_RXALL; 7562 7563 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7564 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7565 7566 netdev->vlan_features |= (NETIF_F_SG | 7567 NETIF_F_TSO | 7568 NETIF_F_TSO6 | 7569 NETIF_F_HW_CSUM); 7570 7571 netdev->priv_flags |= IFF_UNICAST_FLT; 7572 7573 netdev->features |= NETIF_F_HIGHDMA; 7574 netdev->vlan_features |= NETIF_F_HIGHDMA; 7575 7576 /* MTU range: 68 - max_hw_frame_size */ 7577 netdev->min_mtu = ETH_MIN_MTU; 7578 netdev->max_mtu = adapter->max_hw_frame_size - 7579 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7580 7581 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7582 adapter->flags |= FLAG_MNG_PT_ENABLED; 7583 7584 /* before reading the NVM, reset the controller to 7585 * put the device in a known good starting state 7586 */ 7587 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7588 7589 /* systems with ASPM and others may see the checksum fail on the first 7590 * attempt. Let's give it a few tries 7591 */ 7592 for (i = 0;; i++) { 7593 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7594 break; 7595 if (i == 2) { 7596 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7597 err = -EIO; 7598 goto err_eeprom; 7599 } 7600 } 7601 7602 e1000_eeprom_checks(adapter); 7603 7604 /* copy the MAC address */ 7605 if (e1000e_read_mac_addr(&adapter->hw)) 7606 dev_err(&pdev->dev, 7607 "NVM Read Error while reading MAC address\n"); 7608 7609 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 7610 7611 if (!is_valid_ether_addr(netdev->dev_addr)) { 7612 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7613 netdev->dev_addr); 7614 err = -EIO; 7615 goto err_eeprom; 7616 } 7617 7618 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7619 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7620 7621 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7622 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7623 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7624 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7625 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7626 7627 /* Initialize link parameters. User can change them with ethtool */ 7628 adapter->hw.mac.autoneg = 1; 7629 adapter->fc_autoneg = true; 7630 adapter->hw.fc.requested_mode = e1000_fc_default; 7631 adapter->hw.fc.current_mode = e1000_fc_default; 7632 adapter->hw.phy.autoneg_advertised = 0x2f; 7633 7634 /* Initial Wake on LAN setting - If APM wake is enabled in 7635 * the EEPROM, enable the ACPI Magic Packet filter 7636 */ 7637 if (adapter->flags & FLAG_APME_IN_WUC) { 7638 /* APME bit in EEPROM is mapped to WUC.APME */ 7639 eeprom_data = er32(WUC); 7640 eeprom_apme_mask = E1000_WUC_APME; 7641 if ((hw->mac.type > e1000_ich10lan) && 7642 (eeprom_data & E1000_WUC_PHY_WAKE)) 7643 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7644 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7645 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7646 (adapter->hw.bus.func == 1)) 7647 ret_val = e1000_read_nvm(&adapter->hw, 7648 NVM_INIT_CONTROL3_PORT_B, 7649 1, &eeprom_data); 7650 else 7651 ret_val = e1000_read_nvm(&adapter->hw, 7652 NVM_INIT_CONTROL3_PORT_A, 7653 1, &eeprom_data); 7654 } 7655 7656 /* fetch WoL from EEPROM */ 7657 if (ret_val) 7658 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7659 else if (eeprom_data & eeprom_apme_mask) 7660 adapter->eeprom_wol |= E1000_WUFC_MAG; 7661 7662 /* now that we have the eeprom settings, apply the special cases 7663 * where the eeprom may be wrong or the board simply won't support 7664 * wake on lan on a particular port 7665 */ 7666 if (!(adapter->flags & FLAG_HAS_WOL)) 7667 adapter->eeprom_wol = 0; 7668 7669 /* initialize the wol settings based on the eeprom settings */ 7670 adapter->wol = adapter->eeprom_wol; 7671 7672 /* make sure adapter isn't asleep if manageability is enabled */ 7673 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7674 (hw->mac.ops.check_mng_mode(hw))) 7675 device_wakeup_enable(&pdev->dev); 7676 7677 /* save off EEPROM version number */ 7678 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7679 7680 if (ret_val) { 7681 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7682 adapter->eeprom_vers = 0; 7683 } 7684 7685 /* init PTP hardware clock */ 7686 e1000e_ptp_init(adapter); 7687 7688 /* reset the hardware with the new settings */ 7689 e1000e_reset(adapter); 7690 7691 /* If the controller has AMT, do not set DRV_LOAD until the interface 7692 * is up. For all other cases, let the f/w know that the h/w is now 7693 * under the control of the driver. 7694 */ 7695 if (!(adapter->flags & FLAG_HAS_AMT)) 7696 e1000e_get_hw_control(adapter); 7697 7698 if (hw->mac.type >= e1000_pch_cnp) 7699 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS; 7700 7701 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7702 err = register_netdev(netdev); 7703 if (err) 7704 goto err_register; 7705 7706 /* carrier off reporting is important to ethtool even BEFORE open */ 7707 netif_carrier_off(netdev); 7708 7709 e1000_print_device_info(adapter); 7710 7711 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE); 7712 7713 if (pci_dev_run_wake(pdev) && hw->mac.type != e1000_pch_cnp) 7714 pm_runtime_put_noidle(&pdev->dev); 7715 7716 return 0; 7717 7718 err_register: 7719 if (!(adapter->flags & FLAG_HAS_AMT)) 7720 e1000e_release_hw_control(adapter); 7721 err_eeprom: 7722 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7723 e1000_phy_hw_reset(&adapter->hw); 7724 err_hw_init: 7725 kfree(adapter->tx_ring); 7726 kfree(adapter->rx_ring); 7727 err_sw_init: 7728 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7729 iounmap(adapter->hw.flash_address); 7730 e1000e_reset_interrupt_capability(adapter); 7731 err_flashmap: 7732 iounmap(adapter->hw.hw_addr); 7733 err_ioremap: 7734 free_netdev(netdev); 7735 err_alloc_etherdev: 7736 pci_disable_pcie_error_reporting(pdev); 7737 pci_release_mem_regions(pdev); 7738 err_pci_reg: 7739 err_dma: 7740 pci_disable_device(pdev); 7741 return err; 7742 } 7743 7744 /** 7745 * e1000_remove - Device Removal Routine 7746 * @pdev: PCI device information struct 7747 * 7748 * e1000_remove is called by the PCI subsystem to alert the driver 7749 * that it should release a PCI device. This could be caused by a 7750 * Hot-Plug event, or because the driver is going to be removed from 7751 * memory. 7752 **/ 7753 static void e1000_remove(struct pci_dev *pdev) 7754 { 7755 struct net_device *netdev = pci_get_drvdata(pdev); 7756 struct e1000_adapter *adapter = netdev_priv(netdev); 7757 7758 e1000e_ptp_remove(adapter); 7759 7760 /* The timers may be rescheduled, so explicitly disable them 7761 * from being rescheduled. 7762 */ 7763 set_bit(__E1000_DOWN, &adapter->state); 7764 del_timer_sync(&adapter->watchdog_timer); 7765 del_timer_sync(&adapter->phy_info_timer); 7766 7767 cancel_work_sync(&adapter->reset_task); 7768 cancel_work_sync(&adapter->watchdog_task); 7769 cancel_work_sync(&adapter->downshift_task); 7770 cancel_work_sync(&adapter->update_phy_task); 7771 cancel_work_sync(&adapter->print_hang_task); 7772 7773 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7774 cancel_work_sync(&adapter->tx_hwtstamp_work); 7775 if (adapter->tx_hwtstamp_skb) { 7776 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7777 adapter->tx_hwtstamp_skb = NULL; 7778 } 7779 } 7780 7781 unregister_netdev(netdev); 7782 7783 if (pci_dev_run_wake(pdev)) 7784 pm_runtime_get_noresume(&pdev->dev); 7785 7786 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7787 * would have already happened in close and is redundant. 7788 */ 7789 e1000e_release_hw_control(adapter); 7790 7791 e1000e_reset_interrupt_capability(adapter); 7792 kfree(adapter->tx_ring); 7793 kfree(adapter->rx_ring); 7794 7795 iounmap(adapter->hw.hw_addr); 7796 if ((adapter->hw.flash_address) && 7797 (adapter->hw.mac.type < e1000_pch_spt)) 7798 iounmap(adapter->hw.flash_address); 7799 pci_release_mem_regions(pdev); 7800 7801 free_netdev(netdev); 7802 7803 /* AER disable */ 7804 pci_disable_pcie_error_reporting(pdev); 7805 7806 pci_disable_device(pdev); 7807 } 7808 7809 /* PCI Error Recovery (ERS) */ 7810 static const struct pci_error_handlers e1000_err_handler = { 7811 .error_detected = e1000_io_error_detected, 7812 .slot_reset = e1000_io_slot_reset, 7813 .resume = e1000_io_resume, 7814 }; 7815 7816 static const struct pci_device_id e1000_pci_tbl[] = { 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7821 board_82571 }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7827 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7832 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7836 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7840 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7842 board_80003es2lan }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7844 board_80003es2lan }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7846 board_80003es2lan }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7848 board_80003es2lan }, 7849 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7858 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7868 7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7872 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7876 7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7881 7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7884 7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, 7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, 7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, 7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, 7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, 7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, 7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp }, 7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp }, 7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp }, 7925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp }, 7926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp }, 7927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp }, 7928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp }, 7929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp }, 7930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_adp }, 7931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_adp }, 7932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_adp }, 7933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_adp }, 7934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_adp }, 7935 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_adp }, 7936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_adp }, 7937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_adp }, 7938 7939 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7940 }; 7941 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7942 7943 static const struct dev_pm_ops e1000_pm_ops = { 7944 #ifdef CONFIG_PM_SLEEP 7945 .prepare = e1000e_pm_prepare, 7946 .suspend = e1000e_pm_suspend, 7947 .resume = e1000e_pm_resume, 7948 .freeze = e1000e_pm_freeze, 7949 .thaw = e1000e_pm_thaw, 7950 .poweroff = e1000e_pm_suspend, 7951 .restore = e1000e_pm_resume, 7952 #endif 7953 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7954 e1000e_pm_runtime_idle) 7955 }; 7956 7957 /* PCI Device API Driver */ 7958 static struct pci_driver e1000_driver = { 7959 .name = e1000e_driver_name, 7960 .id_table = e1000_pci_tbl, 7961 .probe = e1000_probe, 7962 .remove = e1000_remove, 7963 .driver = { 7964 .pm = &e1000_pm_ops, 7965 }, 7966 .shutdown = e1000_shutdown, 7967 .err_handler = &e1000_err_handler 7968 }; 7969 7970 /** 7971 * e1000_init_module - Driver Registration Routine 7972 * 7973 * e1000_init_module is the first routine called when the driver is 7974 * loaded. All it does is register with the PCI subsystem. 7975 **/ 7976 static int __init e1000_init_module(void) 7977 { 7978 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7979 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7980 7981 return pci_register_driver(&e1000_driver); 7982 } 7983 module_init(e1000_init_module); 7984 7985 /** 7986 * e1000_exit_module - Driver Exit Cleanup Routine 7987 * 7988 * e1000_exit_module is called just before the driver is removed 7989 * from memory. 7990 **/ 7991 static void __exit e1000_exit_module(void) 7992 { 7993 pci_unregister_driver(&e1000_driver); 7994 } 7995 module_exit(e1000_exit_module); 7996 7997 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7998 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7999 MODULE_LICENSE("GPL v2"); 8000 8001 /* netdev.c */ 8002