1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <linux/pci.h> 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/types.h> 10 #include <linux/avf/virtchnl.h> 11 #include <linux/net/intel/i40e_client.h> 12 #include <net/devlink.h> 13 #include <net/pkt_cls.h> 14 #include <net/udp_tunnel.h> 15 #include "i40e_dcb.h" 16 #include "i40e_debug.h" 17 #include "i40e_devlink.h" 18 #include "i40e_io.h" 19 #include "i40e_prototype.h" 20 #include "i40e_register.h" 21 #include "i40e_txrx.h" 22 23 /* Useful i40e defaults */ 24 #define I40E_MAX_VEB 16 25 26 #define I40E_MAX_NUM_DESCRIPTORS 4096 27 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 28 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 29 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 30 #define I40E_MIN_NUM_DESCRIPTORS 64 31 #define I40E_MIN_MSIX 2 32 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 33 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 34 /* max 16 qps */ 35 #define i40e_default_queues_per_vmdq(pf) \ 36 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 37 #define I40E_DEFAULT_QUEUES_PER_VF 4 38 #define I40E_MAX_VF_QUEUES 16 39 #define i40e_pf_get_max_q_per_tc(pf) \ 40 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 41 #define I40E_FDIR_RING_COUNT 32 42 #define I40E_MAX_AQ_BUF_SIZE 4096 43 #define I40E_AQ_LEN 256 44 #define I40E_MIN_ARQ_LEN 1 45 #define I40E_MIN_ASQ_LEN 2 46 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 47 #define I40E_MAX_USER_PRIORITY 8 48 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 49 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 50 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 51 52 #define I40E_PHY_DEBUG_ALL \ 53 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 54 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 55 56 #define I40E_OEM_EETRACK_ID 0xffffffff 57 #define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0) 58 #define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12) 59 #define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8) 60 #define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0) 61 #define I40E_OEM_VER_MASK GENMASK(31, 24) 62 #define I40E_OEM_GEN_MASK GENMASK(31, 24) 63 #define I40E_OEM_SNAP_MASK GENMASK(23, 16) 64 #define I40E_OEM_RELEASE_MASK GENMASK(15, 0) 65 66 #define I40E_RX_DESC(R, i) \ 67 (&(((union i40e_rx_desc *)((R)->desc))[i])) 68 #define I40E_TX_DESC(R, i) \ 69 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 70 #define I40E_TX_CTXTDESC(R, i) \ 71 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 72 #define I40E_TX_FDIRDESC(R, i) \ 73 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 74 75 /* BW rate limiting */ 76 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 77 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 78 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 79 80 /* driver state flags */ 81 enum i40e_state_t { 82 __I40E_TESTING, 83 __I40E_CONFIG_BUSY, 84 __I40E_CONFIG_DONE, 85 __I40E_DOWN, 86 __I40E_SERVICE_SCHED, 87 __I40E_ADMINQ_EVENT_PENDING, 88 __I40E_MDD_EVENT_PENDING, 89 __I40E_VFLR_EVENT_PENDING, 90 __I40E_RESET_RECOVERY_PENDING, 91 __I40E_TIMEOUT_RECOVERY_PENDING, 92 __I40E_MISC_IRQ_REQUESTED, 93 __I40E_RESET_INTR_RECEIVED, 94 __I40E_REINIT_REQUESTED, 95 __I40E_PF_RESET_REQUESTED, 96 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 97 __I40E_CORE_RESET_REQUESTED, 98 __I40E_GLOBAL_RESET_REQUESTED, 99 __I40E_EMP_RESET_INTR_RECEIVED, 100 __I40E_SUSPENDED, 101 __I40E_PTP_TX_IN_PROGRESS, 102 __I40E_BAD_EEPROM, 103 __I40E_DOWN_REQUESTED, 104 __I40E_FD_FLUSH_REQUESTED, 105 __I40E_FD_ATR_AUTO_DISABLED, 106 __I40E_FD_SB_AUTO_DISABLED, 107 __I40E_RESET_FAILED, 108 __I40E_PORT_SUSPENDED, 109 __I40E_VF_DISABLE, 110 __I40E_MACVLAN_SYNC_PENDING, 111 __I40E_TEMP_LINK_POLLING, 112 __I40E_CLIENT_SERVICE_REQUESTED, 113 __I40E_CLIENT_L2_CHANGE, 114 __I40E_CLIENT_RESET, 115 __I40E_VIRTCHNL_OP_PENDING, 116 __I40E_RECOVERY_MODE, 117 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 118 __I40E_IN_REMOVE, 119 __I40E_VFS_RELEASING, 120 /* This must be last as it determines the size of the BITMAP */ 121 __I40E_STATE_SIZE__, 122 }; 123 124 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 125 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 126 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 127 128 /* VSI state flags */ 129 enum i40e_vsi_state_t { 130 __I40E_VSI_DOWN, 131 __I40E_VSI_NEEDS_RESTART, 132 __I40E_VSI_SYNCING_FILTERS, 133 __I40E_VSI_OVERFLOW_PROMISC, 134 __I40E_VSI_REINIT_REQUESTED, 135 __I40E_VSI_DOWN_REQUESTED, 136 __I40E_VSI_RELEASING, 137 /* This must be last as it determines the size of the BITMAP */ 138 __I40E_VSI_STATE_SIZE__, 139 }; 140 141 enum i40e_interrupt_policy { 142 I40E_INTERRUPT_BEST_CASE, 143 I40E_INTERRUPT_MEDIUM, 144 I40E_INTERRUPT_LOWEST 145 }; 146 147 struct i40e_lump_tracking { 148 u16 num_entries; 149 u16 list[]; 150 #define I40E_PILE_VALID_BIT 0x8000 151 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 152 }; 153 154 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 155 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 156 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 157 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 158 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 159 160 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 161 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 162 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 163 164 enum i40e_fd_stat_idx { 165 I40E_FD_STAT_ATR, 166 I40E_FD_STAT_SB, 167 I40E_FD_STAT_ATR_TUNNEL, 168 I40E_FD_STAT_PF_COUNT 169 }; 170 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 171 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 172 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 173 #define I40E_FD_SB_STAT_IDX(pf_id) \ 174 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 175 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 176 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 177 178 /* The following structure contains the data parsed from the user-defined 179 * field of the ethtool_rx_flow_spec structure. 180 */ 181 struct i40e_rx_flow_userdef { 182 bool flex_filter; 183 u16 flex_word; 184 u16 flex_offset; 185 }; 186 187 struct i40e_fdir_filter { 188 struct hlist_node fdir_node; 189 /* filter ipnut set */ 190 u8 flow_type; 191 u8 ipl4_proto; 192 /* TX packet view of src and dst */ 193 __be32 dst_ip; 194 __be32 src_ip; 195 __be32 dst_ip6[4]; 196 __be32 src_ip6[4]; 197 __be16 src_port; 198 __be16 dst_port; 199 __be32 sctp_v_tag; 200 201 __be16 vlan_etype; 202 __be16 vlan_tag; 203 /* Flexible data to match within the packet payload */ 204 __be16 flex_word; 205 u16 flex_offset; 206 bool flex_filter; 207 208 /* filter control */ 209 u16 q_index; 210 u8 flex_off; 211 u8 pctype; 212 u16 dest_vsi; 213 u8 dest_ctl; 214 u8 fd_status; 215 u16 cnt_index; 216 u32 fd_id; 217 }; 218 219 #define I40E_CLOUD_FIELD_OMAC BIT(0) 220 #define I40E_CLOUD_FIELD_IMAC BIT(1) 221 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 222 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 223 #define I40E_CLOUD_FIELD_IIP BIT(4) 224 225 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 226 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 227 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 228 I40E_CLOUD_FIELD_IVLAN) 229 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 230 I40E_CLOUD_FIELD_TEN_ID) 231 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 232 I40E_CLOUD_FIELD_IMAC | \ 233 I40E_CLOUD_FIELD_TEN_ID) 234 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 235 I40E_CLOUD_FIELD_IVLAN | \ 236 I40E_CLOUD_FIELD_TEN_ID) 237 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 238 239 struct i40e_cloud_filter { 240 struct hlist_node cloud_node; 241 unsigned long cookie; 242 /* cloud filter input set follows */ 243 u8 dst_mac[ETH_ALEN]; 244 u8 src_mac[ETH_ALEN]; 245 __be16 vlan_id; 246 u16 seid; /* filter control */ 247 __be16 dst_port; 248 __be16 src_port; 249 u32 tenant_id; 250 union { 251 struct { 252 struct in_addr dst_ip; 253 struct in_addr src_ip; 254 } v4; 255 struct { 256 struct in6_addr dst_ip6; 257 struct in6_addr src_ip6; 258 } v6; 259 } ip; 260 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 261 #define src_ipv6 ip.v6.src_ip6.s6_addr32 262 #define dst_ipv4 ip.v4.dst_ip.s_addr 263 #define src_ipv4 ip.v4.src_ip.s_addr 264 u16 n_proto; /* Ethernet Protocol */ 265 u8 ip_proto; /* IPPROTO value */ 266 u8 flags; 267 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 268 u8 tunnel_type; 269 }; 270 271 #define I40E_DCB_PRIO_TYPE_STRICT 0 272 #define I40E_DCB_PRIO_TYPE_ETS 1 273 #define I40E_DCB_STRICT_PRIO_CREDITS 127 274 /* DCB per TC information data structure */ 275 struct i40e_tc_info { 276 u16 qoffset; /* Queue offset from base queue */ 277 u16 qcount; /* Total Queues */ 278 u8 netdev_tc; /* Netdev TC index if netdev associated */ 279 }; 280 281 /* TC configuration data structure */ 282 struct i40e_tc_configuration { 283 u8 numtc; /* Total number of enabled TCs */ 284 u8 enabled_tc; /* TC map */ 285 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 286 }; 287 288 #define I40E_UDP_PORT_INDEX_UNUSED 255 289 struct i40e_udp_port_config { 290 /* AdminQ command interface expects port number in Host byte order */ 291 u16 port; 292 u8 type; 293 u8 filter_index; 294 }; 295 296 /* macros related to FLX_PIT */ 297 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 298 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 299 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 300 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 301 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 302 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 303 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 304 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 305 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 306 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 307 I40E_FLEX_SET_FSIZE(fsize) | \ 308 I40E_FLEX_SET_SRC_WORD(src)) 309 310 311 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 312 313 /* macros related to GLQF_ORT */ 314 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 315 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 316 I40E_GLQF_ORT_PIT_INDX_MASK) 317 318 #define I40E_ORT_SET_COUNT(count) (((count) << \ 319 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 320 I40E_GLQF_ORT_FIELD_CNT_MASK) 321 322 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 323 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 324 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 325 326 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 327 I40E_ORT_SET_COUNT(count) | \ 328 I40E_ORT_SET_PAYLOAD(payload)) 329 330 #define I40E_L3_GLQF_ORT_IDX 34 331 #define I40E_L4_GLQF_ORT_IDX 35 332 333 /* Flex PIT register index */ 334 #define I40E_FLEX_PIT_IDX_START_L3 3 335 #define I40E_FLEX_PIT_IDX_START_L4 6 336 337 #define I40E_FLEX_PIT_TABLE_SIZE 3 338 339 #define I40E_FLEX_DEST_UNUSED 63 340 341 #define I40E_FLEX_INDEX_ENTRIES 8 342 343 /* Flex MASK to disable all flexible entries */ 344 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 345 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 346 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 347 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 348 349 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \ 350 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \ 351 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \ 352 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \ 353 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \ 354 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)) 355 356 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ 357 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ 358 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ 359 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ 360 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ 361 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) 362 363 struct i40e_flex_pit { 364 struct list_head list; 365 u16 src_offset; 366 u8 pit_index; 367 }; 368 369 struct i40e_fwd_adapter { 370 struct net_device *netdev; 371 int bit_no; 372 }; 373 374 struct i40e_channel { 375 struct list_head list; 376 bool initialized; 377 u8 type; 378 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 379 u16 stat_counter_idx; 380 u16 base_queue; 381 u16 num_queue_pairs; /* Requested by user */ 382 u16 seid; 383 384 u8 enabled_tc; 385 struct i40e_aqc_vsi_properties_data info; 386 387 u64 max_tx_rate; 388 struct i40e_fwd_adapter *fwd; 389 390 /* track this channel belongs to which VSI */ 391 struct i40e_vsi *parent_vsi; 392 }; 393 394 struct i40e_ptp_pins_settings; 395 396 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 397 { 398 return !!ch->fwd; 399 } 400 401 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch) 402 { 403 if (i40e_is_channel_macvlan(ch)) 404 return ch->fwd->netdev->dev_addr; 405 else 406 return NULL; 407 } 408 409 /* struct that defines the Ethernet device */ 410 struct i40e_pf { 411 struct pci_dev *pdev; 412 struct devlink_port devlink_port; 413 struct i40e_hw hw; 414 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 415 struct msix_entry *msix_entries; 416 bool fc_autoneg_status; 417 418 u16 eeprom_version; 419 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 420 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 421 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 422 u16 num_req_vfs; /* num VFs requested for this PF */ 423 u16 num_vf_qps; /* num queue pairs per VF */ 424 u16 num_lan_qps; /* num lan queues this PF has set up */ 425 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 426 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 427 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 428 int iwarp_base_vector; 429 int queues_left; /* queues left unclaimed */ 430 u16 alloc_rss_size; /* allocated RSS queues */ 431 u16 rss_size_max; /* HW defined max RSS queues */ 432 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 433 u16 num_alloc_vsi; /* num VSIs this driver supports */ 434 u8 atr_sample_rate; 435 bool wol_en; 436 437 struct hlist_head fdir_filter_list; 438 u16 fdir_pf_active_filters; 439 unsigned long fd_flush_timestamp; 440 u32 fd_flush_cnt; 441 u32 fd_add_err; 442 u32 fd_atr_cnt; 443 444 /* Book-keeping of side-band filter count per flow-type. 445 * This is used to detect and handle input set changes for 446 * respective flow-type. 447 */ 448 u16 fd_tcp4_filter_cnt; 449 u16 fd_udp4_filter_cnt; 450 u16 fd_sctp4_filter_cnt; 451 u16 fd_ip4_filter_cnt; 452 453 u16 fd_tcp6_filter_cnt; 454 u16 fd_udp6_filter_cnt; 455 u16 fd_sctp6_filter_cnt; 456 u16 fd_ip6_filter_cnt; 457 458 /* Flexible filter table values that need to be programmed into 459 * hardware, which expects L3 and L4 to be programmed separately. We 460 * need to ensure that the values are in ascended order and don't have 461 * duplicates, so we track each L3 and L4 values in separate lists. 462 */ 463 struct list_head l3_flex_pit_list; 464 struct list_head l4_flex_pit_list; 465 466 struct udp_tunnel_nic_shared udp_tunnel_shared; 467 struct udp_tunnel_nic_info udp_tunnel_nic; 468 469 struct hlist_head cloud_filter_list; 470 u16 num_cloud_filters; 471 472 enum i40e_interrupt_policy int_policy; 473 u16 rx_itr_default; 474 u16 tx_itr_default; 475 u32 msg_enable; 476 char int_name[I40E_INT_NAME_STR_LEN]; 477 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 478 unsigned long service_timer_period; 479 unsigned long service_timer_previous; 480 struct timer_list service_timer; 481 struct work_struct service_task; 482 483 u32 hw_features; 484 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 485 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 486 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 487 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 488 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 489 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 490 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 491 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 492 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 493 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 494 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 495 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 496 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 497 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 498 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 499 #define I40E_HW_STOP_FW_LLDP BIT(16) 500 #define I40E_HW_PORT_ID_VALID BIT(17) 501 #define I40E_HW_RESTART_AUTONEG BIT(18) 502 503 u32 flags; 504 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 505 #define I40E_FLAG_MSI_ENABLED BIT(1) 506 #define I40E_FLAG_MSIX_ENABLED BIT(2) 507 #define I40E_FLAG_RSS_ENABLED BIT(3) 508 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 509 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 510 #define I40E_FLAG_DCB_CAPABLE BIT(6) 511 #define I40E_FLAG_DCB_ENABLED BIT(7) 512 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 513 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 514 #define I40E_FLAG_MFP_ENABLED BIT(10) 515 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 516 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 517 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 518 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 519 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 520 #define I40E_FLAG_LEGACY_RX BIT(16) 521 #define I40E_FLAG_PTP BIT(17) 522 #define I40E_FLAG_IWARP_ENABLED BIT(18) 523 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 524 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 525 #define I40E_FLAG_TC_MQPRIO BIT(21) 526 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 527 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 528 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 529 #define I40E_FLAG_RS_FEC BIT(25) 530 #define I40E_FLAG_BASE_R_FEC BIT(26) 531 /* TOTAL_PORT_SHUTDOWN 532 * Allows to physically disable the link on the NIC's port. 533 * If enabled, (after link down request from the OS) 534 * no link, traffic or led activity is possible on that port. 535 * 536 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 537 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 538 * and cannot be disabled by system admin at that time. 539 * The functionalities are exclusive in terms of configuration, but they also 540 * have similar behavior (allowing to disable physical link of the port), 541 * with following differences: 542 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 543 * supported by whole family of 7xx Intel Ethernet Controllers 544 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 545 * only if motherboard's BIOS and NIC's FW has support of it 546 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 547 * by sending phy_type=0 to NIC's FW 548 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 549 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 550 * in abilities field of i40e_aq_set_phy_config structure 551 */ 552 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 553 #define I40E_FLAG_VF_VLAN_PRUNING BIT(28) 554 555 struct i40e_client_instance *cinst; 556 bool stat_offsets_loaded; 557 struct i40e_hw_port_stats stats; 558 struct i40e_hw_port_stats stats_offsets; 559 u32 tx_timeout_count; 560 u32 tx_timeout_recovery_level; 561 unsigned long tx_timeout_last_recovery; 562 u32 tx_sluggish_count; 563 u32 hw_csum_rx_error; 564 u32 led_status; 565 u16 corer_count; /* Core reset count */ 566 u16 globr_count; /* Global reset count */ 567 u16 empr_count; /* EMP reset count */ 568 u16 pfr_count; /* PF reset count */ 569 u16 sw_int_count; /* SW interrupt count */ 570 571 struct mutex switch_mutex; 572 u16 lan_vsi; /* our default LAN VSI */ 573 u16 lan_veb; /* initial relay, if exists */ 574 #define I40E_NO_VEB 0xffff 575 #define I40E_NO_VSI 0xffff 576 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 577 struct i40e_vsi **vsi; 578 struct i40e_veb *veb[I40E_MAX_VEB]; 579 580 struct i40e_lump_tracking *qp_pile; 581 struct i40e_lump_tracking *irq_pile; 582 583 /* switch config info */ 584 u16 pf_seid; 585 u16 main_vsi_seid; 586 u16 mac_seid; 587 struct kobject *switch_kobj; 588 #ifdef CONFIG_DEBUG_FS 589 struct dentry *i40e_dbg_pf; 590 #endif /* CONFIG_DEBUG_FS */ 591 bool cur_promisc; 592 593 u16 instance; /* A unique number per i40e_pf instance in the system */ 594 595 /* sr-iov config info */ 596 struct i40e_vf *vf; 597 int num_alloc_vfs; /* actual number of VFs allocated */ 598 u32 vf_aq_requests; 599 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 600 601 /* DCBx/DCBNL capability for PF that indicates 602 * whether DCBx is managed by firmware or host 603 * based agent (LLDPAD). Also, indicates what 604 * flavor of DCBx protocol (IEEE/CEE) is supported 605 * by the device. For now we're supporting IEEE 606 * mode only. 607 */ 608 u16 dcbx_cap; 609 610 struct i40e_filter_control_settings filter_settings; 611 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 612 struct i40e_dcbx_config tmp_cfg; 613 614 /* GPIO defines used by PTP */ 615 #define I40E_SDP3_2 18 616 #define I40E_SDP3_3 19 617 #define I40E_GPIO_4 20 618 #define I40E_LED2_0 26 619 #define I40E_LED2_1 27 620 #define I40E_LED3_0 28 621 #define I40E_LED3_1 29 622 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \ 623 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 624 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \ 625 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 626 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \ 627 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 628 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \ 629 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 630 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2) 631 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \ 632 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 633 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \ 634 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 635 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \ 636 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 637 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \ 638 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 639 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \ 640 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 641 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \ 642 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 643 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \ 644 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 645 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \ 646 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 647 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \ 648 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 649 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 650 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 651 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \ 652 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 653 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \ 654 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 655 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \ 656 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 657 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 658 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 659 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0) 660 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \ 661 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \ 662 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 663 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 664 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1) 665 #define I40E_GLGEN_GPIO_CTL_LED_INIT \ 666 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \ 667 I40E_GLGEN_GPIO_CTL_DIR_OUT | \ 668 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \ 669 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \ 670 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \ 671 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN) 672 #define I40E_PRTTSYN_AUX_1_INSTNT \ 673 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 674 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \ 675 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 676 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 677 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \ 678 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD) 679 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */ 680 #define I40E_PTP_2_SEC_DELAY 2 681 682 struct ptp_clock *ptp_clock; 683 struct ptp_clock_info ptp_caps; 684 struct sk_buff *ptp_tx_skb; 685 unsigned long ptp_tx_start; 686 struct hwtstamp_config tstamp_config; 687 struct timespec64 ptp_prev_hw_time; 688 struct work_struct ptp_pps_work; 689 struct work_struct ptp_extts0_work; 690 struct work_struct ptp_extts1_work; 691 ktime_t ptp_reset_start; 692 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 693 u32 ptp_adj_mult; 694 u32 tx_hwtstamp_timeouts; 695 u32 tx_hwtstamp_skipped; 696 u32 rx_hwtstamp_cleared; 697 u32 latch_event_flags; 698 u64 ptp_pps_start; 699 u32 pps_delay; 700 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 701 struct ptp_pin_desc ptp_pin[3]; 702 unsigned long latch_events[4]; 703 bool ptp_tx; 704 bool ptp_rx; 705 struct i40e_ptp_pins_settings *ptp_pins; 706 u16 rss_table_size; /* HW RSS table size */ 707 u32 max_bw; 708 u32 min_bw; 709 710 u32 ioremap_len; 711 u32 fd_inv; 712 u16 phy_led_val; 713 714 u16 override_q_count; 715 u16 last_sw_conf_flags; 716 u16 last_sw_conf_valid_flags; 717 /* List to keep previous DDP profiles to be rolled back in the future */ 718 struct list_head ddp_old_prof; 719 }; 720 721 /** 722 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 723 * @macaddr: the MAC Address as the base key 724 * 725 * Simply copies the address and returns it as a u64 for hashing 726 **/ 727 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 728 { 729 u64 key = 0; 730 731 ether_addr_copy((u8 *)&key, macaddr); 732 return key; 733 } 734 735 enum i40e_filter_state { 736 I40E_FILTER_INVALID = 0, /* Invalid state */ 737 I40E_FILTER_NEW, /* New, not sent to FW yet */ 738 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 739 I40E_FILTER_FAILED, /* Rejected by FW */ 740 I40E_FILTER_REMOVE, /* To be removed */ 741 /* There is no 'removed' state; the filter struct is freed */ 742 }; 743 struct i40e_mac_filter { 744 struct hlist_node hlist; 745 u8 macaddr[ETH_ALEN]; 746 #define I40E_VLAN_ANY -1 747 s16 vlan; 748 enum i40e_filter_state state; 749 }; 750 751 /* Wrapper structure to keep track of filters while we are preparing to send 752 * firmware commands. We cannot send firmware commands while holding a 753 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 754 * a separate structure, which will track the state change and update the real 755 * filter while under lock. We can't simply hold the filters in a separate 756 * list, as this opens a window for a race condition when adding new MAC 757 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 758 */ 759 struct i40e_new_mac_filter { 760 struct hlist_node hlist; 761 struct i40e_mac_filter *f; 762 763 /* Track future changes to state separately */ 764 enum i40e_filter_state state; 765 }; 766 767 struct i40e_veb { 768 struct i40e_pf *pf; 769 u16 idx; 770 u16 veb_idx; /* index of VEB parent */ 771 u16 seid; 772 u16 uplink_seid; 773 u16 stats_idx; /* index of VEB parent */ 774 u8 enabled_tc; 775 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 776 u16 flags; 777 u16 bw_limit; 778 u8 bw_max_quanta; 779 bool is_abs_credits; 780 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 781 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 782 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 783 struct kobject *kobj; 784 bool stat_offsets_loaded; 785 struct i40e_eth_stats stats; 786 struct i40e_eth_stats stats_offsets; 787 struct i40e_veb_tc_stats tc_stats; 788 struct i40e_veb_tc_stats tc_stats_offsets; 789 }; 790 791 /* struct that defines a VSI, associated with a dev */ 792 struct i40e_vsi { 793 struct net_device *netdev; 794 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 795 bool netdev_registered; 796 bool stat_offsets_loaded; 797 798 u32 current_netdev_flags; 799 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 800 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 801 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 802 unsigned long flags; 803 804 /* Per VSI lock to protect elements/hash (MAC filter) */ 805 spinlock_t mac_filter_hash_lock; 806 /* Fixed size hash table with 2^8 buckets for MAC filters */ 807 DECLARE_HASHTABLE(mac_filter_hash, 8); 808 bool has_vlan_filter; 809 810 /* VSI stats */ 811 struct rtnl_link_stats64 net_stats; 812 struct rtnl_link_stats64 net_stats_offsets; 813 struct i40e_eth_stats eth_stats; 814 struct i40e_eth_stats eth_stats_offsets; 815 u64 tx_restart; 816 u64 tx_busy; 817 u64 tx_linearize; 818 u64 tx_force_wb; 819 u64 tx_stopped; 820 u64 rx_buf_failed; 821 u64 rx_page_failed; 822 u64 rx_page_reuse; 823 u64 rx_page_alloc; 824 u64 rx_page_waive; 825 u64 rx_page_busy; 826 827 /* These are containers of ring pointers, allocated at run-time */ 828 struct i40e_ring **rx_rings; 829 struct i40e_ring **tx_rings; 830 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 831 832 u32 active_filters; 833 u32 promisc_threshold; 834 835 u16 work_limit; 836 u16 int_rate_limit; /* value in usecs */ 837 838 u16 rss_table_size; /* HW RSS table size */ 839 u16 rss_size; /* Allocated RSS queues */ 840 u8 *rss_hkey_user; /* User configured hash keys */ 841 u8 *rss_lut_user; /* User configured lookup table entries */ 842 843 844 u16 max_frame; 845 u16 rx_buf_len; 846 847 struct bpf_prog *xdp_prog; 848 849 /* List of q_vectors allocated to this VSI */ 850 struct i40e_q_vector **q_vectors; 851 int num_q_vectors; 852 int base_vector; 853 bool irqs_ready; 854 855 u16 seid; /* HW index of this VSI (absolute index) */ 856 u16 id; /* VSI number */ 857 u16 uplink_seid; 858 859 u16 base_queue; /* vsi's first queue in hw array */ 860 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 861 u16 req_queue_pairs; /* User requested queue pairs */ 862 u16 num_queue_pairs; /* Used tx and rx pairs */ 863 u16 num_tx_desc; 864 u16 num_rx_desc; 865 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 866 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 867 868 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 869 struct i40e_tc_configuration tc_config; 870 struct i40e_aqc_vsi_properties_data info; 871 872 /* VSI BW limit (absolute across all TCs) */ 873 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 874 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 875 876 /* Relative TC credits across VSIs */ 877 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 878 /* TC BW limit credits within VSI */ 879 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 880 /* TC BW limit max quanta within VSI */ 881 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 882 883 struct i40e_pf *back; /* Backreference to associated PF */ 884 u16 idx; /* index in pf->vsi[] */ 885 u16 veb_idx; /* index of VEB parent */ 886 struct kobject *kobj; /* sysfs object */ 887 bool current_isup; /* Sync 'link up' logging */ 888 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 889 890 /* channel specific fields */ 891 u16 cnt_q_avail; /* num of queues available for channel usage */ 892 u16 orig_rss_size; 893 u16 current_rss_size; 894 bool reconfig_rss; 895 896 u16 next_base_queue; /* next queue to be used for channel setup */ 897 898 struct list_head ch_list; 899 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 900 901 /* macvlan fields */ 902 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 903 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 904 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 905 struct list_head macvlan_list; 906 int macvlan_cnt; 907 908 void *priv; /* client driver data reference. */ 909 910 /* VSI specific handlers */ 911 irqreturn_t (*irq_handler)(int irq, void *data); 912 913 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 914 } ____cacheline_internodealigned_in_smp; 915 916 struct i40e_netdev_priv { 917 struct i40e_vsi *vsi; 918 }; 919 920 extern struct ida i40e_client_ida; 921 922 /* struct that defines an interrupt vector */ 923 struct i40e_q_vector { 924 struct i40e_vsi *vsi; 925 926 u16 v_idx; /* index in the vsi->q_vector array. */ 927 u16 reg_idx; /* register index of the interrupt */ 928 929 struct napi_struct napi; 930 931 struct i40e_ring_container rx; 932 struct i40e_ring_container tx; 933 934 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 935 u8 num_ringpairs; /* total number of ring pairs in vector */ 936 937 cpumask_t affinity_mask; 938 struct irq_affinity_notify affinity_notify; 939 940 struct rcu_head rcu; /* to avoid race with update stats on free */ 941 char name[I40E_INT_NAME_STR_LEN]; 942 bool arm_wb_state; 943 int irq_num; /* IRQ assigned to this q_vector */ 944 } ____cacheline_internodealigned_in_smp; 945 946 /* lan device */ 947 struct i40e_device { 948 struct list_head list; 949 struct i40e_pf *pf; 950 }; 951 952 /** 953 * i40e_info_nvm_ver - format the NVM version string 954 * @hw: ptr to the hardware info 955 * @buf: string buffer to store 956 * @len: buffer size 957 * 958 * Formats NVM version string as: 959 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID 960 * <nvm_major>.<nvm_minor> otherwise 961 **/ 962 static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len) 963 { 964 struct i40e_nvm_info *nvm = &hw->nvm; 965 966 if (nvm->eetrack == I40E_OEM_EETRACK_ID) { 967 u32 full_ver = nvm->oem_ver; 968 u8 gen, snap; 969 u16 release; 970 971 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver); 972 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver); 973 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver); 974 snprintf(buf, len, "%x.%x.%x", gen, snap, release); 975 } else { 976 u8 major, minor; 977 978 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version); 979 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version); 980 snprintf(buf, len, "%x.%02x", major, minor); 981 } 982 } 983 984 /** 985 * i40e_info_eetrack - format the EETrackID string 986 * @hw: ptr to the hardware info 987 * @buf: string buffer to store 988 * @len: buffer size 989 * 990 * Returns hexadecimally formated EETrackID if it is 991 * different from I40E_OEM_EETRACK_ID or empty string. 992 **/ 993 static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len) 994 { 995 struct i40e_nvm_info *nvm = &hw->nvm; 996 997 buf[0] = '\0'; 998 if (nvm->eetrack != I40E_OEM_EETRACK_ID) 999 snprintf(buf, len, "0x%08x", nvm->eetrack); 1000 } 1001 1002 /** 1003 * i40e_info_civd_ver - format the NVM version strings 1004 * @hw: ptr to the hardware info 1005 * @buf: string buffer to store 1006 * @len: buffer size 1007 * 1008 * Returns formated combo image version if adapter's EETrackID is 1009 * different from I40E_OEM_EETRACK_ID or empty string. 1010 **/ 1011 static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len) 1012 { 1013 struct i40e_nvm_info *nvm = &hw->nvm; 1014 1015 buf[0] = '\0'; 1016 if (nvm->eetrack != I40E_OEM_EETRACK_ID) { 1017 u32 full_ver = nvm->oem_ver; 1018 u8 major, minor; 1019 u16 build; 1020 1021 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver); 1022 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver); 1023 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver); 1024 snprintf(buf, len, "%d.%d.%d", major, build, minor); 1025 } 1026 } 1027 1028 /** 1029 * i40e_nvm_version_str - format the NVM version strings 1030 * @hw: ptr to the hardware info 1031 * @buf: string buffer to store 1032 * @len: buffer size 1033 **/ 1034 static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf, 1035 size_t len) 1036 { 1037 char ver[16] = " "; 1038 1039 /* Get NVM version */ 1040 i40e_info_nvm_ver(hw, buf, len); 1041 1042 /* Append EETrackID if provided */ 1043 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1); 1044 if (strlen(ver) > 1) 1045 strlcat(buf, ver, len); 1046 1047 /* Append combo image version if provided */ 1048 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1); 1049 if (strlen(ver) > 1) 1050 strlcat(buf, ver, len); 1051 1052 return buf; 1053 } 1054 1055 /** 1056 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 1057 * @netdev: the corresponding netdev 1058 * 1059 * Return the PF struct for the given netdev 1060 **/ 1061 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 1062 { 1063 struct i40e_netdev_priv *np = netdev_priv(netdev); 1064 struct i40e_vsi *vsi = np->vsi; 1065 1066 return vsi->back; 1067 } 1068 1069 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 1070 irqreturn_t (*irq_handler)(int, void *)) 1071 { 1072 vsi->irq_handler = irq_handler; 1073 } 1074 1075 /** 1076 * i40e_get_fd_cnt_all - get the total FD filter space available 1077 * @pf: pointer to the PF struct 1078 **/ 1079 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 1080 { 1081 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 1082 } 1083 1084 /** 1085 * i40e_read_fd_input_set - reads value of flow director input set register 1086 * @pf: pointer to the PF struct 1087 * @addr: register addr 1088 * 1089 * This function reads value of flow director input set register 1090 * specified by 'addr' (which is specific to flow-type) 1091 **/ 1092 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 1093 { 1094 u64 val; 1095 1096 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 1097 val <<= 32; 1098 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 1099 1100 return val; 1101 } 1102 1103 /** 1104 * i40e_write_fd_input_set - writes value into flow director input set register 1105 * @pf: pointer to the PF struct 1106 * @addr: register addr 1107 * @val: value to be written 1108 * 1109 * This function writes specified value to the register specified by 'addr'. 1110 * This register is input set register based on flow-type. 1111 **/ 1112 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1113 u16 addr, u64 val) 1114 { 1115 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1116 (u32)(val >> 32)); 1117 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1118 (u32)(val & 0xFFFFFFFFULL)); 1119 } 1120 1121 /** 1122 * i40e_get_pf_count - get PCI PF count. 1123 * @hw: pointer to a hw. 1124 * 1125 * Reports the function number of the highest PCI physical 1126 * function plus 1 as it is loaded from the NVM. 1127 * 1128 * Return: PCI PF count. 1129 **/ 1130 static inline u32 i40e_get_pf_count(struct i40e_hw *hw) 1131 { 1132 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, 1133 rd32(hw, I40E_GLGEN_PCIFCNCNT)); 1134 } 1135 1136 /* needed by i40e_ethtool.c */ 1137 int i40e_up(struct i40e_vsi *vsi); 1138 void i40e_down(struct i40e_vsi *vsi); 1139 extern const char i40e_driver_name[]; 1140 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1141 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1142 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1143 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1144 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1145 u16 rss_table_size, u16 rss_size); 1146 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1147 /** 1148 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1149 * @pf: PF to search for VSI 1150 * @type: Value indicating type of VSI we are looking for 1151 **/ 1152 static inline struct i40e_vsi * 1153 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1154 { 1155 int i; 1156 1157 for (i = 0; i < pf->num_alloc_vsi; i++) { 1158 struct i40e_vsi *vsi = pf->vsi[i]; 1159 1160 if (vsi && vsi->type == type) 1161 return vsi; 1162 } 1163 1164 return NULL; 1165 } 1166 void i40e_update_stats(struct i40e_vsi *vsi); 1167 void i40e_update_veb_stats(struct i40e_veb *veb); 1168 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1169 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1170 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1171 bool printconfig); 1172 1173 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1174 struct i40e_fdir_filter *input, bool add); 1175 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1176 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1177 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1178 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1179 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1180 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1181 void i40e_set_ethtool_ops(struct net_device *netdev); 1182 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1183 const u8 *macaddr, s16 vlan); 1184 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1185 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1186 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1187 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1188 u16 uplink, u32 param1); 1189 int i40e_vsi_release(struct i40e_vsi *vsi); 1190 void i40e_service_event_schedule(struct i40e_pf *pf); 1191 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1192 u8 *msg, u16 len); 1193 1194 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1195 bool enable); 1196 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1197 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1198 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1199 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1200 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1201 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1202 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1203 u16 downlink_seid, u8 enabled_tc); 1204 void i40e_veb_release(struct i40e_veb *veb); 1205 1206 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1207 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1208 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1209 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1210 void i40e_pf_reset_stats(struct i40e_pf *pf); 1211 #ifdef CONFIG_DEBUG_FS 1212 void i40e_dbg_pf_init(struct i40e_pf *pf); 1213 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1214 void i40e_dbg_init(void); 1215 void i40e_dbg_exit(void); 1216 #else 1217 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1218 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1219 static inline void i40e_dbg_init(void) {} 1220 static inline void i40e_dbg_exit(void) {} 1221 #endif /* CONFIG_DEBUG_FS*/ 1222 /* needed by client drivers */ 1223 int i40e_lan_add_device(struct i40e_pf *pf); 1224 int i40e_lan_del_device(struct i40e_pf *pf); 1225 void i40e_client_subtask(struct i40e_pf *pf); 1226 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1227 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1228 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1229 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1230 void i40e_client_update_msix_info(struct i40e_pf *pf); 1231 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1232 /** 1233 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1234 * @vsi: pointer to a vsi 1235 * @vector: enable a particular Hw Interrupt vector, without base_vector 1236 **/ 1237 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1238 { 1239 struct i40e_pf *pf = vsi->back; 1240 struct i40e_hw *hw = &pf->hw; 1241 u32 val; 1242 1243 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1244 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1245 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1246 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1247 /* skip the flush */ 1248 } 1249 1250 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1251 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1252 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1253 int i40e_open(struct net_device *netdev); 1254 int i40e_close(struct net_device *netdev); 1255 int i40e_vsi_open(struct i40e_vsi *vsi); 1256 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1257 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1258 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1259 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1260 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1261 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1262 const u8 *macaddr); 1263 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1264 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1265 int i40e_count_filters(struct i40e_vsi *vsi); 1266 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1267 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1268 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1269 { 1270 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP); 1271 } 1272 1273 #ifdef CONFIG_I40E_DCB 1274 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1275 struct i40e_dcbx_config *old_cfg, 1276 struct i40e_dcbx_config *new_cfg); 1277 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1278 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1279 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1280 struct i40e_dcbx_config *old_cfg, 1281 struct i40e_dcbx_config *new_cfg); 1282 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1283 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1284 #endif /* CONFIG_I40E_DCB */ 1285 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1286 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1287 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1288 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1289 void i40e_ptp_set_increment(struct i40e_pf *pf); 1290 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1291 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1292 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1293 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1294 void i40e_ptp_init(struct i40e_pf *pf); 1295 void i40e_ptp_stop(struct i40e_pf *pf); 1296 int i40e_ptp_alloc_pins(struct i40e_pf *pf); 1297 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset); 1298 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1299 int i40e_get_partition_bw_setting(struct i40e_pf *pf); 1300 int i40e_set_partition_bw_setting(struct i40e_pf *pf); 1301 int i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1302 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1303 1304 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1305 1306 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1307 { 1308 return !!READ_ONCE(vsi->xdp_prog); 1309 } 1310 1311 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1312 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1313 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1314 struct i40e_cloud_filter *filter, 1315 bool add); 1316 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1317 struct i40e_cloud_filter *filter, 1318 bool add); 1319 1320 /** 1321 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF 1322 * @pf: pointer to a pf. 1323 * 1324 * Check and return value of flag I40E_FLAG_TC_MQPRIO. 1325 * 1326 * Return: I40E_FLAG_TC_MQPRIO set state. 1327 **/ 1328 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf) 1329 { 1330 return pf->flags & I40E_FLAG_TC_MQPRIO; 1331 } 1332 1333 /** 1334 * i40e_hw_to_pf - get pf pointer from the hardware structure 1335 * @hw: pointer to the device HW structure 1336 **/ 1337 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw) 1338 { 1339 return container_of(hw, struct i40e_pf, hw); 1340 } 1341 1342 struct device *i40e_hw_to_dev(struct i40e_hw *hw); 1343 1344 #endif /* _I40E_H_ */ 1345