1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e_status.h" 5 #include "i40e_type.h" 6 #include "i40e_register.h" 7 #include "i40e_adminq.h" 8 #include "i40e_prototype.h" 9 10 static void i40e_resume_aq(struct i40e_hw *hw); 11 12 /** 13 * i40e_adminq_init_regs - Initialize AdminQ registers 14 * @hw: pointer to the hardware structure 15 * 16 * This assumes the alloc_asq and alloc_arq functions have already been called 17 **/ 18 static void i40e_adminq_init_regs(struct i40e_hw *hw) 19 { 20 /* set head and tail registers in our local struct */ 21 if (i40e_is_vf(hw)) { 22 hw->aq.asq.tail = I40E_VF_ATQT1; 23 hw->aq.asq.head = I40E_VF_ATQH1; 24 hw->aq.asq.len = I40E_VF_ATQLEN1; 25 hw->aq.asq.bal = I40E_VF_ATQBAL1; 26 hw->aq.asq.bah = I40E_VF_ATQBAH1; 27 hw->aq.arq.tail = I40E_VF_ARQT1; 28 hw->aq.arq.head = I40E_VF_ARQH1; 29 hw->aq.arq.len = I40E_VF_ARQLEN1; 30 hw->aq.arq.bal = I40E_VF_ARQBAL1; 31 hw->aq.arq.bah = I40E_VF_ARQBAH1; 32 } else { 33 hw->aq.asq.tail = I40E_PF_ATQT; 34 hw->aq.asq.head = I40E_PF_ATQH; 35 hw->aq.asq.len = I40E_PF_ATQLEN; 36 hw->aq.asq.bal = I40E_PF_ATQBAL; 37 hw->aq.asq.bah = I40E_PF_ATQBAH; 38 hw->aq.arq.tail = I40E_PF_ARQT; 39 hw->aq.arq.head = I40E_PF_ARQH; 40 hw->aq.arq.len = I40E_PF_ARQLEN; 41 hw->aq.arq.bal = I40E_PF_ARQBAL; 42 hw->aq.arq.bah = I40E_PF_ARQBAH; 43 } 44 } 45 46 /** 47 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings 48 * @hw: pointer to the hardware structure 49 **/ 50 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 51 { 52 i40e_status ret_code; 53 54 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 55 i40e_mem_atq_ring, 56 (hw->aq.num_asq_entries * 57 sizeof(struct i40e_aq_desc)), 58 I40E_ADMINQ_DESC_ALIGNMENT); 59 if (ret_code) 60 return ret_code; 61 62 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, 63 (hw->aq.num_asq_entries * 64 sizeof(struct i40e_asq_cmd_details))); 65 if (ret_code) { 66 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 67 return ret_code; 68 } 69 70 return ret_code; 71 } 72 73 /** 74 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings 75 * @hw: pointer to the hardware structure 76 **/ 77 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 78 { 79 i40e_status ret_code; 80 81 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 82 i40e_mem_arq_ring, 83 (hw->aq.num_arq_entries * 84 sizeof(struct i40e_aq_desc)), 85 I40E_ADMINQ_DESC_ALIGNMENT); 86 87 return ret_code; 88 } 89 90 /** 91 * i40e_free_adminq_asq - Free Admin Queue send rings 92 * @hw: pointer to the hardware structure 93 * 94 * This assumes the posted send buffers have already been cleaned 95 * and de-allocated 96 **/ 97 static void i40e_free_adminq_asq(struct i40e_hw *hw) 98 { 99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 100 } 101 102 /** 103 * i40e_free_adminq_arq - Free Admin Queue receive rings 104 * @hw: pointer to the hardware structure 105 * 106 * This assumes the posted receive buffers have already been cleaned 107 * and de-allocated 108 **/ 109 static void i40e_free_adminq_arq(struct i40e_hw *hw) 110 { 111 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 112 } 113 114 /** 115 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue 116 * @hw: pointer to the hardware structure 117 **/ 118 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) 119 { 120 i40e_status ret_code; 121 struct i40e_aq_desc *desc; 122 struct i40e_dma_mem *bi; 123 int i; 124 125 /* We'll be allocating the buffer info memory first, then we can 126 * allocate the mapped buffers for the event processing 127 */ 128 129 /* buffer_info structures do not need alignment */ 130 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, 131 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); 132 if (ret_code) 133 goto alloc_arq_bufs; 134 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; 135 136 /* allocate the mapped buffers */ 137 for (i = 0; i < hw->aq.num_arq_entries; i++) { 138 bi = &hw->aq.arq.r.arq_bi[i]; 139 ret_code = i40e_allocate_dma_mem(hw, bi, 140 i40e_mem_arq_buf, 141 hw->aq.arq_buf_size, 142 I40E_ADMINQ_DESC_ALIGNMENT); 143 if (ret_code) 144 goto unwind_alloc_arq_bufs; 145 146 /* now configure the descriptors for use */ 147 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 148 149 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 150 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 151 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 152 desc->opcode = 0; 153 /* This is in accordance with Admin queue design, there is no 154 * register for buffer size configuration 155 */ 156 desc->datalen = cpu_to_le16((u16)bi->size); 157 desc->retval = 0; 158 desc->cookie_high = 0; 159 desc->cookie_low = 0; 160 desc->params.external.addr_high = 161 cpu_to_le32(upper_32_bits(bi->pa)); 162 desc->params.external.addr_low = 163 cpu_to_le32(lower_32_bits(bi->pa)); 164 desc->params.external.param0 = 0; 165 desc->params.external.param1 = 0; 166 } 167 168 alloc_arq_bufs: 169 return ret_code; 170 171 unwind_alloc_arq_bufs: 172 /* don't try to free the one that failed... */ 173 i--; 174 for (; i >= 0; i--) 175 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 176 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 177 178 return ret_code; 179 } 180 181 /** 182 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue 183 * @hw: pointer to the hardware structure 184 **/ 185 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) 186 { 187 i40e_status ret_code; 188 struct i40e_dma_mem *bi; 189 int i; 190 191 /* No mapped memory needed yet, just the buffer info structures */ 192 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, 193 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); 194 if (ret_code) 195 goto alloc_asq_bufs; 196 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; 197 198 /* allocate the mapped buffers */ 199 for (i = 0; i < hw->aq.num_asq_entries; i++) { 200 bi = &hw->aq.asq.r.asq_bi[i]; 201 ret_code = i40e_allocate_dma_mem(hw, bi, 202 i40e_mem_asq_buf, 203 hw->aq.asq_buf_size, 204 I40E_ADMINQ_DESC_ALIGNMENT); 205 if (ret_code) 206 goto unwind_alloc_asq_bufs; 207 } 208 alloc_asq_bufs: 209 return ret_code; 210 211 unwind_alloc_asq_bufs: 212 /* don't try to free the one that failed... */ 213 i--; 214 for (; i >= 0; i--) 215 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 216 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 217 218 return ret_code; 219 } 220 221 /** 222 * i40e_free_arq_bufs - Free receive queue buffer info elements 223 * @hw: pointer to the hardware structure 224 **/ 225 static void i40e_free_arq_bufs(struct i40e_hw *hw) 226 { 227 int i; 228 229 /* free descriptors */ 230 for (i = 0; i < hw->aq.num_arq_entries; i++) 231 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 232 233 /* free the descriptor memory */ 234 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 235 236 /* free the dma header */ 237 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 238 } 239 240 /** 241 * i40e_free_asq_bufs - Free send queue buffer info elements 242 * @hw: pointer to the hardware structure 243 **/ 244 static void i40e_free_asq_bufs(struct i40e_hw *hw) 245 { 246 int i; 247 248 /* only unmap if the address is non-NULL */ 249 for (i = 0; i < hw->aq.num_asq_entries; i++) 250 if (hw->aq.asq.r.asq_bi[i].pa) 251 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 252 253 /* free the buffer info list */ 254 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); 255 256 /* free the descriptor memory */ 257 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 258 259 /* free the dma header */ 260 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 261 } 262 263 /** 264 * i40e_config_asq_regs - configure ASQ registers 265 * @hw: pointer to the hardware structure 266 * 267 * Configure base address and length registers for the transmit queue 268 **/ 269 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) 270 { 271 i40e_status ret_code = 0; 272 u32 reg = 0; 273 274 /* Clear Head and Tail */ 275 wr32(hw, hw->aq.asq.head, 0); 276 wr32(hw, hw->aq.asq.tail, 0); 277 278 /* set starting point */ 279 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 280 I40E_PF_ATQLEN_ATQENABLE_MASK)); 281 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); 282 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); 283 284 /* Check one register to verify that config was applied */ 285 reg = rd32(hw, hw->aq.asq.bal); 286 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 287 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 288 289 return ret_code; 290 } 291 292 /** 293 * i40e_config_arq_regs - ARQ register configuration 294 * @hw: pointer to the hardware structure 295 * 296 * Configure base address and length registers for the receive (event queue) 297 **/ 298 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) 299 { 300 i40e_status ret_code = 0; 301 u32 reg = 0; 302 303 /* Clear Head and Tail */ 304 wr32(hw, hw->aq.arq.head, 0); 305 wr32(hw, hw->aq.arq.tail, 0); 306 307 /* set starting point */ 308 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | 309 I40E_PF_ARQLEN_ARQENABLE_MASK)); 310 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); 311 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); 312 313 /* Update tail in the HW to post pre-allocated buffers */ 314 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 315 316 /* Check one register to verify that config was applied */ 317 reg = rd32(hw, hw->aq.arq.bal); 318 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 319 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 320 321 return ret_code; 322 } 323 324 /** 325 * i40e_init_asq - main initialization routine for ASQ 326 * @hw: pointer to the hardware structure 327 * 328 * This is the main initialization routine for the Admin Send Queue 329 * Prior to calling this function, drivers *MUST* set the following fields 330 * in the hw->aq structure: 331 * - hw->aq.num_asq_entries 332 * - hw->aq.arq_buf_size 333 * 334 * Do *NOT* hold the lock when calling this as the memory allocation routines 335 * called are not going to be atomic context safe 336 **/ 337 static i40e_status i40e_init_asq(struct i40e_hw *hw) 338 { 339 i40e_status ret_code = 0; 340 341 if (hw->aq.asq.count > 0) { 342 /* queue already initialized */ 343 ret_code = I40E_ERR_NOT_READY; 344 goto init_adminq_exit; 345 } 346 347 /* verify input for valid configuration */ 348 if ((hw->aq.num_asq_entries == 0) || 349 (hw->aq.asq_buf_size == 0)) { 350 ret_code = I40E_ERR_CONFIG; 351 goto init_adminq_exit; 352 } 353 354 hw->aq.asq.next_to_use = 0; 355 hw->aq.asq.next_to_clean = 0; 356 357 /* allocate the ring memory */ 358 ret_code = i40e_alloc_adminq_asq_ring(hw); 359 if (ret_code) 360 goto init_adminq_exit; 361 362 /* allocate buffers in the rings */ 363 ret_code = i40e_alloc_asq_bufs(hw); 364 if (ret_code) 365 goto init_adminq_free_rings; 366 367 /* initialize base registers */ 368 ret_code = i40e_config_asq_regs(hw); 369 if (ret_code) 370 goto init_adminq_free_rings; 371 372 /* success! */ 373 hw->aq.asq.count = hw->aq.num_asq_entries; 374 goto init_adminq_exit; 375 376 init_adminq_free_rings: 377 i40e_free_adminq_asq(hw); 378 379 init_adminq_exit: 380 return ret_code; 381 } 382 383 /** 384 * i40e_init_arq - initialize ARQ 385 * @hw: pointer to the hardware structure 386 * 387 * The main initialization routine for the Admin Receive (Event) Queue. 388 * Prior to calling this function, drivers *MUST* set the following fields 389 * in the hw->aq structure: 390 * - hw->aq.num_asq_entries 391 * - hw->aq.arq_buf_size 392 * 393 * Do *NOT* hold the lock when calling this as the memory allocation routines 394 * called are not going to be atomic context safe 395 **/ 396 static i40e_status i40e_init_arq(struct i40e_hw *hw) 397 { 398 i40e_status ret_code = 0; 399 400 if (hw->aq.arq.count > 0) { 401 /* queue already initialized */ 402 ret_code = I40E_ERR_NOT_READY; 403 goto init_adminq_exit; 404 } 405 406 /* verify input for valid configuration */ 407 if ((hw->aq.num_arq_entries == 0) || 408 (hw->aq.arq_buf_size == 0)) { 409 ret_code = I40E_ERR_CONFIG; 410 goto init_adminq_exit; 411 } 412 413 hw->aq.arq.next_to_use = 0; 414 hw->aq.arq.next_to_clean = 0; 415 416 /* allocate the ring memory */ 417 ret_code = i40e_alloc_adminq_arq_ring(hw); 418 if (ret_code) 419 goto init_adminq_exit; 420 421 /* allocate buffers in the rings */ 422 ret_code = i40e_alloc_arq_bufs(hw); 423 if (ret_code) 424 goto init_adminq_free_rings; 425 426 /* initialize base registers */ 427 ret_code = i40e_config_arq_regs(hw); 428 if (ret_code) 429 goto init_adminq_free_rings; 430 431 /* success! */ 432 hw->aq.arq.count = hw->aq.num_arq_entries; 433 goto init_adminq_exit; 434 435 init_adminq_free_rings: 436 i40e_free_adminq_arq(hw); 437 438 init_adminq_exit: 439 return ret_code; 440 } 441 442 /** 443 * i40e_shutdown_asq - shutdown the ASQ 444 * @hw: pointer to the hardware structure 445 * 446 * The main shutdown routine for the Admin Send Queue 447 **/ 448 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) 449 { 450 i40e_status ret_code = 0; 451 452 mutex_lock(&hw->aq.asq_mutex); 453 454 if (hw->aq.asq.count == 0) { 455 ret_code = I40E_ERR_NOT_READY; 456 goto shutdown_asq_out; 457 } 458 459 /* Stop firmware AdminQ processing */ 460 wr32(hw, hw->aq.asq.head, 0); 461 wr32(hw, hw->aq.asq.tail, 0); 462 wr32(hw, hw->aq.asq.len, 0); 463 wr32(hw, hw->aq.asq.bal, 0); 464 wr32(hw, hw->aq.asq.bah, 0); 465 466 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ 467 468 /* free ring buffers */ 469 i40e_free_asq_bufs(hw); 470 471 shutdown_asq_out: 472 mutex_unlock(&hw->aq.asq_mutex); 473 return ret_code; 474 } 475 476 /** 477 * i40e_shutdown_arq - shutdown ARQ 478 * @hw: pointer to the hardware structure 479 * 480 * The main shutdown routine for the Admin Receive Queue 481 **/ 482 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) 483 { 484 i40e_status ret_code = 0; 485 486 mutex_lock(&hw->aq.arq_mutex); 487 488 if (hw->aq.arq.count == 0) { 489 ret_code = I40E_ERR_NOT_READY; 490 goto shutdown_arq_out; 491 } 492 493 /* Stop firmware AdminQ processing */ 494 wr32(hw, hw->aq.arq.head, 0); 495 wr32(hw, hw->aq.arq.tail, 0); 496 wr32(hw, hw->aq.arq.len, 0); 497 wr32(hw, hw->aq.arq.bal, 0); 498 wr32(hw, hw->aq.arq.bah, 0); 499 500 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ 501 502 /* free ring buffers */ 503 i40e_free_arq_bufs(hw); 504 505 shutdown_arq_out: 506 mutex_unlock(&hw->aq.arq_mutex); 507 return ret_code; 508 } 509 510 /** 511 * i40e_set_hw_flags - set HW flags 512 * @hw: pointer to the hardware structure 513 **/ 514 static void i40e_set_hw_flags(struct i40e_hw *hw) 515 { 516 struct i40e_adminq_info *aq = &hw->aq; 517 518 hw->flags = 0; 519 520 switch (hw->mac.type) { 521 case I40E_MAC_XL710: 522 if (aq->api_maj_ver > 1 || 523 (aq->api_maj_ver == 1 && 524 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 525 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 526 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 527 /* The ability to RX (not drop) 802.1ad frames */ 528 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; 529 } 530 break; 531 case I40E_MAC_X722: 532 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 533 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 534 535 if (aq->api_maj_ver > 1 || 536 (aq->api_maj_ver == 1 && 537 aq->api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722)) 538 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 539 /* fall through */ 540 default: 541 break; 542 } 543 544 /* Newer versions of firmware require lock when reading the NVM */ 545 if (aq->api_maj_ver > 1 || 546 (aq->api_maj_ver == 1 && 547 aq->api_min_ver >= 5)) 548 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 549 550 if (aq->api_maj_ver > 1 || 551 (aq->api_maj_ver == 1 && 552 aq->api_min_ver >= 8)) { 553 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT; 554 hw->flags |= I40E_HW_FLAG_DROP_MODE; 555 } 556 557 if (aq->api_maj_ver > 1 || 558 (aq->api_maj_ver == 1 && 559 aq->api_min_ver >= 9)) 560 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED; 561 } 562 563 /** 564 * i40e_init_adminq - main initialization routine for Admin Queue 565 * @hw: pointer to the hardware structure 566 * 567 * Prior to calling this function, drivers *MUST* set the following fields 568 * in the hw->aq structure: 569 * - hw->aq.num_asq_entries 570 * - hw->aq.num_arq_entries 571 * - hw->aq.arq_buf_size 572 * - hw->aq.asq_buf_size 573 **/ 574 i40e_status i40e_init_adminq(struct i40e_hw *hw) 575 { 576 u16 cfg_ptr, oem_hi, oem_lo; 577 u16 eetrack_lo, eetrack_hi; 578 i40e_status ret_code; 579 int retry = 0; 580 581 /* verify input for valid configuration */ 582 if ((hw->aq.num_arq_entries == 0) || 583 (hw->aq.num_asq_entries == 0) || 584 (hw->aq.arq_buf_size == 0) || 585 (hw->aq.asq_buf_size == 0)) { 586 ret_code = I40E_ERR_CONFIG; 587 goto init_adminq_exit; 588 } 589 590 /* Set up register offsets */ 591 i40e_adminq_init_regs(hw); 592 593 /* setup ASQ command write back timeout */ 594 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; 595 596 /* allocate the ASQ */ 597 ret_code = i40e_init_asq(hw); 598 if (ret_code) 599 goto init_adminq_destroy_locks; 600 601 /* allocate the ARQ */ 602 ret_code = i40e_init_arq(hw); 603 if (ret_code) 604 goto init_adminq_free_asq; 605 606 /* There are some cases where the firmware may not be quite ready 607 * for AdminQ operations, so we retry the AdminQ setup a few times 608 * if we see timeouts in this first AQ call. 609 */ 610 do { 611 ret_code = i40e_aq_get_firmware_version(hw, 612 &hw->aq.fw_maj_ver, 613 &hw->aq.fw_min_ver, 614 &hw->aq.fw_build, 615 &hw->aq.api_maj_ver, 616 &hw->aq.api_min_ver, 617 NULL); 618 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) 619 break; 620 retry++; 621 msleep(100); 622 i40e_resume_aq(hw); 623 } while (retry < 10); 624 if (ret_code != I40E_SUCCESS) 625 goto init_adminq_free_arq; 626 627 /* Some features were introduced in different FW API version 628 * for different MAC type. 629 */ 630 i40e_set_hw_flags(hw); 631 632 /* get the NVM version info */ 633 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, 634 &hw->nvm.version); 635 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 636 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 637 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 638 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 639 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), 640 &oem_hi); 641 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), 642 &oem_lo); 643 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; 644 645 if (hw->mac.type == I40E_MAC_XL710 && 646 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 647 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 648 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 649 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 650 } 651 if (hw->mac.type == I40E_MAC_X722 && 652 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 653 hw->aq.api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) { 654 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 655 } 656 657 /* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */ 658 if (hw->aq.api_maj_ver > 1 || 659 (hw->aq.api_maj_ver == 1 && 660 hw->aq.api_min_ver >= 7)) 661 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; 662 663 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { 664 ret_code = I40E_ERR_FIRMWARE_API_VERSION; 665 goto init_adminq_free_arq; 666 } 667 668 /* pre-emptive resource lock release */ 669 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 670 hw->nvm_release_on_done = false; 671 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 672 673 ret_code = 0; 674 675 /* success! */ 676 goto init_adminq_exit; 677 678 init_adminq_free_arq: 679 i40e_shutdown_arq(hw); 680 init_adminq_free_asq: 681 i40e_shutdown_asq(hw); 682 init_adminq_destroy_locks: 683 684 init_adminq_exit: 685 return ret_code; 686 } 687 688 /** 689 * i40e_shutdown_adminq - shutdown routine for the Admin Queue 690 * @hw: pointer to the hardware structure 691 **/ 692 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) 693 { 694 i40e_status ret_code = 0; 695 696 if (i40e_check_asq_alive(hw)) 697 i40e_aq_queue_shutdown(hw, true); 698 699 i40e_shutdown_asq(hw); 700 i40e_shutdown_arq(hw); 701 702 if (hw->nvm_buff.va) 703 i40e_free_virt_mem(hw, &hw->nvm_buff); 704 705 return ret_code; 706 } 707 708 /** 709 * i40e_clean_asq - cleans Admin send queue 710 * @hw: pointer to the hardware structure 711 * 712 * returns the number of free desc 713 **/ 714 static u16 i40e_clean_asq(struct i40e_hw *hw) 715 { 716 struct i40e_adminq_ring *asq = &(hw->aq.asq); 717 struct i40e_asq_cmd_details *details; 718 u16 ntc = asq->next_to_clean; 719 struct i40e_aq_desc desc_cb; 720 struct i40e_aq_desc *desc; 721 722 desc = I40E_ADMINQ_DESC(*asq, ntc); 723 details = I40E_ADMINQ_DETAILS(*asq, ntc); 724 while (rd32(hw, hw->aq.asq.head) != ntc) { 725 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, 726 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); 727 728 if (details->callback) { 729 I40E_ADMINQ_CALLBACK cb_func = 730 (I40E_ADMINQ_CALLBACK)details->callback; 731 desc_cb = *desc; 732 cb_func(hw, &desc_cb); 733 } 734 memset(desc, 0, sizeof(*desc)); 735 memset(details, 0, sizeof(*details)); 736 ntc++; 737 if (ntc == asq->count) 738 ntc = 0; 739 desc = I40E_ADMINQ_DESC(*asq, ntc); 740 details = I40E_ADMINQ_DETAILS(*asq, ntc); 741 } 742 743 asq->next_to_clean = ntc; 744 745 return I40E_DESC_UNUSED(asq); 746 } 747 748 /** 749 * i40e_asq_done - check if FW has processed the Admin Send Queue 750 * @hw: pointer to the hw struct 751 * 752 * Returns true if the firmware has processed all descriptors on the 753 * admin send queue. Returns false if there are still requests pending. 754 **/ 755 static bool i40e_asq_done(struct i40e_hw *hw) 756 { 757 /* AQ designers suggest use of head for better 758 * timing reliability than DD bit 759 */ 760 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; 761 762 } 763 764 /** 765 * i40e_asq_send_command - send command to Admin Queue 766 * @hw: pointer to the hw struct 767 * @desc: prefilled descriptor describing the command (non DMA mem) 768 * @buff: buffer to use for indirect commands 769 * @buff_size: size of buffer for indirect commands 770 * @cmd_details: pointer to command details structure 771 * 772 * This is the main send command driver routine for the Admin Queue send 773 * queue. It runs the queue, cleans the queue, etc 774 **/ 775 i40e_status i40e_asq_send_command(struct i40e_hw *hw, 776 struct i40e_aq_desc *desc, 777 void *buff, /* can be NULL */ 778 u16 buff_size, 779 struct i40e_asq_cmd_details *cmd_details) 780 { 781 i40e_status status = 0; 782 struct i40e_dma_mem *dma_buff = NULL; 783 struct i40e_asq_cmd_details *details; 784 struct i40e_aq_desc *desc_on_ring; 785 bool cmd_completed = false; 786 u16 retval = 0; 787 u32 val = 0; 788 789 mutex_lock(&hw->aq.asq_mutex); 790 791 if (hw->aq.asq.count == 0) { 792 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 793 "AQTX: Admin queue not initialized.\n"); 794 status = I40E_ERR_QUEUE_EMPTY; 795 goto asq_send_command_error; 796 } 797 798 hw->aq.asq_last_status = I40E_AQ_RC_OK; 799 800 val = rd32(hw, hw->aq.asq.head); 801 if (val >= hw->aq.num_asq_entries) { 802 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 803 "AQTX: head overrun at %d\n", val); 804 status = I40E_ERR_ADMIN_QUEUE_FULL; 805 goto asq_send_command_error; 806 } 807 808 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); 809 if (cmd_details) { 810 *details = *cmd_details; 811 812 /* If the cmd_details are defined copy the cookie. The 813 * cpu_to_le32 is not needed here because the data is ignored 814 * by the FW, only used by the driver 815 */ 816 if (details->cookie) { 817 desc->cookie_high = 818 cpu_to_le32(upper_32_bits(details->cookie)); 819 desc->cookie_low = 820 cpu_to_le32(lower_32_bits(details->cookie)); 821 } 822 } else { 823 memset(details, 0, sizeof(struct i40e_asq_cmd_details)); 824 } 825 826 /* clear requested flags and then set additional flags if defined */ 827 desc->flags &= ~cpu_to_le16(details->flags_dis); 828 desc->flags |= cpu_to_le16(details->flags_ena); 829 830 if (buff_size > hw->aq.asq_buf_size) { 831 i40e_debug(hw, 832 I40E_DEBUG_AQ_MESSAGE, 833 "AQTX: Invalid buffer size: %d.\n", 834 buff_size); 835 status = I40E_ERR_INVALID_SIZE; 836 goto asq_send_command_error; 837 } 838 839 if (details->postpone && !details->async) { 840 i40e_debug(hw, 841 I40E_DEBUG_AQ_MESSAGE, 842 "AQTX: Async flag not set along with postpone flag"); 843 status = I40E_ERR_PARAM; 844 goto asq_send_command_error; 845 } 846 847 /* call clean and check queue available function to reclaim the 848 * descriptors that were processed by FW, the function returns the 849 * number of desc available 850 */ 851 /* the clean function called here could be called in a separate thread 852 * in case of asynchronous completions 853 */ 854 if (i40e_clean_asq(hw) == 0) { 855 i40e_debug(hw, 856 I40E_DEBUG_AQ_MESSAGE, 857 "AQTX: Error queue is full.\n"); 858 status = I40E_ERR_ADMIN_QUEUE_FULL; 859 goto asq_send_command_error; 860 } 861 862 /* initialize the temp desc pointer with the right desc */ 863 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); 864 865 /* if the desc is available copy the temp desc to the right place */ 866 *desc_on_ring = *desc; 867 868 /* if buff is not NULL assume indirect command */ 869 if (buff != NULL) { 870 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); 871 /* copy the user buff into the respective DMA buff */ 872 memcpy(dma_buff->va, buff, buff_size); 873 desc_on_ring->datalen = cpu_to_le16(buff_size); 874 875 /* Update the address values in the desc with the pa value 876 * for respective buffer 877 */ 878 desc_on_ring->params.external.addr_high = 879 cpu_to_le32(upper_32_bits(dma_buff->pa)); 880 desc_on_ring->params.external.addr_low = 881 cpu_to_le32(lower_32_bits(dma_buff->pa)); 882 } 883 884 /* bump the tail */ 885 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); 886 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, 887 buff, buff_size); 888 (hw->aq.asq.next_to_use)++; 889 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 890 hw->aq.asq.next_to_use = 0; 891 if (!details->postpone) 892 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); 893 894 /* if cmd_details are not defined or async flag is not set, 895 * we need to wait for desc write back 896 */ 897 if (!details->async && !details->postpone) { 898 u32 total_delay = 0; 899 900 do { 901 /* AQ designers suggest use of head for better 902 * timing reliability than DD bit 903 */ 904 if (i40e_asq_done(hw)) 905 break; 906 udelay(50); 907 total_delay += 50; 908 } while (total_delay < hw->aq.asq_cmd_timeout); 909 } 910 911 /* if ready, copy the desc back to temp */ 912 if (i40e_asq_done(hw)) { 913 *desc = *desc_on_ring; 914 if (buff != NULL) 915 memcpy(buff, dma_buff->va, buff_size); 916 retval = le16_to_cpu(desc->retval); 917 if (retval != 0) { 918 i40e_debug(hw, 919 I40E_DEBUG_AQ_MESSAGE, 920 "AQTX: Command completed with error 0x%X.\n", 921 retval); 922 923 /* strip off FW internal code */ 924 retval &= 0xff; 925 } 926 cmd_completed = true; 927 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 928 status = 0; 929 else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY) 930 status = I40E_ERR_NOT_READY; 931 else 932 status = I40E_ERR_ADMIN_QUEUE_ERROR; 933 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 934 } 935 936 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, 937 "AQTX: desc and buffer writeback:\n"); 938 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); 939 940 /* save writeback aq if requested */ 941 if (details->wb_desc) 942 *details->wb_desc = *desc_on_ring; 943 944 /* update the error if time out occurred */ 945 if ((!cmd_completed) && 946 (!details->async && !details->postpone)) { 947 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { 948 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 949 "AQTX: AQ Critical error.\n"); 950 status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR; 951 } else { 952 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 953 "AQTX: Writeback timeout.\n"); 954 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; 955 } 956 } 957 958 asq_send_command_error: 959 mutex_unlock(&hw->aq.asq_mutex); 960 return status; 961 } 962 963 /** 964 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function 965 * @desc: pointer to the temp descriptor (non DMA mem) 966 * @opcode: the opcode can be used to decide which flags to turn off or on 967 * 968 * Fill the desc with default values 969 **/ 970 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 971 u16 opcode) 972 { 973 /* zero out the desc */ 974 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 975 desc->opcode = cpu_to_le16(opcode); 976 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); 977 } 978 979 /** 980 * i40e_clean_arq_element 981 * @hw: pointer to the hw struct 982 * @e: event info from the receive descriptor, includes any buffers 983 * @pending: number of events that could be left to process 984 * 985 * This function cleans one Admin Receive Queue element and returns 986 * the contents through e. It can also return how many events are 987 * left to process through 'pending' 988 **/ 989 i40e_status i40e_clean_arq_element(struct i40e_hw *hw, 990 struct i40e_arq_event_info *e, 991 u16 *pending) 992 { 993 i40e_status ret_code = 0; 994 u16 ntc = hw->aq.arq.next_to_clean; 995 struct i40e_aq_desc *desc; 996 struct i40e_dma_mem *bi; 997 u16 desc_idx; 998 u16 datalen; 999 u16 flags; 1000 u16 ntu; 1001 1002 /* pre-clean the event info */ 1003 memset(&e->desc, 0, sizeof(e->desc)); 1004 1005 /* take the lock before we start messing with the ring */ 1006 mutex_lock(&hw->aq.arq_mutex); 1007 1008 if (hw->aq.arq.count == 0) { 1009 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 1010 "AQRX: Admin queue not initialized.\n"); 1011 ret_code = I40E_ERR_QUEUE_EMPTY; 1012 goto clean_arq_element_err; 1013 } 1014 1015 /* set next_to_use to head */ 1016 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; 1017 if (ntu == ntc) { 1018 /* nothing to do - shouldn't need to update ring's values */ 1019 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; 1020 goto clean_arq_element_out; 1021 } 1022 1023 /* now clean the next descriptor */ 1024 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 1025 desc_idx = ntc; 1026 1027 hw->aq.arq_last_status = 1028 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 1029 flags = le16_to_cpu(desc->flags); 1030 if (flags & I40E_AQ_FLAG_ERR) { 1031 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 1032 i40e_debug(hw, 1033 I40E_DEBUG_AQ_MESSAGE, 1034 "AQRX: Event received with error 0x%X.\n", 1035 hw->aq.arq_last_status); 1036 } 1037 1038 e->desc = *desc; 1039 datalen = le16_to_cpu(desc->datalen); 1040 e->msg_len = min(datalen, e->buf_len); 1041 if (e->msg_buf != NULL && (e->msg_len != 0)) 1042 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, 1043 e->msg_len); 1044 1045 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); 1046 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, 1047 hw->aq.arq_buf_size); 1048 1049 /* Restore the original datalen and buffer address in the desc, 1050 * FW updates datalen to indicate the event message 1051 * size 1052 */ 1053 bi = &hw->aq.arq.r.arq_bi[ntc]; 1054 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 1055 1056 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 1057 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 1058 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 1059 desc->datalen = cpu_to_le16((u16)bi->size); 1060 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1061 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1062 1063 /* set tail = the last cleaned desc index. */ 1064 wr32(hw, hw->aq.arq.tail, ntc); 1065 /* ntc is updated to tail + 1 */ 1066 ntc++; 1067 if (ntc == hw->aq.num_arq_entries) 1068 ntc = 0; 1069 hw->aq.arq.next_to_clean = ntc; 1070 hw->aq.arq.next_to_use = ntu; 1071 1072 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc); 1073 clean_arq_element_out: 1074 /* Set pending if needed, unlock and return */ 1075 if (pending) 1076 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); 1077 clean_arq_element_err: 1078 mutex_unlock(&hw->aq.arq_mutex); 1079 1080 return ret_code; 1081 } 1082 1083 static void i40e_resume_aq(struct i40e_hw *hw) 1084 { 1085 /* Registers are reset after PF reset */ 1086 hw->aq.asq.next_to_use = 0; 1087 hw->aq.asq.next_to_clean = 0; 1088 1089 i40e_config_asq_regs(hw); 1090 1091 hw->aq.arq.next_to_use = 0; 1092 hw->aq.arq.next_to_clean = 0; 1093 1094 i40e_config_arq_regs(hw); 1095 } 1096