1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e_status.h" 5 #include "i40e_type.h" 6 #include "i40e_register.h" 7 #include "i40e_adminq.h" 8 #include "i40e_prototype.h" 9 10 static void i40e_resume_aq(struct i40e_hw *hw); 11 12 /** 13 * i40e_adminq_init_regs - Initialize AdminQ registers 14 * @hw: pointer to the hardware structure 15 * 16 * This assumes the alloc_asq and alloc_arq functions have already been called 17 **/ 18 static void i40e_adminq_init_regs(struct i40e_hw *hw) 19 { 20 /* set head and tail registers in our local struct */ 21 if (i40e_is_vf(hw)) { 22 hw->aq.asq.tail = I40E_VF_ATQT1; 23 hw->aq.asq.head = I40E_VF_ATQH1; 24 hw->aq.asq.len = I40E_VF_ATQLEN1; 25 hw->aq.asq.bal = I40E_VF_ATQBAL1; 26 hw->aq.asq.bah = I40E_VF_ATQBAH1; 27 hw->aq.arq.tail = I40E_VF_ARQT1; 28 hw->aq.arq.head = I40E_VF_ARQH1; 29 hw->aq.arq.len = I40E_VF_ARQLEN1; 30 hw->aq.arq.bal = I40E_VF_ARQBAL1; 31 hw->aq.arq.bah = I40E_VF_ARQBAH1; 32 } else { 33 hw->aq.asq.tail = I40E_PF_ATQT; 34 hw->aq.asq.head = I40E_PF_ATQH; 35 hw->aq.asq.len = I40E_PF_ATQLEN; 36 hw->aq.asq.bal = I40E_PF_ATQBAL; 37 hw->aq.asq.bah = I40E_PF_ATQBAH; 38 hw->aq.arq.tail = I40E_PF_ARQT; 39 hw->aq.arq.head = I40E_PF_ARQH; 40 hw->aq.arq.len = I40E_PF_ARQLEN; 41 hw->aq.arq.bal = I40E_PF_ARQBAL; 42 hw->aq.arq.bah = I40E_PF_ARQBAH; 43 } 44 } 45 46 /** 47 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings 48 * @hw: pointer to the hardware structure 49 **/ 50 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 51 { 52 i40e_status ret_code; 53 54 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 55 i40e_mem_atq_ring, 56 (hw->aq.num_asq_entries * 57 sizeof(struct i40e_aq_desc)), 58 I40E_ADMINQ_DESC_ALIGNMENT); 59 if (ret_code) 60 return ret_code; 61 62 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, 63 (hw->aq.num_asq_entries * 64 sizeof(struct i40e_asq_cmd_details))); 65 if (ret_code) { 66 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 67 return ret_code; 68 } 69 70 return ret_code; 71 } 72 73 /** 74 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings 75 * @hw: pointer to the hardware structure 76 **/ 77 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 78 { 79 i40e_status ret_code; 80 81 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 82 i40e_mem_arq_ring, 83 (hw->aq.num_arq_entries * 84 sizeof(struct i40e_aq_desc)), 85 I40E_ADMINQ_DESC_ALIGNMENT); 86 87 return ret_code; 88 } 89 90 /** 91 * i40e_free_adminq_asq - Free Admin Queue send rings 92 * @hw: pointer to the hardware structure 93 * 94 * This assumes the posted send buffers have already been cleaned 95 * and de-allocated 96 **/ 97 static void i40e_free_adminq_asq(struct i40e_hw *hw) 98 { 99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 100 } 101 102 /** 103 * i40e_free_adminq_arq - Free Admin Queue receive rings 104 * @hw: pointer to the hardware structure 105 * 106 * This assumes the posted receive buffers have already been cleaned 107 * and de-allocated 108 **/ 109 static void i40e_free_adminq_arq(struct i40e_hw *hw) 110 { 111 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 112 } 113 114 /** 115 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue 116 * @hw: pointer to the hardware structure 117 **/ 118 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) 119 { 120 i40e_status ret_code; 121 struct i40e_aq_desc *desc; 122 struct i40e_dma_mem *bi; 123 int i; 124 125 /* We'll be allocating the buffer info memory first, then we can 126 * allocate the mapped buffers for the event processing 127 */ 128 129 /* buffer_info structures do not need alignment */ 130 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, 131 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); 132 if (ret_code) 133 goto alloc_arq_bufs; 134 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; 135 136 /* allocate the mapped buffers */ 137 for (i = 0; i < hw->aq.num_arq_entries; i++) { 138 bi = &hw->aq.arq.r.arq_bi[i]; 139 ret_code = i40e_allocate_dma_mem(hw, bi, 140 i40e_mem_arq_buf, 141 hw->aq.arq_buf_size, 142 I40E_ADMINQ_DESC_ALIGNMENT); 143 if (ret_code) 144 goto unwind_alloc_arq_bufs; 145 146 /* now configure the descriptors for use */ 147 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 148 149 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 150 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 151 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 152 desc->opcode = 0; 153 /* This is in accordance with Admin queue design, there is no 154 * register for buffer size configuration 155 */ 156 desc->datalen = cpu_to_le16((u16)bi->size); 157 desc->retval = 0; 158 desc->cookie_high = 0; 159 desc->cookie_low = 0; 160 desc->params.external.addr_high = 161 cpu_to_le32(upper_32_bits(bi->pa)); 162 desc->params.external.addr_low = 163 cpu_to_le32(lower_32_bits(bi->pa)); 164 desc->params.external.param0 = 0; 165 desc->params.external.param1 = 0; 166 } 167 168 alloc_arq_bufs: 169 return ret_code; 170 171 unwind_alloc_arq_bufs: 172 /* don't try to free the one that failed... */ 173 i--; 174 for (; i >= 0; i--) 175 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 176 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 177 178 return ret_code; 179 } 180 181 /** 182 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue 183 * @hw: pointer to the hardware structure 184 **/ 185 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) 186 { 187 i40e_status ret_code; 188 struct i40e_dma_mem *bi; 189 int i; 190 191 /* No mapped memory needed yet, just the buffer info structures */ 192 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, 193 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); 194 if (ret_code) 195 goto alloc_asq_bufs; 196 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; 197 198 /* allocate the mapped buffers */ 199 for (i = 0; i < hw->aq.num_asq_entries; i++) { 200 bi = &hw->aq.asq.r.asq_bi[i]; 201 ret_code = i40e_allocate_dma_mem(hw, bi, 202 i40e_mem_asq_buf, 203 hw->aq.asq_buf_size, 204 I40E_ADMINQ_DESC_ALIGNMENT); 205 if (ret_code) 206 goto unwind_alloc_asq_bufs; 207 } 208 alloc_asq_bufs: 209 return ret_code; 210 211 unwind_alloc_asq_bufs: 212 /* don't try to free the one that failed... */ 213 i--; 214 for (; i >= 0; i--) 215 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 216 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 217 218 return ret_code; 219 } 220 221 /** 222 * i40e_free_arq_bufs - Free receive queue buffer info elements 223 * @hw: pointer to the hardware structure 224 **/ 225 static void i40e_free_arq_bufs(struct i40e_hw *hw) 226 { 227 int i; 228 229 /* free descriptors */ 230 for (i = 0; i < hw->aq.num_arq_entries; i++) 231 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 232 233 /* free the descriptor memory */ 234 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 235 236 /* free the dma header */ 237 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 238 } 239 240 /** 241 * i40e_free_asq_bufs - Free send queue buffer info elements 242 * @hw: pointer to the hardware structure 243 **/ 244 static void i40e_free_asq_bufs(struct i40e_hw *hw) 245 { 246 int i; 247 248 /* only unmap if the address is non-NULL */ 249 for (i = 0; i < hw->aq.num_asq_entries; i++) 250 if (hw->aq.asq.r.asq_bi[i].pa) 251 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 252 253 /* free the buffer info list */ 254 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); 255 256 /* free the descriptor memory */ 257 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 258 259 /* free the dma header */ 260 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 261 } 262 263 /** 264 * i40e_config_asq_regs - configure ASQ registers 265 * @hw: pointer to the hardware structure 266 * 267 * Configure base address and length registers for the transmit queue 268 **/ 269 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) 270 { 271 i40e_status ret_code = 0; 272 u32 reg = 0; 273 274 /* Clear Head and Tail */ 275 wr32(hw, hw->aq.asq.head, 0); 276 wr32(hw, hw->aq.asq.tail, 0); 277 278 /* set starting point */ 279 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 280 I40E_PF_ATQLEN_ATQENABLE_MASK)); 281 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); 282 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); 283 284 /* Check one register to verify that config was applied */ 285 reg = rd32(hw, hw->aq.asq.bal); 286 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 287 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 288 289 return ret_code; 290 } 291 292 /** 293 * i40e_config_arq_regs - ARQ register configuration 294 * @hw: pointer to the hardware structure 295 * 296 * Configure base address and length registers for the receive (event queue) 297 **/ 298 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) 299 { 300 i40e_status ret_code = 0; 301 u32 reg = 0; 302 303 /* Clear Head and Tail */ 304 wr32(hw, hw->aq.arq.head, 0); 305 wr32(hw, hw->aq.arq.tail, 0); 306 307 /* set starting point */ 308 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | 309 I40E_PF_ARQLEN_ARQENABLE_MASK)); 310 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); 311 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); 312 313 /* Update tail in the HW to post pre-allocated buffers */ 314 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 315 316 /* Check one register to verify that config was applied */ 317 reg = rd32(hw, hw->aq.arq.bal); 318 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 319 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 320 321 return ret_code; 322 } 323 324 /** 325 * i40e_init_asq - main initialization routine for ASQ 326 * @hw: pointer to the hardware structure 327 * 328 * This is the main initialization routine for the Admin Send Queue 329 * Prior to calling this function, drivers *MUST* set the following fields 330 * in the hw->aq structure: 331 * - hw->aq.num_asq_entries 332 * - hw->aq.arq_buf_size 333 * 334 * Do *NOT* hold the lock when calling this as the memory allocation routines 335 * called are not going to be atomic context safe 336 **/ 337 static i40e_status i40e_init_asq(struct i40e_hw *hw) 338 { 339 i40e_status ret_code = 0; 340 341 if (hw->aq.asq.count > 0) { 342 /* queue already initialized */ 343 ret_code = I40E_ERR_NOT_READY; 344 goto init_adminq_exit; 345 } 346 347 /* verify input for valid configuration */ 348 if ((hw->aq.num_asq_entries == 0) || 349 (hw->aq.asq_buf_size == 0)) { 350 ret_code = I40E_ERR_CONFIG; 351 goto init_adminq_exit; 352 } 353 354 hw->aq.asq.next_to_use = 0; 355 hw->aq.asq.next_to_clean = 0; 356 357 /* allocate the ring memory */ 358 ret_code = i40e_alloc_adminq_asq_ring(hw); 359 if (ret_code) 360 goto init_adminq_exit; 361 362 /* allocate buffers in the rings */ 363 ret_code = i40e_alloc_asq_bufs(hw); 364 if (ret_code) 365 goto init_adminq_free_rings; 366 367 /* initialize base registers */ 368 ret_code = i40e_config_asq_regs(hw); 369 if (ret_code) 370 goto init_adminq_free_rings; 371 372 /* success! */ 373 hw->aq.asq.count = hw->aq.num_asq_entries; 374 goto init_adminq_exit; 375 376 init_adminq_free_rings: 377 i40e_free_adminq_asq(hw); 378 379 init_adminq_exit: 380 return ret_code; 381 } 382 383 /** 384 * i40e_init_arq - initialize ARQ 385 * @hw: pointer to the hardware structure 386 * 387 * The main initialization routine for the Admin Receive (Event) Queue. 388 * Prior to calling this function, drivers *MUST* set the following fields 389 * in the hw->aq structure: 390 * - hw->aq.num_asq_entries 391 * - hw->aq.arq_buf_size 392 * 393 * Do *NOT* hold the lock when calling this as the memory allocation routines 394 * called are not going to be atomic context safe 395 **/ 396 static i40e_status i40e_init_arq(struct i40e_hw *hw) 397 { 398 i40e_status ret_code = 0; 399 400 if (hw->aq.arq.count > 0) { 401 /* queue already initialized */ 402 ret_code = I40E_ERR_NOT_READY; 403 goto init_adminq_exit; 404 } 405 406 /* verify input for valid configuration */ 407 if ((hw->aq.num_arq_entries == 0) || 408 (hw->aq.arq_buf_size == 0)) { 409 ret_code = I40E_ERR_CONFIG; 410 goto init_adminq_exit; 411 } 412 413 hw->aq.arq.next_to_use = 0; 414 hw->aq.arq.next_to_clean = 0; 415 416 /* allocate the ring memory */ 417 ret_code = i40e_alloc_adminq_arq_ring(hw); 418 if (ret_code) 419 goto init_adminq_exit; 420 421 /* allocate buffers in the rings */ 422 ret_code = i40e_alloc_arq_bufs(hw); 423 if (ret_code) 424 goto init_adminq_free_rings; 425 426 /* initialize base registers */ 427 ret_code = i40e_config_arq_regs(hw); 428 if (ret_code) 429 goto init_adminq_free_rings; 430 431 /* success! */ 432 hw->aq.arq.count = hw->aq.num_arq_entries; 433 goto init_adminq_exit; 434 435 init_adminq_free_rings: 436 i40e_free_adminq_arq(hw); 437 438 init_adminq_exit: 439 return ret_code; 440 } 441 442 /** 443 * i40e_shutdown_asq - shutdown the ASQ 444 * @hw: pointer to the hardware structure 445 * 446 * The main shutdown routine for the Admin Send Queue 447 **/ 448 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) 449 { 450 i40e_status ret_code = 0; 451 452 mutex_lock(&hw->aq.asq_mutex); 453 454 if (hw->aq.asq.count == 0) { 455 ret_code = I40E_ERR_NOT_READY; 456 goto shutdown_asq_out; 457 } 458 459 /* Stop firmware AdminQ processing */ 460 wr32(hw, hw->aq.asq.head, 0); 461 wr32(hw, hw->aq.asq.tail, 0); 462 wr32(hw, hw->aq.asq.len, 0); 463 wr32(hw, hw->aq.asq.bal, 0); 464 wr32(hw, hw->aq.asq.bah, 0); 465 466 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ 467 468 /* free ring buffers */ 469 i40e_free_asq_bufs(hw); 470 471 shutdown_asq_out: 472 mutex_unlock(&hw->aq.asq_mutex); 473 return ret_code; 474 } 475 476 /** 477 * i40e_shutdown_arq - shutdown ARQ 478 * @hw: pointer to the hardware structure 479 * 480 * The main shutdown routine for the Admin Receive Queue 481 **/ 482 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) 483 { 484 i40e_status ret_code = 0; 485 486 mutex_lock(&hw->aq.arq_mutex); 487 488 if (hw->aq.arq.count == 0) { 489 ret_code = I40E_ERR_NOT_READY; 490 goto shutdown_arq_out; 491 } 492 493 /* Stop firmware AdminQ processing */ 494 wr32(hw, hw->aq.arq.head, 0); 495 wr32(hw, hw->aq.arq.tail, 0); 496 wr32(hw, hw->aq.arq.len, 0); 497 wr32(hw, hw->aq.arq.bal, 0); 498 wr32(hw, hw->aq.arq.bah, 0); 499 500 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ 501 502 /* free ring buffers */ 503 i40e_free_arq_bufs(hw); 504 505 shutdown_arq_out: 506 mutex_unlock(&hw->aq.arq_mutex); 507 return ret_code; 508 } 509 510 /** 511 * i40e_set_hw_flags - set HW flags 512 * @hw: pointer to the hardware structure 513 **/ 514 static void i40e_set_hw_flags(struct i40e_hw *hw) 515 { 516 struct i40e_adminq_info *aq = &hw->aq; 517 518 hw->flags = 0; 519 520 switch (hw->mac.type) { 521 case I40E_MAC_XL710: 522 if (aq->api_maj_ver > 1 || 523 (aq->api_maj_ver == 1 && 524 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 525 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 526 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 527 /* The ability to RX (not drop) 802.1ad frames */ 528 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; 529 } 530 break; 531 case I40E_MAC_X722: 532 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 533 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 534 535 if (aq->api_maj_ver > 1 || 536 (aq->api_maj_ver == 1 && 537 aq->api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722)) 538 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 539 540 if (aq->api_maj_ver > 1 || 541 (aq->api_maj_ver == 1 && 542 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_X722)) 543 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 544 /* fall through */ 545 default: 546 break; 547 } 548 549 /* Newer versions of firmware require lock when reading the NVM */ 550 if (aq->api_maj_ver > 1 || 551 (aq->api_maj_ver == 1 && 552 aq->api_min_ver >= 5)) 553 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 554 555 if (aq->api_maj_ver > 1 || 556 (aq->api_maj_ver == 1 && 557 aq->api_min_ver >= 8)) { 558 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT; 559 hw->flags |= I40E_HW_FLAG_DROP_MODE; 560 } 561 562 if (aq->api_maj_ver > 1 || 563 (aq->api_maj_ver == 1 && 564 aq->api_min_ver >= 9)) 565 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED; 566 } 567 568 /** 569 * i40e_init_adminq - main initialization routine for Admin Queue 570 * @hw: pointer to the hardware structure 571 * 572 * Prior to calling this function, drivers *MUST* set the following fields 573 * in the hw->aq structure: 574 * - hw->aq.num_asq_entries 575 * - hw->aq.num_arq_entries 576 * - hw->aq.arq_buf_size 577 * - hw->aq.asq_buf_size 578 **/ 579 i40e_status i40e_init_adminq(struct i40e_hw *hw) 580 { 581 u16 cfg_ptr, oem_hi, oem_lo; 582 u16 eetrack_lo, eetrack_hi; 583 i40e_status ret_code; 584 int retry = 0; 585 586 /* verify input for valid configuration */ 587 if ((hw->aq.num_arq_entries == 0) || 588 (hw->aq.num_asq_entries == 0) || 589 (hw->aq.arq_buf_size == 0) || 590 (hw->aq.asq_buf_size == 0)) { 591 ret_code = I40E_ERR_CONFIG; 592 goto init_adminq_exit; 593 } 594 595 /* Set up register offsets */ 596 i40e_adminq_init_regs(hw); 597 598 /* setup ASQ command write back timeout */ 599 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; 600 601 /* allocate the ASQ */ 602 ret_code = i40e_init_asq(hw); 603 if (ret_code) 604 goto init_adminq_destroy_locks; 605 606 /* allocate the ARQ */ 607 ret_code = i40e_init_arq(hw); 608 if (ret_code) 609 goto init_adminq_free_asq; 610 611 /* There are some cases where the firmware may not be quite ready 612 * for AdminQ operations, so we retry the AdminQ setup a few times 613 * if we see timeouts in this first AQ call. 614 */ 615 do { 616 ret_code = i40e_aq_get_firmware_version(hw, 617 &hw->aq.fw_maj_ver, 618 &hw->aq.fw_min_ver, 619 &hw->aq.fw_build, 620 &hw->aq.api_maj_ver, 621 &hw->aq.api_min_ver, 622 NULL); 623 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) 624 break; 625 retry++; 626 msleep(100); 627 i40e_resume_aq(hw); 628 } while (retry < 10); 629 if (ret_code != I40E_SUCCESS) 630 goto init_adminq_free_arq; 631 632 /* Some features were introduced in different FW API version 633 * for different MAC type. 634 */ 635 i40e_set_hw_flags(hw); 636 637 /* get the NVM version info */ 638 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, 639 &hw->nvm.version); 640 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 641 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 642 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 643 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 644 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), 645 &oem_hi); 646 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), 647 &oem_lo); 648 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; 649 650 if (hw->mac.type == I40E_MAC_XL710 && 651 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 652 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 653 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 654 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 655 } 656 if (hw->mac.type == I40E_MAC_X722 && 657 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 658 hw->aq.api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) { 659 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; 660 } 661 662 /* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */ 663 if (hw->aq.api_maj_ver > 1 || 664 (hw->aq.api_maj_ver == 1 && 665 hw->aq.api_min_ver >= 7)) 666 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; 667 668 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { 669 ret_code = I40E_ERR_FIRMWARE_API_VERSION; 670 goto init_adminq_free_arq; 671 } 672 673 /* pre-emptive resource lock release */ 674 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 675 hw->nvm_release_on_done = false; 676 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 677 678 ret_code = 0; 679 680 /* success! */ 681 goto init_adminq_exit; 682 683 init_adminq_free_arq: 684 i40e_shutdown_arq(hw); 685 init_adminq_free_asq: 686 i40e_shutdown_asq(hw); 687 init_adminq_destroy_locks: 688 689 init_adminq_exit: 690 return ret_code; 691 } 692 693 /** 694 * i40e_shutdown_adminq - shutdown routine for the Admin Queue 695 * @hw: pointer to the hardware structure 696 **/ 697 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) 698 { 699 i40e_status ret_code = 0; 700 701 if (i40e_check_asq_alive(hw)) 702 i40e_aq_queue_shutdown(hw, true); 703 704 i40e_shutdown_asq(hw); 705 i40e_shutdown_arq(hw); 706 707 if (hw->nvm_buff.va) 708 i40e_free_virt_mem(hw, &hw->nvm_buff); 709 710 return ret_code; 711 } 712 713 /** 714 * i40e_clean_asq - cleans Admin send queue 715 * @hw: pointer to the hardware structure 716 * 717 * returns the number of free desc 718 **/ 719 static u16 i40e_clean_asq(struct i40e_hw *hw) 720 { 721 struct i40e_adminq_ring *asq = &(hw->aq.asq); 722 struct i40e_asq_cmd_details *details; 723 u16 ntc = asq->next_to_clean; 724 struct i40e_aq_desc desc_cb; 725 struct i40e_aq_desc *desc; 726 727 desc = I40E_ADMINQ_DESC(*asq, ntc); 728 details = I40E_ADMINQ_DETAILS(*asq, ntc); 729 while (rd32(hw, hw->aq.asq.head) != ntc) { 730 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, 731 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); 732 733 if (details->callback) { 734 I40E_ADMINQ_CALLBACK cb_func = 735 (I40E_ADMINQ_CALLBACK)details->callback; 736 desc_cb = *desc; 737 cb_func(hw, &desc_cb); 738 } 739 memset(desc, 0, sizeof(*desc)); 740 memset(details, 0, sizeof(*details)); 741 ntc++; 742 if (ntc == asq->count) 743 ntc = 0; 744 desc = I40E_ADMINQ_DESC(*asq, ntc); 745 details = I40E_ADMINQ_DETAILS(*asq, ntc); 746 } 747 748 asq->next_to_clean = ntc; 749 750 return I40E_DESC_UNUSED(asq); 751 } 752 753 /** 754 * i40e_asq_done - check if FW has processed the Admin Send Queue 755 * @hw: pointer to the hw struct 756 * 757 * Returns true if the firmware has processed all descriptors on the 758 * admin send queue. Returns false if there are still requests pending. 759 **/ 760 static bool i40e_asq_done(struct i40e_hw *hw) 761 { 762 /* AQ designers suggest use of head for better 763 * timing reliability than DD bit 764 */ 765 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; 766 767 } 768 769 /** 770 * i40e_asq_send_command - send command to Admin Queue 771 * @hw: pointer to the hw struct 772 * @desc: prefilled descriptor describing the command (non DMA mem) 773 * @buff: buffer to use for indirect commands 774 * @buff_size: size of buffer for indirect commands 775 * @cmd_details: pointer to command details structure 776 * 777 * This is the main send command driver routine for the Admin Queue send 778 * queue. It runs the queue, cleans the queue, etc 779 **/ 780 i40e_status i40e_asq_send_command(struct i40e_hw *hw, 781 struct i40e_aq_desc *desc, 782 void *buff, /* can be NULL */ 783 u16 buff_size, 784 struct i40e_asq_cmd_details *cmd_details) 785 { 786 i40e_status status = 0; 787 struct i40e_dma_mem *dma_buff = NULL; 788 struct i40e_asq_cmd_details *details; 789 struct i40e_aq_desc *desc_on_ring; 790 bool cmd_completed = false; 791 u16 retval = 0; 792 u32 val = 0; 793 794 mutex_lock(&hw->aq.asq_mutex); 795 796 if (hw->aq.asq.count == 0) { 797 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 798 "AQTX: Admin queue not initialized.\n"); 799 status = I40E_ERR_QUEUE_EMPTY; 800 goto asq_send_command_error; 801 } 802 803 hw->aq.asq_last_status = I40E_AQ_RC_OK; 804 805 val = rd32(hw, hw->aq.asq.head); 806 if (val >= hw->aq.num_asq_entries) { 807 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 808 "AQTX: head overrun at %d\n", val); 809 status = I40E_ERR_ADMIN_QUEUE_FULL; 810 goto asq_send_command_error; 811 } 812 813 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); 814 if (cmd_details) { 815 *details = *cmd_details; 816 817 /* If the cmd_details are defined copy the cookie. The 818 * cpu_to_le32 is not needed here because the data is ignored 819 * by the FW, only used by the driver 820 */ 821 if (details->cookie) { 822 desc->cookie_high = 823 cpu_to_le32(upper_32_bits(details->cookie)); 824 desc->cookie_low = 825 cpu_to_le32(lower_32_bits(details->cookie)); 826 } 827 } else { 828 memset(details, 0, sizeof(struct i40e_asq_cmd_details)); 829 } 830 831 /* clear requested flags and then set additional flags if defined */ 832 desc->flags &= ~cpu_to_le16(details->flags_dis); 833 desc->flags |= cpu_to_le16(details->flags_ena); 834 835 if (buff_size > hw->aq.asq_buf_size) { 836 i40e_debug(hw, 837 I40E_DEBUG_AQ_MESSAGE, 838 "AQTX: Invalid buffer size: %d.\n", 839 buff_size); 840 status = I40E_ERR_INVALID_SIZE; 841 goto asq_send_command_error; 842 } 843 844 if (details->postpone && !details->async) { 845 i40e_debug(hw, 846 I40E_DEBUG_AQ_MESSAGE, 847 "AQTX: Async flag not set along with postpone flag"); 848 status = I40E_ERR_PARAM; 849 goto asq_send_command_error; 850 } 851 852 /* call clean and check queue available function to reclaim the 853 * descriptors that were processed by FW, the function returns the 854 * number of desc available 855 */ 856 /* the clean function called here could be called in a separate thread 857 * in case of asynchronous completions 858 */ 859 if (i40e_clean_asq(hw) == 0) { 860 i40e_debug(hw, 861 I40E_DEBUG_AQ_MESSAGE, 862 "AQTX: Error queue is full.\n"); 863 status = I40E_ERR_ADMIN_QUEUE_FULL; 864 goto asq_send_command_error; 865 } 866 867 /* initialize the temp desc pointer with the right desc */ 868 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); 869 870 /* if the desc is available copy the temp desc to the right place */ 871 *desc_on_ring = *desc; 872 873 /* if buff is not NULL assume indirect command */ 874 if (buff != NULL) { 875 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); 876 /* copy the user buff into the respective DMA buff */ 877 memcpy(dma_buff->va, buff, buff_size); 878 desc_on_ring->datalen = cpu_to_le16(buff_size); 879 880 /* Update the address values in the desc with the pa value 881 * for respective buffer 882 */ 883 desc_on_ring->params.external.addr_high = 884 cpu_to_le32(upper_32_bits(dma_buff->pa)); 885 desc_on_ring->params.external.addr_low = 886 cpu_to_le32(lower_32_bits(dma_buff->pa)); 887 } 888 889 /* bump the tail */ 890 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); 891 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, 892 buff, buff_size); 893 (hw->aq.asq.next_to_use)++; 894 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 895 hw->aq.asq.next_to_use = 0; 896 if (!details->postpone) 897 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); 898 899 /* if cmd_details are not defined or async flag is not set, 900 * we need to wait for desc write back 901 */ 902 if (!details->async && !details->postpone) { 903 u32 total_delay = 0; 904 905 do { 906 /* AQ designers suggest use of head for better 907 * timing reliability than DD bit 908 */ 909 if (i40e_asq_done(hw)) 910 break; 911 udelay(50); 912 total_delay += 50; 913 } while (total_delay < hw->aq.asq_cmd_timeout); 914 } 915 916 /* if ready, copy the desc back to temp */ 917 if (i40e_asq_done(hw)) { 918 *desc = *desc_on_ring; 919 if (buff != NULL) 920 memcpy(buff, dma_buff->va, buff_size); 921 retval = le16_to_cpu(desc->retval); 922 if (retval != 0) { 923 i40e_debug(hw, 924 I40E_DEBUG_AQ_MESSAGE, 925 "AQTX: Command completed with error 0x%X.\n", 926 retval); 927 928 /* strip off FW internal code */ 929 retval &= 0xff; 930 } 931 cmd_completed = true; 932 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 933 status = 0; 934 else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY) 935 status = I40E_ERR_NOT_READY; 936 else 937 status = I40E_ERR_ADMIN_QUEUE_ERROR; 938 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 939 } 940 941 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, 942 "AQTX: desc and buffer writeback:\n"); 943 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); 944 945 /* save writeback aq if requested */ 946 if (details->wb_desc) 947 *details->wb_desc = *desc_on_ring; 948 949 /* update the error if time out occurred */ 950 if ((!cmd_completed) && 951 (!details->async && !details->postpone)) { 952 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { 953 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 954 "AQTX: AQ Critical error.\n"); 955 status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR; 956 } else { 957 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 958 "AQTX: Writeback timeout.\n"); 959 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; 960 } 961 } 962 963 asq_send_command_error: 964 mutex_unlock(&hw->aq.asq_mutex); 965 return status; 966 } 967 968 /** 969 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function 970 * @desc: pointer to the temp descriptor (non DMA mem) 971 * @opcode: the opcode can be used to decide which flags to turn off or on 972 * 973 * Fill the desc with default values 974 **/ 975 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 976 u16 opcode) 977 { 978 /* zero out the desc */ 979 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 980 desc->opcode = cpu_to_le16(opcode); 981 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); 982 } 983 984 /** 985 * i40e_clean_arq_element 986 * @hw: pointer to the hw struct 987 * @e: event info from the receive descriptor, includes any buffers 988 * @pending: number of events that could be left to process 989 * 990 * This function cleans one Admin Receive Queue element and returns 991 * the contents through e. It can also return how many events are 992 * left to process through 'pending' 993 **/ 994 i40e_status i40e_clean_arq_element(struct i40e_hw *hw, 995 struct i40e_arq_event_info *e, 996 u16 *pending) 997 { 998 i40e_status ret_code = 0; 999 u16 ntc = hw->aq.arq.next_to_clean; 1000 struct i40e_aq_desc *desc; 1001 struct i40e_dma_mem *bi; 1002 u16 desc_idx; 1003 u16 datalen; 1004 u16 flags; 1005 u16 ntu; 1006 1007 /* pre-clean the event info */ 1008 memset(&e->desc, 0, sizeof(e->desc)); 1009 1010 /* take the lock before we start messing with the ring */ 1011 mutex_lock(&hw->aq.arq_mutex); 1012 1013 if (hw->aq.arq.count == 0) { 1014 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 1015 "AQRX: Admin queue not initialized.\n"); 1016 ret_code = I40E_ERR_QUEUE_EMPTY; 1017 goto clean_arq_element_err; 1018 } 1019 1020 /* set next_to_use to head */ 1021 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; 1022 if (ntu == ntc) { 1023 /* nothing to do - shouldn't need to update ring's values */ 1024 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; 1025 goto clean_arq_element_out; 1026 } 1027 1028 /* now clean the next descriptor */ 1029 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 1030 desc_idx = ntc; 1031 1032 hw->aq.arq_last_status = 1033 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 1034 flags = le16_to_cpu(desc->flags); 1035 if (flags & I40E_AQ_FLAG_ERR) { 1036 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 1037 i40e_debug(hw, 1038 I40E_DEBUG_AQ_MESSAGE, 1039 "AQRX: Event received with error 0x%X.\n", 1040 hw->aq.arq_last_status); 1041 } 1042 1043 e->desc = *desc; 1044 datalen = le16_to_cpu(desc->datalen); 1045 e->msg_len = min(datalen, e->buf_len); 1046 if (e->msg_buf != NULL && (e->msg_len != 0)) 1047 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, 1048 e->msg_len); 1049 1050 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); 1051 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, 1052 hw->aq.arq_buf_size); 1053 1054 /* Restore the original datalen and buffer address in the desc, 1055 * FW updates datalen to indicate the event message 1056 * size 1057 */ 1058 bi = &hw->aq.arq.r.arq_bi[ntc]; 1059 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 1060 1061 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 1062 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 1063 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 1064 desc->datalen = cpu_to_le16((u16)bi->size); 1065 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1066 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1067 1068 /* set tail = the last cleaned desc index. */ 1069 wr32(hw, hw->aq.arq.tail, ntc); 1070 /* ntc is updated to tail + 1 */ 1071 ntc++; 1072 if (ntc == hw->aq.num_arq_entries) 1073 ntc = 0; 1074 hw->aq.arq.next_to_clean = ntc; 1075 hw->aq.arq.next_to_use = ntu; 1076 1077 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc); 1078 clean_arq_element_out: 1079 /* Set pending if needed, unlock and return */ 1080 if (pending) 1081 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); 1082 clean_arq_element_err: 1083 mutex_unlock(&hw->aq.arq_mutex); 1084 1085 return ret_code; 1086 } 1087 1088 static void i40e_resume_aq(struct i40e_hw *hw) 1089 { 1090 /* Registers are reset after PF reset */ 1091 hw->aq.asq.next_to_use = 0; 1092 hw->aq.asq.next_to_clean = 0; 1093 1094 i40e_config_asq_regs(hw); 1095 1096 hw->aq.arq.next_to_use = 0; 1097 hw->aq.arq.next_to_clean = 0; 1098 1099 i40e_config_arq_regs(hw); 1100 } 1101