1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_TYPE_H_ 5 #define _I40E_TYPE_H_ 6 7 #include <uapi/linux/if_ether.h> 8 #include "i40e_adminq.h" 9 #include "i40e_hmc.h" 10 11 #define I40E_MAX_VSI_QP 16 12 #define I40E_MAX_VF_VSI 4 13 #define I40E_MAX_CHAINED_RX_BUFFERS 5 14 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 15 16 /* Max default timeout in ms, */ 17 #define I40E_MAX_NVM_TIMEOUT 18000 18 19 /* Max timeout in ms for the phy to respond */ 20 #define I40E_MAX_PHY_TIMEOUT 500 21 22 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 23 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 24 25 /* forward declaration */ 26 struct i40e_hw; 27 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 28 29 /* Data type manipulation macros. */ 30 31 #define I40E_DESC_UNUSED(R) \ 32 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 33 (R)->next_to_clean - (R)->next_to_use - 1) 34 35 /* bitfields for Tx queue mapping in QTX_CTL */ 36 #define I40E_QTX_CTL_VF_QUEUE 0x0 37 #define I40E_QTX_CTL_VM_QUEUE 0x1 38 #define I40E_QTX_CTL_PF_QUEUE 0x2 39 40 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_GLGEN_MSCA_STCODE_MASK 41 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_GLGEN_MSCA_OPCODE_MASK(1) 42 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_GLGEN_MSCA_OPCODE_MASK(2) 43 44 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_GLGEN_MSCA_STCODE_MASK 45 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_GLGEN_MSCA_OPCODE_MASK(0) 46 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_GLGEN_MSCA_OPCODE_MASK(1) 47 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_GLGEN_MSCA_OPCODE_MASK(3) 48 49 #define I40E_PHY_COM_REG_PAGE 0x1E 50 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0 51 #define I40E_PHY_LED_MANUAL_ON 0x100 52 #define I40E_PHY_LED_PROV_REG_1 0xC430 53 #define I40E_PHY_LED_MODE_MASK 0xFFFF 54 #define I40E_PHY_LED_MODE_ORIG 0x80000000 55 56 /* These are structs for managing the hardware information and the operations. 57 * The structures of function pointers are filled out at init time when we 58 * know for sure exactly which hardware we're working with. This gives us the 59 * flexibility of using the same main driver code but adapting to slightly 60 * different hardware needs as new parts are developed. For this architecture, 61 * the Firmware and AdminQ are intended to insulate the driver from most of the 62 * future changes, but these structures will also do part of the job. 63 */ 64 enum i40e_mac_type { 65 I40E_MAC_UNKNOWN = 0, 66 I40E_MAC_XL710, 67 I40E_MAC_VF, 68 I40E_MAC_X722, 69 I40E_MAC_X722_VF, 70 I40E_MAC_GENERIC, 71 }; 72 73 enum i40e_media_type { 74 I40E_MEDIA_TYPE_UNKNOWN = 0, 75 I40E_MEDIA_TYPE_FIBER, 76 I40E_MEDIA_TYPE_BASET, 77 I40E_MEDIA_TYPE_BACKPLANE, 78 I40E_MEDIA_TYPE_CX4, 79 I40E_MEDIA_TYPE_DA, 80 I40E_MEDIA_TYPE_VIRTUAL 81 }; 82 83 enum i40e_fc_mode { 84 I40E_FC_NONE = 0, 85 I40E_FC_RX_PAUSE, 86 I40E_FC_TX_PAUSE, 87 I40E_FC_FULL, 88 I40E_FC_PFC, 89 I40E_FC_DEFAULT 90 }; 91 92 enum i40e_set_fc_aq_failures { 93 I40E_SET_FC_AQ_FAIL_NONE = 0, 94 I40E_SET_FC_AQ_FAIL_GET = 1, 95 I40E_SET_FC_AQ_FAIL_SET = 2, 96 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 97 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 98 }; 99 100 enum i40e_vsi_type { 101 I40E_VSI_MAIN = 0, 102 I40E_VSI_VMDQ1 = 1, 103 I40E_VSI_VMDQ2 = 2, 104 I40E_VSI_CTRL = 3, 105 I40E_VSI_FCOE = 4, 106 I40E_VSI_MIRROR = 5, 107 I40E_VSI_SRIOV = 6, 108 I40E_VSI_FDIR = 7, 109 I40E_VSI_IWARP = 8, 110 I40E_VSI_TYPE_UNKNOWN 111 }; 112 113 enum i40e_queue_type { 114 I40E_QUEUE_TYPE_RX = 0, 115 I40E_QUEUE_TYPE_TX, 116 I40E_QUEUE_TYPE_PE_CEQ, 117 I40E_QUEUE_TYPE_UNKNOWN 118 }; 119 120 struct i40e_link_status { 121 enum i40e_aq_phy_type phy_type; 122 enum i40e_aq_link_speed link_speed; 123 u8 link_info; 124 u8 an_info; 125 u8 req_fec_info; 126 u8 fec_info; 127 u8 ext_info; 128 u8 loopback; 129 /* is Link Status Event notification to SW enabled */ 130 bool lse_enable; 131 u16 max_frame_size; 132 bool crc_enable; 133 u8 pacing; 134 u8 requested_speeds; 135 u8 module_type[3]; 136 /* 1st byte: module identifier */ 137 #define I40E_MODULE_TYPE_SFP 0x03 138 /* 3rd byte: ethernet compliance codes for 1G */ 139 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 140 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 141 }; 142 143 struct i40e_phy_info { 144 struct i40e_link_status link_info; 145 struct i40e_link_status link_info_old; 146 bool get_link_info; 147 enum i40e_media_type media_type; 148 /* all the phy types the NVM is capable of */ 149 u64 phy_types; 150 }; 151 152 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) 153 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) 154 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) 155 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) 156 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) 157 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) 158 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) 159 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) 160 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) 161 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) 162 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) 163 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) 164 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) 165 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) 166 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) 167 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) 168 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) 169 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) 170 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) 171 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) 172 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) 173 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) 174 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) 175 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) 176 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) 177 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) 178 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ 179 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) 180 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) 181 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some 182 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit 183 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, 184 * a shift is needed to adjust for this with values larger than 31. The 185 * only affected values are I40E_PHY_TYPE_25GBASE_*. 186 */ 187 #define I40E_PHY_TYPE_OFFSET 1 188 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ 189 I40E_PHY_TYPE_OFFSET) 190 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ 191 I40E_PHY_TYPE_OFFSET) 192 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 193 I40E_PHY_TYPE_OFFSET) 194 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 195 I40E_PHY_TYPE_OFFSET) 196 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 197 I40E_PHY_TYPE_OFFSET) 198 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 199 I40E_PHY_TYPE_OFFSET) 200 /* Offset for 2.5G/5G PHY Types value to bit number conversion */ 201 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) 202 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T) 203 #define I40E_HW_CAP_MAX_GPIO 30 204 /* Capabilities of a PF or a VF or the whole device */ 205 struct i40e_hw_capabilities { 206 u32 switch_mode; 207 208 /* Cloud filter modes: 209 * Mode1: Filter on L4 port only 210 * Mode2: Filter for non-tunneled traffic 211 * Mode3: Filter for tunnel traffic 212 */ 213 #define I40E_CLOUD_FILTER_MODE1 0x6 214 #define I40E_CLOUD_FILTER_MODE2 0x7 215 #define I40E_SWITCH_MODE_MASK 0xF 216 217 u32 management_mode; 218 u32 mng_protocols_over_mctp; 219 u32 npar_enable; 220 u32 os2bmc; 221 u32 valid_functions; 222 bool sr_iov_1_1; 223 bool vmdq; 224 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 225 bool evb_802_1_qbh; /* Bridge Port Extension */ 226 bool dcb; 227 bool fcoe; 228 bool iscsi; /* Indicates iSCSI enabled */ 229 bool flex10_enable; 230 bool flex10_capable; 231 u32 flex10_mode; 232 233 u32 flex10_status; 234 235 bool sec_rev_disabled; 236 bool update_disabled; 237 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 238 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 239 240 bool mgmt_cem; 241 bool ieee_1588; 242 bool iwarp; 243 bool fd; 244 u32 fd_filters_guaranteed; 245 u32 fd_filters_best_effort; 246 bool rss; 247 u32 rss_table_size; 248 u32 rss_table_entry_width; 249 bool led[I40E_HW_CAP_MAX_GPIO]; 250 bool sdp[I40E_HW_CAP_MAX_GPIO]; 251 u32 nvm_image_type; 252 u32 num_flow_director_filters; 253 u32 num_vfs; 254 u32 vf_base_id; 255 u32 num_vsis; 256 u32 num_rx_qp; 257 u32 num_tx_qp; 258 u32 base_queue; 259 u32 num_msix_vectors; 260 u32 num_msix_vectors_vf; 261 u32 led_pin_num; 262 u32 sdp_pin_num; 263 u32 mdio_port_num; 264 u32 mdio_port_mode; 265 u8 rx_buf_chain_len; 266 u32 enabled_tcmap; 267 u32 maxtc; 268 u64 wr_csr_prot; 269 }; 270 271 struct i40e_mac_info { 272 enum i40e_mac_type type; 273 u8 addr[ETH_ALEN]; 274 u8 perm_addr[ETH_ALEN]; 275 u8 san_addr[ETH_ALEN]; 276 u8 port_addr[ETH_ALEN]; 277 u16 max_fcoeq; 278 }; 279 280 enum i40e_aq_resources_ids { 281 I40E_NVM_RESOURCE_ID = 1 282 }; 283 284 enum i40e_aq_resource_access_type { 285 I40E_RESOURCE_READ = 1, 286 I40E_RESOURCE_WRITE 287 }; 288 289 struct i40e_nvm_info { 290 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 291 u32 timeout; /* [ms] */ 292 u16 sr_size; /* Shadow RAM size in words */ 293 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 294 u16 version; /* NVM package version */ 295 u32 eetrack; /* NVM data version */ 296 u32 oem_ver; /* OEM version info */ 297 }; 298 299 /* definitions used in NVM update support */ 300 301 enum i40e_nvmupd_cmd { 302 I40E_NVMUPD_INVALID, 303 I40E_NVMUPD_READ_CON, 304 I40E_NVMUPD_READ_SNT, 305 I40E_NVMUPD_READ_LCB, 306 I40E_NVMUPD_READ_SA, 307 I40E_NVMUPD_WRITE_ERA, 308 I40E_NVMUPD_WRITE_CON, 309 I40E_NVMUPD_WRITE_SNT, 310 I40E_NVMUPD_WRITE_LCB, 311 I40E_NVMUPD_WRITE_SA, 312 I40E_NVMUPD_CSUM_CON, 313 I40E_NVMUPD_CSUM_SA, 314 I40E_NVMUPD_CSUM_LCB, 315 I40E_NVMUPD_STATUS, 316 I40E_NVMUPD_EXEC_AQ, 317 I40E_NVMUPD_GET_AQ_RESULT, 318 I40E_NVMUPD_GET_AQ_EVENT, 319 }; 320 321 enum i40e_nvmupd_state { 322 I40E_NVMUPD_STATE_INIT, 323 I40E_NVMUPD_STATE_READING, 324 I40E_NVMUPD_STATE_WRITING, 325 I40E_NVMUPD_STATE_INIT_WAIT, 326 I40E_NVMUPD_STATE_WRITE_WAIT, 327 I40E_NVMUPD_STATE_ERROR 328 }; 329 330 /* nvm_access definition and its masks/shifts need to be accessible to 331 * application, core driver, and shared code. Where is the right file? 332 */ 333 #define I40E_NVM_READ 0xB 334 #define I40E_NVM_WRITE 0xC 335 336 #define I40E_NVM_MOD_PNT_MASK 0xFF 337 338 #define I40E_NVM_TRANS_SHIFT 8 339 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 340 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 341 #define I40E_NVM_PRESERVATION_FLAGS_MASK \ 342 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) 343 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 344 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 345 #define I40E_NVM_CON 0x0 346 #define I40E_NVM_SNT 0x1 347 #define I40E_NVM_LCB 0x2 348 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 349 #define I40E_NVM_ERA 0x4 350 #define I40E_NVM_CSUM 0x8 351 #define I40E_NVM_AQE 0xe 352 #define I40E_NVM_EXEC 0xf 353 354 355 #define I40E_NVMUPD_MAX_DATA 4096 356 357 struct i40e_nvm_access { 358 u32 command; 359 u32 config; 360 u32 offset; /* in bytes */ 361 u32 data_size; /* in bytes */ 362 u8 data[1]; 363 }; 364 365 /* (Q)SFP module access definitions */ 366 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 367 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 368 #define I40E_MODULE_REVISION_ADDR 0x01 369 #define I40E_MODULE_SFF_8472_COMP 0x5E 370 #define I40E_MODULE_SFF_8472_SWAP 0x5C 371 #define I40E_MODULE_SFF_ADDR_MODE 0x04 372 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40 373 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D 374 #define I40E_MODULE_TYPE_QSFP28 0x11 375 #define I40E_MODULE_QSFP_MAX_LEN 640 376 377 /* PCI bus types */ 378 enum i40e_bus_type { 379 i40e_bus_type_unknown = 0, 380 i40e_bus_type_pci, 381 i40e_bus_type_pcix, 382 i40e_bus_type_pci_express, 383 i40e_bus_type_reserved 384 }; 385 386 /* PCI bus speeds */ 387 enum i40e_bus_speed { 388 i40e_bus_speed_unknown = 0, 389 i40e_bus_speed_33 = 33, 390 i40e_bus_speed_66 = 66, 391 i40e_bus_speed_100 = 100, 392 i40e_bus_speed_120 = 120, 393 i40e_bus_speed_133 = 133, 394 i40e_bus_speed_2500 = 2500, 395 i40e_bus_speed_5000 = 5000, 396 i40e_bus_speed_8000 = 8000, 397 i40e_bus_speed_reserved 398 }; 399 400 /* PCI bus widths */ 401 enum i40e_bus_width { 402 i40e_bus_width_unknown = 0, 403 i40e_bus_width_pcie_x1 = 1, 404 i40e_bus_width_pcie_x2 = 2, 405 i40e_bus_width_pcie_x4 = 4, 406 i40e_bus_width_pcie_x8 = 8, 407 i40e_bus_width_32 = 32, 408 i40e_bus_width_64 = 64, 409 i40e_bus_width_reserved 410 }; 411 412 /* Bus parameters */ 413 struct i40e_bus_info { 414 enum i40e_bus_speed speed; 415 enum i40e_bus_width width; 416 enum i40e_bus_type type; 417 418 u16 func; 419 u16 device; 420 u16 lan_id; 421 u16 bus_id; 422 }; 423 424 /* Flow control (FC) parameters */ 425 struct i40e_fc_info { 426 enum i40e_fc_mode current_mode; /* FC mode in effect */ 427 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 428 }; 429 430 #define I40E_MAX_TRAFFIC_CLASS 8 431 #define I40E_MAX_USER_PRIORITY 8 432 #define I40E_DCBX_MAX_APPS 32 433 #define I40E_LLDPDU_SIZE 1500 434 #define I40E_TLV_STATUS_OPER 0x1 435 #define I40E_TLV_STATUS_SYNC 0x2 436 #define I40E_TLV_STATUS_ERR 0x4 437 #define I40E_CEE_OPER_MAX_APPS 3 438 #define I40E_APP_PROTOID_FCOE 0x8906 439 #define I40E_APP_PROTOID_ISCSI 0x0cbc 440 #define I40E_APP_PROTOID_FIP 0x8914 441 #define I40E_APP_SEL_ETHTYPE 0x1 442 #define I40E_APP_SEL_TCPIP 0x2 443 #define I40E_CEE_APP_SEL_ETHTYPE 0x0 444 #define I40E_CEE_APP_SEL_TCPIP 0x1 445 446 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 447 struct i40e_dcb_ets_config { 448 u8 willing; 449 u8 cbs; 450 u8 maxtcs; 451 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 452 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 453 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 454 }; 455 456 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 457 struct i40e_dcb_pfc_config { 458 u8 willing; 459 u8 mbc; 460 u8 pfccap; 461 u8 pfcenable; 462 }; 463 464 /* CEE or IEEE 802.1Qaz Application Priority data */ 465 struct i40e_dcb_app_priority_table { 466 u8 priority; 467 u8 selector; 468 u16 protocolid; 469 }; 470 471 struct i40e_dcbx_config { 472 u8 dcbx_mode; 473 #define I40E_DCBX_MODE_CEE 0x1 474 #define I40E_DCBX_MODE_IEEE 0x2 475 u8 app_mode; 476 #define I40E_DCBX_APPS_NON_WILLING 0x1 477 u32 numapps; 478 u32 tlv_status; /* CEE mode TLV status */ 479 struct i40e_dcb_ets_config etscfg; 480 struct i40e_dcb_ets_config etsrec; 481 struct i40e_dcb_pfc_config pfc; 482 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 483 }; 484 485 /* Port hardware description */ 486 struct i40e_hw { 487 u8 __iomem *hw_addr; 488 489 /* subsystem structs */ 490 struct i40e_phy_info phy; 491 struct i40e_mac_info mac; 492 struct i40e_bus_info bus; 493 struct i40e_nvm_info nvm; 494 struct i40e_fc_info fc; 495 496 /* PBA ID */ 497 const char *pba_id; 498 499 /* pci info */ 500 u16 device_id; 501 u16 vendor_id; 502 u16 subsystem_device_id; 503 u16 subsystem_vendor_id; 504 u8 revision_id; 505 u8 port; 506 bool adapter_stopped; 507 508 /* capabilities for entire device and PCI func */ 509 struct i40e_hw_capabilities dev_caps; 510 struct i40e_hw_capabilities func_caps; 511 512 /* Flow Director shared filter space */ 513 u16 fdir_shared_filter_count; 514 515 /* device profile info */ 516 u8 pf_id; 517 u16 main_vsi_seid; 518 519 /* for multi-function MACs */ 520 u16 partition_id; 521 u16 num_partitions; 522 u16 num_ports; 523 524 /* Closest numa node to the device */ 525 u16 numa_node; 526 527 /* Admin Queue info */ 528 struct i40e_adminq_info aq; 529 530 /* state of nvm update process */ 531 enum i40e_nvmupd_state nvmupd_state; 532 struct i40e_aq_desc nvm_wb_desc; 533 struct i40e_aq_desc nvm_aq_event_desc; 534 struct i40e_virt_mem nvm_buff; 535 bool nvm_release_on_done; 536 u16 nvm_wait_opcode; 537 538 /* HMC info */ 539 struct i40e_hmc_info hmc; /* HMC info struct */ 540 541 /* LLDP/DCBX Status */ 542 u16 dcbx_status; 543 544 /* DCBX info */ 545 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 546 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 547 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 548 549 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 550 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 551 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 552 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 553 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 554 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5) 555 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6) 556 #define I40E_HW_FLAG_DROP_MODE BIT_ULL(7) 557 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8) 558 u64 flags; 559 560 /* Used in set switch config AQ command */ 561 u16 switch_tag; 562 u16 first_tag; 563 u16 second_tag; 564 565 /* debug mask */ 566 u32 debug_mask; 567 char err_str[16]; 568 }; 569 570 static inline bool i40e_is_vf(struct i40e_hw *hw) 571 { 572 return (hw->mac.type == I40E_MAC_VF || 573 hw->mac.type == I40E_MAC_X722_VF); 574 } 575 576 struct i40e_driver_version { 577 u8 major_version; 578 u8 minor_version; 579 u8 build_version; 580 u8 subbuild_version; 581 u8 driver_string[32]; 582 }; 583 584 /* RX Descriptors */ 585 union i40e_16byte_rx_desc { 586 struct { 587 __le64 pkt_addr; /* Packet buffer address */ 588 __le64 hdr_addr; /* Header buffer address */ 589 } read; 590 struct { 591 struct i40e_16b_rx_wb_qw0 { 592 struct { 593 union { 594 __le16 mirroring_status; 595 __le16 fcoe_ctx_id; 596 } mirr_fcoe; 597 __le16 l2tag1; 598 } lo_dword; 599 union { 600 __le32 rss; /* RSS Hash */ 601 __le32 fd_id; /* Flow director filter id */ 602 __le32 fcoe_param; /* FCoE DDP Context id */ 603 } hi_dword; 604 } qword0; 605 struct { 606 /* ext status/error/pktype/length */ 607 __le64 status_error_len; 608 } qword1; 609 } wb; /* writeback */ 610 struct { 611 u64 qword[2]; 612 } raw; 613 }; 614 615 union i40e_32byte_rx_desc { 616 struct { 617 __le64 pkt_addr; /* Packet buffer address */ 618 __le64 hdr_addr; /* Header buffer address */ 619 /* bit 0 of hdr_buffer_addr is DD bit */ 620 __le64 rsvd1; 621 __le64 rsvd2; 622 } read; 623 struct { 624 struct i40e_32b_rx_wb_qw0 { 625 struct { 626 union { 627 __le16 mirroring_status; 628 __le16 fcoe_ctx_id; 629 } mirr_fcoe; 630 __le16 l2tag1; 631 } lo_dword; 632 union { 633 __le32 rss; /* RSS Hash */ 634 __le32 fcoe_param; /* FCoE DDP Context id */ 635 /* Flow director filter id in case of 636 * Programming status desc WB 637 */ 638 __le32 fd_id; 639 } hi_dword; 640 } qword0; 641 struct { 642 /* status/error/pktype/length */ 643 __le64 status_error_len; 644 } qword1; 645 struct { 646 __le16 ext_status; /* extended status */ 647 __le16 rsvd; 648 __le16 l2tag2_1; 649 __le16 l2tag2_2; 650 } qword2; 651 struct { 652 union { 653 __le32 flex_bytes_lo; 654 __le32 pe_status; 655 } lo_dword; 656 union { 657 __le32 flex_bytes_hi; 658 __le32 fd_id; 659 } hi_dword; 660 } qword3; 661 } wb; /* writeback */ 662 struct { 663 u64 qword[4]; 664 } raw; 665 }; 666 667 enum i40e_rx_desc_status_bits { 668 /* Note: These are predefined bit offsets */ 669 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 670 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 671 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 672 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 673 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 674 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 675 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 676 /* Note: Bit 8 is reserved in X710 and XL710 */ 677 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 678 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 679 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 680 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 681 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 682 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 683 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 684 /* Note: For non-tunnel packets INT_UDP_0 is the right status for 685 * UDP header 686 */ 687 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 688 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 689 }; 690 691 #define I40E_RXD_QW1_STATUS_SHIFT 0 692 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \ 693 << I40E_RXD_QW1_STATUS_SHIFT) 694 695 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 696 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 697 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 698 699 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 700 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \ 701 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 702 703 enum i40e_rx_desc_fltstat_values { 704 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 705 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 706 I40E_RX_DESC_FLTSTAT_RSV = 2, 707 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 708 }; 709 710 #define I40E_RXD_QW1_ERROR_SHIFT 19 711 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 712 713 enum i40e_rx_desc_error_bits { 714 /* Note: These are predefined bit offsets */ 715 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 716 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 717 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 718 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 719 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 720 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 721 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 722 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 723 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 724 }; 725 726 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 727 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 728 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 729 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 730 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 731 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 732 }; 733 734 #define I40E_RXD_QW1_PTYPE_SHIFT 30 735 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 736 737 /* Packet type non-ip values */ 738 enum i40e_rx_l2_ptype { 739 I40E_RX_PTYPE_L2_RESERVED = 0, 740 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 741 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 742 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 743 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 744 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 745 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 746 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 747 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 748 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 749 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 750 I40E_RX_PTYPE_L2_ARP = 11, 751 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 752 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 753 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 754 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 755 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 756 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 757 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 758 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 759 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 760 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 761 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 762 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 763 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 764 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 765 }; 766 767 struct i40e_rx_ptype_decoded { 768 u32 known:1; 769 u32 outer_ip:1; 770 u32 outer_ip_ver:1; 771 u32 outer_frag:1; 772 u32 tunnel_type:3; 773 u32 tunnel_end_prot:2; 774 u32 tunnel_end_frag:1; 775 u32 inner_prot:4; 776 u32 payload_layer:3; 777 }; 778 779 enum i40e_rx_ptype_outer_ip { 780 I40E_RX_PTYPE_OUTER_L2 = 0, 781 I40E_RX_PTYPE_OUTER_IP = 1 782 }; 783 784 enum i40e_rx_ptype_outer_ip_ver { 785 I40E_RX_PTYPE_OUTER_NONE = 0, 786 I40E_RX_PTYPE_OUTER_IPV4 = 0, 787 I40E_RX_PTYPE_OUTER_IPV6 = 1 788 }; 789 790 enum i40e_rx_ptype_outer_fragmented { 791 I40E_RX_PTYPE_NOT_FRAG = 0, 792 I40E_RX_PTYPE_FRAG = 1 793 }; 794 795 enum i40e_rx_ptype_tunnel_type { 796 I40E_RX_PTYPE_TUNNEL_NONE = 0, 797 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 798 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 799 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 800 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 801 }; 802 803 enum i40e_rx_ptype_tunnel_end_prot { 804 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 805 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 806 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 807 }; 808 809 enum i40e_rx_ptype_inner_prot { 810 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 811 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 812 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 813 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 814 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 815 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 816 }; 817 818 enum i40e_rx_ptype_payload_layer { 819 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 820 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 821 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 822 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 823 }; 824 825 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 826 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 827 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 828 829 830 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 831 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 832 833 enum i40e_rx_desc_ext_status_bits { 834 /* Note: These are predefined bit offsets */ 835 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 836 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 837 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 838 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 839 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 840 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 841 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 842 }; 843 844 enum i40e_rx_desc_pe_status_bits { 845 /* Note: These are predefined bit offsets */ 846 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 847 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 848 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 849 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 850 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 851 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 852 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 853 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 854 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 855 }; 856 857 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 858 859 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 860 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 861 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 862 863 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 864 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 865 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 866 867 enum i40e_rx_prog_status_desc_status_bits { 868 /* Note: These are predefined bit offsets */ 869 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 870 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 871 }; 872 873 enum i40e_rx_prog_status_desc_prog_id_masks { 874 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 875 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 876 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 877 }; 878 879 enum i40e_rx_prog_status_desc_error_bits { 880 /* Note: These are predefined bit offsets */ 881 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 882 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 883 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 884 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 885 }; 886 887 /* TX Descriptor */ 888 struct i40e_tx_desc { 889 __le64 buffer_addr; /* Address of descriptor's data buf */ 890 __le64 cmd_type_offset_bsz; 891 }; 892 893 894 enum i40e_tx_desc_dtype_value { 895 I40E_TX_DESC_DTYPE_DATA = 0x0, 896 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 897 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 898 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 899 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 900 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 901 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 902 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 903 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 904 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 905 }; 906 907 #define I40E_TXD_QW1_CMD_SHIFT 4 908 909 enum i40e_tx_desc_cmd_bits { 910 I40E_TX_DESC_CMD_EOP = 0x0001, 911 I40E_TX_DESC_CMD_RS = 0x0002, 912 I40E_TX_DESC_CMD_ICRC = 0x0004, 913 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 914 I40E_TX_DESC_CMD_DUMMY = 0x0010, 915 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 916 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 917 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 918 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 919 I40E_TX_DESC_CMD_FCOET = 0x0080, 920 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 921 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 922 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 923 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 924 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 925 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 926 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 927 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 928 }; 929 930 #define I40E_TXD_QW1_OFFSET_SHIFT 16 931 932 enum i40e_tx_desc_length_fields { 933 /* Note: These are predefined bit offsets */ 934 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 935 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 936 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 937 }; 938 939 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 940 941 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 942 943 /* Context descriptors */ 944 struct i40e_tx_context_desc { 945 __le32 tunneling_params; 946 __le16 l2tag2; 947 __le16 rsvd; 948 __le64 type_cmd_tso_mss; 949 }; 950 951 952 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 953 954 enum i40e_tx_ctx_desc_cmd_bits { 955 I40E_TX_CTX_DESC_TSO = 0x01, 956 I40E_TX_CTX_DESC_TSYN = 0x02, 957 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 958 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 959 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 960 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 961 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 962 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 963 I40E_TX_CTX_DESC_SWPE = 0x40 964 }; 965 966 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 967 968 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 969 970 971 972 enum i40e_tx_ctx_desc_eipt_offload { 973 I40E_TX_CTX_EXT_IP_NONE = 0x0, 974 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 975 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 976 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 977 }; 978 979 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 980 981 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 982 983 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 984 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 985 986 987 988 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 989 990 991 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 992 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 993 struct i40e_filter_program_desc { 994 __le32 qindex_flex_ptype_vsi; 995 __le32 rsvd; 996 __le32 dtype_cmd_cntindex; 997 __le32 fd_id; 998 }; 999 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1000 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1001 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1002 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1003 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1004 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1005 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1006 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1007 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1008 1009 /* Packet Classifier Types for filters */ 1010 enum i40e_filter_pctype { 1011 /* Note: Values 0-28 are reserved for future use. 1012 * Value 29, 30, 32 are not supported on XL710 and X710. 1013 */ 1014 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 1015 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 1016 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1017 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 1018 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1019 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1020 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1021 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1022 /* Note: Values 37-38 are reserved for future use. 1023 * Value 39, 40, 42 are not supported on XL710 and X710. 1024 */ 1025 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 1026 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 1027 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1028 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 1029 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1030 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1031 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1032 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1033 /* Note: Value 47 is reserved for future use */ 1034 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1035 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1036 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1037 /* Note: Values 51-62 are reserved for future use */ 1038 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1039 }; 1040 1041 enum i40e_filter_program_desc_dest { 1042 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1043 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1044 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1045 }; 1046 1047 enum i40e_filter_program_desc_fd_status { 1048 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1049 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1050 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1051 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1052 }; 1053 1054 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1055 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1056 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1057 1058 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1059 1060 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1061 1062 enum i40e_filter_program_desc_pcmd { 1063 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1064 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1065 }; 1066 1067 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1068 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1069 1070 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1071 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1072 1073 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1074 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1075 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1076 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1077 1078 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1079 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1080 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1081 1082 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1083 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1084 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1085 1086 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1087 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1088 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1089 1090 enum i40e_filter_type { 1091 I40E_FLOW_DIRECTOR_FLTR = 0, 1092 I40E_PE_QUAD_HASH_FLTR = 1, 1093 I40E_ETHERTYPE_FLTR, 1094 I40E_FCOE_CTX_FLTR, 1095 I40E_MAC_VLAN_FLTR, 1096 I40E_HASH_FLTR 1097 }; 1098 1099 struct i40e_vsi_context { 1100 u16 seid; 1101 u16 uplink_seid; 1102 u16 vsi_number; 1103 u16 vsis_allocated; 1104 u16 vsis_unallocated; 1105 u16 flags; 1106 u8 pf_num; 1107 u8 vf_num; 1108 u8 connection_type; 1109 struct i40e_aqc_vsi_properties_data info; 1110 }; 1111 1112 struct i40e_veb_context { 1113 u16 seid; 1114 u16 uplink_seid; 1115 u16 veb_number; 1116 u16 vebs_allocated; 1117 u16 vebs_unallocated; 1118 u16 flags; 1119 struct i40e_aqc_get_veb_parameters_completion info; 1120 }; 1121 1122 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1123 struct i40e_eth_stats { 1124 u64 rx_bytes; /* gorc */ 1125 u64 rx_unicast; /* uprc */ 1126 u64 rx_multicast; /* mprc */ 1127 u64 rx_broadcast; /* bprc */ 1128 u64 rx_discards; /* rdpc */ 1129 u64 rx_unknown_protocol; /* rupp */ 1130 u64 tx_bytes; /* gotc */ 1131 u64 tx_unicast; /* uptc */ 1132 u64 tx_multicast; /* mptc */ 1133 u64 tx_broadcast; /* bptc */ 1134 u64 tx_discards; /* tdpc */ 1135 u64 tx_errors; /* tepc */ 1136 u64 rx_discards_other; /* rxerr1 */ 1137 }; 1138 1139 /* Statistics collected per VEB per TC */ 1140 struct i40e_veb_tc_stats { 1141 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1142 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1143 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1144 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1145 }; 1146 1147 /* Statistics collected by the MAC */ 1148 struct i40e_hw_port_stats { 1149 /* eth stats collected by the port */ 1150 struct i40e_eth_stats eth; 1151 1152 /* additional port specific stats */ 1153 u64 tx_dropped_link_down; /* tdold */ 1154 u64 crc_errors; /* crcerrs */ 1155 u64 illegal_bytes; /* illerrc */ 1156 u64 error_bytes; /* errbc */ 1157 u64 mac_local_faults; /* mlfc */ 1158 u64 mac_remote_faults; /* mrfc */ 1159 u64 rx_length_errors; /* rlec */ 1160 u64 link_xon_rx; /* lxonrxc */ 1161 u64 link_xoff_rx; /* lxoffrxc */ 1162 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1163 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1164 u64 link_xon_tx; /* lxontxc */ 1165 u64 link_xoff_tx; /* lxofftxc */ 1166 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1167 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1168 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1169 u64 rx_size_64; /* prc64 */ 1170 u64 rx_size_127; /* prc127 */ 1171 u64 rx_size_255; /* prc255 */ 1172 u64 rx_size_511; /* prc511 */ 1173 u64 rx_size_1023; /* prc1023 */ 1174 u64 rx_size_1522; /* prc1522 */ 1175 u64 rx_size_big; /* prc9522 */ 1176 u64 rx_undersize; /* ruc */ 1177 u64 rx_fragments; /* rfc */ 1178 u64 rx_oversize; /* roc */ 1179 u64 rx_jabber; /* rjc */ 1180 u64 tx_size_64; /* ptc64 */ 1181 u64 tx_size_127; /* ptc127 */ 1182 u64 tx_size_255; /* ptc255 */ 1183 u64 tx_size_511; /* ptc511 */ 1184 u64 tx_size_1023; /* ptc1023 */ 1185 u64 tx_size_1522; /* ptc1522 */ 1186 u64 tx_size_big; /* ptc9522 */ 1187 u64 mac_short_packet_dropped; /* mspdc */ 1188 u64 checksum_error; /* xec */ 1189 /* flow director stats */ 1190 u64 fd_atr_match; 1191 u64 fd_sb_match; 1192 u64 fd_atr_tunnel_match; 1193 u32 fd_atr_status; 1194 u32 fd_sb_status; 1195 /* EEE LPI */ 1196 u32 tx_lpi_status; 1197 u32 rx_lpi_status; 1198 u64 tx_lpi_count; /* etlpic */ 1199 u64 rx_lpi_count; /* erlpic */ 1200 }; 1201 1202 /* Checksum and Shadow RAM pointers */ 1203 #define I40E_SR_NVM_CONTROL_WORD 0x00 1204 #define I40E_EMP_MODULE_PTR 0x0F 1205 #define I40E_SR_EMP_MODULE_PTR 0x48 1206 #define I40E_SR_PBA_FLAGS 0x15 1207 #define I40E_SR_PBA_BLOCK_PTR 0x16 1208 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1209 #define I40E_NVM_OEM_VER_OFF 0x83 1210 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1211 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1212 #define I40E_SR_NVM_EETRACK_LO 0x2D 1213 #define I40E_SR_NVM_EETRACK_HI 0x2E 1214 #define I40E_SR_VPD_PTR 0x2F 1215 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1216 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1217 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1218 1219 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1220 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1221 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1222 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1223 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1224 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1225 #define I40E_PTR_TYPE BIT(15) 1226 #define I40E_SR_OCP_CFG_WORD0 0x2B 1227 #define I40E_SR_OCP_ENABLED BIT(15) 1228 1229 /* Shadow RAM related */ 1230 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1231 #define I40E_SR_WORDS_IN_1KB 512 1232 /* Checksum should be calculated such that after adding all the words, 1233 * including the checksum word itself, the sum should be 0xBABA. 1234 */ 1235 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1236 1237 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1238 1239 enum i40e_switch_element_types { 1240 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1241 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1242 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1243 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1244 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1245 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1246 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1247 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1248 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1249 }; 1250 1251 /* Supported EtherType filters */ 1252 enum i40e_ether_type_index { 1253 I40E_ETHER_TYPE_1588 = 0, 1254 I40E_ETHER_TYPE_FIP = 1, 1255 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1256 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1257 I40E_ETHER_TYPE_LLDP = 4, 1258 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1259 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1260 I40E_ETHER_TYPE_QCN_CNM = 7, 1261 I40E_ETHER_TYPE_8021X = 8, 1262 I40E_ETHER_TYPE_ARP = 9, 1263 I40E_ETHER_TYPE_RSV1 = 10, 1264 I40E_ETHER_TYPE_RSV2 = 11, 1265 }; 1266 1267 /* Filter context base size is 1K */ 1268 #define I40E_HASH_FILTER_BASE_SIZE 1024 1269 /* Supported Hash filter values */ 1270 enum i40e_hash_filter_size { 1271 I40E_HASH_FILTER_SIZE_1K = 0, 1272 I40E_HASH_FILTER_SIZE_2K = 1, 1273 I40E_HASH_FILTER_SIZE_4K = 2, 1274 I40E_HASH_FILTER_SIZE_8K = 3, 1275 I40E_HASH_FILTER_SIZE_16K = 4, 1276 I40E_HASH_FILTER_SIZE_32K = 5, 1277 I40E_HASH_FILTER_SIZE_64K = 6, 1278 I40E_HASH_FILTER_SIZE_128K = 7, 1279 I40E_HASH_FILTER_SIZE_256K = 8, 1280 I40E_HASH_FILTER_SIZE_512K = 9, 1281 I40E_HASH_FILTER_SIZE_1M = 10, 1282 }; 1283 1284 /* DMA context base size is 0.5K */ 1285 #define I40E_DMA_CNTX_BASE_SIZE 512 1286 /* Supported DMA context values */ 1287 enum i40e_dma_cntx_size { 1288 I40E_DMA_CNTX_SIZE_512 = 0, 1289 I40E_DMA_CNTX_SIZE_1K = 1, 1290 I40E_DMA_CNTX_SIZE_2K = 2, 1291 I40E_DMA_CNTX_SIZE_4K = 3, 1292 I40E_DMA_CNTX_SIZE_8K = 4, 1293 I40E_DMA_CNTX_SIZE_16K = 5, 1294 I40E_DMA_CNTX_SIZE_32K = 6, 1295 I40E_DMA_CNTX_SIZE_64K = 7, 1296 I40E_DMA_CNTX_SIZE_128K = 8, 1297 I40E_DMA_CNTX_SIZE_256K = 9, 1298 }; 1299 1300 /* Supported Hash look up table (LUT) sizes */ 1301 enum i40e_hash_lut_size { 1302 I40E_HASH_LUT_SIZE_128 = 0, 1303 I40E_HASH_LUT_SIZE_512 = 1, 1304 }; 1305 1306 /* Structure to hold a per PF filter control settings */ 1307 struct i40e_filter_control_settings { 1308 /* number of PE Quad Hash filter buckets */ 1309 enum i40e_hash_filter_size pe_filt_num; 1310 /* number of PE Quad Hash contexts */ 1311 enum i40e_dma_cntx_size pe_cntx_num; 1312 /* number of FCoE filter buckets */ 1313 enum i40e_hash_filter_size fcoe_filt_num; 1314 /* number of FCoE DDP contexts */ 1315 enum i40e_dma_cntx_size fcoe_cntx_num; 1316 /* size of the Hash LUT */ 1317 enum i40e_hash_lut_size hash_lut_size; 1318 /* enable FDIR filters for PF and its VFs */ 1319 bool enable_fdir; 1320 /* enable Ethertype filters for PF and its VFs */ 1321 bool enable_ethtype; 1322 /* enable MAC/VLAN filters for PF and its VFs */ 1323 bool enable_macvlan; 1324 }; 1325 1326 /* Structure to hold device level control filter counts */ 1327 struct i40e_control_filter_stats { 1328 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1329 u16 etype_used; /* Used perfect EtherType filters */ 1330 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1331 u16 etype_free; /* Un-used perfect EtherType filters */ 1332 }; 1333 1334 enum i40e_reset_type { 1335 I40E_RESET_POR = 0, 1336 I40E_RESET_CORER = 1, 1337 I40E_RESET_GLOBR = 2, 1338 I40E_RESET_EMPR = 3, 1339 }; 1340 1341 /* IEEE 802.1AB LLDP Agent Variables from NVM */ 1342 #define I40E_NVM_LLDP_CFG_PTR 0x06 1343 #define I40E_SR_LLDP_CFG_PTR 0x31 1344 struct i40e_lldp_variables { 1345 u16 length; 1346 u16 adminstatus; 1347 u16 msgfasttx; 1348 u16 msgtxinterval; 1349 u16 txparams; 1350 u16 timers; 1351 u16 crc8; 1352 }; 1353 1354 /* Offsets into Alternate Ram */ 1355 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1356 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1357 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1358 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1359 1360 /* Alternate Ram Bandwidth Masks */ 1361 #define I40E_ALT_BW_VALUE_MASK 0xFF 1362 #define I40E_ALT_BW_VALID_MASK 0x80000000 1363 1364 /* RSS Hash Table Size */ 1365 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1366 1367 /* INPUT SET MASK for RSS, flow director, and flexible payload */ 1368 #define I40E_X722_L3_SRC_SHIFT 49 1369 #define I40E_X722_L3_SRC_MASK (0x3ULL << I40E_X722_L3_SRC_SHIFT) 1370 #define I40E_X722_L3_DST_SHIFT 41 1371 #define I40E_X722_L3_DST_MASK (0x3ULL << I40E_X722_L3_DST_SHIFT) 1372 #define I40E_L3_SRC_SHIFT 47 1373 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) 1374 #define I40E_L3_V6_SRC_SHIFT 43 1375 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT) 1376 #define I40E_L3_DST_SHIFT 35 1377 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT) 1378 #define I40E_L3_V6_DST_SHIFT 35 1379 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) 1380 #define I40E_L4_SRC_SHIFT 34 1381 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) 1382 #define I40E_L4_DST_SHIFT 33 1383 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) 1384 #define I40E_VERIFY_TAG_SHIFT 31 1385 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) 1386 #define I40E_VLAN_SRC_SHIFT 55 1387 #define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT) 1388 1389 #define I40E_FLEX_50_SHIFT 13 1390 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) 1391 #define I40E_FLEX_51_SHIFT 12 1392 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) 1393 #define I40E_FLEX_52_SHIFT 11 1394 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) 1395 #define I40E_FLEX_53_SHIFT 10 1396 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT) 1397 #define I40E_FLEX_54_SHIFT 9 1398 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1399 #define I40E_FLEX_55_SHIFT 8 1400 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1401 #define I40E_FLEX_56_SHIFT 7 1402 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1403 #define I40E_FLEX_57_SHIFT 6 1404 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) 1405 1406 /* Version format for Dynamic Device Personalization(DDP) */ 1407 struct i40e_ddp_version { 1408 u8 major; 1409 u8 minor; 1410 u8 update; 1411 u8 draft; 1412 }; 1413 1414 #define I40E_DDP_NAME_SIZE 32 1415 1416 /* Package header */ 1417 struct i40e_package_header { 1418 struct i40e_ddp_version version; 1419 u32 segment_count; 1420 u32 segment_offset[]; 1421 }; 1422 1423 /* Generic segment header */ 1424 struct i40e_generic_seg_header { 1425 #define SEGMENT_TYPE_METADATA 0x00000001 1426 #define SEGMENT_TYPE_I40E 0x00000011 1427 u32 type; 1428 struct i40e_ddp_version version; 1429 u32 size; 1430 char name[I40E_DDP_NAME_SIZE]; 1431 }; 1432 1433 struct i40e_metadata_segment { 1434 struct i40e_generic_seg_header header; 1435 struct i40e_ddp_version version; 1436 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF 1437 u32 track_id; 1438 char name[I40E_DDP_NAME_SIZE]; 1439 }; 1440 1441 struct i40e_device_id_entry { 1442 u32 vendor_dev_id; 1443 u32 sub_vendor_dev_id; 1444 }; 1445 1446 struct i40e_profile_segment { 1447 struct i40e_generic_seg_header header; 1448 struct i40e_ddp_version version; 1449 char name[I40E_DDP_NAME_SIZE]; 1450 u32 device_table_count; 1451 struct i40e_device_id_entry device_table[]; 1452 }; 1453 1454 struct i40e_section_table { 1455 u32 section_count; 1456 u32 section_offset[]; 1457 }; 1458 1459 struct i40e_profile_section_header { 1460 u16 tbl_size; 1461 u16 data_end; 1462 struct { 1463 #define SECTION_TYPE_INFO 0x00000010 1464 #define SECTION_TYPE_MMIO 0x00000800 1465 #define SECTION_TYPE_RB_MMIO 0x00001800 1466 #define SECTION_TYPE_AQ 0x00000801 1467 #define SECTION_TYPE_RB_AQ 0x00001801 1468 #define SECTION_TYPE_NOTE 0x80000000 1469 u32 type; 1470 u32 offset; 1471 u32 size; 1472 } section; 1473 }; 1474 1475 struct i40e_profile_tlv_section_record { 1476 u8 rtype; 1477 u8 type; 1478 u16 len; 1479 u8 data[12]; 1480 }; 1481 1482 /* Generic AQ section in proflie */ 1483 struct i40e_profile_aq_section { 1484 u16 opcode; 1485 u16 flags; 1486 u8 param[16]; 1487 u16 datalen; 1488 u8 data[]; 1489 }; 1490 1491 struct i40e_profile_info { 1492 u32 track_id; 1493 struct i40e_ddp_version version; 1494 u8 op; 1495 #define I40E_DDP_ADD_TRACKID 0x01 1496 #define I40E_DDP_REMOVE_TRACKID 0x02 1497 u8 reserved[7]; 1498 u8 name[I40E_DDP_NAME_SIZE]; 1499 }; 1500 #endif /* _I40E_TYPE_H_ */ 1501