1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _IAVF_TYPE_H_ 5 #define _IAVF_TYPE_H_ 6 7 #include "iavf_status.h" 8 #include "iavf_osdep.h" 9 #include "iavf_register.h" 10 #include "iavf_adminq.h" 11 #include "iavf_devids.h" 12 13 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7 14 15 /* IAVF_MASK is a macro used on 32 bit registers */ 16 #define IAVF_MASK(mask, shift) ((u32)(mask) << (shift)) 17 18 #define IAVF_MAX_VSI_QP 16 19 #define IAVF_MAX_VF_VSI 3 20 #define IAVF_MAX_CHAINED_RX_BUFFERS 5 21 22 /* forward declaration */ 23 struct iavf_hw; 24 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 25 26 /* Data type manipulation macros. */ 27 28 #define IAVF_DESC_UNUSED(R) \ 29 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 30 (R)->next_to_clean - (R)->next_to_use - 1) 31 32 /* bitfields for Tx queue mapping in QTX_CTL */ 33 #define IAVF_QTX_CTL_VF_QUEUE 0x0 34 #define IAVF_QTX_CTL_VM_QUEUE 0x1 35 #define IAVF_QTX_CTL_PF_QUEUE 0x2 36 37 /* debug masks - set these bits in hw->debug_mask to control output */ 38 enum iavf_debug_mask { 39 IAVF_DEBUG_INIT = 0x00000001, 40 IAVF_DEBUG_RELEASE = 0x00000002, 41 42 IAVF_DEBUG_LINK = 0x00000010, 43 IAVF_DEBUG_PHY = 0x00000020, 44 IAVF_DEBUG_HMC = 0x00000040, 45 IAVF_DEBUG_NVM = 0x00000080, 46 IAVF_DEBUG_LAN = 0x00000100, 47 IAVF_DEBUG_FLOW = 0x00000200, 48 IAVF_DEBUG_DCB = 0x00000400, 49 IAVF_DEBUG_DIAG = 0x00000800, 50 IAVF_DEBUG_FD = 0x00001000, 51 IAVF_DEBUG_PACKAGE = 0x00002000, 52 53 IAVF_DEBUG_AQ_MESSAGE = 0x01000000, 54 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000, 55 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000, 56 IAVF_DEBUG_AQ_COMMAND = 0x06000000, 57 IAVF_DEBUG_AQ = 0x0F000000, 58 59 IAVF_DEBUG_USER = 0xF0000000, 60 61 IAVF_DEBUG_ALL = 0xFFFFFFFF 62 }; 63 64 /* These are structs for managing the hardware information and the operations. 65 * The structures of function pointers are filled out at init time when we 66 * know for sure exactly which hardware we're working with. This gives us the 67 * flexibility of using the same main driver code but adapting to slightly 68 * different hardware needs as new parts are developed. For this architecture, 69 * the Firmware and AdminQ are intended to insulate the driver from most of the 70 * future changes, but these structures will also do part of the job. 71 */ 72 enum iavf_vsi_type { 73 IAVF_VSI_MAIN = 0, 74 IAVF_VSI_VMDQ1 = 1, 75 IAVF_VSI_VMDQ2 = 2, 76 IAVF_VSI_CTRL = 3, 77 IAVF_VSI_FCOE = 4, 78 IAVF_VSI_MIRROR = 5, 79 IAVF_VSI_SRIOV = 6, 80 IAVF_VSI_FDIR = 7, 81 IAVF_VSI_TYPE_UNKNOWN 82 }; 83 84 enum iavf_queue_type { 85 IAVF_QUEUE_TYPE_RX = 0, 86 IAVF_QUEUE_TYPE_TX, 87 IAVF_QUEUE_TYPE_PE_CEQ, 88 IAVF_QUEUE_TYPE_UNKNOWN 89 }; 90 91 #define IAVF_HW_CAP_MAX_GPIO 30 92 /* Capabilities of a PF or a VF or the whole device */ 93 struct iavf_hw_capabilities { 94 bool dcb; 95 bool fcoe; 96 u32 num_vsis; 97 u32 num_rx_qp; 98 u32 num_tx_qp; 99 u32 base_queue; 100 u32 num_msix_vectors_vf; 101 }; 102 103 struct iavf_mac_info { 104 u8 addr[ETH_ALEN]; 105 u8 perm_addr[ETH_ALEN]; 106 }; 107 108 /* PCI bus types */ 109 enum iavf_bus_type { 110 iavf_bus_type_unknown = 0, 111 iavf_bus_type_pci, 112 iavf_bus_type_pcix, 113 iavf_bus_type_pci_express, 114 iavf_bus_type_reserved 115 }; 116 117 /* PCI bus speeds */ 118 enum iavf_bus_speed { 119 iavf_bus_speed_unknown = 0, 120 iavf_bus_speed_33 = 33, 121 iavf_bus_speed_66 = 66, 122 iavf_bus_speed_100 = 100, 123 iavf_bus_speed_120 = 120, 124 iavf_bus_speed_133 = 133, 125 iavf_bus_speed_2500 = 2500, 126 iavf_bus_speed_5000 = 5000, 127 iavf_bus_speed_8000 = 8000, 128 iavf_bus_speed_reserved 129 }; 130 131 /* PCI bus widths */ 132 enum iavf_bus_width { 133 iavf_bus_width_unknown = 0, 134 iavf_bus_width_pcie_x1 = 1, 135 iavf_bus_width_pcie_x2 = 2, 136 iavf_bus_width_pcie_x4 = 4, 137 iavf_bus_width_pcie_x8 = 8, 138 iavf_bus_width_32 = 32, 139 iavf_bus_width_64 = 64, 140 iavf_bus_width_reserved 141 }; 142 143 /* Bus parameters */ 144 struct iavf_bus_info { 145 enum iavf_bus_speed speed; 146 enum iavf_bus_width width; 147 enum iavf_bus_type type; 148 149 u16 func; 150 u16 device; 151 u16 lan_id; 152 u16 bus_id; 153 }; 154 155 #define IAVF_MAX_USER_PRIORITY 8 156 /* Port hardware description */ 157 struct iavf_hw { 158 u8 __iomem *hw_addr; 159 void *back; 160 161 /* subsystem structs */ 162 struct iavf_mac_info mac; 163 struct iavf_bus_info bus; 164 165 /* pci info */ 166 u16 device_id; 167 u16 vendor_id; 168 u16 subsystem_device_id; 169 u16 subsystem_vendor_id; 170 u8 revision_id; 171 172 /* capabilities for entire device and PCI func */ 173 struct iavf_hw_capabilities dev_caps; 174 175 /* Admin Queue info */ 176 struct iavf_adminq_info aq; 177 178 /* debug mask */ 179 u32 debug_mask; 180 char err_str[16]; 181 }; 182 183 /* RX Descriptors */ 184 union iavf_16byte_rx_desc { 185 struct { 186 __le64 pkt_addr; /* Packet buffer address */ 187 __le64 hdr_addr; /* Header buffer address */ 188 } read; 189 struct { 190 struct { 191 struct { 192 union { 193 __le16 mirroring_status; 194 __le16 fcoe_ctx_id; 195 } mirr_fcoe; 196 __le16 l2tag1; 197 } lo_dword; 198 union { 199 __le32 rss; /* RSS Hash */ 200 __le32 fd_id; /* Flow director filter id */ 201 __le32 fcoe_param; /* FCoE DDP Context id */ 202 } hi_dword; 203 } qword0; 204 struct { 205 /* ext status/error/pktype/length */ 206 __le64 status_error_len; 207 } qword1; 208 } wb; /* writeback */ 209 }; 210 211 union iavf_32byte_rx_desc { 212 struct { 213 __le64 pkt_addr; /* Packet buffer address */ 214 __le64 hdr_addr; /* Header buffer address */ 215 /* bit 0 of hdr_buffer_addr is DD bit */ 216 __le64 rsvd1; 217 __le64 rsvd2; 218 } read; 219 struct { 220 struct { 221 struct { 222 union { 223 __le16 mirroring_status; 224 __le16 fcoe_ctx_id; 225 } mirr_fcoe; 226 __le16 l2tag1; 227 } lo_dword; 228 union { 229 __le32 rss; /* RSS Hash */ 230 __le32 fcoe_param; /* FCoE DDP Context id */ 231 /* Flow director filter id in case of 232 * Programming status desc WB 233 */ 234 __le32 fd_id; 235 } hi_dword; 236 } qword0; 237 struct { 238 /* status/error/pktype/length */ 239 __le64 status_error_len; 240 } qword1; 241 struct { 242 __le16 ext_status; /* extended status */ 243 __le16 rsvd; 244 __le16 l2tag2_1; 245 __le16 l2tag2_2; 246 } qword2; 247 struct { 248 union { 249 __le32 flex_bytes_lo; 250 __le32 pe_status; 251 } lo_dword; 252 union { 253 __le32 flex_bytes_hi; 254 __le32 fd_id; 255 } hi_dword; 256 } qword3; 257 } wb; /* writeback */ 258 }; 259 260 enum iavf_rx_desc_status_bits { 261 /* Note: These are predefined bit offsets */ 262 IAVF_RX_DESC_STATUS_DD_SHIFT = 0, 263 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1, 264 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 265 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3, 266 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4, 267 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 268 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 269 /* Note: Bit 8 is reserved in X710 and XL710 */ 270 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 271 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 272 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11, 273 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 274 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14, 275 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 276 IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 277 /* Note: For non-tunnel packets INT_UDP_0 is the right status for 278 * UDP header 279 */ 280 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 281 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 282 }; 283 284 #define IAVF_RXD_QW1_STATUS_SHIFT 0 285 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ 286 << IAVF_RXD_QW1_STATUS_SHIFT) 287 288 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT 289 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 290 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT) 291 292 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT 293 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK \ 294 BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT) 295 296 enum iavf_rx_desc_fltstat_values { 297 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0, 298 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 299 IAVF_RX_DESC_FLTSTAT_RSV = 2, 300 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3, 301 }; 302 303 #define IAVF_RXD_QW1_ERROR_SHIFT 19 304 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT) 305 306 enum iavf_rx_desc_error_bits { 307 /* Note: These are predefined bit offsets */ 308 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0, 309 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1, 310 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2, 311 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 312 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3, 313 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4, 314 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5, 315 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 316 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7 317 }; 318 319 enum iavf_rx_desc_error_l3l4e_fcoe_masks { 320 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0, 321 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1, 322 IAVF_RX_DESC_ERROR_L3L4E_FC = 2, 323 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 324 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 325 }; 326 327 #define IAVF_RXD_QW1_PTYPE_SHIFT 30 328 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT) 329 330 /* Packet type non-ip values */ 331 enum iavf_rx_l2_ptype { 332 IAVF_RX_PTYPE_L2_RESERVED = 0, 333 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1, 334 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 335 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3, 336 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4, 337 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 338 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6, 339 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7, 340 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8, 341 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9, 342 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10, 343 IAVF_RX_PTYPE_L2_ARP = 11, 344 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12, 345 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 346 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 347 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 348 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 349 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 350 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 351 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 352 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 353 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 354 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 355 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 356 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 357 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 358 }; 359 360 struct iavf_rx_ptype_decoded { 361 u32 known:1; 362 u32 outer_ip:1; 363 u32 outer_ip_ver:1; 364 u32 outer_frag:1; 365 u32 tunnel_type:3; 366 u32 tunnel_end_prot:2; 367 u32 tunnel_end_frag:1; 368 u32 inner_prot:4; 369 u32 payload_layer:3; 370 }; 371 372 enum iavf_rx_ptype_outer_ip { 373 IAVF_RX_PTYPE_OUTER_L2 = 0, 374 IAVF_RX_PTYPE_OUTER_IP = 1 375 }; 376 377 enum iavf_rx_ptype_outer_ip_ver { 378 IAVF_RX_PTYPE_OUTER_NONE = 0, 379 IAVF_RX_PTYPE_OUTER_IPV4 = 0, 380 IAVF_RX_PTYPE_OUTER_IPV6 = 1 381 }; 382 383 enum iavf_rx_ptype_outer_fragmented { 384 IAVF_RX_PTYPE_NOT_FRAG = 0, 385 IAVF_RX_PTYPE_FRAG = 1 386 }; 387 388 enum iavf_rx_ptype_tunnel_type { 389 IAVF_RX_PTYPE_TUNNEL_NONE = 0, 390 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1, 391 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 392 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 393 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 394 }; 395 396 enum iavf_rx_ptype_tunnel_end_prot { 397 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0, 398 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1, 399 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2, 400 }; 401 402 enum iavf_rx_ptype_inner_prot { 403 IAVF_RX_PTYPE_INNER_PROT_NONE = 0, 404 IAVF_RX_PTYPE_INNER_PROT_UDP = 1, 405 IAVF_RX_PTYPE_INNER_PROT_TCP = 2, 406 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3, 407 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4, 408 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5 409 }; 410 411 enum iavf_rx_ptype_payload_layer { 412 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 413 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 414 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 415 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 416 }; 417 418 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38 419 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 420 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) 421 422 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52 423 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 424 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT) 425 426 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63 427 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT) 428 429 enum iavf_rx_desc_ext_status_bits { 430 /* Note: These are predefined bit offsets */ 431 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 432 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 433 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 434 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 435 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 436 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 437 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 438 }; 439 440 enum iavf_rx_desc_pe_status_bits { 441 /* Note: These are predefined bit offsets */ 442 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 443 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 444 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 445 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 446 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 447 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 448 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27, 449 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 450 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 451 }; 452 453 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 454 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000 455 456 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 457 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 458 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 459 460 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 461 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 462 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 463 464 enum iavf_rx_prog_status_desc_status_bits { 465 /* Note: These are predefined bit offsets */ 466 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 467 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 468 }; 469 470 enum iavf_rx_prog_status_desc_prog_id_masks { 471 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 472 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 473 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 474 }; 475 476 enum iavf_rx_prog_status_desc_error_bits { 477 /* Note: These are predefined bit offsets */ 478 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 479 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 480 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 481 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 482 }; 483 484 /* TX Descriptor */ 485 struct iavf_tx_desc { 486 __le64 buffer_addr; /* Address of descriptor's data buf */ 487 __le64 cmd_type_offset_bsz; 488 }; 489 490 #define IAVF_TXD_QW1_DTYPE_SHIFT 0 491 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT) 492 493 enum iavf_tx_desc_dtype_value { 494 IAVF_TX_DESC_DTYPE_DATA = 0x0, 495 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 496 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1, 497 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2, 498 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8, 499 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9, 500 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB, 501 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 502 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 503 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF 504 }; 505 506 #define IAVF_TXD_QW1_CMD_SHIFT 4 507 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT) 508 509 enum iavf_tx_desc_cmd_bits { 510 IAVF_TX_DESC_CMD_EOP = 0x0001, 511 IAVF_TX_DESC_CMD_RS = 0x0002, 512 IAVF_TX_DESC_CMD_ICRC = 0x0004, 513 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008, 514 IAVF_TX_DESC_CMD_DUMMY = 0x0010, 515 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 516 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 517 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 518 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 519 IAVF_TX_DESC_CMD_FCOET = 0x0080, 520 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 521 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 522 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 523 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 524 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 525 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 526 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 527 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 528 }; 529 530 #define IAVF_TXD_QW1_OFFSET_SHIFT 16 531 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 532 IAVF_TXD_QW1_OFFSET_SHIFT) 533 534 enum iavf_tx_desc_length_fields { 535 /* Note: These are predefined bit offsets */ 536 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 537 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 538 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 539 }; 540 541 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34 542 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 543 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) 544 545 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48 546 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT) 547 548 /* Context descriptors */ 549 struct iavf_tx_context_desc { 550 __le32 tunneling_params; 551 __le16 l2tag2; 552 __le16 rsvd; 553 __le64 type_cmd_tso_mss; 554 }; 555 556 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4 557 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT) 558 559 enum iavf_tx_ctx_desc_cmd_bits { 560 IAVF_TX_CTX_DESC_TSO = 0x01, 561 IAVF_TX_CTX_DESC_TSYN = 0x02, 562 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04, 563 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 564 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 565 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 566 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 567 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30, 568 IAVF_TX_CTX_DESC_SWPE = 0x40 569 }; 570 571 /* Packet Classifier Types for filters */ 572 enum iavf_filter_pctype { 573 /* Note: Values 0-28 are reserved for future use. 574 * Value 29, 30, 32 are not supported on XL710 and X710. 575 */ 576 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 577 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 578 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 579 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 580 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 581 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 582 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 583 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36, 584 /* Note: Values 37-38 are reserved for future use. 585 * Value 39, 40, 42 are not supported on XL710 and X710. 586 */ 587 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 588 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 589 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 590 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 591 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 592 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 593 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 594 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46, 595 /* Note: Value 47 is reserved for future use */ 596 IAVF_FILTER_PCTYPE_FCOE_OX = 48, 597 IAVF_FILTER_PCTYPE_FCOE_RX = 49, 598 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50, 599 /* Note: Values 51-62 are reserved for future use */ 600 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63, 601 }; 602 603 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30 604 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 605 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) 606 607 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50 608 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 609 IAVF_TXD_CTX_QW1_MSS_SHIFT) 610 611 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50 612 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT) 613 614 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0 615 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 616 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT) 617 618 enum iavf_tx_ctx_desc_eipt_offload { 619 IAVF_TX_CTX_EXT_IP_NONE = 0x0, 620 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1, 621 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 622 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3 623 }; 624 625 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 626 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 627 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 628 629 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9 630 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 631 632 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT) 633 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 634 635 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 636 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \ 637 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT) 638 639 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK 640 641 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12 642 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 643 IAVF_TXD_CTX_QW0_NATLEN_SHIFT) 644 645 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19 646 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 647 IAVF_TXD_CTX_QW0_DECTTL_SHIFT) 648 649 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23 650 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT) 651 652 /* Statistics collected by each port, VSI, VEB, and S-channel */ 653 struct iavf_eth_stats { 654 u64 rx_bytes; /* gorc */ 655 u64 rx_unicast; /* uprc */ 656 u64 rx_multicast; /* mprc */ 657 u64 rx_broadcast; /* bprc */ 658 u64 rx_discards; /* rdpc */ 659 u64 rx_unknown_protocol; /* rupp */ 660 u64 tx_bytes; /* gotc */ 661 u64 tx_unicast; /* uptc */ 662 u64 tx_multicast; /* mptc */ 663 u64 tx_broadcast; /* bptc */ 664 u64 tx_discards; /* tdpc */ 665 u64 tx_errors; /* tepc */ 666 }; 667 #endif /* _IAVF_TYPE_H_ */ 668