1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 *******************************************************************************/ 26 27 #ifndef _E1000_82575_H_ 28 #define _E1000_82575_H_ 29 30 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw); 31 void igb_power_up_serdes_link_82575(struct e1000_hw *hw); 32 void igb_power_down_phy_copper_82575(struct e1000_hw *hw); 33 void igb_rx_fifo_flush_82575(struct e1000_hw *hw); 34 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr, 35 u8 *data); 36 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr, 37 u8 data); 38 39 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 40 (ID_LED_DEF1_DEF2 << 8) | \ 41 (ID_LED_DEF1_DEF2 << 4) | \ 42 (ID_LED_OFF1_ON2)) 43 44 #define E1000_RAR_ENTRIES_82575 16 45 #define E1000_RAR_ENTRIES_82576 24 46 #define E1000_RAR_ENTRIES_82580 24 47 #define E1000_RAR_ENTRIES_I350 32 48 49 #define E1000_SW_SYNCH_MB 0x00000100 50 #define E1000_STAT_DEV_RST_SET 0x00100000 51 #define E1000_CTRL_DEV_RST 0x20000000 52 53 /* SRRCTL bit definitions */ 54 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 55 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 56 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 57 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 58 #define E1000_SRRCTL_DROP_EN 0x80000000 59 #define E1000_SRRCTL_TIMESTAMP 0x40000000 60 61 62 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 63 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 64 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 65 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 66 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 67 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 68 69 #define E1000_EICR_TX_QUEUE ( \ 70 E1000_EICR_TX_QUEUE0 | \ 71 E1000_EICR_TX_QUEUE1 | \ 72 E1000_EICR_TX_QUEUE2 | \ 73 E1000_EICR_TX_QUEUE3) 74 75 #define E1000_EICR_RX_QUEUE ( \ 76 E1000_EICR_RX_QUEUE0 | \ 77 E1000_EICR_RX_QUEUE1 | \ 78 E1000_EICR_RX_QUEUE2 | \ 79 E1000_EICR_RX_QUEUE3) 80 81 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 82 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 83 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 84 85 /* Receive Descriptor - Advanced */ 86 union e1000_adv_rx_desc { 87 struct { 88 __le64 pkt_addr; /* Packet buffer address */ 89 __le64 hdr_addr; /* Header buffer address */ 90 } read; 91 struct { 92 struct { 93 struct { 94 __le16 pkt_info; /* RSS type, Packet type */ 95 __le16 hdr_info; /* Split Header, 96 * header buffer length */ 97 } lo_dword; 98 union { 99 __le32 rss; /* RSS Hash */ 100 struct { 101 __le16 ip_id; /* IP id */ 102 __le16 csum; /* Packet Checksum */ 103 } csum_ip; 104 } hi_dword; 105 } lower; 106 struct { 107 __le32 status_error; /* ext status/error */ 108 __le16 length; /* Packet length */ 109 __le16 vlan; /* VLAN tag */ 110 } upper; 111 } wb; /* writeback */ 112 }; 113 114 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 115 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 116 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 117 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 118 119 /* Transmit Descriptor - Advanced */ 120 union e1000_adv_tx_desc { 121 struct { 122 __le64 buffer_addr; /* Address of descriptor's data buf */ 123 __le32 cmd_type_len; 124 __le32 olinfo_status; 125 } read; 126 struct { 127 __le64 rsvd; /* Reserved */ 128 __le32 nxtseq_seed; 129 __le32 status; 130 } wb; 131 }; 132 133 /* Adv Transmit Descriptor Config Masks */ 134 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 135 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 136 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 137 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 138 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 139 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 140 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 141 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 142 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 143 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 144 145 /* Context descriptors */ 146 struct e1000_adv_tx_context_desc { 147 __le32 vlan_macip_lens; 148 __le32 seqnum_seed; 149 __le32 type_tucmd_mlhl; 150 __le32 mss_l4len_idx; 151 }; 152 153 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 154 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 155 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 156 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ 157 /* IPSec Encrypt Enable for ESP */ 158 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 159 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 160 /* Adv ctxt IPSec SA IDX mask */ 161 /* Adv ctxt IPSec ESP len mask */ 162 163 /* Additional Transmit Descriptor Control definitions */ 164 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 165 /* Tx Queue Arbitration Priority 0=low, 1=high */ 166 167 /* Additional Receive Descriptor Control definitions */ 168 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 169 170 /* Direct Cache Access (DCA) definitions */ 171 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ 172 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 173 174 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 175 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 176 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 177 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 178 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 179 180 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 181 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 182 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 183 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 184 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 185 186 /* Additional DCA related definitions, note change in position of CPUID */ 187 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 188 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 189 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ 190 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ 191 192 /* ETQF register bit definitions */ 193 #define E1000_ETQF_FILTER_ENABLE (1 << 26) 194 #define E1000_ETQF_1588 (1 << 30) 195 196 /* FTQF register bit definitions */ 197 #define E1000_FTQF_VF_BP 0x00008000 198 #define E1000_FTQF_1588_TIME_STAMP 0x08000000 199 #define E1000_FTQF_MASK 0xF0000000 200 #define E1000_FTQF_MASK_PROTO_BP 0x10000000 201 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 202 203 #define E1000_NVM_APME_82575 0x0400 204 #define MAX_NUM_VFS 8 205 206 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ 207 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ 208 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 209 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 210 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 211 212 /* Easy defines for setting default pool, would normally be left a zero */ 213 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 214 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 215 216 /* Other useful VMD_CTL register defines */ 217 #define E1000_VT_CTL_IGNORE_MAC (1 << 28) 218 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 219 #define E1000_VT_CTL_VM_REPL_EN (1 << 30) 220 221 /* Per VM Offload register setup */ 222 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 223 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 224 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 225 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 226 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 227 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 228 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 229 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 230 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 231 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 232 233 #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */ 234 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 235 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 236 237 #define E1000_VLVF_ARRAY_SIZE 32 238 #define E1000_VLVF_VLANID_MASK 0x00000FFF 239 #define E1000_VLVF_POOLSEL_SHIFT 12 240 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 241 #define E1000_VLVF_LVLAN 0x00100000 242 #define E1000_VLVF_VLANID_ENABLE 0x80000000 243 244 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 245 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 246 247 #define E1000_IOVCTL 0x05BBC 248 #define E1000_IOVCTL_REUSE_VFQ 0x00000001 249 250 #define E1000_RPLOLR_STRVLAN 0x40000000 251 #define E1000_RPLOLR_STRCRC 0x80000000 252 253 #define E1000_DTXCTL_8023LL 0x0004 254 #define E1000_DTXCTL_VLAN_ADDED 0x0008 255 #define E1000_DTXCTL_OOS_ENABLE 0x0010 256 #define E1000_DTXCTL_MDP_EN 0x0020 257 #define E1000_DTXCTL_SPOOF_INT 0x0040 258 259 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 260 261 #define ALL_QUEUES 0xFFFF 262 263 /* RX packet buffer size defines */ 264 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 265 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int); 266 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool); 267 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool); 268 u16 igb_rxpbs_adjust_82580(u32 data); 269 s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data); 270 s32 igb_set_eee_i350(struct e1000_hw *); 271 s32 igb_set_eee_i354(struct e1000_hw *); 272 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status); 273 274 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8 275 #define E1000_EMC_INTERNAL_DATA 0x00 276 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20 277 #define E1000_EMC_DIODE1_DATA 0x01 278 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19 279 #define E1000_EMC_DIODE2_DATA 0x23 280 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A 281 #define E1000_EMC_DIODE3_DATA 0x2A 282 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30 283 #endif 284