1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 struct igb_q_vector *new_q_vector; 1206 1207 new_q_vector = kzalloc(size, GFP_KERNEL); 1208 if (new_q_vector) 1209 kfree_rcu(q_vector, rcu); 1210 q_vector = new_q_vector; 1211 } else { 1212 memset(q_vector, 0, size); 1213 } 1214 if (!q_vector) 1215 return -ENOMEM; 1216 1217 /* initialize NAPI */ 1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct net_device *netdev = adapter->netdev; 1690 struct e1000_hw *hw = &adapter->hw; 1691 struct igb_ring *ring; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 ring = adapter->tx_ring[queue]; 1698 1699 /* If any of the Qav features is enabled, configure queues as SR and 1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1701 * as SP. 1702 */ 1703 if (ring->cbs_enable || ring->launchtime_enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 } else { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1709 } 1710 1711 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1712 if (ring->cbs_enable || queue == 0) { 1713 /* i210 does not allow the queue 0 to be in the Strict 1714 * Priority mode while the Qav mode is enabled, so, 1715 * instead of disabling strict priority mode, we give 1716 * queue 0 the maximum of credits possible. 1717 * 1718 * See section 8.12.19 of the i210 datasheet, "Note: 1719 * Queue0 QueueMode must be set to 1b when 1720 * TransmitMode is set to Qav." 1721 */ 1722 if (queue == 0 && !ring->cbs_enable) { 1723 /* max "linkspeed" idleslope in kbps */ 1724 ring->idleslope = 1000000; 1725 ring->hicredit = ETH_FRAME_LEN; 1726 } 1727 1728 /* Always set data transfer arbitration to credit-based 1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1730 * the queues. 1731 */ 1732 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1735 1736 /* According to i210 datasheet section 7.2.7.7, we should set 1737 * the 'idleSlope' field from TQAVCC register following the 1738 * equation: 1739 * 1740 * For 100 Mbps link speed: 1741 * 1742 * value = BW * 0x7735 * 0.2 (E1) 1743 * 1744 * For 1000Mbps link speed: 1745 * 1746 * value = BW * 0x7735 * 2 (E2) 1747 * 1748 * E1 and E2 can be merged into one equation as shown below. 1749 * Note that 'link-speed' is in Mbps. 1750 * 1751 * value = BW * 0x7735 * 2 * link-speed 1752 * -------------- (E3) 1753 * 1000 1754 * 1755 * 'BW' is the percentage bandwidth out of full link speed 1756 * which can be found with the following equation. Note that 1757 * idleSlope here is the parameter from this function which 1758 * is in kbps. 1759 * 1760 * BW = idleSlope 1761 * ----------------- (E4) 1762 * link-speed * 1000 1763 * 1764 * That said, we can come up with a generic equation to 1765 * calculate the value we should set it TQAVCC register by 1766 * replacing 'BW' in E3 by E4. The resulting equation is: 1767 * 1768 * value = idleSlope * 0x7735 * 2 * link-speed 1769 * ----------------- -------------- (E5) 1770 * link-speed * 1000 1000 1771 * 1772 * 'link-speed' is present in both sides of the fraction so 1773 * it is canceled out. The final equation is the following: 1774 * 1775 * value = idleSlope * 61034 1776 * ----------------- (E6) 1777 * 1000000 1778 * 1779 * NOTE: For i210, given the above, we can see that idleslope 1780 * is represented in 16.38431 kbps units by the value at 1781 * the TQAVCC register (1Gbps / 61034), which reduces 1782 * the granularity for idleslope increments. 1783 * For instance, if you want to configure a 2576kbps 1784 * idleslope, the value to be written on the register 1785 * would have to be 157.23. If rounded down, you end 1786 * up with less bandwidth available than originally 1787 * required (~2572 kbps). If rounded up, you end up 1788 * with a higher bandwidth (~2589 kbps). Below the 1789 * approach we take is to always round up the 1790 * calculated value, so the resulting bandwidth might 1791 * be slightly higher for some configurations. 1792 */ 1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1794 1795 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1797 tqavcc |= value; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 wr32(E1000_I210_TQAVHC(queue), 1801 0x80000000 + ring->hicredit * 0x7735); 1802 } else { 1803 1804 /* Set idleSlope to zero. */ 1805 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1808 1809 /* Set hiCredit to zero. */ 1810 wr32(E1000_I210_TQAVHC(queue), 0); 1811 1812 /* If CBS is not enabled for any queues anymore, then return to 1813 * the default state of Data Transmission Arbitration on 1814 * TQAVCTRL. 1815 */ 1816 if (!is_any_cbs_enabled(adapter)) { 1817 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* If LaunchTime is enabled, set DataTranTIM. */ 1824 if (ring->launchtime_enable) { 1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1826 * for any of the SR queues, and configure fetchtime delta. 1827 * XXX NOTE: 1828 * - LaunchTime will be enabled for all SR queues. 1829 * - A fixed offset can be added relative to the launch 1830 * time of all packets if configured at reg LAUNCH_OS0. 1831 * We are keeping it as 0 for now (default value). 1832 */ 1833 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1835 E1000_TQAVCTRL_FETCHTIME_DELTA; 1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1837 } else { 1838 /* If Launchtime is not enabled for any SR queues anymore, 1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1840 * effectively disabling Launchtime. 1841 */ 1842 if (!is_any_txtime_enabled(adapter)) { 1843 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1847 } 1848 } 1849 1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1851 * CBS are not configurable by software so we don't do any 'controller 1852 * configuration' in respect to these parameters. 1853 */ 1854 1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1856 ring->cbs_enable ? "enabled" : "disabled", 1857 ring->launchtime_enable ? "enabled" : "disabled", 1858 queue, 1859 ring->idleslope, ring->sendslope, 1860 ring->hicredit, ring->locredit); 1861 } 1862 1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1864 bool enable) 1865 { 1866 struct igb_ring *ring; 1867 1868 if (queue < 0 || queue > adapter->num_tx_queues) 1869 return -EINVAL; 1870 1871 ring = adapter->tx_ring[queue]; 1872 ring->launchtime_enable = enable; 1873 1874 return 0; 1875 } 1876 1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1878 bool enable, int idleslope, int sendslope, 1879 int hicredit, int locredit) 1880 { 1881 struct igb_ring *ring; 1882 1883 if (queue < 0 || queue > adapter->num_tx_queues) 1884 return -EINVAL; 1885 1886 ring = adapter->tx_ring[queue]; 1887 1888 ring->cbs_enable = enable; 1889 ring->idleslope = idleslope; 1890 ring->sendslope = sendslope; 1891 ring->hicredit = hicredit; 1892 ring->locredit = locredit; 1893 1894 return 0; 1895 } 1896 1897 /** 1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1899 * @adapter: pointer to adapter struct 1900 * 1901 * Configure TQAVCTRL register switching the controller's Tx mode 1902 * if FQTSS mode is enabled or disabled. Additionally, will issue 1903 * a call to igb_config_tx_modes() per queue so any previously saved 1904 * Tx parameters are applied. 1905 **/ 1906 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1907 { 1908 struct net_device *netdev = adapter->netdev; 1909 struct e1000_hw *hw = &adapter->hw; 1910 u32 val; 1911 1912 /* Only i210 controller supports changing the transmission mode. */ 1913 if (hw->mac.type != e1000_i210) 1914 return; 1915 1916 if (is_fqtss_enabled(adapter)) { 1917 int i, max_queue; 1918 1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1921 * so SP queues wait for SR ones. 1922 */ 1923 val = rd32(E1000_I210_TQAVCTRL); 1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1926 wr32(E1000_I210_TQAVCTRL, val); 1927 1928 /* Configure Tx and Rx packet buffers sizes as described in 1929 * i210 datasheet section 7.2.7.7. 1930 */ 1931 val = rd32(E1000_TXPBS); 1932 val &= ~I210_TXPBSIZE_MASK; 1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1935 wr32(E1000_TXPBS, val); 1936 1937 val = rd32(E1000_RXPBS); 1938 val &= ~I210_RXPBSIZE_MASK; 1939 val |= I210_RXPBSIZE_PB_30KB; 1940 wr32(E1000_RXPBS, val); 1941 1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1943 * register should not exceed the buffer size programmed in 1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1945 * so according to the datasheet we should set MAX_TPKT_SIZE to 1946 * 4kB / 64. 1947 * 1948 * However, when we do so, no frame from queue 2 and 3 are 1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1950 * or _equal_ to the buffer size programmed in TXPBS. For this 1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1952 */ 1953 val = (4096 - 1) / 64; 1954 wr32(E1000_I210_DTXMXPKTSZ, val); 1955 1956 /* Since FQTSS mode is enabled, apply any CBS configuration 1957 * previously set. If no previous CBS configuration has been 1958 * done, then the initial configuration is applied, which means 1959 * CBS is disabled. 1960 */ 1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1963 1964 for (i = 0; i < max_queue; i++) { 1965 igb_config_tx_modes(adapter, i); 1966 } 1967 } else { 1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1971 1972 val = rd32(E1000_I210_TQAVCTRL); 1973 /* According to Section 8.12.21, the other flags we've set when 1974 * enabling FQTSS are not relevant when disabling FQTSS so we 1975 * don't set they here. 1976 */ 1977 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1978 wr32(E1000_I210_TQAVCTRL, val); 1979 } 1980 1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1982 "enabled" : "disabled"); 1983 } 1984 1985 /** 1986 * igb_configure - configure the hardware for RX and TX 1987 * @adapter: private board structure 1988 **/ 1989 static void igb_configure(struct igb_adapter *adapter) 1990 { 1991 struct net_device *netdev = adapter->netdev; 1992 int i; 1993 1994 igb_get_hw_control(adapter); 1995 igb_set_rx_mode(netdev); 1996 igb_setup_tx_mode(adapter); 1997 1998 igb_restore_vlan(adapter); 1999 2000 igb_setup_tctl(adapter); 2001 igb_setup_mrqc(adapter); 2002 igb_setup_rctl(adapter); 2003 2004 igb_nfc_filter_restore(adapter); 2005 igb_configure_tx(adapter); 2006 igb_configure_rx(adapter); 2007 2008 igb_rx_fifo_flush_82575(&adapter->hw); 2009 2010 /* call igb_desc_unused which always leaves 2011 * at least 1 descriptor unused to make sure 2012 * next_to_use != next_to_clean 2013 */ 2014 for (i = 0; i < adapter->num_rx_queues; i++) { 2015 struct igb_ring *ring = adapter->rx_ring[i]; 2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2017 } 2018 } 2019 2020 /** 2021 * igb_power_up_link - Power up the phy/serdes link 2022 * @adapter: address of board private structure 2023 **/ 2024 void igb_power_up_link(struct igb_adapter *adapter) 2025 { 2026 igb_reset_phy(&adapter->hw); 2027 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_up_phy_copper(&adapter->hw); 2030 else 2031 igb_power_up_serdes_link_82575(&adapter->hw); 2032 2033 igb_setup_link(&adapter->hw); 2034 } 2035 2036 /** 2037 * igb_power_down_link - Power down the phy/serdes link 2038 * @adapter: address of board private structure 2039 */ 2040 static void igb_power_down_link(struct igb_adapter *adapter) 2041 { 2042 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2043 igb_power_down_phy_copper_82575(&adapter->hw); 2044 else 2045 igb_shutdown_serdes_link_82575(&adapter->hw); 2046 } 2047 2048 /** 2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2050 * @adapter: address of the board private structure 2051 **/ 2052 static void igb_check_swap_media(struct igb_adapter *adapter) 2053 { 2054 struct e1000_hw *hw = &adapter->hw; 2055 u32 ctrl_ext, connsw; 2056 bool swap_now = false; 2057 2058 ctrl_ext = rd32(E1000_CTRL_EXT); 2059 connsw = rd32(E1000_CONNSW); 2060 2061 /* need to live swap if current media is copper and we have fiber/serdes 2062 * to go to. 2063 */ 2064 2065 if ((hw->phy.media_type == e1000_media_type_copper) && 2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2067 swap_now = true; 2068 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2069 !(connsw & E1000_CONNSW_SERDESD)) { 2070 /* copper signal takes time to appear */ 2071 if (adapter->copper_tries < 4) { 2072 adapter->copper_tries++; 2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2074 wr32(E1000_CONNSW, connsw); 2075 return; 2076 } else { 2077 adapter->copper_tries = 0; 2078 if ((connsw & E1000_CONNSW_PHYSD) && 2079 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2080 swap_now = true; 2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2082 wr32(E1000_CONNSW, connsw); 2083 } 2084 } 2085 } 2086 2087 if (!swap_now) 2088 return; 2089 2090 switch (hw->phy.media_type) { 2091 case e1000_media_type_copper: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to fiber/serdes\n"); 2094 ctrl_ext |= 2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 adapter->copper_tries = 0; 2098 break; 2099 case e1000_media_type_internal_serdes: 2100 case e1000_media_type_fiber: 2101 netdev_info(adapter->netdev, 2102 "MAS: changing media to copper\n"); 2103 ctrl_ext &= 2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2105 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2106 break; 2107 default: 2108 /* shouldn't get here during regular operation */ 2109 netdev_err(adapter->netdev, 2110 "AMS: Invalid media type found, returning\n"); 2111 break; 2112 } 2113 wr32(E1000_CTRL_EXT, ctrl_ext); 2114 } 2115 2116 /** 2117 * igb_up - Open the interface and prepare it to handle traffic 2118 * @adapter: board private structure 2119 **/ 2120 int igb_up(struct igb_adapter *adapter) 2121 { 2122 struct e1000_hw *hw = &adapter->hw; 2123 int i; 2124 2125 /* hardware has been reset, we need to reload some things */ 2126 igb_configure(adapter); 2127 2128 clear_bit(__IGB_DOWN, &adapter->state); 2129 2130 for (i = 0; i < adapter->num_q_vectors; i++) 2131 napi_enable(&(adapter->q_vector[i]->napi)); 2132 2133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2134 igb_configure_msix(adapter); 2135 else 2136 igb_assign_vector(adapter->q_vector[0], 0); 2137 2138 /* Clear any pending interrupts. */ 2139 rd32(E1000_TSICR); 2140 rd32(E1000_ICR); 2141 igb_irq_enable(adapter); 2142 2143 /* notify VFs that reset has been completed */ 2144 if (adapter->vfs_allocated_count) { 2145 u32 reg_data = rd32(E1000_CTRL_EXT); 2146 2147 reg_data |= E1000_CTRL_EXT_PFRSTD; 2148 wr32(E1000_CTRL_EXT, reg_data); 2149 } 2150 2151 netif_tx_start_all_queues(adapter->netdev); 2152 2153 /* start the watchdog. */ 2154 hw->mac.get_link_status = 1; 2155 schedule_work(&adapter->watchdog_task); 2156 2157 if ((adapter->flags & IGB_FLAG_EEE) && 2158 (!hw->dev_spec._82575.eee_disable)) 2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2160 2161 return 0; 2162 } 2163 2164 void igb_down(struct igb_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 struct e1000_hw *hw = &adapter->hw; 2168 u32 tctl, rctl; 2169 int i; 2170 2171 /* signal that we're down so the interrupt handler does not 2172 * reschedule our watchdog timer 2173 */ 2174 set_bit(__IGB_DOWN, &adapter->state); 2175 2176 /* disable receives in the hardware */ 2177 rctl = rd32(E1000_RCTL); 2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2179 /* flush and sleep below */ 2180 2181 igb_nfc_filter_exit(adapter); 2182 2183 netif_carrier_off(netdev); 2184 netif_tx_stop_all_queues(netdev); 2185 2186 /* disable transmits in the hardware */ 2187 tctl = rd32(E1000_TCTL); 2188 tctl &= ~E1000_TCTL_EN; 2189 wr32(E1000_TCTL, tctl); 2190 /* flush both disables and wait for them to finish */ 2191 wrfl(); 2192 usleep_range(10000, 11000); 2193 2194 igb_irq_disable(adapter); 2195 2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2197 2198 for (i = 0; i < adapter->num_q_vectors; i++) { 2199 if (adapter->q_vector[i]) { 2200 napi_synchronize(&adapter->q_vector[i]->napi); 2201 napi_disable(&adapter->q_vector[i]->napi); 2202 } 2203 } 2204 2205 del_timer_sync(&adapter->watchdog_timer); 2206 del_timer_sync(&adapter->phy_info_timer); 2207 2208 /* record the stats before reset*/ 2209 spin_lock(&adapter->stats64_lock); 2210 igb_update_stats(adapter); 2211 spin_unlock(&adapter->stats64_lock); 2212 2213 adapter->link_speed = 0; 2214 adapter->link_duplex = 0; 2215 2216 if (!pci_channel_offline(adapter->pdev)) 2217 igb_reset(adapter); 2218 2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2221 2222 igb_clean_all_tx_rings(adapter); 2223 igb_clean_all_rx_rings(adapter); 2224 #ifdef CONFIG_IGB_DCA 2225 2226 /* since we reset the hardware DCA settings were cleared */ 2227 igb_setup_dca(adapter); 2228 #endif 2229 } 2230 2231 void igb_reinit_locked(struct igb_adapter *adapter) 2232 { 2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2234 usleep_range(1000, 2000); 2235 igb_down(adapter); 2236 igb_up(adapter); 2237 clear_bit(__IGB_RESETTING, &adapter->state); 2238 } 2239 2240 /** igb_enable_mas - Media Autosense re-enable after swap 2241 * 2242 * @adapter: adapter struct 2243 **/ 2244 static void igb_enable_mas(struct igb_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 connsw = rd32(E1000_CONNSW); 2248 2249 /* configure for SerDes media detect */ 2250 if ((hw->phy.media_type == e1000_media_type_copper) && 2251 (!(connsw & E1000_CONNSW_SERDESD))) { 2252 connsw |= E1000_CONNSW_ENRGSRC; 2253 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2254 wr32(E1000_CONNSW, connsw); 2255 wrfl(); 2256 } 2257 } 2258 2259 #ifdef CONFIG_IGB_HWMON 2260 /** 2261 * igb_set_i2c_bb - Init I2C interface 2262 * @hw: pointer to hardware structure 2263 **/ 2264 static void igb_set_i2c_bb(struct e1000_hw *hw) 2265 { 2266 u32 ctrl_ext; 2267 s32 i2cctl; 2268 2269 ctrl_ext = rd32(E1000_CTRL_EXT); 2270 ctrl_ext |= E1000_CTRL_I2C_ENA; 2271 wr32(E1000_CTRL_EXT, ctrl_ext); 2272 wrfl(); 2273 2274 i2cctl = rd32(E1000_I2CPARAMS); 2275 i2cctl |= E1000_I2CBB_EN 2276 | E1000_I2C_CLK_OE_N 2277 | E1000_I2C_DATA_OE_N; 2278 wr32(E1000_I2CPARAMS, i2cctl); 2279 wrfl(); 2280 } 2281 #endif 2282 2283 void igb_reset(struct igb_adapter *adapter) 2284 { 2285 struct pci_dev *pdev = adapter->pdev; 2286 struct e1000_hw *hw = &adapter->hw; 2287 struct e1000_mac_info *mac = &hw->mac; 2288 struct e1000_fc_info *fc = &hw->fc; 2289 u32 pba, hwm; 2290 2291 /* Repartition Pba for greater than 9k mtu 2292 * To take effect CTRL.RST is required. 2293 */ 2294 switch (mac->type) { 2295 case e1000_i350: 2296 case e1000_i354: 2297 case e1000_82580: 2298 pba = rd32(E1000_RXPBS); 2299 pba = igb_rxpbs_adjust_82580(pba); 2300 break; 2301 case e1000_82576: 2302 pba = rd32(E1000_RXPBS); 2303 pba &= E1000_RXPBS_SIZE_MASK_82576; 2304 break; 2305 case e1000_82575: 2306 case e1000_i210: 2307 case e1000_i211: 2308 default: 2309 pba = E1000_PBA_34K; 2310 break; 2311 } 2312 2313 if (mac->type == e1000_82575) { 2314 u32 min_rx_space, min_tx_space, needed_tx_space; 2315 2316 /* write Rx PBA so that hardware can report correct Tx PBA */ 2317 wr32(E1000_PBA, pba); 2318 2319 /* To maintain wire speed transmits, the Tx FIFO should be 2320 * large enough to accommodate two full transmit packets, 2321 * rounded up to the next 1KB and expressed in KB. Likewise, 2322 * the Rx FIFO should be large enough to accommodate at least 2323 * one full receive packet and is similarly rounded up and 2324 * expressed in KB. 2325 */ 2326 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2327 2328 /* The Tx FIFO also stores 16 bytes of information about the Tx 2329 * but don't include Ethernet FCS because hardware appends it. 2330 * We only need to round down to the nearest 512 byte block 2331 * count since the value we care about is 2 frames, not 1. 2332 */ 2333 min_tx_space = adapter->max_frame_size; 2334 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2335 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2336 2337 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2338 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2339 2340 /* If current Tx allocation is less than the min Tx FIFO size, 2341 * and the min Tx FIFO size is less than the current Rx FIFO 2342 * allocation, take space away from current Rx allocation. 2343 */ 2344 if (needed_tx_space < pba) { 2345 pba -= needed_tx_space; 2346 2347 /* if short on Rx space, Rx wins and must trump Tx 2348 * adjustment 2349 */ 2350 if (pba < min_rx_space) 2351 pba = min_rx_space; 2352 } 2353 2354 /* adjust PBA for jumbo frames */ 2355 wr32(E1000_PBA, pba); 2356 } 2357 2358 /* flow control settings 2359 * The high water mark must be low enough to fit one full frame 2360 * after transmitting the pause frame. As such we must have enough 2361 * space to allow for us to complete our current transmit and then 2362 * receive the frame that is in progress from the link partner. 2363 * Set it to: 2364 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2365 */ 2366 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2367 2368 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2369 fc->low_water = fc->high_water - 16; 2370 fc->pause_time = 0xFFFF; 2371 fc->send_xon = 1; 2372 fc->current_mode = fc->requested_mode; 2373 2374 /* disable receive for all VFs and wait one second */ 2375 if (adapter->vfs_allocated_count) { 2376 int i; 2377 2378 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2379 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2380 2381 /* ping all the active vfs to let them know we are going down */ 2382 igb_ping_all_vfs(adapter); 2383 2384 /* disable transmits and receives */ 2385 wr32(E1000_VFRE, 0); 2386 wr32(E1000_VFTE, 0); 2387 } 2388 2389 /* Allow time for pending master requests to run */ 2390 hw->mac.ops.reset_hw(hw); 2391 wr32(E1000_WUC, 0); 2392 2393 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2394 /* need to resetup here after media swap */ 2395 adapter->ei.get_invariants(hw); 2396 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2397 } 2398 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2399 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2400 igb_enable_mas(adapter); 2401 } 2402 if (hw->mac.ops.init_hw(hw)) 2403 dev_err(&pdev->dev, "Hardware Error\n"); 2404 2405 /* RAR registers were cleared during init_hw, clear mac table */ 2406 igb_flush_mac_table(adapter); 2407 __dev_uc_unsync(adapter->netdev, NULL); 2408 2409 /* Recover default RAR entry */ 2410 igb_set_default_mac_filter(adapter); 2411 2412 /* Flow control settings reset on hardware reset, so guarantee flow 2413 * control is off when forcing speed. 2414 */ 2415 if (!hw->mac.autoneg) 2416 igb_force_mac_fc(hw); 2417 2418 igb_init_dmac(adapter, pba); 2419 #ifdef CONFIG_IGB_HWMON 2420 /* Re-initialize the thermal sensor on i350 devices. */ 2421 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2422 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2423 /* If present, re-initialize the external thermal sensor 2424 * interface. 2425 */ 2426 if (adapter->ets) 2427 igb_set_i2c_bb(hw); 2428 mac->ops.init_thermal_sensor_thresh(hw); 2429 } 2430 } 2431 #endif 2432 /* Re-establish EEE setting */ 2433 if (hw->phy.media_type == e1000_media_type_copper) { 2434 switch (mac->type) { 2435 case e1000_i350: 2436 case e1000_i210: 2437 case e1000_i211: 2438 igb_set_eee_i350(hw, true, true); 2439 break; 2440 case e1000_i354: 2441 igb_set_eee_i354(hw, true, true); 2442 break; 2443 default: 2444 break; 2445 } 2446 } 2447 if (!netif_running(adapter->netdev)) 2448 igb_power_down_link(adapter); 2449 2450 igb_update_mng_vlan(adapter); 2451 2452 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2453 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2454 2455 /* Re-enable PTP, where applicable. */ 2456 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2457 igb_ptp_reset(adapter); 2458 2459 igb_get_phy_info(hw); 2460 } 2461 2462 static netdev_features_t igb_fix_features(struct net_device *netdev, 2463 netdev_features_t features) 2464 { 2465 /* Since there is no support for separate Rx/Tx vlan accel 2466 * enable/disable make sure Tx flag is always in same state as Rx. 2467 */ 2468 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2469 features |= NETIF_F_HW_VLAN_CTAG_TX; 2470 else 2471 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2472 2473 return features; 2474 } 2475 2476 static int igb_set_features(struct net_device *netdev, 2477 netdev_features_t features) 2478 { 2479 netdev_features_t changed = netdev->features ^ features; 2480 struct igb_adapter *adapter = netdev_priv(netdev); 2481 2482 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2483 igb_vlan_mode(netdev, features); 2484 2485 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2486 return 0; 2487 2488 if (!(features & NETIF_F_NTUPLE)) { 2489 struct hlist_node *node2; 2490 struct igb_nfc_filter *rule; 2491 2492 spin_lock(&adapter->nfc_lock); 2493 hlist_for_each_entry_safe(rule, node2, 2494 &adapter->nfc_filter_list, nfc_node) { 2495 igb_erase_filter(adapter, rule); 2496 hlist_del(&rule->nfc_node); 2497 kfree(rule); 2498 } 2499 spin_unlock(&adapter->nfc_lock); 2500 adapter->nfc_filter_count = 0; 2501 } 2502 2503 netdev->features = features; 2504 2505 if (netif_running(netdev)) 2506 igb_reinit_locked(adapter); 2507 else 2508 igb_reset(adapter); 2509 2510 return 1; 2511 } 2512 2513 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2514 struct net_device *dev, 2515 const unsigned char *addr, u16 vid, 2516 u16 flags, 2517 struct netlink_ext_ack *extack) 2518 { 2519 /* guarantee we can provide a unique filter for the unicast address */ 2520 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2521 struct igb_adapter *adapter = netdev_priv(dev); 2522 int vfn = adapter->vfs_allocated_count; 2523 2524 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2525 return -ENOMEM; 2526 } 2527 2528 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2529 } 2530 2531 #define IGB_MAX_MAC_HDR_LEN 127 2532 #define IGB_MAX_NETWORK_HDR_LEN 511 2533 2534 static netdev_features_t 2535 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2536 netdev_features_t features) 2537 { 2538 unsigned int network_hdr_len, mac_hdr_len; 2539 2540 /* Make certain the headers can be described by a context descriptor */ 2541 mac_hdr_len = skb_network_header(skb) - skb->data; 2542 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2543 return features & ~(NETIF_F_HW_CSUM | 2544 NETIF_F_SCTP_CRC | 2545 NETIF_F_GSO_UDP_L4 | 2546 NETIF_F_HW_VLAN_CTAG_TX | 2547 NETIF_F_TSO | 2548 NETIF_F_TSO6); 2549 2550 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2551 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2552 return features & ~(NETIF_F_HW_CSUM | 2553 NETIF_F_SCTP_CRC | 2554 NETIF_F_GSO_UDP_L4 | 2555 NETIF_F_TSO | 2556 NETIF_F_TSO6); 2557 2558 /* We can only support IPV4 TSO in tunnels if we can mangle the 2559 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2560 */ 2561 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2562 features &= ~NETIF_F_TSO; 2563 2564 return features; 2565 } 2566 2567 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2568 { 2569 if (!is_fqtss_enabled(adapter)) { 2570 enable_fqtss(adapter, true); 2571 return; 2572 } 2573 2574 igb_config_tx_modes(adapter, queue); 2575 2576 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2577 enable_fqtss(adapter, false); 2578 } 2579 2580 static int igb_offload_cbs(struct igb_adapter *adapter, 2581 struct tc_cbs_qopt_offload *qopt) 2582 { 2583 struct e1000_hw *hw = &adapter->hw; 2584 int err; 2585 2586 /* CBS offloading is only supported by i210 controller. */ 2587 if (hw->mac.type != e1000_i210) 2588 return -EOPNOTSUPP; 2589 2590 /* CBS offloading is only supported by queue 0 and queue 1. */ 2591 if (qopt->queue < 0 || qopt->queue > 1) 2592 return -EINVAL; 2593 2594 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2595 qopt->idleslope, qopt->sendslope, 2596 qopt->hicredit, qopt->locredit); 2597 if (err) 2598 return err; 2599 2600 igb_offload_apply(adapter, qopt->queue); 2601 2602 return 0; 2603 } 2604 2605 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2606 #define VLAN_PRIO_FULL_MASK (0x07) 2607 2608 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2609 struct flow_cls_offload *f, 2610 int traffic_class, 2611 struct igb_nfc_filter *input) 2612 { 2613 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2614 struct flow_dissector *dissector = rule->match.dissector; 2615 struct netlink_ext_ack *extack = f->common.extack; 2616 2617 if (dissector->used_keys & 2618 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2619 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2620 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2621 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2622 NL_SET_ERR_MSG_MOD(extack, 2623 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2624 return -EOPNOTSUPP; 2625 } 2626 2627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2628 struct flow_match_eth_addrs match; 2629 2630 flow_rule_match_eth_addrs(rule, &match); 2631 if (!is_zero_ether_addr(match.mask->dst)) { 2632 if (!is_broadcast_ether_addr(match.mask->dst)) { 2633 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2634 return -EINVAL; 2635 } 2636 2637 input->filter.match_flags |= 2638 IGB_FILTER_FLAG_DST_MAC_ADDR; 2639 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2640 } 2641 2642 if (!is_zero_ether_addr(match.mask->src)) { 2643 if (!is_broadcast_ether_addr(match.mask->src)) { 2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2645 return -EINVAL; 2646 } 2647 2648 input->filter.match_flags |= 2649 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2650 ether_addr_copy(input->filter.src_addr, match.key->src); 2651 } 2652 } 2653 2654 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2655 struct flow_match_basic match; 2656 2657 flow_rule_match_basic(rule, &match); 2658 if (match.mask->n_proto) { 2659 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2660 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2661 return -EINVAL; 2662 } 2663 2664 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2665 input->filter.etype = match.key->n_proto; 2666 } 2667 } 2668 2669 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2670 struct flow_match_vlan match; 2671 2672 flow_rule_match_vlan(rule, &match); 2673 if (match.mask->vlan_priority) { 2674 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2675 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2676 return -EINVAL; 2677 } 2678 2679 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2680 input->filter.vlan_tci = 2681 (__force __be16)match.key->vlan_priority; 2682 } 2683 } 2684 2685 input->action = traffic_class; 2686 input->cookie = f->cookie; 2687 2688 return 0; 2689 } 2690 2691 static int igb_configure_clsflower(struct igb_adapter *adapter, 2692 struct flow_cls_offload *cls_flower) 2693 { 2694 struct netlink_ext_ack *extack = cls_flower->common.extack; 2695 struct igb_nfc_filter *filter, *f; 2696 int err, tc; 2697 2698 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2699 if (tc < 0) { 2700 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2701 return -EINVAL; 2702 } 2703 2704 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2705 if (!filter) 2706 return -ENOMEM; 2707 2708 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2709 if (err < 0) 2710 goto err_parse; 2711 2712 spin_lock(&adapter->nfc_lock); 2713 2714 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2715 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2716 err = -EEXIST; 2717 NL_SET_ERR_MSG_MOD(extack, 2718 "This filter is already set in ethtool"); 2719 goto err_locked; 2720 } 2721 } 2722 2723 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2724 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2725 err = -EEXIST; 2726 NL_SET_ERR_MSG_MOD(extack, 2727 "This filter is already set in cls_flower"); 2728 goto err_locked; 2729 } 2730 } 2731 2732 err = igb_add_filter(adapter, filter); 2733 if (err < 0) { 2734 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2735 goto err_locked; 2736 } 2737 2738 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2739 2740 spin_unlock(&adapter->nfc_lock); 2741 2742 return 0; 2743 2744 err_locked: 2745 spin_unlock(&adapter->nfc_lock); 2746 2747 err_parse: 2748 kfree(filter); 2749 2750 return err; 2751 } 2752 2753 static int igb_delete_clsflower(struct igb_adapter *adapter, 2754 struct flow_cls_offload *cls_flower) 2755 { 2756 struct igb_nfc_filter *filter; 2757 int err; 2758 2759 spin_lock(&adapter->nfc_lock); 2760 2761 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2762 if (filter->cookie == cls_flower->cookie) 2763 break; 2764 2765 if (!filter) { 2766 err = -ENOENT; 2767 goto out; 2768 } 2769 2770 err = igb_erase_filter(adapter, filter); 2771 if (err < 0) 2772 goto out; 2773 2774 hlist_del(&filter->nfc_node); 2775 kfree(filter); 2776 2777 out: 2778 spin_unlock(&adapter->nfc_lock); 2779 2780 return err; 2781 } 2782 2783 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2784 struct flow_cls_offload *cls_flower) 2785 { 2786 switch (cls_flower->command) { 2787 case FLOW_CLS_REPLACE: 2788 return igb_configure_clsflower(adapter, cls_flower); 2789 case FLOW_CLS_DESTROY: 2790 return igb_delete_clsflower(adapter, cls_flower); 2791 case FLOW_CLS_STATS: 2792 return -EOPNOTSUPP; 2793 default: 2794 return -EOPNOTSUPP; 2795 } 2796 } 2797 2798 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2799 void *cb_priv) 2800 { 2801 struct igb_adapter *adapter = cb_priv; 2802 2803 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2804 return -EOPNOTSUPP; 2805 2806 switch (type) { 2807 case TC_SETUP_CLSFLOWER: 2808 return igb_setup_tc_cls_flower(adapter, type_data); 2809 2810 default: 2811 return -EOPNOTSUPP; 2812 } 2813 } 2814 2815 static int igb_offload_txtime(struct igb_adapter *adapter, 2816 struct tc_etf_qopt_offload *qopt) 2817 { 2818 struct e1000_hw *hw = &adapter->hw; 2819 int err; 2820 2821 /* Launchtime offloading is only supported by i210 controller. */ 2822 if (hw->mac.type != e1000_i210) 2823 return -EOPNOTSUPP; 2824 2825 /* Launchtime offloading is only supported by queues 0 and 1. */ 2826 if (qopt->queue < 0 || qopt->queue > 1) 2827 return -EINVAL; 2828 2829 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2830 if (err) 2831 return err; 2832 2833 igb_offload_apply(adapter, qopt->queue); 2834 2835 return 0; 2836 } 2837 2838 static int igb_tc_query_caps(struct igb_adapter *adapter, 2839 struct tc_query_caps_base *base) 2840 { 2841 switch (base->type) { 2842 case TC_SETUP_QDISC_TAPRIO: { 2843 struct tc_taprio_caps *caps = base->caps; 2844 2845 caps->broken_mqprio = true; 2846 2847 return 0; 2848 } 2849 default: 2850 return -EOPNOTSUPP; 2851 } 2852 } 2853 2854 static LIST_HEAD(igb_block_cb_list); 2855 2856 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2857 void *type_data) 2858 { 2859 struct igb_adapter *adapter = netdev_priv(dev); 2860 2861 switch (type) { 2862 case TC_QUERY_CAPS: 2863 return igb_tc_query_caps(adapter, type_data); 2864 case TC_SETUP_QDISC_CBS: 2865 return igb_offload_cbs(adapter, type_data); 2866 case TC_SETUP_BLOCK: 2867 return flow_block_cb_setup_simple(type_data, 2868 &igb_block_cb_list, 2869 igb_setup_tc_block_cb, 2870 adapter, adapter, true); 2871 2872 case TC_SETUP_QDISC_ETF: 2873 return igb_offload_txtime(adapter, type_data); 2874 2875 default: 2876 return -EOPNOTSUPP; 2877 } 2878 } 2879 2880 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2881 { 2882 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2883 struct igb_adapter *adapter = netdev_priv(dev); 2884 struct bpf_prog *prog = bpf->prog, *old_prog; 2885 bool running = netif_running(dev); 2886 bool need_reset; 2887 2888 /* verify igb ring attributes are sufficient for XDP */ 2889 for (i = 0; i < adapter->num_rx_queues; i++) { 2890 struct igb_ring *ring = adapter->rx_ring[i]; 2891 2892 if (frame_size > igb_rx_bufsz(ring)) { 2893 NL_SET_ERR_MSG_MOD(bpf->extack, 2894 "The RX buffer size is too small for the frame size"); 2895 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2896 igb_rx_bufsz(ring), frame_size); 2897 return -EINVAL; 2898 } 2899 } 2900 2901 old_prog = xchg(&adapter->xdp_prog, prog); 2902 need_reset = (!!prog != !!old_prog); 2903 2904 /* device is up and bpf is added/removed, must setup the RX queues */ 2905 if (need_reset && running) { 2906 igb_close(dev); 2907 } else { 2908 for (i = 0; i < adapter->num_rx_queues; i++) 2909 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2910 adapter->xdp_prog); 2911 } 2912 2913 if (old_prog) 2914 bpf_prog_put(old_prog); 2915 2916 /* bpf is just replaced, RXQ and MTU are already setup */ 2917 if (!need_reset) { 2918 return 0; 2919 } else { 2920 if (prog) 2921 xdp_features_set_redirect_target(dev, true); 2922 else 2923 xdp_features_clear_redirect_target(dev); 2924 } 2925 2926 if (running) 2927 igb_open(dev); 2928 2929 return 0; 2930 } 2931 2932 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2933 { 2934 switch (xdp->command) { 2935 case XDP_SETUP_PROG: 2936 return igb_xdp_setup(dev, xdp); 2937 default: 2938 return -EINVAL; 2939 } 2940 } 2941 2942 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2943 { 2944 /* Force memory writes to complete before letting h/w know there 2945 * are new descriptors to fetch. 2946 */ 2947 wmb(); 2948 writel(ring->next_to_use, ring->tail); 2949 } 2950 2951 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2952 { 2953 unsigned int r_idx = smp_processor_id(); 2954 2955 if (r_idx >= adapter->num_tx_queues) 2956 r_idx = r_idx % adapter->num_tx_queues; 2957 2958 return adapter->tx_ring[r_idx]; 2959 } 2960 2961 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2962 { 2963 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2964 int cpu = smp_processor_id(); 2965 struct igb_ring *tx_ring; 2966 struct netdev_queue *nq; 2967 u32 ret; 2968 2969 if (unlikely(!xdpf)) 2970 return IGB_XDP_CONSUMED; 2971 2972 /* During program transitions its possible adapter->xdp_prog is assigned 2973 * but ring has not been configured yet. In this case simply abort xmit. 2974 */ 2975 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2976 if (unlikely(!tx_ring)) 2977 return IGB_XDP_CONSUMED; 2978 2979 nq = txring_txq(tx_ring); 2980 __netif_tx_lock(nq, cpu); 2981 /* Avoid transmit queue timeout since we share it with the slow path */ 2982 txq_trans_cond_update(nq); 2983 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2984 __netif_tx_unlock(nq); 2985 2986 return ret; 2987 } 2988 2989 static int igb_xdp_xmit(struct net_device *dev, int n, 2990 struct xdp_frame **frames, u32 flags) 2991 { 2992 struct igb_adapter *adapter = netdev_priv(dev); 2993 int cpu = smp_processor_id(); 2994 struct igb_ring *tx_ring; 2995 struct netdev_queue *nq; 2996 int nxmit = 0; 2997 int i; 2998 2999 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 3000 return -ENETDOWN; 3001 3002 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3003 return -EINVAL; 3004 3005 /* During program transitions its possible adapter->xdp_prog is assigned 3006 * but ring has not been configured yet. In this case simply abort xmit. 3007 */ 3008 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 3009 if (unlikely(!tx_ring)) 3010 return -ENXIO; 3011 3012 nq = txring_txq(tx_ring); 3013 __netif_tx_lock(nq, cpu); 3014 3015 /* Avoid transmit queue timeout since we share it with the slow path */ 3016 txq_trans_cond_update(nq); 3017 3018 for (i = 0; i < n; i++) { 3019 struct xdp_frame *xdpf = frames[i]; 3020 int err; 3021 3022 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3023 if (err != IGB_XDP_TX) 3024 break; 3025 nxmit++; 3026 } 3027 3028 __netif_tx_unlock(nq); 3029 3030 if (unlikely(flags & XDP_XMIT_FLUSH)) 3031 igb_xdp_ring_update_tail(tx_ring); 3032 3033 return nxmit; 3034 } 3035 3036 static const struct net_device_ops igb_netdev_ops = { 3037 .ndo_open = igb_open, 3038 .ndo_stop = igb_close, 3039 .ndo_start_xmit = igb_xmit_frame, 3040 .ndo_get_stats64 = igb_get_stats64, 3041 .ndo_set_rx_mode = igb_set_rx_mode, 3042 .ndo_set_mac_address = igb_set_mac, 3043 .ndo_change_mtu = igb_change_mtu, 3044 .ndo_eth_ioctl = igb_ioctl, 3045 .ndo_tx_timeout = igb_tx_timeout, 3046 .ndo_validate_addr = eth_validate_addr, 3047 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3048 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3049 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3050 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3051 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3052 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3053 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3054 .ndo_get_vf_config = igb_ndo_get_vf_config, 3055 .ndo_fix_features = igb_fix_features, 3056 .ndo_set_features = igb_set_features, 3057 .ndo_fdb_add = igb_ndo_fdb_add, 3058 .ndo_features_check = igb_features_check, 3059 .ndo_setup_tc = igb_setup_tc, 3060 .ndo_bpf = igb_xdp, 3061 .ndo_xdp_xmit = igb_xdp_xmit, 3062 }; 3063 3064 /** 3065 * igb_set_fw_version - Configure version string for ethtool 3066 * @adapter: adapter struct 3067 **/ 3068 void igb_set_fw_version(struct igb_adapter *adapter) 3069 { 3070 struct e1000_hw *hw = &adapter->hw; 3071 struct e1000_fw_version fw; 3072 3073 igb_get_fw_version(hw, &fw); 3074 3075 switch (hw->mac.type) { 3076 case e1000_i210: 3077 case e1000_i211: 3078 if (!(igb_get_flash_presence_i210(hw))) { 3079 snprintf(adapter->fw_version, 3080 sizeof(adapter->fw_version), 3081 "%2d.%2d-%d", 3082 fw.invm_major, fw.invm_minor, 3083 fw.invm_img_type); 3084 break; 3085 } 3086 fallthrough; 3087 default: 3088 /* if option is rom valid, display its version too */ 3089 if (fw.or_valid) { 3090 snprintf(adapter->fw_version, 3091 sizeof(adapter->fw_version), 3092 "%d.%d, 0x%08x, %d.%d.%d", 3093 fw.eep_major, fw.eep_minor, fw.etrack_id, 3094 fw.or_major, fw.or_build, fw.or_patch); 3095 /* no option rom */ 3096 } else if (fw.etrack_id != 0X0000) { 3097 snprintf(adapter->fw_version, 3098 sizeof(adapter->fw_version), 3099 "%d.%d, 0x%08x", 3100 fw.eep_major, fw.eep_minor, fw.etrack_id); 3101 } else { 3102 snprintf(adapter->fw_version, 3103 sizeof(adapter->fw_version), 3104 "%d.%d.%d", 3105 fw.eep_major, fw.eep_minor, fw.eep_build); 3106 } 3107 break; 3108 } 3109 } 3110 3111 /** 3112 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3113 * 3114 * @adapter: adapter struct 3115 **/ 3116 static void igb_init_mas(struct igb_adapter *adapter) 3117 { 3118 struct e1000_hw *hw = &adapter->hw; 3119 u16 eeprom_data; 3120 3121 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3122 switch (hw->bus.func) { 3123 case E1000_FUNC_0: 3124 if (eeprom_data & IGB_MAS_ENABLE_0) { 3125 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3126 netdev_info(adapter->netdev, 3127 "MAS: Enabling Media Autosense for port %d\n", 3128 hw->bus.func); 3129 } 3130 break; 3131 case E1000_FUNC_1: 3132 if (eeprom_data & IGB_MAS_ENABLE_1) { 3133 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3134 netdev_info(adapter->netdev, 3135 "MAS: Enabling Media Autosense for port %d\n", 3136 hw->bus.func); 3137 } 3138 break; 3139 case E1000_FUNC_2: 3140 if (eeprom_data & IGB_MAS_ENABLE_2) { 3141 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3142 netdev_info(adapter->netdev, 3143 "MAS: Enabling Media Autosense for port %d\n", 3144 hw->bus.func); 3145 } 3146 break; 3147 case E1000_FUNC_3: 3148 if (eeprom_data & IGB_MAS_ENABLE_3) { 3149 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3150 netdev_info(adapter->netdev, 3151 "MAS: Enabling Media Autosense for port %d\n", 3152 hw->bus.func); 3153 } 3154 break; 3155 default: 3156 /* Shouldn't get here */ 3157 netdev_err(adapter->netdev, 3158 "MAS: Invalid port configuration, returning\n"); 3159 break; 3160 } 3161 } 3162 3163 /** 3164 * igb_init_i2c - Init I2C interface 3165 * @adapter: pointer to adapter structure 3166 **/ 3167 static s32 igb_init_i2c(struct igb_adapter *adapter) 3168 { 3169 s32 status = 0; 3170 3171 /* I2C interface supported on i350 devices */ 3172 if (adapter->hw.mac.type != e1000_i350) 3173 return 0; 3174 3175 /* Initialize the i2c bus which is controlled by the registers. 3176 * This bus will use the i2c_algo_bit structure that implements 3177 * the protocol through toggling of the 4 bits in the register. 3178 */ 3179 adapter->i2c_adap.owner = THIS_MODULE; 3180 adapter->i2c_algo = igb_i2c_algo; 3181 adapter->i2c_algo.data = adapter; 3182 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3183 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3184 strscpy(adapter->i2c_adap.name, "igb BB", 3185 sizeof(adapter->i2c_adap.name)); 3186 status = i2c_bit_add_bus(&adapter->i2c_adap); 3187 return status; 3188 } 3189 3190 /** 3191 * igb_probe - Device Initialization Routine 3192 * @pdev: PCI device information struct 3193 * @ent: entry in igb_pci_tbl 3194 * 3195 * Returns 0 on success, negative on failure 3196 * 3197 * igb_probe initializes an adapter identified by a pci_dev structure. 3198 * The OS initialization, configuring of the adapter private structure, 3199 * and a hardware reset occur. 3200 **/ 3201 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3202 { 3203 struct net_device *netdev; 3204 struct igb_adapter *adapter; 3205 struct e1000_hw *hw; 3206 u16 eeprom_data = 0; 3207 s32 ret_val; 3208 static int global_quad_port_a; /* global quad port a indication */ 3209 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3210 u8 part_str[E1000_PBANUM_LENGTH]; 3211 int err; 3212 3213 /* Catch broken hardware that put the wrong VF device ID in 3214 * the PCIe SR-IOV capability. 3215 */ 3216 if (pdev->is_virtfn) { 3217 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3218 pci_name(pdev), pdev->vendor, pdev->device); 3219 return -EINVAL; 3220 } 3221 3222 err = pci_enable_device_mem(pdev); 3223 if (err) 3224 return err; 3225 3226 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3227 if (err) { 3228 dev_err(&pdev->dev, 3229 "No usable DMA configuration, aborting\n"); 3230 goto err_dma; 3231 } 3232 3233 err = pci_request_mem_regions(pdev, igb_driver_name); 3234 if (err) 3235 goto err_pci_reg; 3236 3237 pci_set_master(pdev); 3238 pci_save_state(pdev); 3239 3240 err = -ENOMEM; 3241 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3242 IGB_MAX_TX_QUEUES); 3243 if (!netdev) 3244 goto err_alloc_etherdev; 3245 3246 SET_NETDEV_DEV(netdev, &pdev->dev); 3247 3248 pci_set_drvdata(pdev, netdev); 3249 adapter = netdev_priv(netdev); 3250 adapter->netdev = netdev; 3251 adapter->pdev = pdev; 3252 hw = &adapter->hw; 3253 hw->back = adapter; 3254 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3255 3256 err = -EIO; 3257 adapter->io_addr = pci_iomap(pdev, 0, 0); 3258 if (!adapter->io_addr) 3259 goto err_ioremap; 3260 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3261 hw->hw_addr = adapter->io_addr; 3262 3263 netdev->netdev_ops = &igb_netdev_ops; 3264 igb_set_ethtool_ops(netdev); 3265 netdev->watchdog_timeo = 5 * HZ; 3266 3267 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3268 3269 netdev->mem_start = pci_resource_start(pdev, 0); 3270 netdev->mem_end = pci_resource_end(pdev, 0); 3271 3272 /* PCI config space info */ 3273 hw->vendor_id = pdev->vendor; 3274 hw->device_id = pdev->device; 3275 hw->revision_id = pdev->revision; 3276 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3277 hw->subsystem_device_id = pdev->subsystem_device; 3278 3279 /* Copy the default MAC, PHY and NVM function pointers */ 3280 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3281 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3282 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3283 /* Initialize skew-specific constants */ 3284 err = ei->get_invariants(hw); 3285 if (err) 3286 goto err_sw_init; 3287 3288 /* setup the private structure */ 3289 err = igb_sw_init(adapter); 3290 if (err) 3291 goto err_sw_init; 3292 3293 igb_get_bus_info_pcie(hw); 3294 3295 hw->phy.autoneg_wait_to_complete = false; 3296 3297 /* Copper options */ 3298 if (hw->phy.media_type == e1000_media_type_copper) { 3299 hw->phy.mdix = AUTO_ALL_MODES; 3300 hw->phy.disable_polarity_correction = false; 3301 hw->phy.ms_type = e1000_ms_hw_default; 3302 } 3303 3304 if (igb_check_reset_block(hw)) 3305 dev_info(&pdev->dev, 3306 "PHY reset is blocked due to SOL/IDER session.\n"); 3307 3308 /* features is initialized to 0 in allocation, it might have bits 3309 * set by igb_sw_init so we should use an or instead of an 3310 * assignment. 3311 */ 3312 netdev->features |= NETIF_F_SG | 3313 NETIF_F_TSO | 3314 NETIF_F_TSO6 | 3315 NETIF_F_RXHASH | 3316 NETIF_F_RXCSUM | 3317 NETIF_F_HW_CSUM; 3318 3319 if (hw->mac.type >= e1000_82576) 3320 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3321 3322 if (hw->mac.type >= e1000_i350) 3323 netdev->features |= NETIF_F_HW_TC; 3324 3325 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3326 NETIF_F_GSO_GRE_CSUM | \ 3327 NETIF_F_GSO_IPXIP4 | \ 3328 NETIF_F_GSO_IPXIP6 | \ 3329 NETIF_F_GSO_UDP_TUNNEL | \ 3330 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3331 3332 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3333 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3334 3335 /* copy netdev features into list of user selectable features */ 3336 netdev->hw_features |= netdev->features | 3337 NETIF_F_HW_VLAN_CTAG_RX | 3338 NETIF_F_HW_VLAN_CTAG_TX | 3339 NETIF_F_RXALL; 3340 3341 if (hw->mac.type >= e1000_i350) 3342 netdev->hw_features |= NETIF_F_NTUPLE; 3343 3344 netdev->features |= NETIF_F_HIGHDMA; 3345 3346 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3347 netdev->mpls_features |= NETIF_F_HW_CSUM; 3348 netdev->hw_enc_features |= netdev->vlan_features; 3349 3350 /* set this bit last since it cannot be part of vlan_features */ 3351 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3352 NETIF_F_HW_VLAN_CTAG_RX | 3353 NETIF_F_HW_VLAN_CTAG_TX; 3354 3355 netdev->priv_flags |= IFF_SUPP_NOFCS; 3356 3357 netdev->priv_flags |= IFF_UNICAST_FLT; 3358 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3359 3360 /* MTU range: 68 - 9216 */ 3361 netdev->min_mtu = ETH_MIN_MTU; 3362 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3363 3364 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3365 3366 /* before reading the NVM, reset the controller to put the device in a 3367 * known good starting state 3368 */ 3369 hw->mac.ops.reset_hw(hw); 3370 3371 /* make sure the NVM is good , i211/i210 parts can have special NVM 3372 * that doesn't contain a checksum 3373 */ 3374 switch (hw->mac.type) { 3375 case e1000_i210: 3376 case e1000_i211: 3377 if (igb_get_flash_presence_i210(hw)) { 3378 if (hw->nvm.ops.validate(hw) < 0) { 3379 dev_err(&pdev->dev, 3380 "The NVM Checksum Is Not Valid\n"); 3381 err = -EIO; 3382 goto err_eeprom; 3383 } 3384 } 3385 break; 3386 default: 3387 if (hw->nvm.ops.validate(hw) < 0) { 3388 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3389 err = -EIO; 3390 goto err_eeprom; 3391 } 3392 break; 3393 } 3394 3395 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3396 /* copy the MAC address out of the NVM */ 3397 if (hw->mac.ops.read_mac_addr(hw)) 3398 dev_err(&pdev->dev, "NVM Read Error\n"); 3399 } 3400 3401 eth_hw_addr_set(netdev, hw->mac.addr); 3402 3403 if (!is_valid_ether_addr(netdev->dev_addr)) { 3404 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3405 err = -EIO; 3406 goto err_eeprom; 3407 } 3408 3409 igb_set_default_mac_filter(adapter); 3410 3411 /* get firmware version for ethtool -i */ 3412 igb_set_fw_version(adapter); 3413 3414 /* configure RXPBSIZE and TXPBSIZE */ 3415 if (hw->mac.type == e1000_i210) { 3416 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3417 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3418 } 3419 3420 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3421 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3422 3423 INIT_WORK(&adapter->reset_task, igb_reset_task); 3424 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3425 3426 /* Initialize link properties that are user-changeable */ 3427 adapter->fc_autoneg = true; 3428 hw->mac.autoneg = true; 3429 hw->phy.autoneg_advertised = 0x2f; 3430 3431 hw->fc.requested_mode = e1000_fc_default; 3432 hw->fc.current_mode = e1000_fc_default; 3433 3434 igb_validate_mdi_setting(hw); 3435 3436 /* By default, support wake on port A */ 3437 if (hw->bus.func == 0) 3438 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3439 3440 /* Check the NVM for wake support on non-port A ports */ 3441 if (hw->mac.type >= e1000_82580) 3442 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3443 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3444 &eeprom_data); 3445 else if (hw->bus.func == 1) 3446 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3447 3448 if (eeprom_data & IGB_EEPROM_APME) 3449 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3450 3451 /* now that we have the eeprom settings, apply the special cases where 3452 * the eeprom may be wrong or the board simply won't support wake on 3453 * lan on a particular port 3454 */ 3455 switch (pdev->device) { 3456 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3457 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3458 break; 3459 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3460 case E1000_DEV_ID_82576_FIBER: 3461 case E1000_DEV_ID_82576_SERDES: 3462 /* Wake events only supported on port A for dual fiber 3463 * regardless of eeprom setting 3464 */ 3465 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3466 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3467 break; 3468 case E1000_DEV_ID_82576_QUAD_COPPER: 3469 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3470 /* if quad port adapter, disable WoL on all but port A */ 3471 if (global_quad_port_a != 0) 3472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3473 else 3474 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3475 /* Reset for multiple quad port adapters */ 3476 if (++global_quad_port_a == 4) 3477 global_quad_port_a = 0; 3478 break; 3479 default: 3480 /* If the device can't wake, don't set software support */ 3481 if (!device_can_wakeup(&adapter->pdev->dev)) 3482 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3483 } 3484 3485 /* initialize the wol settings based on the eeprom settings */ 3486 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3487 adapter->wol |= E1000_WUFC_MAG; 3488 3489 /* Some vendors want WoL disabled by default, but still supported */ 3490 if ((hw->mac.type == e1000_i350) && 3491 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3492 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3493 adapter->wol = 0; 3494 } 3495 3496 /* Some vendors want the ability to Use the EEPROM setting as 3497 * enable/disable only, and not for capability 3498 */ 3499 if (((hw->mac.type == e1000_i350) || 3500 (hw->mac.type == e1000_i354)) && 3501 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3502 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3503 adapter->wol = 0; 3504 } 3505 if (hw->mac.type == e1000_i350) { 3506 if (((pdev->subsystem_device == 0x5001) || 3507 (pdev->subsystem_device == 0x5002)) && 3508 (hw->bus.func == 0)) { 3509 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3510 adapter->wol = 0; 3511 } 3512 if (pdev->subsystem_device == 0x1F52) 3513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3514 } 3515 3516 device_set_wakeup_enable(&adapter->pdev->dev, 3517 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3518 3519 /* reset the hardware with the new settings */ 3520 igb_reset(adapter); 3521 3522 /* Init the I2C interface */ 3523 err = igb_init_i2c(adapter); 3524 if (err) { 3525 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3526 goto err_eeprom; 3527 } 3528 3529 /* let the f/w know that the h/w is now under the control of the 3530 * driver. 3531 */ 3532 igb_get_hw_control(adapter); 3533 3534 strcpy(netdev->name, "eth%d"); 3535 err = register_netdev(netdev); 3536 if (err) 3537 goto err_register; 3538 3539 /* carrier off reporting is important to ethtool even BEFORE open */ 3540 netif_carrier_off(netdev); 3541 3542 #ifdef CONFIG_IGB_DCA 3543 if (dca_add_requester(&pdev->dev) == 0) { 3544 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3545 dev_info(&pdev->dev, "DCA enabled\n"); 3546 igb_setup_dca(adapter); 3547 } 3548 3549 #endif 3550 #ifdef CONFIG_IGB_HWMON 3551 /* Initialize the thermal sensor on i350 devices. */ 3552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3553 u16 ets_word; 3554 3555 /* Read the NVM to determine if this i350 device supports an 3556 * external thermal sensor. 3557 */ 3558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3559 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3560 adapter->ets = true; 3561 else 3562 adapter->ets = false; 3563 /* Only enable I2C bit banging if an external thermal 3564 * sensor is supported. 3565 */ 3566 if (adapter->ets) 3567 igb_set_i2c_bb(hw); 3568 hw->mac.ops.init_thermal_sensor_thresh(hw); 3569 if (igb_sysfs_init(adapter)) 3570 dev_err(&pdev->dev, 3571 "failed to allocate sysfs resources\n"); 3572 } else { 3573 adapter->ets = false; 3574 } 3575 #endif 3576 /* Check if Media Autosense is enabled */ 3577 adapter->ei = *ei; 3578 if (hw->dev_spec._82575.mas_capable) 3579 igb_init_mas(adapter); 3580 3581 /* do hw tstamp init after resetting */ 3582 igb_ptp_init(adapter); 3583 3584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3585 /* print bus type/speed/width info, not applicable to i354 */ 3586 if (hw->mac.type != e1000_i354) { 3587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3588 netdev->name, 3589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3591 "unknown"), 3592 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3593 "Width x4" : 3594 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3595 "Width x2" : 3596 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3597 "Width x1" : "unknown"), netdev->dev_addr); 3598 } 3599 3600 if ((hw->mac.type == e1000_82576 && 3601 rd32(E1000_EECD) & E1000_EECD_PRES) || 3602 (hw->mac.type >= e1000_i210 || 3603 igb_get_flash_presence_i210(hw))) { 3604 ret_val = igb_read_part_string(hw, part_str, 3605 E1000_PBANUM_LENGTH); 3606 } else { 3607 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3608 } 3609 3610 if (ret_val) 3611 strcpy(part_str, "Unknown"); 3612 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3613 dev_info(&pdev->dev, 3614 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3615 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3616 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3617 adapter->num_rx_queues, adapter->num_tx_queues); 3618 if (hw->phy.media_type == e1000_media_type_copper) { 3619 switch (hw->mac.type) { 3620 case e1000_i350: 3621 case e1000_i210: 3622 case e1000_i211: 3623 /* Enable EEE for internal copper PHY devices */ 3624 err = igb_set_eee_i350(hw, true, true); 3625 if ((!err) && 3626 (!hw->dev_spec._82575.eee_disable)) { 3627 adapter->eee_advert = 3628 MDIO_EEE_100TX | MDIO_EEE_1000T; 3629 adapter->flags |= IGB_FLAG_EEE; 3630 } 3631 break; 3632 case e1000_i354: 3633 if ((rd32(E1000_CTRL_EXT) & 3634 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3635 err = igb_set_eee_i354(hw, true, true); 3636 if ((!err) && 3637 (!hw->dev_spec._82575.eee_disable)) { 3638 adapter->eee_advert = 3639 MDIO_EEE_100TX | MDIO_EEE_1000T; 3640 adapter->flags |= IGB_FLAG_EEE; 3641 } 3642 } 3643 break; 3644 default: 3645 break; 3646 } 3647 } 3648 3649 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3650 3651 pm_runtime_put_noidle(&pdev->dev); 3652 return 0; 3653 3654 err_register: 3655 igb_release_hw_control(adapter); 3656 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3657 err_eeprom: 3658 if (!igb_check_reset_block(hw)) 3659 igb_reset_phy(hw); 3660 3661 if (hw->flash_address) 3662 iounmap(hw->flash_address); 3663 err_sw_init: 3664 kfree(adapter->mac_table); 3665 kfree(adapter->shadow_vfta); 3666 igb_clear_interrupt_scheme(adapter); 3667 #ifdef CONFIG_PCI_IOV 3668 igb_disable_sriov(pdev); 3669 #endif 3670 pci_iounmap(pdev, adapter->io_addr); 3671 err_ioremap: 3672 free_netdev(netdev); 3673 err_alloc_etherdev: 3674 pci_release_mem_regions(pdev); 3675 err_pci_reg: 3676 err_dma: 3677 pci_disable_device(pdev); 3678 return err; 3679 } 3680 3681 #ifdef CONFIG_PCI_IOV 3682 static int igb_disable_sriov(struct pci_dev *pdev) 3683 { 3684 struct net_device *netdev = pci_get_drvdata(pdev); 3685 struct igb_adapter *adapter = netdev_priv(netdev); 3686 struct e1000_hw *hw = &adapter->hw; 3687 unsigned long flags; 3688 3689 /* reclaim resources allocated to VFs */ 3690 if (adapter->vf_data) { 3691 /* disable iov and allow time for transactions to clear */ 3692 if (pci_vfs_assigned(pdev)) { 3693 dev_warn(&pdev->dev, 3694 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3695 return -EPERM; 3696 } else { 3697 pci_disable_sriov(pdev); 3698 msleep(500); 3699 } 3700 spin_lock_irqsave(&adapter->vfs_lock, flags); 3701 kfree(adapter->vf_mac_list); 3702 adapter->vf_mac_list = NULL; 3703 kfree(adapter->vf_data); 3704 adapter->vf_data = NULL; 3705 adapter->vfs_allocated_count = 0; 3706 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3707 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3708 wrfl(); 3709 msleep(100); 3710 dev_info(&pdev->dev, "IOV Disabled\n"); 3711 3712 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3713 adapter->flags |= IGB_FLAG_DMAC; 3714 } 3715 3716 return 0; 3717 } 3718 3719 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3720 { 3721 struct net_device *netdev = pci_get_drvdata(pdev); 3722 struct igb_adapter *adapter = netdev_priv(netdev); 3723 int old_vfs = pci_num_vf(pdev); 3724 struct vf_mac_filter *mac_list; 3725 int err = 0; 3726 int num_vf_mac_filters, i; 3727 3728 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3729 err = -EPERM; 3730 goto out; 3731 } 3732 if (!num_vfs) 3733 goto out; 3734 3735 if (old_vfs) { 3736 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3737 old_vfs, max_vfs); 3738 adapter->vfs_allocated_count = old_vfs; 3739 } else 3740 adapter->vfs_allocated_count = num_vfs; 3741 3742 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3743 sizeof(struct vf_data_storage), GFP_KERNEL); 3744 3745 /* if allocation failed then we do not support SR-IOV */ 3746 if (!adapter->vf_data) { 3747 adapter->vfs_allocated_count = 0; 3748 err = -ENOMEM; 3749 goto out; 3750 } 3751 3752 /* Due to the limited number of RAR entries calculate potential 3753 * number of MAC filters available for the VFs. Reserve entries 3754 * for PF default MAC, PF MAC filters and at least one RAR entry 3755 * for each VF for VF MAC. 3756 */ 3757 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3758 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3759 adapter->vfs_allocated_count); 3760 3761 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3762 sizeof(struct vf_mac_filter), 3763 GFP_KERNEL); 3764 3765 mac_list = adapter->vf_mac_list; 3766 INIT_LIST_HEAD(&adapter->vf_macs.l); 3767 3768 if (adapter->vf_mac_list) { 3769 /* Initialize list of VF MAC filters */ 3770 for (i = 0; i < num_vf_mac_filters; i++) { 3771 mac_list->vf = -1; 3772 mac_list->free = true; 3773 list_add(&mac_list->l, &adapter->vf_macs.l); 3774 mac_list++; 3775 } 3776 } else { 3777 /* If we could not allocate memory for the VF MAC filters 3778 * we can continue without this feature but warn user. 3779 */ 3780 dev_err(&pdev->dev, 3781 "Unable to allocate memory for VF MAC filter list\n"); 3782 } 3783 3784 /* only call pci_enable_sriov() if no VFs are allocated already */ 3785 if (!old_vfs) { 3786 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3787 if (err) 3788 goto err_out; 3789 } 3790 dev_info(&pdev->dev, "%d VFs allocated\n", 3791 adapter->vfs_allocated_count); 3792 for (i = 0; i < adapter->vfs_allocated_count; i++) 3793 igb_vf_configure(adapter, i); 3794 3795 /* DMA Coalescing is not supported in IOV mode. */ 3796 adapter->flags &= ~IGB_FLAG_DMAC; 3797 goto out; 3798 3799 err_out: 3800 kfree(adapter->vf_mac_list); 3801 adapter->vf_mac_list = NULL; 3802 kfree(adapter->vf_data); 3803 adapter->vf_data = NULL; 3804 adapter->vfs_allocated_count = 0; 3805 out: 3806 return err; 3807 } 3808 3809 #endif 3810 /** 3811 * igb_remove_i2c - Cleanup I2C interface 3812 * @adapter: pointer to adapter structure 3813 **/ 3814 static void igb_remove_i2c(struct igb_adapter *adapter) 3815 { 3816 /* free the adapter bus structure */ 3817 i2c_del_adapter(&adapter->i2c_adap); 3818 } 3819 3820 /** 3821 * igb_remove - Device Removal Routine 3822 * @pdev: PCI device information struct 3823 * 3824 * igb_remove is called by the PCI subsystem to alert the driver 3825 * that it should release a PCI device. The could be caused by a 3826 * Hot-Plug event, or because the driver is going to be removed from 3827 * memory. 3828 **/ 3829 static void igb_remove(struct pci_dev *pdev) 3830 { 3831 struct net_device *netdev = pci_get_drvdata(pdev); 3832 struct igb_adapter *adapter = netdev_priv(netdev); 3833 struct e1000_hw *hw = &adapter->hw; 3834 3835 pm_runtime_get_noresume(&pdev->dev); 3836 #ifdef CONFIG_IGB_HWMON 3837 igb_sysfs_exit(adapter); 3838 #endif 3839 igb_remove_i2c(adapter); 3840 igb_ptp_stop(adapter); 3841 /* The watchdog timer may be rescheduled, so explicitly 3842 * disable watchdog from being rescheduled. 3843 */ 3844 set_bit(__IGB_DOWN, &adapter->state); 3845 del_timer_sync(&adapter->watchdog_timer); 3846 del_timer_sync(&adapter->phy_info_timer); 3847 3848 cancel_work_sync(&adapter->reset_task); 3849 cancel_work_sync(&adapter->watchdog_task); 3850 3851 #ifdef CONFIG_IGB_DCA 3852 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3853 dev_info(&pdev->dev, "DCA disabled\n"); 3854 dca_remove_requester(&pdev->dev); 3855 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3856 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3857 } 3858 #endif 3859 3860 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3861 * would have already happened in close and is redundant. 3862 */ 3863 igb_release_hw_control(adapter); 3864 3865 #ifdef CONFIG_PCI_IOV 3866 rtnl_lock(); 3867 igb_disable_sriov(pdev); 3868 rtnl_unlock(); 3869 #endif 3870 3871 unregister_netdev(netdev); 3872 3873 igb_clear_interrupt_scheme(adapter); 3874 3875 pci_iounmap(pdev, adapter->io_addr); 3876 if (hw->flash_address) 3877 iounmap(hw->flash_address); 3878 pci_release_mem_regions(pdev); 3879 3880 kfree(adapter->mac_table); 3881 kfree(adapter->shadow_vfta); 3882 free_netdev(netdev); 3883 3884 pci_disable_device(pdev); 3885 } 3886 3887 /** 3888 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3889 * @adapter: board private structure to initialize 3890 * 3891 * This function initializes the vf specific data storage and then attempts to 3892 * allocate the VFs. The reason for ordering it this way is because it is much 3893 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3894 * the memory for the VFs. 3895 **/ 3896 static void igb_probe_vfs(struct igb_adapter *adapter) 3897 { 3898 #ifdef CONFIG_PCI_IOV 3899 struct pci_dev *pdev = adapter->pdev; 3900 struct e1000_hw *hw = &adapter->hw; 3901 3902 /* Virtualization features not supported on i210 family. */ 3903 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3904 return; 3905 3906 /* Of the below we really only want the effect of getting 3907 * IGB_FLAG_HAS_MSIX set (if available), without which 3908 * igb_enable_sriov() has no effect. 3909 */ 3910 igb_set_interrupt_capability(adapter, true); 3911 igb_reset_interrupt_capability(adapter); 3912 3913 pci_sriov_set_totalvfs(pdev, 7); 3914 igb_enable_sriov(pdev, max_vfs); 3915 3916 #endif /* CONFIG_PCI_IOV */ 3917 } 3918 3919 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3920 { 3921 struct e1000_hw *hw = &adapter->hw; 3922 unsigned int max_rss_queues; 3923 3924 /* Determine the maximum number of RSS queues supported. */ 3925 switch (hw->mac.type) { 3926 case e1000_i211: 3927 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3928 break; 3929 case e1000_82575: 3930 case e1000_i210: 3931 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3932 break; 3933 case e1000_i350: 3934 /* I350 cannot do RSS and SR-IOV at the same time */ 3935 if (!!adapter->vfs_allocated_count) { 3936 max_rss_queues = 1; 3937 break; 3938 } 3939 fallthrough; 3940 case e1000_82576: 3941 if (!!adapter->vfs_allocated_count) { 3942 max_rss_queues = 2; 3943 break; 3944 } 3945 fallthrough; 3946 case e1000_82580: 3947 case e1000_i354: 3948 default: 3949 max_rss_queues = IGB_MAX_RX_QUEUES; 3950 break; 3951 } 3952 3953 return max_rss_queues; 3954 } 3955 3956 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3957 { 3958 u32 max_rss_queues; 3959 3960 max_rss_queues = igb_get_max_rss_queues(adapter); 3961 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3962 3963 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3964 } 3965 3966 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3967 const u32 max_rss_queues) 3968 { 3969 struct e1000_hw *hw = &adapter->hw; 3970 3971 /* Determine if we need to pair queues. */ 3972 switch (hw->mac.type) { 3973 case e1000_82575: 3974 case e1000_i211: 3975 /* Device supports enough interrupts without queue pairing. */ 3976 break; 3977 case e1000_82576: 3978 case e1000_82580: 3979 case e1000_i350: 3980 case e1000_i354: 3981 case e1000_i210: 3982 default: 3983 /* If rss_queues > half of max_rss_queues, pair the queues in 3984 * order to conserve interrupts due to limited supply. 3985 */ 3986 if (adapter->rss_queues > (max_rss_queues / 2)) 3987 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3988 else 3989 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3990 break; 3991 } 3992 } 3993 3994 /** 3995 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3996 * @adapter: board private structure to initialize 3997 * 3998 * igb_sw_init initializes the Adapter private data structure. 3999 * Fields are initialized based on PCI device information and 4000 * OS network device settings (MTU size). 4001 **/ 4002 static int igb_sw_init(struct igb_adapter *adapter) 4003 { 4004 struct e1000_hw *hw = &adapter->hw; 4005 struct net_device *netdev = adapter->netdev; 4006 struct pci_dev *pdev = adapter->pdev; 4007 4008 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4009 4010 /* set default ring sizes */ 4011 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4012 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4013 4014 /* set default ITR values */ 4015 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4016 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4017 4018 /* set default work limits */ 4019 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4020 4021 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4022 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4023 4024 spin_lock_init(&adapter->nfc_lock); 4025 spin_lock_init(&adapter->stats64_lock); 4026 4027 /* init spinlock to avoid concurrency of VF resources */ 4028 spin_lock_init(&adapter->vfs_lock); 4029 #ifdef CONFIG_PCI_IOV 4030 switch (hw->mac.type) { 4031 case e1000_82576: 4032 case e1000_i350: 4033 if (max_vfs > 7) { 4034 dev_warn(&pdev->dev, 4035 "Maximum of 7 VFs per PF, using max\n"); 4036 max_vfs = adapter->vfs_allocated_count = 7; 4037 } else 4038 adapter->vfs_allocated_count = max_vfs; 4039 if (adapter->vfs_allocated_count) 4040 dev_warn(&pdev->dev, 4041 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4042 break; 4043 default: 4044 break; 4045 } 4046 #endif /* CONFIG_PCI_IOV */ 4047 4048 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4049 adapter->flags |= IGB_FLAG_HAS_MSIX; 4050 4051 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4052 sizeof(struct igb_mac_addr), 4053 GFP_KERNEL); 4054 if (!adapter->mac_table) 4055 return -ENOMEM; 4056 4057 igb_probe_vfs(adapter); 4058 4059 igb_init_queue_configuration(adapter); 4060 4061 /* Setup and initialize a copy of the hw vlan table array */ 4062 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4063 GFP_KERNEL); 4064 if (!adapter->shadow_vfta) 4065 return -ENOMEM; 4066 4067 /* This call may decrease the number of queues */ 4068 if (igb_init_interrupt_scheme(adapter, true)) { 4069 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4070 return -ENOMEM; 4071 } 4072 4073 /* Explicitly disable IRQ since the NIC can be in any state. */ 4074 igb_irq_disable(adapter); 4075 4076 if (hw->mac.type >= e1000_i350) 4077 adapter->flags &= ~IGB_FLAG_DMAC; 4078 4079 set_bit(__IGB_DOWN, &adapter->state); 4080 return 0; 4081 } 4082 4083 /** 4084 * __igb_open - Called when a network interface is made active 4085 * @netdev: network interface device structure 4086 * @resuming: indicates whether we are in a resume call 4087 * 4088 * Returns 0 on success, negative value on failure 4089 * 4090 * The open entry point is called when a network interface is made 4091 * active by the system (IFF_UP). At this point all resources needed 4092 * for transmit and receive operations are allocated, the interrupt 4093 * handler is registered with the OS, the watchdog timer is started, 4094 * and the stack is notified that the interface is ready. 4095 **/ 4096 static int __igb_open(struct net_device *netdev, bool resuming) 4097 { 4098 struct igb_adapter *adapter = netdev_priv(netdev); 4099 struct e1000_hw *hw = &adapter->hw; 4100 struct pci_dev *pdev = adapter->pdev; 4101 int err; 4102 int i; 4103 4104 /* disallow open during test */ 4105 if (test_bit(__IGB_TESTING, &adapter->state)) { 4106 WARN_ON(resuming); 4107 return -EBUSY; 4108 } 4109 4110 if (!resuming) 4111 pm_runtime_get_sync(&pdev->dev); 4112 4113 netif_carrier_off(netdev); 4114 4115 /* allocate transmit descriptors */ 4116 err = igb_setup_all_tx_resources(adapter); 4117 if (err) 4118 goto err_setup_tx; 4119 4120 /* allocate receive descriptors */ 4121 err = igb_setup_all_rx_resources(adapter); 4122 if (err) 4123 goto err_setup_rx; 4124 4125 igb_power_up_link(adapter); 4126 4127 /* before we allocate an interrupt, we must be ready to handle it. 4128 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4129 * as soon as we call pci_request_irq, so we have to setup our 4130 * clean_rx handler before we do so. 4131 */ 4132 igb_configure(adapter); 4133 4134 err = igb_request_irq(adapter); 4135 if (err) 4136 goto err_req_irq; 4137 4138 /* Notify the stack of the actual queue counts. */ 4139 err = netif_set_real_num_tx_queues(adapter->netdev, 4140 adapter->num_tx_queues); 4141 if (err) 4142 goto err_set_queues; 4143 4144 err = netif_set_real_num_rx_queues(adapter->netdev, 4145 adapter->num_rx_queues); 4146 if (err) 4147 goto err_set_queues; 4148 4149 /* From here on the code is the same as igb_up() */ 4150 clear_bit(__IGB_DOWN, &adapter->state); 4151 4152 for (i = 0; i < adapter->num_q_vectors; i++) 4153 napi_enable(&(adapter->q_vector[i]->napi)); 4154 4155 /* Clear any pending interrupts. */ 4156 rd32(E1000_TSICR); 4157 rd32(E1000_ICR); 4158 4159 igb_irq_enable(adapter); 4160 4161 /* notify VFs that reset has been completed */ 4162 if (adapter->vfs_allocated_count) { 4163 u32 reg_data = rd32(E1000_CTRL_EXT); 4164 4165 reg_data |= E1000_CTRL_EXT_PFRSTD; 4166 wr32(E1000_CTRL_EXT, reg_data); 4167 } 4168 4169 netif_tx_start_all_queues(netdev); 4170 4171 if (!resuming) 4172 pm_runtime_put(&pdev->dev); 4173 4174 /* start the watchdog. */ 4175 hw->mac.get_link_status = 1; 4176 schedule_work(&adapter->watchdog_task); 4177 4178 return 0; 4179 4180 err_set_queues: 4181 igb_free_irq(adapter); 4182 err_req_irq: 4183 igb_release_hw_control(adapter); 4184 igb_power_down_link(adapter); 4185 igb_free_all_rx_resources(adapter); 4186 err_setup_rx: 4187 igb_free_all_tx_resources(adapter); 4188 err_setup_tx: 4189 igb_reset(adapter); 4190 if (!resuming) 4191 pm_runtime_put(&pdev->dev); 4192 4193 return err; 4194 } 4195 4196 int igb_open(struct net_device *netdev) 4197 { 4198 return __igb_open(netdev, false); 4199 } 4200 4201 /** 4202 * __igb_close - Disables a network interface 4203 * @netdev: network interface device structure 4204 * @suspending: indicates we are in a suspend call 4205 * 4206 * Returns 0, this is not allowed to fail 4207 * 4208 * The close entry point is called when an interface is de-activated 4209 * by the OS. The hardware is still under the driver's control, but 4210 * needs to be disabled. A global MAC reset is issued to stop the 4211 * hardware, and all transmit and receive resources are freed. 4212 **/ 4213 static int __igb_close(struct net_device *netdev, bool suspending) 4214 { 4215 struct igb_adapter *adapter = netdev_priv(netdev); 4216 struct pci_dev *pdev = adapter->pdev; 4217 4218 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4219 4220 if (!suspending) 4221 pm_runtime_get_sync(&pdev->dev); 4222 4223 igb_down(adapter); 4224 igb_free_irq(adapter); 4225 4226 igb_free_all_tx_resources(adapter); 4227 igb_free_all_rx_resources(adapter); 4228 4229 if (!suspending) 4230 pm_runtime_put_sync(&pdev->dev); 4231 return 0; 4232 } 4233 4234 int igb_close(struct net_device *netdev) 4235 { 4236 if (netif_device_present(netdev) || netdev->dismantle) 4237 return __igb_close(netdev, false); 4238 return 0; 4239 } 4240 4241 /** 4242 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4243 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4244 * 4245 * Return 0 on success, negative on failure 4246 **/ 4247 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4248 { 4249 struct device *dev = tx_ring->dev; 4250 int size; 4251 4252 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4253 4254 tx_ring->tx_buffer_info = vmalloc(size); 4255 if (!tx_ring->tx_buffer_info) 4256 goto err; 4257 4258 /* round up to nearest 4K */ 4259 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4260 tx_ring->size = ALIGN(tx_ring->size, 4096); 4261 4262 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4263 &tx_ring->dma, GFP_KERNEL); 4264 if (!tx_ring->desc) 4265 goto err; 4266 4267 tx_ring->next_to_use = 0; 4268 tx_ring->next_to_clean = 0; 4269 4270 return 0; 4271 4272 err: 4273 vfree(tx_ring->tx_buffer_info); 4274 tx_ring->tx_buffer_info = NULL; 4275 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4276 return -ENOMEM; 4277 } 4278 4279 /** 4280 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4281 * (Descriptors) for all queues 4282 * @adapter: board private structure 4283 * 4284 * Return 0 on success, negative on failure 4285 **/ 4286 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4287 { 4288 struct pci_dev *pdev = adapter->pdev; 4289 int i, err = 0; 4290 4291 for (i = 0; i < adapter->num_tx_queues; i++) { 4292 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4293 if (err) { 4294 dev_err(&pdev->dev, 4295 "Allocation for Tx Queue %u failed\n", i); 4296 for (i--; i >= 0; i--) 4297 igb_free_tx_resources(adapter->tx_ring[i]); 4298 break; 4299 } 4300 } 4301 4302 return err; 4303 } 4304 4305 /** 4306 * igb_setup_tctl - configure the transmit control registers 4307 * @adapter: Board private structure 4308 **/ 4309 void igb_setup_tctl(struct igb_adapter *adapter) 4310 { 4311 struct e1000_hw *hw = &adapter->hw; 4312 u32 tctl; 4313 4314 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4315 wr32(E1000_TXDCTL(0), 0); 4316 4317 /* Program the Transmit Control Register */ 4318 tctl = rd32(E1000_TCTL); 4319 tctl &= ~E1000_TCTL_CT; 4320 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4321 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4322 4323 igb_config_collision_dist(hw); 4324 4325 /* Enable transmits */ 4326 tctl |= E1000_TCTL_EN; 4327 4328 wr32(E1000_TCTL, tctl); 4329 } 4330 4331 /** 4332 * igb_configure_tx_ring - Configure transmit ring after Reset 4333 * @adapter: board private structure 4334 * @ring: tx ring to configure 4335 * 4336 * Configure a transmit ring after a reset. 4337 **/ 4338 void igb_configure_tx_ring(struct igb_adapter *adapter, 4339 struct igb_ring *ring) 4340 { 4341 struct e1000_hw *hw = &adapter->hw; 4342 u32 txdctl = 0; 4343 u64 tdba = ring->dma; 4344 int reg_idx = ring->reg_idx; 4345 4346 wr32(E1000_TDLEN(reg_idx), 4347 ring->count * sizeof(union e1000_adv_tx_desc)); 4348 wr32(E1000_TDBAL(reg_idx), 4349 tdba & 0x00000000ffffffffULL); 4350 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4351 4352 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4353 wr32(E1000_TDH(reg_idx), 0); 4354 writel(0, ring->tail); 4355 4356 txdctl |= IGB_TX_PTHRESH; 4357 txdctl |= IGB_TX_HTHRESH << 8; 4358 txdctl |= IGB_TX_WTHRESH << 16; 4359 4360 /* reinitialize tx_buffer_info */ 4361 memset(ring->tx_buffer_info, 0, 4362 sizeof(struct igb_tx_buffer) * ring->count); 4363 4364 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4365 wr32(E1000_TXDCTL(reg_idx), txdctl); 4366 } 4367 4368 /** 4369 * igb_configure_tx - Configure transmit Unit after Reset 4370 * @adapter: board private structure 4371 * 4372 * Configure the Tx unit of the MAC after a reset. 4373 **/ 4374 static void igb_configure_tx(struct igb_adapter *adapter) 4375 { 4376 struct e1000_hw *hw = &adapter->hw; 4377 int i; 4378 4379 /* disable the queues */ 4380 for (i = 0; i < adapter->num_tx_queues; i++) 4381 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4382 4383 wrfl(); 4384 usleep_range(10000, 20000); 4385 4386 for (i = 0; i < adapter->num_tx_queues; i++) 4387 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4388 } 4389 4390 /** 4391 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4392 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4393 * 4394 * Returns 0 on success, negative on failure 4395 **/ 4396 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4397 { 4398 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4399 struct device *dev = rx_ring->dev; 4400 int size, res; 4401 4402 /* XDP RX-queue info */ 4403 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4404 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4405 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4406 rx_ring->queue_index, 0); 4407 if (res < 0) { 4408 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4409 rx_ring->queue_index); 4410 return res; 4411 } 4412 4413 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4414 4415 rx_ring->rx_buffer_info = vmalloc(size); 4416 if (!rx_ring->rx_buffer_info) 4417 goto err; 4418 4419 /* Round up to nearest 4K */ 4420 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4421 rx_ring->size = ALIGN(rx_ring->size, 4096); 4422 4423 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4424 &rx_ring->dma, GFP_KERNEL); 4425 if (!rx_ring->desc) 4426 goto err; 4427 4428 rx_ring->next_to_alloc = 0; 4429 rx_ring->next_to_clean = 0; 4430 rx_ring->next_to_use = 0; 4431 4432 rx_ring->xdp_prog = adapter->xdp_prog; 4433 4434 return 0; 4435 4436 err: 4437 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4438 vfree(rx_ring->rx_buffer_info); 4439 rx_ring->rx_buffer_info = NULL; 4440 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4441 return -ENOMEM; 4442 } 4443 4444 /** 4445 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4446 * (Descriptors) for all queues 4447 * @adapter: board private structure 4448 * 4449 * Return 0 on success, negative on failure 4450 **/ 4451 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4452 { 4453 struct pci_dev *pdev = adapter->pdev; 4454 int i, err = 0; 4455 4456 for (i = 0; i < adapter->num_rx_queues; i++) { 4457 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4458 if (err) { 4459 dev_err(&pdev->dev, 4460 "Allocation for Rx Queue %u failed\n", i); 4461 for (i--; i >= 0; i--) 4462 igb_free_rx_resources(adapter->rx_ring[i]); 4463 break; 4464 } 4465 } 4466 4467 return err; 4468 } 4469 4470 /** 4471 * igb_setup_mrqc - configure the multiple receive queue control registers 4472 * @adapter: Board private structure 4473 **/ 4474 static void igb_setup_mrqc(struct igb_adapter *adapter) 4475 { 4476 struct e1000_hw *hw = &adapter->hw; 4477 u32 mrqc, rxcsum; 4478 u32 j, num_rx_queues; 4479 u32 rss_key[10]; 4480 4481 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4482 for (j = 0; j < 10; j++) 4483 wr32(E1000_RSSRK(j), rss_key[j]); 4484 4485 num_rx_queues = adapter->rss_queues; 4486 4487 switch (hw->mac.type) { 4488 case e1000_82576: 4489 /* 82576 supports 2 RSS queues for SR-IOV */ 4490 if (adapter->vfs_allocated_count) 4491 num_rx_queues = 2; 4492 break; 4493 default: 4494 break; 4495 } 4496 4497 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4498 for (j = 0; j < IGB_RETA_SIZE; j++) 4499 adapter->rss_indir_tbl[j] = 4500 (j * num_rx_queues) / IGB_RETA_SIZE; 4501 adapter->rss_indir_tbl_init = num_rx_queues; 4502 } 4503 igb_write_rss_indir_tbl(adapter); 4504 4505 /* Disable raw packet checksumming so that RSS hash is placed in 4506 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4507 * offloads as they are enabled by default 4508 */ 4509 rxcsum = rd32(E1000_RXCSUM); 4510 rxcsum |= E1000_RXCSUM_PCSD; 4511 4512 if (adapter->hw.mac.type >= e1000_82576) 4513 /* Enable Receive Checksum Offload for SCTP */ 4514 rxcsum |= E1000_RXCSUM_CRCOFL; 4515 4516 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4517 wr32(E1000_RXCSUM, rxcsum); 4518 4519 /* Generate RSS hash based on packet types, TCP/UDP 4520 * port numbers and/or IPv4/v6 src and dst addresses 4521 */ 4522 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4523 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4524 E1000_MRQC_RSS_FIELD_IPV6 | 4525 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4526 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4527 4528 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4529 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4530 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4531 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4532 4533 /* If VMDq is enabled then we set the appropriate mode for that, else 4534 * we default to RSS so that an RSS hash is calculated per packet even 4535 * if we are only using one queue 4536 */ 4537 if (adapter->vfs_allocated_count) { 4538 if (hw->mac.type > e1000_82575) { 4539 /* Set the default pool for the PF's first queue */ 4540 u32 vtctl = rd32(E1000_VT_CTL); 4541 4542 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4543 E1000_VT_CTL_DISABLE_DEF_POOL); 4544 vtctl |= adapter->vfs_allocated_count << 4545 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4546 wr32(E1000_VT_CTL, vtctl); 4547 } 4548 if (adapter->rss_queues > 1) 4549 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4550 else 4551 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4552 } else { 4553 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4554 } 4555 igb_vmm_control(adapter); 4556 4557 wr32(E1000_MRQC, mrqc); 4558 } 4559 4560 /** 4561 * igb_setup_rctl - configure the receive control registers 4562 * @adapter: Board private structure 4563 **/ 4564 void igb_setup_rctl(struct igb_adapter *adapter) 4565 { 4566 struct e1000_hw *hw = &adapter->hw; 4567 u32 rctl; 4568 4569 rctl = rd32(E1000_RCTL); 4570 4571 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4572 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4573 4574 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4575 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4576 4577 /* enable stripping of CRC. It's unlikely this will break BMC 4578 * redirection as it did with e1000. Newer features require 4579 * that the HW strips the CRC. 4580 */ 4581 rctl |= E1000_RCTL_SECRC; 4582 4583 /* disable store bad packets and clear size bits. */ 4584 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4585 4586 /* enable LPE to allow for reception of jumbo frames */ 4587 rctl |= E1000_RCTL_LPE; 4588 4589 /* disable queue 0 to prevent tail write w/o re-config */ 4590 wr32(E1000_RXDCTL(0), 0); 4591 4592 /* Attention!!! For SR-IOV PF driver operations you must enable 4593 * queue drop for all VF and PF queues to prevent head of line blocking 4594 * if an un-trusted VF does not provide descriptors to hardware. 4595 */ 4596 if (adapter->vfs_allocated_count) { 4597 /* set all queue drop enable bits */ 4598 wr32(E1000_QDE, ALL_QUEUES); 4599 } 4600 4601 /* This is useful for sniffing bad packets. */ 4602 if (adapter->netdev->features & NETIF_F_RXALL) { 4603 /* UPE and MPE will be handled by normal PROMISC logic 4604 * in e1000e_set_rx_mode 4605 */ 4606 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4607 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4608 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4609 4610 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4611 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4612 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4613 * and that breaks VLANs. 4614 */ 4615 } 4616 4617 wr32(E1000_RCTL, rctl); 4618 } 4619 4620 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4621 int vfn) 4622 { 4623 struct e1000_hw *hw = &adapter->hw; 4624 u32 vmolr; 4625 4626 if (size > MAX_JUMBO_FRAME_SIZE) 4627 size = MAX_JUMBO_FRAME_SIZE; 4628 4629 vmolr = rd32(E1000_VMOLR(vfn)); 4630 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4631 vmolr |= size | E1000_VMOLR_LPE; 4632 wr32(E1000_VMOLR(vfn), vmolr); 4633 4634 return 0; 4635 } 4636 4637 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4638 int vfn, bool enable) 4639 { 4640 struct e1000_hw *hw = &adapter->hw; 4641 u32 val, reg; 4642 4643 if (hw->mac.type < e1000_82576) 4644 return; 4645 4646 if (hw->mac.type == e1000_i350) 4647 reg = E1000_DVMOLR(vfn); 4648 else 4649 reg = E1000_VMOLR(vfn); 4650 4651 val = rd32(reg); 4652 if (enable) 4653 val |= E1000_VMOLR_STRVLAN; 4654 else 4655 val &= ~(E1000_VMOLR_STRVLAN); 4656 wr32(reg, val); 4657 } 4658 4659 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4660 int vfn, bool aupe) 4661 { 4662 struct e1000_hw *hw = &adapter->hw; 4663 u32 vmolr; 4664 4665 /* This register exists only on 82576 and newer so if we are older then 4666 * we should exit and do nothing 4667 */ 4668 if (hw->mac.type < e1000_82576) 4669 return; 4670 4671 vmolr = rd32(E1000_VMOLR(vfn)); 4672 if (aupe) 4673 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4674 else 4675 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4676 4677 /* clear all bits that might not be set */ 4678 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4679 4680 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4681 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4682 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4683 * multicast packets 4684 */ 4685 if (vfn <= adapter->vfs_allocated_count) 4686 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4687 4688 wr32(E1000_VMOLR(vfn), vmolr); 4689 } 4690 4691 /** 4692 * igb_setup_srrctl - configure the split and replication receive control 4693 * registers 4694 * @adapter: Board private structure 4695 * @ring: receive ring to be configured 4696 **/ 4697 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4698 { 4699 struct e1000_hw *hw = &adapter->hw; 4700 int reg_idx = ring->reg_idx; 4701 u32 srrctl = 0; 4702 4703 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4704 if (ring_uses_large_buffer(ring)) 4705 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4706 else 4707 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4708 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4709 if (hw->mac.type >= e1000_82580) 4710 srrctl |= E1000_SRRCTL_TIMESTAMP; 4711 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4712 * queues and rx flow control is disabled 4713 */ 4714 if (adapter->vfs_allocated_count || 4715 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4716 adapter->num_rx_queues > 1)) 4717 srrctl |= E1000_SRRCTL_DROP_EN; 4718 4719 wr32(E1000_SRRCTL(reg_idx), srrctl); 4720 } 4721 4722 /** 4723 * igb_configure_rx_ring - Configure a receive ring after Reset 4724 * @adapter: board private structure 4725 * @ring: receive ring to be configured 4726 * 4727 * Configure the Rx unit of the MAC after a reset. 4728 **/ 4729 void igb_configure_rx_ring(struct igb_adapter *adapter, 4730 struct igb_ring *ring) 4731 { 4732 struct e1000_hw *hw = &adapter->hw; 4733 union e1000_adv_rx_desc *rx_desc; 4734 u64 rdba = ring->dma; 4735 int reg_idx = ring->reg_idx; 4736 u32 rxdctl = 0; 4737 4738 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4739 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4740 MEM_TYPE_PAGE_SHARED, NULL)); 4741 4742 /* disable the queue */ 4743 wr32(E1000_RXDCTL(reg_idx), 0); 4744 4745 /* Set DMA base address registers */ 4746 wr32(E1000_RDBAL(reg_idx), 4747 rdba & 0x00000000ffffffffULL); 4748 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4749 wr32(E1000_RDLEN(reg_idx), 4750 ring->count * sizeof(union e1000_adv_rx_desc)); 4751 4752 /* initialize head and tail */ 4753 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4754 wr32(E1000_RDH(reg_idx), 0); 4755 writel(0, ring->tail); 4756 4757 /* set descriptor configuration */ 4758 igb_setup_srrctl(adapter, ring); 4759 4760 /* set filtering for VMDQ pools */ 4761 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4762 4763 rxdctl |= IGB_RX_PTHRESH; 4764 rxdctl |= IGB_RX_HTHRESH << 8; 4765 rxdctl |= IGB_RX_WTHRESH << 16; 4766 4767 /* initialize rx_buffer_info */ 4768 memset(ring->rx_buffer_info, 0, 4769 sizeof(struct igb_rx_buffer) * ring->count); 4770 4771 /* initialize Rx descriptor 0 */ 4772 rx_desc = IGB_RX_DESC(ring, 0); 4773 rx_desc->wb.upper.length = 0; 4774 4775 /* enable receive descriptor fetching */ 4776 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4777 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4778 } 4779 4780 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4781 struct igb_ring *rx_ring) 4782 { 4783 /* set build_skb and buffer size flags */ 4784 clear_ring_build_skb_enabled(rx_ring); 4785 clear_ring_uses_large_buffer(rx_ring); 4786 4787 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4788 return; 4789 4790 set_ring_build_skb_enabled(rx_ring); 4791 4792 #if (PAGE_SIZE < 8192) 4793 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4794 return; 4795 4796 set_ring_uses_large_buffer(rx_ring); 4797 #endif 4798 } 4799 4800 /** 4801 * igb_configure_rx - Configure receive Unit after Reset 4802 * @adapter: board private structure 4803 * 4804 * Configure the Rx unit of the MAC after a reset. 4805 **/ 4806 static void igb_configure_rx(struct igb_adapter *adapter) 4807 { 4808 int i; 4809 4810 /* set the correct pool for the PF default MAC address in entry 0 */ 4811 igb_set_default_mac_filter(adapter); 4812 4813 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4814 * the Base and Length of the Rx Descriptor Ring 4815 */ 4816 for (i = 0; i < adapter->num_rx_queues; i++) { 4817 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4818 4819 igb_set_rx_buffer_len(adapter, rx_ring); 4820 igb_configure_rx_ring(adapter, rx_ring); 4821 } 4822 } 4823 4824 /** 4825 * igb_free_tx_resources - Free Tx Resources per Queue 4826 * @tx_ring: Tx descriptor ring for a specific queue 4827 * 4828 * Free all transmit software resources 4829 **/ 4830 void igb_free_tx_resources(struct igb_ring *tx_ring) 4831 { 4832 igb_clean_tx_ring(tx_ring); 4833 4834 vfree(tx_ring->tx_buffer_info); 4835 tx_ring->tx_buffer_info = NULL; 4836 4837 /* if not set, then don't free */ 4838 if (!tx_ring->desc) 4839 return; 4840 4841 dma_free_coherent(tx_ring->dev, tx_ring->size, 4842 tx_ring->desc, tx_ring->dma); 4843 4844 tx_ring->desc = NULL; 4845 } 4846 4847 /** 4848 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4849 * @adapter: board private structure 4850 * 4851 * Free all transmit software resources 4852 **/ 4853 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4854 { 4855 int i; 4856 4857 for (i = 0; i < adapter->num_tx_queues; i++) 4858 if (adapter->tx_ring[i]) 4859 igb_free_tx_resources(adapter->tx_ring[i]); 4860 } 4861 4862 /** 4863 * igb_clean_tx_ring - Free Tx Buffers 4864 * @tx_ring: ring to be cleaned 4865 **/ 4866 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4867 { 4868 u16 i = tx_ring->next_to_clean; 4869 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4870 4871 while (i != tx_ring->next_to_use) { 4872 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4873 4874 /* Free all the Tx ring sk_buffs or xdp frames */ 4875 if (tx_buffer->type == IGB_TYPE_SKB) 4876 dev_kfree_skb_any(tx_buffer->skb); 4877 else 4878 xdp_return_frame(tx_buffer->xdpf); 4879 4880 /* unmap skb header data */ 4881 dma_unmap_single(tx_ring->dev, 4882 dma_unmap_addr(tx_buffer, dma), 4883 dma_unmap_len(tx_buffer, len), 4884 DMA_TO_DEVICE); 4885 4886 /* check for eop_desc to determine the end of the packet */ 4887 eop_desc = tx_buffer->next_to_watch; 4888 tx_desc = IGB_TX_DESC(tx_ring, i); 4889 4890 /* unmap remaining buffers */ 4891 while (tx_desc != eop_desc) { 4892 tx_buffer++; 4893 tx_desc++; 4894 i++; 4895 if (unlikely(i == tx_ring->count)) { 4896 i = 0; 4897 tx_buffer = tx_ring->tx_buffer_info; 4898 tx_desc = IGB_TX_DESC(tx_ring, 0); 4899 } 4900 4901 /* unmap any remaining paged data */ 4902 if (dma_unmap_len(tx_buffer, len)) 4903 dma_unmap_page(tx_ring->dev, 4904 dma_unmap_addr(tx_buffer, dma), 4905 dma_unmap_len(tx_buffer, len), 4906 DMA_TO_DEVICE); 4907 } 4908 4909 tx_buffer->next_to_watch = NULL; 4910 4911 /* move us one more past the eop_desc for start of next pkt */ 4912 tx_buffer++; 4913 i++; 4914 if (unlikely(i == tx_ring->count)) { 4915 i = 0; 4916 tx_buffer = tx_ring->tx_buffer_info; 4917 } 4918 } 4919 4920 /* reset BQL for queue */ 4921 netdev_tx_reset_queue(txring_txq(tx_ring)); 4922 4923 /* reset next_to_use and next_to_clean */ 4924 tx_ring->next_to_use = 0; 4925 tx_ring->next_to_clean = 0; 4926 } 4927 4928 /** 4929 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4930 * @adapter: board private structure 4931 **/ 4932 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4933 { 4934 int i; 4935 4936 for (i = 0; i < adapter->num_tx_queues; i++) 4937 if (adapter->tx_ring[i]) 4938 igb_clean_tx_ring(adapter->tx_ring[i]); 4939 } 4940 4941 /** 4942 * igb_free_rx_resources - Free Rx Resources 4943 * @rx_ring: ring to clean the resources from 4944 * 4945 * Free all receive software resources 4946 **/ 4947 void igb_free_rx_resources(struct igb_ring *rx_ring) 4948 { 4949 igb_clean_rx_ring(rx_ring); 4950 4951 rx_ring->xdp_prog = NULL; 4952 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4953 vfree(rx_ring->rx_buffer_info); 4954 rx_ring->rx_buffer_info = NULL; 4955 4956 /* if not set, then don't free */ 4957 if (!rx_ring->desc) 4958 return; 4959 4960 dma_free_coherent(rx_ring->dev, rx_ring->size, 4961 rx_ring->desc, rx_ring->dma); 4962 4963 rx_ring->desc = NULL; 4964 } 4965 4966 /** 4967 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4968 * @adapter: board private structure 4969 * 4970 * Free all receive software resources 4971 **/ 4972 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4973 { 4974 int i; 4975 4976 for (i = 0; i < adapter->num_rx_queues; i++) 4977 if (adapter->rx_ring[i]) 4978 igb_free_rx_resources(adapter->rx_ring[i]); 4979 } 4980 4981 /** 4982 * igb_clean_rx_ring - Free Rx Buffers per Queue 4983 * @rx_ring: ring to free buffers from 4984 **/ 4985 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4986 { 4987 u16 i = rx_ring->next_to_clean; 4988 4989 dev_kfree_skb(rx_ring->skb); 4990 rx_ring->skb = NULL; 4991 4992 /* Free all the Rx ring sk_buffs */ 4993 while (i != rx_ring->next_to_alloc) { 4994 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4995 4996 /* Invalidate cache lines that may have been written to by 4997 * device so that we avoid corrupting memory. 4998 */ 4999 dma_sync_single_range_for_cpu(rx_ring->dev, 5000 buffer_info->dma, 5001 buffer_info->page_offset, 5002 igb_rx_bufsz(rx_ring), 5003 DMA_FROM_DEVICE); 5004 5005 /* free resources associated with mapping */ 5006 dma_unmap_page_attrs(rx_ring->dev, 5007 buffer_info->dma, 5008 igb_rx_pg_size(rx_ring), 5009 DMA_FROM_DEVICE, 5010 IGB_RX_DMA_ATTR); 5011 __page_frag_cache_drain(buffer_info->page, 5012 buffer_info->pagecnt_bias); 5013 5014 i++; 5015 if (i == rx_ring->count) 5016 i = 0; 5017 } 5018 5019 rx_ring->next_to_alloc = 0; 5020 rx_ring->next_to_clean = 0; 5021 rx_ring->next_to_use = 0; 5022 } 5023 5024 /** 5025 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5026 * @adapter: board private structure 5027 **/ 5028 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5029 { 5030 int i; 5031 5032 for (i = 0; i < adapter->num_rx_queues; i++) 5033 if (adapter->rx_ring[i]) 5034 igb_clean_rx_ring(adapter->rx_ring[i]); 5035 } 5036 5037 /** 5038 * igb_set_mac - Change the Ethernet Address of the NIC 5039 * @netdev: network interface device structure 5040 * @p: pointer to an address structure 5041 * 5042 * Returns 0 on success, negative on failure 5043 **/ 5044 static int igb_set_mac(struct net_device *netdev, void *p) 5045 { 5046 struct igb_adapter *adapter = netdev_priv(netdev); 5047 struct e1000_hw *hw = &adapter->hw; 5048 struct sockaddr *addr = p; 5049 5050 if (!is_valid_ether_addr(addr->sa_data)) 5051 return -EADDRNOTAVAIL; 5052 5053 eth_hw_addr_set(netdev, addr->sa_data); 5054 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5055 5056 /* set the correct pool for the new PF MAC address in entry 0 */ 5057 igb_set_default_mac_filter(adapter); 5058 5059 return 0; 5060 } 5061 5062 /** 5063 * igb_write_mc_addr_list - write multicast addresses to MTA 5064 * @netdev: network interface device structure 5065 * 5066 * Writes multicast address list to the MTA hash table. 5067 * Returns: -ENOMEM on failure 5068 * 0 on no addresses written 5069 * X on writing X addresses to MTA 5070 **/ 5071 static int igb_write_mc_addr_list(struct net_device *netdev) 5072 { 5073 struct igb_adapter *adapter = netdev_priv(netdev); 5074 struct e1000_hw *hw = &adapter->hw; 5075 struct netdev_hw_addr *ha; 5076 u8 *mta_list; 5077 int i; 5078 5079 if (netdev_mc_empty(netdev)) { 5080 /* nothing to program, so clear mc list */ 5081 igb_update_mc_addr_list(hw, NULL, 0); 5082 igb_restore_vf_multicasts(adapter); 5083 return 0; 5084 } 5085 5086 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5087 if (!mta_list) 5088 return -ENOMEM; 5089 5090 /* The shared function expects a packed array of only addresses. */ 5091 i = 0; 5092 netdev_for_each_mc_addr(ha, netdev) 5093 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5094 5095 igb_update_mc_addr_list(hw, mta_list, i); 5096 kfree(mta_list); 5097 5098 return netdev_mc_count(netdev); 5099 } 5100 5101 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5102 { 5103 struct e1000_hw *hw = &adapter->hw; 5104 u32 i, pf_id; 5105 5106 switch (hw->mac.type) { 5107 case e1000_i210: 5108 case e1000_i211: 5109 case e1000_i350: 5110 /* VLAN filtering needed for VLAN prio filter */ 5111 if (adapter->netdev->features & NETIF_F_NTUPLE) 5112 break; 5113 fallthrough; 5114 case e1000_82576: 5115 case e1000_82580: 5116 case e1000_i354: 5117 /* VLAN filtering needed for pool filtering */ 5118 if (adapter->vfs_allocated_count) 5119 break; 5120 fallthrough; 5121 default: 5122 return 1; 5123 } 5124 5125 /* We are already in VLAN promisc, nothing to do */ 5126 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5127 return 0; 5128 5129 if (!adapter->vfs_allocated_count) 5130 goto set_vfta; 5131 5132 /* Add PF to all active pools */ 5133 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5134 5135 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5136 u32 vlvf = rd32(E1000_VLVF(i)); 5137 5138 vlvf |= BIT(pf_id); 5139 wr32(E1000_VLVF(i), vlvf); 5140 } 5141 5142 set_vfta: 5143 /* Set all bits in the VLAN filter table array */ 5144 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5145 hw->mac.ops.write_vfta(hw, i, ~0U); 5146 5147 /* Set flag so we don't redo unnecessary work */ 5148 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5149 5150 return 0; 5151 } 5152 5153 #define VFTA_BLOCK_SIZE 8 5154 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5155 { 5156 struct e1000_hw *hw = &adapter->hw; 5157 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5158 u32 vid_start = vfta_offset * 32; 5159 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5160 u32 i, vid, word, bits, pf_id; 5161 5162 /* guarantee that we don't scrub out management VLAN */ 5163 vid = adapter->mng_vlan_id; 5164 if (vid >= vid_start && vid < vid_end) 5165 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5166 5167 if (!adapter->vfs_allocated_count) 5168 goto set_vfta; 5169 5170 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5171 5172 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5173 u32 vlvf = rd32(E1000_VLVF(i)); 5174 5175 /* pull VLAN ID from VLVF */ 5176 vid = vlvf & VLAN_VID_MASK; 5177 5178 /* only concern ourselves with a certain range */ 5179 if (vid < vid_start || vid >= vid_end) 5180 continue; 5181 5182 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5183 /* record VLAN ID in VFTA */ 5184 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5185 5186 /* if PF is part of this then continue */ 5187 if (test_bit(vid, adapter->active_vlans)) 5188 continue; 5189 } 5190 5191 /* remove PF from the pool */ 5192 bits = ~BIT(pf_id); 5193 bits &= rd32(E1000_VLVF(i)); 5194 wr32(E1000_VLVF(i), bits); 5195 } 5196 5197 set_vfta: 5198 /* extract values from active_vlans and write back to VFTA */ 5199 for (i = VFTA_BLOCK_SIZE; i--;) { 5200 vid = (vfta_offset + i) * 32; 5201 word = vid / BITS_PER_LONG; 5202 bits = vid % BITS_PER_LONG; 5203 5204 vfta[i] |= adapter->active_vlans[word] >> bits; 5205 5206 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5207 } 5208 } 5209 5210 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5211 { 5212 u32 i; 5213 5214 /* We are not in VLAN promisc, nothing to do */ 5215 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5216 return; 5217 5218 /* Set flag so we don't redo unnecessary work */ 5219 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5220 5221 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5222 igb_scrub_vfta(adapter, i); 5223 } 5224 5225 /** 5226 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5227 * @netdev: network interface device structure 5228 * 5229 * The set_rx_mode entry point is called whenever the unicast or multicast 5230 * address lists or the network interface flags are updated. This routine is 5231 * responsible for configuring the hardware for proper unicast, multicast, 5232 * promiscuous mode, and all-multi behavior. 5233 **/ 5234 static void igb_set_rx_mode(struct net_device *netdev) 5235 { 5236 struct igb_adapter *adapter = netdev_priv(netdev); 5237 struct e1000_hw *hw = &adapter->hw; 5238 unsigned int vfn = adapter->vfs_allocated_count; 5239 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5240 int count; 5241 5242 /* Check for Promiscuous and All Multicast modes */ 5243 if (netdev->flags & IFF_PROMISC) { 5244 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5245 vmolr |= E1000_VMOLR_MPME; 5246 5247 /* enable use of UTA filter to force packets to default pool */ 5248 if (hw->mac.type == e1000_82576) 5249 vmolr |= E1000_VMOLR_ROPE; 5250 } else { 5251 if (netdev->flags & IFF_ALLMULTI) { 5252 rctl |= E1000_RCTL_MPE; 5253 vmolr |= E1000_VMOLR_MPME; 5254 } else { 5255 /* Write addresses to the MTA, if the attempt fails 5256 * then we should just turn on promiscuous mode so 5257 * that we can at least receive multicast traffic 5258 */ 5259 count = igb_write_mc_addr_list(netdev); 5260 if (count < 0) { 5261 rctl |= E1000_RCTL_MPE; 5262 vmolr |= E1000_VMOLR_MPME; 5263 } else if (count) { 5264 vmolr |= E1000_VMOLR_ROMPE; 5265 } 5266 } 5267 } 5268 5269 /* Write addresses to available RAR registers, if there is not 5270 * sufficient space to store all the addresses then enable 5271 * unicast promiscuous mode 5272 */ 5273 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5274 rctl |= E1000_RCTL_UPE; 5275 vmolr |= E1000_VMOLR_ROPE; 5276 } 5277 5278 /* enable VLAN filtering by default */ 5279 rctl |= E1000_RCTL_VFE; 5280 5281 /* disable VLAN filtering for modes that require it */ 5282 if ((netdev->flags & IFF_PROMISC) || 5283 (netdev->features & NETIF_F_RXALL)) { 5284 /* if we fail to set all rules then just clear VFE */ 5285 if (igb_vlan_promisc_enable(adapter)) 5286 rctl &= ~E1000_RCTL_VFE; 5287 } else { 5288 igb_vlan_promisc_disable(adapter); 5289 } 5290 5291 /* update state of unicast, multicast, and VLAN filtering modes */ 5292 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5293 E1000_RCTL_VFE); 5294 wr32(E1000_RCTL, rctl); 5295 5296 #if (PAGE_SIZE < 8192) 5297 if (!adapter->vfs_allocated_count) { 5298 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5299 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5300 } 5301 #endif 5302 wr32(E1000_RLPML, rlpml); 5303 5304 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5305 * the VMOLR to enable the appropriate modes. Without this workaround 5306 * we will have issues with VLAN tag stripping not being done for frames 5307 * that are only arriving because we are the default pool 5308 */ 5309 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5310 return; 5311 5312 /* set UTA to appropriate mode */ 5313 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5314 5315 vmolr |= rd32(E1000_VMOLR(vfn)) & 5316 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5317 5318 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5319 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5320 #if (PAGE_SIZE < 8192) 5321 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5322 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5323 else 5324 #endif 5325 vmolr |= MAX_JUMBO_FRAME_SIZE; 5326 vmolr |= E1000_VMOLR_LPE; 5327 5328 wr32(E1000_VMOLR(vfn), vmolr); 5329 5330 igb_restore_vf_multicasts(adapter); 5331 } 5332 5333 static void igb_check_wvbr(struct igb_adapter *adapter) 5334 { 5335 struct e1000_hw *hw = &adapter->hw; 5336 u32 wvbr = 0; 5337 5338 switch (hw->mac.type) { 5339 case e1000_82576: 5340 case e1000_i350: 5341 wvbr = rd32(E1000_WVBR); 5342 if (!wvbr) 5343 return; 5344 break; 5345 default: 5346 break; 5347 } 5348 5349 adapter->wvbr |= wvbr; 5350 } 5351 5352 #define IGB_STAGGERED_QUEUE_OFFSET 8 5353 5354 static void igb_spoof_check(struct igb_adapter *adapter) 5355 { 5356 int j; 5357 5358 if (!adapter->wvbr) 5359 return; 5360 5361 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5362 if (adapter->wvbr & BIT(j) || 5363 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5364 dev_warn(&adapter->pdev->dev, 5365 "Spoof event(s) detected on VF %d\n", j); 5366 adapter->wvbr &= 5367 ~(BIT(j) | 5368 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5369 } 5370 } 5371 } 5372 5373 /* Need to wait a few seconds after link up to get diagnostic information from 5374 * the phy 5375 */ 5376 static void igb_update_phy_info(struct timer_list *t) 5377 { 5378 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5379 igb_get_phy_info(&adapter->hw); 5380 } 5381 5382 /** 5383 * igb_has_link - check shared code for link and determine up/down 5384 * @adapter: pointer to driver private info 5385 **/ 5386 bool igb_has_link(struct igb_adapter *adapter) 5387 { 5388 struct e1000_hw *hw = &adapter->hw; 5389 bool link_active = false; 5390 5391 /* get_link_status is set on LSC (link status) interrupt or 5392 * rx sequence error interrupt. get_link_status will stay 5393 * false until the e1000_check_for_link establishes link 5394 * for copper adapters ONLY 5395 */ 5396 switch (hw->phy.media_type) { 5397 case e1000_media_type_copper: 5398 if (!hw->mac.get_link_status) 5399 return true; 5400 fallthrough; 5401 case e1000_media_type_internal_serdes: 5402 hw->mac.ops.check_for_link(hw); 5403 link_active = !hw->mac.get_link_status; 5404 break; 5405 default: 5406 case e1000_media_type_unknown: 5407 break; 5408 } 5409 5410 if (((hw->mac.type == e1000_i210) || 5411 (hw->mac.type == e1000_i211)) && 5412 (hw->phy.id == I210_I_PHY_ID)) { 5413 if (!netif_carrier_ok(adapter->netdev)) { 5414 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5415 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5416 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5417 adapter->link_check_timeout = jiffies; 5418 } 5419 } 5420 5421 return link_active; 5422 } 5423 5424 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5425 { 5426 bool ret = false; 5427 u32 ctrl_ext, thstat; 5428 5429 /* check for thermal sensor event on i350 copper only */ 5430 if (hw->mac.type == e1000_i350) { 5431 thstat = rd32(E1000_THSTAT); 5432 ctrl_ext = rd32(E1000_CTRL_EXT); 5433 5434 if ((hw->phy.media_type == e1000_media_type_copper) && 5435 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5436 ret = !!(thstat & event); 5437 } 5438 5439 return ret; 5440 } 5441 5442 /** 5443 * igb_check_lvmmc - check for malformed packets received 5444 * and indicated in LVMMC register 5445 * @adapter: pointer to adapter 5446 **/ 5447 static void igb_check_lvmmc(struct igb_adapter *adapter) 5448 { 5449 struct e1000_hw *hw = &adapter->hw; 5450 u32 lvmmc; 5451 5452 lvmmc = rd32(E1000_LVMMC); 5453 if (lvmmc) { 5454 if (unlikely(net_ratelimit())) { 5455 netdev_warn(adapter->netdev, 5456 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5457 lvmmc); 5458 } 5459 } 5460 } 5461 5462 /** 5463 * igb_watchdog - Timer Call-back 5464 * @t: pointer to timer_list containing our private info pointer 5465 **/ 5466 static void igb_watchdog(struct timer_list *t) 5467 { 5468 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5469 /* Do the rest outside of interrupt context */ 5470 schedule_work(&adapter->watchdog_task); 5471 } 5472 5473 static void igb_watchdog_task(struct work_struct *work) 5474 { 5475 struct igb_adapter *adapter = container_of(work, 5476 struct igb_adapter, 5477 watchdog_task); 5478 struct e1000_hw *hw = &adapter->hw; 5479 struct e1000_phy_info *phy = &hw->phy; 5480 struct net_device *netdev = adapter->netdev; 5481 u32 link; 5482 int i; 5483 u32 connsw; 5484 u16 phy_data, retry_count = 20; 5485 5486 link = igb_has_link(adapter); 5487 5488 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5489 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5490 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5491 else 5492 link = false; 5493 } 5494 5495 /* Force link down if we have fiber to swap to */ 5496 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5497 if (hw->phy.media_type == e1000_media_type_copper) { 5498 connsw = rd32(E1000_CONNSW); 5499 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5500 link = 0; 5501 } 5502 } 5503 if (link) { 5504 /* Perform a reset if the media type changed. */ 5505 if (hw->dev_spec._82575.media_changed) { 5506 hw->dev_spec._82575.media_changed = false; 5507 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5508 igb_reset(adapter); 5509 } 5510 /* Cancel scheduled suspend requests. */ 5511 pm_runtime_resume(netdev->dev.parent); 5512 5513 if (!netif_carrier_ok(netdev)) { 5514 u32 ctrl; 5515 5516 hw->mac.ops.get_speed_and_duplex(hw, 5517 &adapter->link_speed, 5518 &adapter->link_duplex); 5519 5520 ctrl = rd32(E1000_CTRL); 5521 /* Links status message must follow this format */ 5522 netdev_info(netdev, 5523 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5524 netdev->name, 5525 adapter->link_speed, 5526 adapter->link_duplex == FULL_DUPLEX ? 5527 "Full" : "Half", 5528 (ctrl & E1000_CTRL_TFCE) && 5529 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5530 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5531 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5532 5533 /* disable EEE if enabled */ 5534 if ((adapter->flags & IGB_FLAG_EEE) && 5535 (adapter->link_duplex == HALF_DUPLEX)) { 5536 dev_info(&adapter->pdev->dev, 5537 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5538 adapter->hw.dev_spec._82575.eee_disable = true; 5539 adapter->flags &= ~IGB_FLAG_EEE; 5540 } 5541 5542 /* check if SmartSpeed worked */ 5543 igb_check_downshift(hw); 5544 if (phy->speed_downgraded) 5545 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5546 5547 /* check for thermal sensor event */ 5548 if (igb_thermal_sensor_event(hw, 5549 E1000_THSTAT_LINK_THROTTLE)) 5550 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5551 5552 /* adjust timeout factor according to speed/duplex */ 5553 adapter->tx_timeout_factor = 1; 5554 switch (adapter->link_speed) { 5555 case SPEED_10: 5556 adapter->tx_timeout_factor = 14; 5557 break; 5558 case SPEED_100: 5559 /* maybe add some timeout factor ? */ 5560 break; 5561 } 5562 5563 if (adapter->link_speed != SPEED_1000 || 5564 !hw->phy.ops.read_reg) 5565 goto no_wait; 5566 5567 /* wait for Remote receiver status OK */ 5568 retry_read_status: 5569 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5570 &phy_data)) { 5571 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5572 retry_count) { 5573 msleep(100); 5574 retry_count--; 5575 goto retry_read_status; 5576 } else if (!retry_count) { 5577 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5578 } 5579 } else { 5580 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5581 } 5582 no_wait: 5583 netif_carrier_on(netdev); 5584 5585 igb_ping_all_vfs(adapter); 5586 igb_check_vf_rate_limit(adapter); 5587 5588 /* link state has changed, schedule phy info update */ 5589 if (!test_bit(__IGB_DOWN, &adapter->state)) 5590 mod_timer(&adapter->phy_info_timer, 5591 round_jiffies(jiffies + 2 * HZ)); 5592 } 5593 } else { 5594 if (netif_carrier_ok(netdev)) { 5595 adapter->link_speed = 0; 5596 adapter->link_duplex = 0; 5597 5598 /* check for thermal sensor event */ 5599 if (igb_thermal_sensor_event(hw, 5600 E1000_THSTAT_PWR_DOWN)) { 5601 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5602 } 5603 5604 /* Links status message must follow this format */ 5605 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5606 netdev->name); 5607 netif_carrier_off(netdev); 5608 5609 igb_ping_all_vfs(adapter); 5610 5611 /* link state has changed, schedule phy info update */ 5612 if (!test_bit(__IGB_DOWN, &adapter->state)) 5613 mod_timer(&adapter->phy_info_timer, 5614 round_jiffies(jiffies + 2 * HZ)); 5615 5616 /* link is down, time to check for alternate media */ 5617 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5618 igb_check_swap_media(adapter); 5619 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5620 schedule_work(&adapter->reset_task); 5621 /* return immediately */ 5622 return; 5623 } 5624 } 5625 pm_schedule_suspend(netdev->dev.parent, 5626 MSEC_PER_SEC * 5); 5627 5628 /* also check for alternate media here */ 5629 } else if (!netif_carrier_ok(netdev) && 5630 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5631 igb_check_swap_media(adapter); 5632 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5633 schedule_work(&adapter->reset_task); 5634 /* return immediately */ 5635 return; 5636 } 5637 } 5638 } 5639 5640 spin_lock(&adapter->stats64_lock); 5641 igb_update_stats(adapter); 5642 spin_unlock(&adapter->stats64_lock); 5643 5644 for (i = 0; i < adapter->num_tx_queues; i++) { 5645 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5646 if (!netif_carrier_ok(netdev)) { 5647 /* We've lost link, so the controller stops DMA, 5648 * but we've got queued Tx work that's never going 5649 * to get done, so reset controller to flush Tx. 5650 * (Do the reset outside of interrupt context). 5651 */ 5652 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5653 adapter->tx_timeout_count++; 5654 schedule_work(&adapter->reset_task); 5655 /* return immediately since reset is imminent */ 5656 return; 5657 } 5658 } 5659 5660 /* Force detection of hung controller every watchdog period */ 5661 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5662 } 5663 5664 /* Cause software interrupt to ensure Rx ring is cleaned */ 5665 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5666 u32 eics = 0; 5667 5668 for (i = 0; i < adapter->num_q_vectors; i++) 5669 eics |= adapter->q_vector[i]->eims_value; 5670 wr32(E1000_EICS, eics); 5671 } else { 5672 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5673 } 5674 5675 igb_spoof_check(adapter); 5676 igb_ptp_rx_hang(adapter); 5677 igb_ptp_tx_hang(adapter); 5678 5679 /* Check LVMMC register on i350/i354 only */ 5680 if ((adapter->hw.mac.type == e1000_i350) || 5681 (adapter->hw.mac.type == e1000_i354)) 5682 igb_check_lvmmc(adapter); 5683 5684 /* Reset the timer */ 5685 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5686 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5687 mod_timer(&adapter->watchdog_timer, 5688 round_jiffies(jiffies + HZ)); 5689 else 5690 mod_timer(&adapter->watchdog_timer, 5691 round_jiffies(jiffies + 2 * HZ)); 5692 } 5693 } 5694 5695 enum latency_range { 5696 lowest_latency = 0, 5697 low_latency = 1, 5698 bulk_latency = 2, 5699 latency_invalid = 255 5700 }; 5701 5702 /** 5703 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5704 * @q_vector: pointer to q_vector 5705 * 5706 * Stores a new ITR value based on strictly on packet size. This 5707 * algorithm is less sophisticated than that used in igb_update_itr, 5708 * due to the difficulty of synchronizing statistics across multiple 5709 * receive rings. The divisors and thresholds used by this function 5710 * were determined based on theoretical maximum wire speed and testing 5711 * data, in order to minimize response time while increasing bulk 5712 * throughput. 5713 * This functionality is controlled by ethtool's coalescing settings. 5714 * NOTE: This function is called only when operating in a multiqueue 5715 * receive environment. 5716 **/ 5717 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5718 { 5719 int new_val = q_vector->itr_val; 5720 int avg_wire_size = 0; 5721 struct igb_adapter *adapter = q_vector->adapter; 5722 unsigned int packets; 5723 5724 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5725 * ints/sec - ITR timer value of 120 ticks. 5726 */ 5727 if (adapter->link_speed != SPEED_1000) { 5728 new_val = IGB_4K_ITR; 5729 goto set_itr_val; 5730 } 5731 5732 packets = q_vector->rx.total_packets; 5733 if (packets) 5734 avg_wire_size = q_vector->rx.total_bytes / packets; 5735 5736 packets = q_vector->tx.total_packets; 5737 if (packets) 5738 avg_wire_size = max_t(u32, avg_wire_size, 5739 q_vector->tx.total_bytes / packets); 5740 5741 /* if avg_wire_size isn't set no work was done */ 5742 if (!avg_wire_size) 5743 goto clear_counts; 5744 5745 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5746 avg_wire_size += 24; 5747 5748 /* Don't starve jumbo frames */ 5749 avg_wire_size = min(avg_wire_size, 3000); 5750 5751 /* Give a little boost to mid-size frames */ 5752 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5753 new_val = avg_wire_size / 3; 5754 else 5755 new_val = avg_wire_size / 2; 5756 5757 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5758 if (new_val < IGB_20K_ITR && 5759 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5760 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5761 new_val = IGB_20K_ITR; 5762 5763 set_itr_val: 5764 if (new_val != q_vector->itr_val) { 5765 q_vector->itr_val = new_val; 5766 q_vector->set_itr = 1; 5767 } 5768 clear_counts: 5769 q_vector->rx.total_bytes = 0; 5770 q_vector->rx.total_packets = 0; 5771 q_vector->tx.total_bytes = 0; 5772 q_vector->tx.total_packets = 0; 5773 } 5774 5775 /** 5776 * igb_update_itr - update the dynamic ITR value based on statistics 5777 * @q_vector: pointer to q_vector 5778 * @ring_container: ring info to update the itr for 5779 * 5780 * Stores a new ITR value based on packets and byte 5781 * counts during the last interrupt. The advantage of per interrupt 5782 * computation is faster updates and more accurate ITR for the current 5783 * traffic pattern. Constants in this function were computed 5784 * based on theoretical maximum wire speed and thresholds were set based 5785 * on testing data as well as attempting to minimize response time 5786 * while increasing bulk throughput. 5787 * This functionality is controlled by ethtool's coalescing settings. 5788 * NOTE: These calculations are only valid when operating in a single- 5789 * queue environment. 5790 **/ 5791 static void igb_update_itr(struct igb_q_vector *q_vector, 5792 struct igb_ring_container *ring_container) 5793 { 5794 unsigned int packets = ring_container->total_packets; 5795 unsigned int bytes = ring_container->total_bytes; 5796 u8 itrval = ring_container->itr; 5797 5798 /* no packets, exit with status unchanged */ 5799 if (packets == 0) 5800 return; 5801 5802 switch (itrval) { 5803 case lowest_latency: 5804 /* handle TSO and jumbo frames */ 5805 if (bytes/packets > 8000) 5806 itrval = bulk_latency; 5807 else if ((packets < 5) && (bytes > 512)) 5808 itrval = low_latency; 5809 break; 5810 case low_latency: /* 50 usec aka 20000 ints/s */ 5811 if (bytes > 10000) { 5812 /* this if handles the TSO accounting */ 5813 if (bytes/packets > 8000) 5814 itrval = bulk_latency; 5815 else if ((packets < 10) || ((bytes/packets) > 1200)) 5816 itrval = bulk_latency; 5817 else if ((packets > 35)) 5818 itrval = lowest_latency; 5819 } else if (bytes/packets > 2000) { 5820 itrval = bulk_latency; 5821 } else if (packets <= 2 && bytes < 512) { 5822 itrval = lowest_latency; 5823 } 5824 break; 5825 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5826 if (bytes > 25000) { 5827 if (packets > 35) 5828 itrval = low_latency; 5829 } else if (bytes < 1500) { 5830 itrval = low_latency; 5831 } 5832 break; 5833 } 5834 5835 /* clear work counters since we have the values we need */ 5836 ring_container->total_bytes = 0; 5837 ring_container->total_packets = 0; 5838 5839 /* write updated itr to ring container */ 5840 ring_container->itr = itrval; 5841 } 5842 5843 static void igb_set_itr(struct igb_q_vector *q_vector) 5844 { 5845 struct igb_adapter *adapter = q_vector->adapter; 5846 u32 new_itr = q_vector->itr_val; 5847 u8 current_itr = 0; 5848 5849 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5850 if (adapter->link_speed != SPEED_1000) { 5851 current_itr = 0; 5852 new_itr = IGB_4K_ITR; 5853 goto set_itr_now; 5854 } 5855 5856 igb_update_itr(q_vector, &q_vector->tx); 5857 igb_update_itr(q_vector, &q_vector->rx); 5858 5859 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5860 5861 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5862 if (current_itr == lowest_latency && 5863 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5864 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5865 current_itr = low_latency; 5866 5867 switch (current_itr) { 5868 /* counts and packets in update_itr are dependent on these numbers */ 5869 case lowest_latency: 5870 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5871 break; 5872 case low_latency: 5873 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5874 break; 5875 case bulk_latency: 5876 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5877 break; 5878 default: 5879 break; 5880 } 5881 5882 set_itr_now: 5883 if (new_itr != q_vector->itr_val) { 5884 /* this attempts to bias the interrupt rate towards Bulk 5885 * by adding intermediate steps when interrupt rate is 5886 * increasing 5887 */ 5888 new_itr = new_itr > q_vector->itr_val ? 5889 max((new_itr * q_vector->itr_val) / 5890 (new_itr + (q_vector->itr_val >> 2)), 5891 new_itr) : new_itr; 5892 /* Don't write the value here; it resets the adapter's 5893 * internal timer, and causes us to delay far longer than 5894 * we should between interrupts. Instead, we write the ITR 5895 * value at the beginning of the next interrupt so the timing 5896 * ends up being correct. 5897 */ 5898 q_vector->itr_val = new_itr; 5899 q_vector->set_itr = 1; 5900 } 5901 } 5902 5903 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5904 struct igb_tx_buffer *first, 5905 u32 vlan_macip_lens, u32 type_tucmd, 5906 u32 mss_l4len_idx) 5907 { 5908 struct e1000_adv_tx_context_desc *context_desc; 5909 u16 i = tx_ring->next_to_use; 5910 struct timespec64 ts; 5911 5912 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5913 5914 i++; 5915 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5916 5917 /* set bits to identify this as an advanced context descriptor */ 5918 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5919 5920 /* For 82575, context index must be unique per ring. */ 5921 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5922 mss_l4len_idx |= tx_ring->reg_idx << 4; 5923 5924 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5925 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5926 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5927 5928 /* We assume there is always a valid tx time available. Invalid times 5929 * should have been handled by the upper layers. 5930 */ 5931 if (tx_ring->launchtime_enable) { 5932 ts = ktime_to_timespec64(first->skb->tstamp); 5933 skb_txtime_consumed(first->skb); 5934 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5935 } else { 5936 context_desc->seqnum_seed = 0; 5937 } 5938 } 5939 5940 static int igb_tso(struct igb_ring *tx_ring, 5941 struct igb_tx_buffer *first, 5942 u8 *hdr_len) 5943 { 5944 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5945 struct sk_buff *skb = first->skb; 5946 union { 5947 struct iphdr *v4; 5948 struct ipv6hdr *v6; 5949 unsigned char *hdr; 5950 } ip; 5951 union { 5952 struct tcphdr *tcp; 5953 struct udphdr *udp; 5954 unsigned char *hdr; 5955 } l4; 5956 u32 paylen, l4_offset; 5957 int err; 5958 5959 if (skb->ip_summed != CHECKSUM_PARTIAL) 5960 return 0; 5961 5962 if (!skb_is_gso(skb)) 5963 return 0; 5964 5965 err = skb_cow_head(skb, 0); 5966 if (err < 0) 5967 return err; 5968 5969 ip.hdr = skb_network_header(skb); 5970 l4.hdr = skb_checksum_start(skb); 5971 5972 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5973 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5974 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5975 5976 /* initialize outer IP header fields */ 5977 if (ip.v4->version == 4) { 5978 unsigned char *csum_start = skb_checksum_start(skb); 5979 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5980 5981 /* IP header will have to cancel out any data that 5982 * is not a part of the outer IP header 5983 */ 5984 ip.v4->check = csum_fold(csum_partial(trans_start, 5985 csum_start - trans_start, 5986 0)); 5987 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5988 5989 ip.v4->tot_len = 0; 5990 first->tx_flags |= IGB_TX_FLAGS_TSO | 5991 IGB_TX_FLAGS_CSUM | 5992 IGB_TX_FLAGS_IPV4; 5993 } else { 5994 ip.v6->payload_len = 0; 5995 first->tx_flags |= IGB_TX_FLAGS_TSO | 5996 IGB_TX_FLAGS_CSUM; 5997 } 5998 5999 /* determine offset of inner transport header */ 6000 l4_offset = l4.hdr - skb->data; 6001 6002 /* remove payload length from inner checksum */ 6003 paylen = skb->len - l4_offset; 6004 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6005 /* compute length of segmentation header */ 6006 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6007 csum_replace_by_diff(&l4.tcp->check, 6008 (__force __wsum)htonl(paylen)); 6009 } else { 6010 /* compute length of segmentation header */ 6011 *hdr_len = sizeof(*l4.udp) + l4_offset; 6012 csum_replace_by_diff(&l4.udp->check, 6013 (__force __wsum)htonl(paylen)); 6014 } 6015 6016 /* update gso size and bytecount with header size */ 6017 first->gso_segs = skb_shinfo(skb)->gso_segs; 6018 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6019 6020 /* MSS L4LEN IDX */ 6021 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6022 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6023 6024 /* VLAN MACLEN IPLEN */ 6025 vlan_macip_lens = l4.hdr - ip.hdr; 6026 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6027 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6028 6029 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6030 type_tucmd, mss_l4len_idx); 6031 6032 return 1; 6033 } 6034 6035 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6036 { 6037 struct sk_buff *skb = first->skb; 6038 u32 vlan_macip_lens = 0; 6039 u32 type_tucmd = 0; 6040 6041 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6042 csum_failed: 6043 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6044 !tx_ring->launchtime_enable) 6045 return; 6046 goto no_csum; 6047 } 6048 6049 switch (skb->csum_offset) { 6050 case offsetof(struct tcphdr, check): 6051 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6052 fallthrough; 6053 case offsetof(struct udphdr, check): 6054 break; 6055 case offsetof(struct sctphdr, checksum): 6056 /* validate that this is actually an SCTP request */ 6057 if (skb_csum_is_sctp(skb)) { 6058 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6059 break; 6060 } 6061 fallthrough; 6062 default: 6063 skb_checksum_help(skb); 6064 goto csum_failed; 6065 } 6066 6067 /* update TX checksum flag */ 6068 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6069 vlan_macip_lens = skb_checksum_start_offset(skb) - 6070 skb_network_offset(skb); 6071 no_csum: 6072 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6073 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6074 6075 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6076 } 6077 6078 #define IGB_SET_FLAG(_input, _flag, _result) \ 6079 ((_flag <= _result) ? \ 6080 ((u32)(_input & _flag) * (_result / _flag)) : \ 6081 ((u32)(_input & _flag) / (_flag / _result))) 6082 6083 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6084 { 6085 /* set type for advanced descriptor with frame checksum insertion */ 6086 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6087 E1000_ADVTXD_DCMD_DEXT | 6088 E1000_ADVTXD_DCMD_IFCS; 6089 6090 /* set HW vlan bit if vlan is present */ 6091 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6092 (E1000_ADVTXD_DCMD_VLE)); 6093 6094 /* set segmentation bits for TSO */ 6095 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6096 (E1000_ADVTXD_DCMD_TSE)); 6097 6098 /* set timestamp bit if present */ 6099 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6100 (E1000_ADVTXD_MAC_TSTAMP)); 6101 6102 /* insert frame checksum */ 6103 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6104 6105 return cmd_type; 6106 } 6107 6108 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6109 union e1000_adv_tx_desc *tx_desc, 6110 u32 tx_flags, unsigned int paylen) 6111 { 6112 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6113 6114 /* 82575 requires a unique index per ring */ 6115 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6116 olinfo_status |= tx_ring->reg_idx << 4; 6117 6118 /* insert L4 checksum */ 6119 olinfo_status |= IGB_SET_FLAG(tx_flags, 6120 IGB_TX_FLAGS_CSUM, 6121 (E1000_TXD_POPTS_TXSM << 8)); 6122 6123 /* insert IPv4 checksum */ 6124 olinfo_status |= IGB_SET_FLAG(tx_flags, 6125 IGB_TX_FLAGS_IPV4, 6126 (E1000_TXD_POPTS_IXSM << 8)); 6127 6128 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6129 } 6130 6131 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6132 { 6133 struct net_device *netdev = tx_ring->netdev; 6134 6135 netif_stop_subqueue(netdev, tx_ring->queue_index); 6136 6137 /* Herbert's original patch had: 6138 * smp_mb__after_netif_stop_queue(); 6139 * but since that doesn't exist yet, just open code it. 6140 */ 6141 smp_mb(); 6142 6143 /* We need to check again in a case another CPU has just 6144 * made room available. 6145 */ 6146 if (igb_desc_unused(tx_ring) < size) 6147 return -EBUSY; 6148 6149 /* A reprieve! */ 6150 netif_wake_subqueue(netdev, tx_ring->queue_index); 6151 6152 u64_stats_update_begin(&tx_ring->tx_syncp2); 6153 tx_ring->tx_stats.restart_queue2++; 6154 u64_stats_update_end(&tx_ring->tx_syncp2); 6155 6156 return 0; 6157 } 6158 6159 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6160 { 6161 if (igb_desc_unused(tx_ring) >= size) 6162 return 0; 6163 return __igb_maybe_stop_tx(tx_ring, size); 6164 } 6165 6166 static int igb_tx_map(struct igb_ring *tx_ring, 6167 struct igb_tx_buffer *first, 6168 const u8 hdr_len) 6169 { 6170 struct sk_buff *skb = first->skb; 6171 struct igb_tx_buffer *tx_buffer; 6172 union e1000_adv_tx_desc *tx_desc; 6173 skb_frag_t *frag; 6174 dma_addr_t dma; 6175 unsigned int data_len, size; 6176 u32 tx_flags = first->tx_flags; 6177 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6178 u16 i = tx_ring->next_to_use; 6179 6180 tx_desc = IGB_TX_DESC(tx_ring, i); 6181 6182 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6183 6184 size = skb_headlen(skb); 6185 data_len = skb->data_len; 6186 6187 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6188 6189 tx_buffer = first; 6190 6191 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6192 if (dma_mapping_error(tx_ring->dev, dma)) 6193 goto dma_error; 6194 6195 /* record length, and DMA address */ 6196 dma_unmap_len_set(tx_buffer, len, size); 6197 dma_unmap_addr_set(tx_buffer, dma, dma); 6198 6199 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6200 6201 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6202 tx_desc->read.cmd_type_len = 6203 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6204 6205 i++; 6206 tx_desc++; 6207 if (i == tx_ring->count) { 6208 tx_desc = IGB_TX_DESC(tx_ring, 0); 6209 i = 0; 6210 } 6211 tx_desc->read.olinfo_status = 0; 6212 6213 dma += IGB_MAX_DATA_PER_TXD; 6214 size -= IGB_MAX_DATA_PER_TXD; 6215 6216 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6217 } 6218 6219 if (likely(!data_len)) 6220 break; 6221 6222 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6223 6224 i++; 6225 tx_desc++; 6226 if (i == tx_ring->count) { 6227 tx_desc = IGB_TX_DESC(tx_ring, 0); 6228 i = 0; 6229 } 6230 tx_desc->read.olinfo_status = 0; 6231 6232 size = skb_frag_size(frag); 6233 data_len -= size; 6234 6235 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6236 size, DMA_TO_DEVICE); 6237 6238 tx_buffer = &tx_ring->tx_buffer_info[i]; 6239 } 6240 6241 /* write last descriptor with RS and EOP bits */ 6242 cmd_type |= size | IGB_TXD_DCMD; 6243 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6244 6245 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6246 6247 /* set the timestamp */ 6248 first->time_stamp = jiffies; 6249 6250 skb_tx_timestamp(skb); 6251 6252 /* Force memory writes to complete before letting h/w know there 6253 * are new descriptors to fetch. (Only applicable for weak-ordered 6254 * memory model archs, such as IA-64). 6255 * 6256 * We also need this memory barrier to make certain all of the 6257 * status bits have been updated before next_to_watch is written. 6258 */ 6259 dma_wmb(); 6260 6261 /* set next_to_watch value indicating a packet is present */ 6262 first->next_to_watch = tx_desc; 6263 6264 i++; 6265 if (i == tx_ring->count) 6266 i = 0; 6267 6268 tx_ring->next_to_use = i; 6269 6270 /* Make sure there is space in the ring for the next send. */ 6271 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6272 6273 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6274 writel(i, tx_ring->tail); 6275 } 6276 return 0; 6277 6278 dma_error: 6279 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6280 tx_buffer = &tx_ring->tx_buffer_info[i]; 6281 6282 /* clear dma mappings for failed tx_buffer_info map */ 6283 while (tx_buffer != first) { 6284 if (dma_unmap_len(tx_buffer, len)) 6285 dma_unmap_page(tx_ring->dev, 6286 dma_unmap_addr(tx_buffer, dma), 6287 dma_unmap_len(tx_buffer, len), 6288 DMA_TO_DEVICE); 6289 dma_unmap_len_set(tx_buffer, len, 0); 6290 6291 if (i-- == 0) 6292 i += tx_ring->count; 6293 tx_buffer = &tx_ring->tx_buffer_info[i]; 6294 } 6295 6296 if (dma_unmap_len(tx_buffer, len)) 6297 dma_unmap_single(tx_ring->dev, 6298 dma_unmap_addr(tx_buffer, dma), 6299 dma_unmap_len(tx_buffer, len), 6300 DMA_TO_DEVICE); 6301 dma_unmap_len_set(tx_buffer, len, 0); 6302 6303 dev_kfree_skb_any(tx_buffer->skb); 6304 tx_buffer->skb = NULL; 6305 6306 tx_ring->next_to_use = i; 6307 6308 return -1; 6309 } 6310 6311 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6312 struct igb_ring *tx_ring, 6313 struct xdp_frame *xdpf) 6314 { 6315 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6316 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6317 u16 count, i, index = tx_ring->next_to_use; 6318 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6319 struct igb_tx_buffer *tx_buffer = tx_head; 6320 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6321 u32 len = xdpf->len, cmd_type, olinfo_status; 6322 void *data = xdpf->data; 6323 6324 count = TXD_USE_COUNT(len); 6325 for (i = 0; i < nr_frags; i++) 6326 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6327 6328 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6329 return IGB_XDP_CONSUMED; 6330 6331 i = 0; 6332 /* record the location of the first descriptor for this packet */ 6333 tx_head->bytecount = xdp_get_frame_len(xdpf); 6334 tx_head->type = IGB_TYPE_XDP; 6335 tx_head->gso_segs = 1; 6336 tx_head->xdpf = xdpf; 6337 6338 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6339 /* 82575 requires a unique index per ring */ 6340 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6341 olinfo_status |= tx_ring->reg_idx << 4; 6342 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6343 6344 for (;;) { 6345 dma_addr_t dma; 6346 6347 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6348 if (dma_mapping_error(tx_ring->dev, dma)) 6349 goto unmap; 6350 6351 /* record length, and DMA address */ 6352 dma_unmap_len_set(tx_buffer, len, len); 6353 dma_unmap_addr_set(tx_buffer, dma, dma); 6354 6355 /* put descriptor type bits */ 6356 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6357 E1000_ADVTXD_DCMD_IFCS | len; 6358 6359 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6360 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6361 6362 tx_buffer->protocol = 0; 6363 6364 if (++index == tx_ring->count) 6365 index = 0; 6366 6367 if (i == nr_frags) 6368 break; 6369 6370 tx_buffer = &tx_ring->tx_buffer_info[index]; 6371 tx_desc = IGB_TX_DESC(tx_ring, index); 6372 tx_desc->read.olinfo_status = 0; 6373 6374 data = skb_frag_address(&sinfo->frags[i]); 6375 len = skb_frag_size(&sinfo->frags[i]); 6376 i++; 6377 } 6378 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6379 6380 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6381 /* set the timestamp */ 6382 tx_head->time_stamp = jiffies; 6383 6384 /* Avoid any potential race with xdp_xmit and cleanup */ 6385 smp_wmb(); 6386 6387 /* set next_to_watch value indicating a packet is present */ 6388 tx_head->next_to_watch = tx_desc; 6389 tx_ring->next_to_use = index; 6390 6391 /* Make sure there is space in the ring for the next send. */ 6392 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6393 6394 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6395 writel(index, tx_ring->tail); 6396 6397 return IGB_XDP_TX; 6398 6399 unmap: 6400 for (;;) { 6401 tx_buffer = &tx_ring->tx_buffer_info[index]; 6402 if (dma_unmap_len(tx_buffer, len)) 6403 dma_unmap_page(tx_ring->dev, 6404 dma_unmap_addr(tx_buffer, dma), 6405 dma_unmap_len(tx_buffer, len), 6406 DMA_TO_DEVICE); 6407 dma_unmap_len_set(tx_buffer, len, 0); 6408 if (tx_buffer == tx_head) 6409 break; 6410 6411 if (!index) 6412 index += tx_ring->count; 6413 index--; 6414 } 6415 6416 return IGB_XDP_CONSUMED; 6417 } 6418 6419 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6420 struct igb_ring *tx_ring) 6421 { 6422 struct igb_tx_buffer *first; 6423 int tso; 6424 u32 tx_flags = 0; 6425 unsigned short f; 6426 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6427 __be16 protocol = vlan_get_protocol(skb); 6428 u8 hdr_len = 0; 6429 6430 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6431 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6432 * + 2 desc gap to keep tail from touching head, 6433 * + 1 desc for context descriptor, 6434 * otherwise try next time 6435 */ 6436 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6437 count += TXD_USE_COUNT(skb_frag_size( 6438 &skb_shinfo(skb)->frags[f])); 6439 6440 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6441 /* this is a hard error */ 6442 return NETDEV_TX_BUSY; 6443 } 6444 6445 /* record the location of the first descriptor for this packet */ 6446 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6447 first->type = IGB_TYPE_SKB; 6448 first->skb = skb; 6449 first->bytecount = skb->len; 6450 first->gso_segs = 1; 6451 6452 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6453 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6454 6455 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6456 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6457 &adapter->state)) { 6458 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6459 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6460 6461 adapter->ptp_tx_skb = skb_get(skb); 6462 adapter->ptp_tx_start = jiffies; 6463 if (adapter->hw.mac.type == e1000_82576) 6464 schedule_work(&adapter->ptp_tx_work); 6465 } else { 6466 adapter->tx_hwtstamp_skipped++; 6467 } 6468 } 6469 6470 if (skb_vlan_tag_present(skb)) { 6471 tx_flags |= IGB_TX_FLAGS_VLAN; 6472 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6473 } 6474 6475 /* record initial flags and protocol */ 6476 first->tx_flags = tx_flags; 6477 first->protocol = protocol; 6478 6479 tso = igb_tso(tx_ring, first, &hdr_len); 6480 if (tso < 0) 6481 goto out_drop; 6482 else if (!tso) 6483 igb_tx_csum(tx_ring, first); 6484 6485 if (igb_tx_map(tx_ring, first, hdr_len)) 6486 goto cleanup_tx_tstamp; 6487 6488 return NETDEV_TX_OK; 6489 6490 out_drop: 6491 dev_kfree_skb_any(first->skb); 6492 first->skb = NULL; 6493 cleanup_tx_tstamp: 6494 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6495 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6496 6497 dev_kfree_skb_any(adapter->ptp_tx_skb); 6498 adapter->ptp_tx_skb = NULL; 6499 if (adapter->hw.mac.type == e1000_82576) 6500 cancel_work_sync(&adapter->ptp_tx_work); 6501 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6502 } 6503 6504 return NETDEV_TX_OK; 6505 } 6506 6507 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6508 struct sk_buff *skb) 6509 { 6510 unsigned int r_idx = skb->queue_mapping; 6511 6512 if (r_idx >= adapter->num_tx_queues) 6513 r_idx = r_idx % adapter->num_tx_queues; 6514 6515 return adapter->tx_ring[r_idx]; 6516 } 6517 6518 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6519 struct net_device *netdev) 6520 { 6521 struct igb_adapter *adapter = netdev_priv(netdev); 6522 6523 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6524 * in order to meet this minimum size requirement. 6525 */ 6526 if (skb_put_padto(skb, 17)) 6527 return NETDEV_TX_OK; 6528 6529 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6530 } 6531 6532 /** 6533 * igb_tx_timeout - Respond to a Tx Hang 6534 * @netdev: network interface device structure 6535 * @txqueue: number of the Tx queue that hung (unused) 6536 **/ 6537 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6538 { 6539 struct igb_adapter *adapter = netdev_priv(netdev); 6540 struct e1000_hw *hw = &adapter->hw; 6541 6542 /* Do the reset outside of interrupt context */ 6543 adapter->tx_timeout_count++; 6544 6545 if (hw->mac.type >= e1000_82580) 6546 hw->dev_spec._82575.global_device_reset = true; 6547 6548 schedule_work(&adapter->reset_task); 6549 wr32(E1000_EICS, 6550 (adapter->eims_enable_mask & ~adapter->eims_other)); 6551 } 6552 6553 static void igb_reset_task(struct work_struct *work) 6554 { 6555 struct igb_adapter *adapter; 6556 adapter = container_of(work, struct igb_adapter, reset_task); 6557 6558 rtnl_lock(); 6559 /* If we're already down or resetting, just bail */ 6560 if (test_bit(__IGB_DOWN, &adapter->state) || 6561 test_bit(__IGB_RESETTING, &adapter->state)) { 6562 rtnl_unlock(); 6563 return; 6564 } 6565 6566 igb_dump(adapter); 6567 netdev_err(adapter->netdev, "Reset adapter\n"); 6568 igb_reinit_locked(adapter); 6569 rtnl_unlock(); 6570 } 6571 6572 /** 6573 * igb_get_stats64 - Get System Network Statistics 6574 * @netdev: network interface device structure 6575 * @stats: rtnl_link_stats64 pointer 6576 **/ 6577 static void igb_get_stats64(struct net_device *netdev, 6578 struct rtnl_link_stats64 *stats) 6579 { 6580 struct igb_adapter *adapter = netdev_priv(netdev); 6581 6582 spin_lock(&adapter->stats64_lock); 6583 igb_update_stats(adapter); 6584 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6585 spin_unlock(&adapter->stats64_lock); 6586 } 6587 6588 /** 6589 * igb_change_mtu - Change the Maximum Transfer Unit 6590 * @netdev: network interface device structure 6591 * @new_mtu: new value for maximum frame size 6592 * 6593 * Returns 0 on success, negative on failure 6594 **/ 6595 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6596 { 6597 struct igb_adapter *adapter = netdev_priv(netdev); 6598 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6599 6600 if (adapter->xdp_prog) { 6601 int i; 6602 6603 for (i = 0; i < adapter->num_rx_queues; i++) { 6604 struct igb_ring *ring = adapter->rx_ring[i]; 6605 6606 if (max_frame > igb_rx_bufsz(ring)) { 6607 netdev_warn(adapter->netdev, 6608 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6609 max_frame); 6610 return -EINVAL; 6611 } 6612 } 6613 } 6614 6615 /* adjust max frame to be at least the size of a standard frame */ 6616 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6617 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6618 6619 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6620 usleep_range(1000, 2000); 6621 6622 /* igb_down has a dependency on max_frame_size */ 6623 adapter->max_frame_size = max_frame; 6624 6625 if (netif_running(netdev)) 6626 igb_down(adapter); 6627 6628 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6629 netdev->mtu, new_mtu); 6630 netdev->mtu = new_mtu; 6631 6632 if (netif_running(netdev)) 6633 igb_up(adapter); 6634 else 6635 igb_reset(adapter); 6636 6637 clear_bit(__IGB_RESETTING, &adapter->state); 6638 6639 return 0; 6640 } 6641 6642 /** 6643 * igb_update_stats - Update the board statistics counters 6644 * @adapter: board private structure 6645 **/ 6646 void igb_update_stats(struct igb_adapter *adapter) 6647 { 6648 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6649 struct e1000_hw *hw = &adapter->hw; 6650 struct pci_dev *pdev = adapter->pdev; 6651 u32 reg, mpc; 6652 int i; 6653 u64 bytes, packets; 6654 unsigned int start; 6655 u64 _bytes, _packets; 6656 6657 /* Prevent stats update while adapter is being reset, or if the pci 6658 * connection is down. 6659 */ 6660 if (adapter->link_speed == 0) 6661 return; 6662 if (pci_channel_offline(pdev)) 6663 return; 6664 6665 bytes = 0; 6666 packets = 0; 6667 6668 rcu_read_lock(); 6669 for (i = 0; i < adapter->num_rx_queues; i++) { 6670 struct igb_ring *ring = adapter->rx_ring[i]; 6671 u32 rqdpc = rd32(E1000_RQDPC(i)); 6672 if (hw->mac.type >= e1000_i210) 6673 wr32(E1000_RQDPC(i), 0); 6674 6675 if (rqdpc) { 6676 ring->rx_stats.drops += rqdpc; 6677 net_stats->rx_fifo_errors += rqdpc; 6678 } 6679 6680 do { 6681 start = u64_stats_fetch_begin(&ring->rx_syncp); 6682 _bytes = ring->rx_stats.bytes; 6683 _packets = ring->rx_stats.packets; 6684 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6685 bytes += _bytes; 6686 packets += _packets; 6687 } 6688 6689 net_stats->rx_bytes = bytes; 6690 net_stats->rx_packets = packets; 6691 6692 bytes = 0; 6693 packets = 0; 6694 for (i = 0; i < adapter->num_tx_queues; i++) { 6695 struct igb_ring *ring = adapter->tx_ring[i]; 6696 do { 6697 start = u64_stats_fetch_begin(&ring->tx_syncp); 6698 _bytes = ring->tx_stats.bytes; 6699 _packets = ring->tx_stats.packets; 6700 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6701 bytes += _bytes; 6702 packets += _packets; 6703 } 6704 net_stats->tx_bytes = bytes; 6705 net_stats->tx_packets = packets; 6706 rcu_read_unlock(); 6707 6708 /* read stats registers */ 6709 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6710 adapter->stats.gprc += rd32(E1000_GPRC); 6711 adapter->stats.gorc += rd32(E1000_GORCL); 6712 rd32(E1000_GORCH); /* clear GORCL */ 6713 adapter->stats.bprc += rd32(E1000_BPRC); 6714 adapter->stats.mprc += rd32(E1000_MPRC); 6715 adapter->stats.roc += rd32(E1000_ROC); 6716 6717 adapter->stats.prc64 += rd32(E1000_PRC64); 6718 adapter->stats.prc127 += rd32(E1000_PRC127); 6719 adapter->stats.prc255 += rd32(E1000_PRC255); 6720 adapter->stats.prc511 += rd32(E1000_PRC511); 6721 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6722 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6723 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6724 adapter->stats.sec += rd32(E1000_SEC); 6725 6726 mpc = rd32(E1000_MPC); 6727 adapter->stats.mpc += mpc; 6728 net_stats->rx_fifo_errors += mpc; 6729 adapter->stats.scc += rd32(E1000_SCC); 6730 adapter->stats.ecol += rd32(E1000_ECOL); 6731 adapter->stats.mcc += rd32(E1000_MCC); 6732 adapter->stats.latecol += rd32(E1000_LATECOL); 6733 adapter->stats.dc += rd32(E1000_DC); 6734 adapter->stats.rlec += rd32(E1000_RLEC); 6735 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6736 adapter->stats.xontxc += rd32(E1000_XONTXC); 6737 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6738 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6739 adapter->stats.fcruc += rd32(E1000_FCRUC); 6740 adapter->stats.gptc += rd32(E1000_GPTC); 6741 adapter->stats.gotc += rd32(E1000_GOTCL); 6742 rd32(E1000_GOTCH); /* clear GOTCL */ 6743 adapter->stats.rnbc += rd32(E1000_RNBC); 6744 adapter->stats.ruc += rd32(E1000_RUC); 6745 adapter->stats.rfc += rd32(E1000_RFC); 6746 adapter->stats.rjc += rd32(E1000_RJC); 6747 adapter->stats.tor += rd32(E1000_TORH); 6748 adapter->stats.tot += rd32(E1000_TOTH); 6749 adapter->stats.tpr += rd32(E1000_TPR); 6750 6751 adapter->stats.ptc64 += rd32(E1000_PTC64); 6752 adapter->stats.ptc127 += rd32(E1000_PTC127); 6753 adapter->stats.ptc255 += rd32(E1000_PTC255); 6754 adapter->stats.ptc511 += rd32(E1000_PTC511); 6755 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6756 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6757 6758 adapter->stats.mptc += rd32(E1000_MPTC); 6759 adapter->stats.bptc += rd32(E1000_BPTC); 6760 6761 adapter->stats.tpt += rd32(E1000_TPT); 6762 adapter->stats.colc += rd32(E1000_COLC); 6763 6764 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6765 /* read internal phy specific stats */ 6766 reg = rd32(E1000_CTRL_EXT); 6767 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6768 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6769 6770 /* this stat has invalid values on i210/i211 */ 6771 if ((hw->mac.type != e1000_i210) && 6772 (hw->mac.type != e1000_i211)) 6773 adapter->stats.tncrs += rd32(E1000_TNCRS); 6774 } 6775 6776 adapter->stats.tsctc += rd32(E1000_TSCTC); 6777 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6778 6779 adapter->stats.iac += rd32(E1000_IAC); 6780 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6781 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6782 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6783 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6784 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6785 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6786 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6787 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6788 6789 /* Fill out the OS statistics structure */ 6790 net_stats->multicast = adapter->stats.mprc; 6791 net_stats->collisions = adapter->stats.colc; 6792 6793 /* Rx Errors */ 6794 6795 /* RLEC on some newer hardware can be incorrect so build 6796 * our own version based on RUC and ROC 6797 */ 6798 net_stats->rx_errors = adapter->stats.rxerrc + 6799 adapter->stats.crcerrs + adapter->stats.algnerrc + 6800 adapter->stats.ruc + adapter->stats.roc + 6801 adapter->stats.cexterr; 6802 net_stats->rx_length_errors = adapter->stats.ruc + 6803 adapter->stats.roc; 6804 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6805 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6806 net_stats->rx_missed_errors = adapter->stats.mpc; 6807 6808 /* Tx Errors */ 6809 net_stats->tx_errors = adapter->stats.ecol + 6810 adapter->stats.latecol; 6811 net_stats->tx_aborted_errors = adapter->stats.ecol; 6812 net_stats->tx_window_errors = adapter->stats.latecol; 6813 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6814 6815 /* Tx Dropped needs to be maintained elsewhere */ 6816 6817 /* Management Stats */ 6818 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6819 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6820 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6821 6822 /* OS2BMC Stats */ 6823 reg = rd32(E1000_MANC); 6824 if (reg & E1000_MANC_EN_BMC2OS) { 6825 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6826 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6827 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6828 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6829 } 6830 } 6831 6832 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6833 { 6834 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6835 struct e1000_hw *hw = &adapter->hw; 6836 struct timespec64 ts; 6837 u32 tsauxc; 6838 6839 if (pin < 0 || pin >= IGB_N_SDP) 6840 return; 6841 6842 spin_lock(&adapter->tmreg_lock); 6843 6844 if (hw->mac.type == e1000_82580 || 6845 hw->mac.type == e1000_i354 || 6846 hw->mac.type == e1000_i350) { 6847 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6848 u32 systiml, systimh, level_mask, level, rem; 6849 u64 systim, now; 6850 6851 /* read systim registers in sequence */ 6852 rd32(E1000_SYSTIMR); 6853 systiml = rd32(E1000_SYSTIML); 6854 systimh = rd32(E1000_SYSTIMH); 6855 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6856 now = timecounter_cyc2time(&adapter->tc, systim); 6857 6858 if (pin < 2) { 6859 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6860 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6861 } else { 6862 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6863 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6864 } 6865 6866 div_u64_rem(now, ns, &rem); 6867 systim = systim + (ns - rem); 6868 6869 /* synchronize pin level with rising/falling edges */ 6870 div_u64_rem(now, ns << 1, &rem); 6871 if (rem < ns) { 6872 /* first half of period */ 6873 if (level == 0) { 6874 /* output is already low, skip this period */ 6875 systim += ns; 6876 pr_notice("igb: periodic output on %s missed falling edge\n", 6877 adapter->sdp_config[pin].name); 6878 } 6879 } else { 6880 /* second half of period */ 6881 if (level == 1) { 6882 /* output is already high, skip this period */ 6883 systim += ns; 6884 pr_notice("igb: periodic output on %s missed rising edge\n", 6885 adapter->sdp_config[pin].name); 6886 } 6887 } 6888 6889 /* for this chip family tv_sec is the upper part of the binary value, 6890 * so not seconds 6891 */ 6892 ts.tv_nsec = (u32)systim; 6893 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6894 } else { 6895 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6896 adapter->perout[tsintr_tt].period); 6897 } 6898 6899 /* u32 conversion of tv_sec is safe until y2106 */ 6900 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6901 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6902 tsauxc = rd32(E1000_TSAUXC); 6903 tsauxc |= TSAUXC_EN_TT0; 6904 wr32(E1000_TSAUXC, tsauxc); 6905 adapter->perout[tsintr_tt].start = ts; 6906 6907 spin_unlock(&adapter->tmreg_lock); 6908 } 6909 6910 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6911 { 6912 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6913 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6914 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6915 struct e1000_hw *hw = &adapter->hw; 6916 struct ptp_clock_event event; 6917 struct timespec64 ts; 6918 6919 if (pin < 0 || pin >= IGB_N_SDP) 6920 return; 6921 6922 if (hw->mac.type == e1000_82580 || 6923 hw->mac.type == e1000_i354 || 6924 hw->mac.type == e1000_i350) { 6925 s64 ns = rd32(auxstmpl); 6926 6927 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6928 ts = ns_to_timespec64(ns); 6929 } else { 6930 ts.tv_nsec = rd32(auxstmpl); 6931 ts.tv_sec = rd32(auxstmph); 6932 } 6933 6934 event.type = PTP_CLOCK_EXTTS; 6935 event.index = tsintr_tt; 6936 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6937 ptp_clock_event(adapter->ptp_clock, &event); 6938 } 6939 6940 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6941 { 6942 struct e1000_hw *hw = &adapter->hw; 6943 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6944 struct ptp_clock_event event; 6945 6946 if (tsicr & TSINTR_SYS_WRAP) { 6947 event.type = PTP_CLOCK_PPS; 6948 if (adapter->ptp_caps.pps) 6949 ptp_clock_event(adapter->ptp_clock, &event); 6950 ack |= TSINTR_SYS_WRAP; 6951 } 6952 6953 if (tsicr & E1000_TSICR_TXTS) { 6954 /* retrieve hardware timestamp */ 6955 schedule_work(&adapter->ptp_tx_work); 6956 ack |= E1000_TSICR_TXTS; 6957 } 6958 6959 if (tsicr & TSINTR_TT0) { 6960 igb_perout(adapter, 0); 6961 ack |= TSINTR_TT0; 6962 } 6963 6964 if (tsicr & TSINTR_TT1) { 6965 igb_perout(adapter, 1); 6966 ack |= TSINTR_TT1; 6967 } 6968 6969 if (tsicr & TSINTR_AUTT0) { 6970 igb_extts(adapter, 0); 6971 ack |= TSINTR_AUTT0; 6972 } 6973 6974 if (tsicr & TSINTR_AUTT1) { 6975 igb_extts(adapter, 1); 6976 ack |= TSINTR_AUTT1; 6977 } 6978 6979 /* acknowledge the interrupts */ 6980 wr32(E1000_TSICR, ack); 6981 } 6982 6983 static irqreturn_t igb_msix_other(int irq, void *data) 6984 { 6985 struct igb_adapter *adapter = data; 6986 struct e1000_hw *hw = &adapter->hw; 6987 u32 icr = rd32(E1000_ICR); 6988 /* reading ICR causes bit 31 of EICR to be cleared */ 6989 6990 if (icr & E1000_ICR_DRSTA) 6991 schedule_work(&adapter->reset_task); 6992 6993 if (icr & E1000_ICR_DOUTSYNC) { 6994 /* HW is reporting DMA is out of sync */ 6995 adapter->stats.doosync++; 6996 /* The DMA Out of Sync is also indication of a spoof event 6997 * in IOV mode. Check the Wrong VM Behavior register to 6998 * see if it is really a spoof event. 6999 */ 7000 igb_check_wvbr(adapter); 7001 } 7002 7003 /* Check for a mailbox event */ 7004 if (icr & E1000_ICR_VMMB) 7005 igb_msg_task(adapter); 7006 7007 if (icr & E1000_ICR_LSC) { 7008 hw->mac.get_link_status = 1; 7009 /* guard against interrupt when we're going down */ 7010 if (!test_bit(__IGB_DOWN, &adapter->state)) 7011 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7012 } 7013 7014 if (icr & E1000_ICR_TS) 7015 igb_tsync_interrupt(adapter); 7016 7017 wr32(E1000_EIMS, adapter->eims_other); 7018 7019 return IRQ_HANDLED; 7020 } 7021 7022 static void igb_write_itr(struct igb_q_vector *q_vector) 7023 { 7024 struct igb_adapter *adapter = q_vector->adapter; 7025 u32 itr_val = q_vector->itr_val & 0x7FFC; 7026 7027 if (!q_vector->set_itr) 7028 return; 7029 7030 if (!itr_val) 7031 itr_val = 0x4; 7032 7033 if (adapter->hw.mac.type == e1000_82575) 7034 itr_val |= itr_val << 16; 7035 else 7036 itr_val |= E1000_EITR_CNT_IGNR; 7037 7038 writel(itr_val, q_vector->itr_register); 7039 q_vector->set_itr = 0; 7040 } 7041 7042 static irqreturn_t igb_msix_ring(int irq, void *data) 7043 { 7044 struct igb_q_vector *q_vector = data; 7045 7046 /* Write the ITR value calculated from the previous interrupt. */ 7047 igb_write_itr(q_vector); 7048 7049 napi_schedule(&q_vector->napi); 7050 7051 return IRQ_HANDLED; 7052 } 7053 7054 #ifdef CONFIG_IGB_DCA 7055 static void igb_update_tx_dca(struct igb_adapter *adapter, 7056 struct igb_ring *tx_ring, 7057 int cpu) 7058 { 7059 struct e1000_hw *hw = &adapter->hw; 7060 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7061 7062 if (hw->mac.type != e1000_82575) 7063 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7064 7065 /* We can enable relaxed ordering for reads, but not writes when 7066 * DCA is enabled. This is due to a known issue in some chipsets 7067 * which will cause the DCA tag to be cleared. 7068 */ 7069 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7070 E1000_DCA_TXCTRL_DATA_RRO_EN | 7071 E1000_DCA_TXCTRL_DESC_DCA_EN; 7072 7073 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7074 } 7075 7076 static void igb_update_rx_dca(struct igb_adapter *adapter, 7077 struct igb_ring *rx_ring, 7078 int cpu) 7079 { 7080 struct e1000_hw *hw = &adapter->hw; 7081 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7082 7083 if (hw->mac.type != e1000_82575) 7084 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7085 7086 /* We can enable relaxed ordering for reads, but not writes when 7087 * DCA is enabled. This is due to a known issue in some chipsets 7088 * which will cause the DCA tag to be cleared. 7089 */ 7090 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7091 E1000_DCA_RXCTRL_DESC_DCA_EN; 7092 7093 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7094 } 7095 7096 static void igb_update_dca(struct igb_q_vector *q_vector) 7097 { 7098 struct igb_adapter *adapter = q_vector->adapter; 7099 int cpu = get_cpu(); 7100 7101 if (q_vector->cpu == cpu) 7102 goto out_no_update; 7103 7104 if (q_vector->tx.ring) 7105 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7106 7107 if (q_vector->rx.ring) 7108 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7109 7110 q_vector->cpu = cpu; 7111 out_no_update: 7112 put_cpu(); 7113 } 7114 7115 static void igb_setup_dca(struct igb_adapter *adapter) 7116 { 7117 struct e1000_hw *hw = &adapter->hw; 7118 int i; 7119 7120 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7121 return; 7122 7123 /* Always use CB2 mode, difference is masked in the CB driver. */ 7124 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7125 7126 for (i = 0; i < adapter->num_q_vectors; i++) { 7127 adapter->q_vector[i]->cpu = -1; 7128 igb_update_dca(adapter->q_vector[i]); 7129 } 7130 } 7131 7132 static int __igb_notify_dca(struct device *dev, void *data) 7133 { 7134 struct net_device *netdev = dev_get_drvdata(dev); 7135 struct igb_adapter *adapter = netdev_priv(netdev); 7136 struct pci_dev *pdev = adapter->pdev; 7137 struct e1000_hw *hw = &adapter->hw; 7138 unsigned long event = *(unsigned long *)data; 7139 7140 switch (event) { 7141 case DCA_PROVIDER_ADD: 7142 /* if already enabled, don't do it again */ 7143 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7144 break; 7145 if (dca_add_requester(dev) == 0) { 7146 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7147 dev_info(&pdev->dev, "DCA enabled\n"); 7148 igb_setup_dca(adapter); 7149 break; 7150 } 7151 fallthrough; /* since DCA is disabled. */ 7152 case DCA_PROVIDER_REMOVE: 7153 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7154 /* without this a class_device is left 7155 * hanging around in the sysfs model 7156 */ 7157 dca_remove_requester(dev); 7158 dev_info(&pdev->dev, "DCA disabled\n"); 7159 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7160 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7161 } 7162 break; 7163 } 7164 7165 return 0; 7166 } 7167 7168 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7169 void *p) 7170 { 7171 int ret_val; 7172 7173 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7174 __igb_notify_dca); 7175 7176 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7177 } 7178 #endif /* CONFIG_IGB_DCA */ 7179 7180 #ifdef CONFIG_PCI_IOV 7181 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7182 { 7183 unsigned char mac_addr[ETH_ALEN]; 7184 7185 eth_zero_addr(mac_addr); 7186 igb_set_vf_mac(adapter, vf, mac_addr); 7187 7188 /* By default spoof check is enabled for all VFs */ 7189 adapter->vf_data[vf].spoofchk_enabled = true; 7190 7191 /* By default VFs are not trusted */ 7192 adapter->vf_data[vf].trusted = false; 7193 7194 return 0; 7195 } 7196 7197 #endif 7198 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7199 { 7200 struct e1000_hw *hw = &adapter->hw; 7201 u32 ping; 7202 int i; 7203 7204 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7205 ping = E1000_PF_CONTROL_MSG; 7206 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7207 ping |= E1000_VT_MSGTYPE_CTS; 7208 igb_write_mbx(hw, &ping, 1, i); 7209 } 7210 } 7211 7212 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7213 { 7214 struct e1000_hw *hw = &adapter->hw; 7215 u32 vmolr = rd32(E1000_VMOLR(vf)); 7216 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7217 7218 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7219 IGB_VF_FLAG_MULTI_PROMISC); 7220 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7221 7222 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7223 vmolr |= E1000_VMOLR_MPME; 7224 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7225 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7226 } else { 7227 /* if we have hashes and we are clearing a multicast promisc 7228 * flag we need to write the hashes to the MTA as this step 7229 * was previously skipped 7230 */ 7231 if (vf_data->num_vf_mc_hashes > 30) { 7232 vmolr |= E1000_VMOLR_MPME; 7233 } else if (vf_data->num_vf_mc_hashes) { 7234 int j; 7235 7236 vmolr |= E1000_VMOLR_ROMPE; 7237 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7238 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7239 } 7240 } 7241 7242 wr32(E1000_VMOLR(vf), vmolr); 7243 7244 /* there are flags left unprocessed, likely not supported */ 7245 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7246 return -EINVAL; 7247 7248 return 0; 7249 } 7250 7251 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7252 u32 *msgbuf, u32 vf) 7253 { 7254 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7255 u16 *hash_list = (u16 *)&msgbuf[1]; 7256 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7257 int i; 7258 7259 /* salt away the number of multicast addresses assigned 7260 * to this VF for later use to restore when the PF multi cast 7261 * list changes 7262 */ 7263 vf_data->num_vf_mc_hashes = n; 7264 7265 /* only up to 30 hash values supported */ 7266 if (n > 30) 7267 n = 30; 7268 7269 /* store the hashes for later use */ 7270 for (i = 0; i < n; i++) 7271 vf_data->vf_mc_hashes[i] = hash_list[i]; 7272 7273 /* Flush and reset the mta with the new values */ 7274 igb_set_rx_mode(adapter->netdev); 7275 7276 return 0; 7277 } 7278 7279 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7280 { 7281 struct e1000_hw *hw = &adapter->hw; 7282 struct vf_data_storage *vf_data; 7283 int i, j; 7284 7285 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7286 u32 vmolr = rd32(E1000_VMOLR(i)); 7287 7288 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7289 7290 vf_data = &adapter->vf_data[i]; 7291 7292 if ((vf_data->num_vf_mc_hashes > 30) || 7293 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7294 vmolr |= E1000_VMOLR_MPME; 7295 } else if (vf_data->num_vf_mc_hashes) { 7296 vmolr |= E1000_VMOLR_ROMPE; 7297 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7298 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7299 } 7300 wr32(E1000_VMOLR(i), vmolr); 7301 } 7302 } 7303 7304 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7305 { 7306 struct e1000_hw *hw = &adapter->hw; 7307 u32 pool_mask, vlvf_mask, i; 7308 7309 /* create mask for VF and other pools */ 7310 pool_mask = E1000_VLVF_POOLSEL_MASK; 7311 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7312 7313 /* drop PF from pool bits */ 7314 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7315 adapter->vfs_allocated_count); 7316 7317 /* Find the vlan filter for this id */ 7318 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7319 u32 vlvf = rd32(E1000_VLVF(i)); 7320 u32 vfta_mask, vid, vfta; 7321 7322 /* remove the vf from the pool */ 7323 if (!(vlvf & vlvf_mask)) 7324 continue; 7325 7326 /* clear out bit from VLVF */ 7327 vlvf ^= vlvf_mask; 7328 7329 /* if other pools are present, just remove ourselves */ 7330 if (vlvf & pool_mask) 7331 goto update_vlvfb; 7332 7333 /* if PF is present, leave VFTA */ 7334 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7335 goto update_vlvf; 7336 7337 vid = vlvf & E1000_VLVF_VLANID_MASK; 7338 vfta_mask = BIT(vid % 32); 7339 7340 /* clear bit from VFTA */ 7341 vfta = adapter->shadow_vfta[vid / 32]; 7342 if (vfta & vfta_mask) 7343 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7344 update_vlvf: 7345 /* clear pool selection enable */ 7346 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7347 vlvf &= E1000_VLVF_POOLSEL_MASK; 7348 else 7349 vlvf = 0; 7350 update_vlvfb: 7351 /* clear pool bits */ 7352 wr32(E1000_VLVF(i), vlvf); 7353 } 7354 } 7355 7356 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7357 { 7358 u32 vlvf; 7359 int idx; 7360 7361 /* short cut the special case */ 7362 if (vlan == 0) 7363 return 0; 7364 7365 /* Search for the VLAN id in the VLVF entries */ 7366 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7367 vlvf = rd32(E1000_VLVF(idx)); 7368 if ((vlvf & VLAN_VID_MASK) == vlan) 7369 break; 7370 } 7371 7372 return idx; 7373 } 7374 7375 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7376 { 7377 struct e1000_hw *hw = &adapter->hw; 7378 u32 bits, pf_id; 7379 int idx; 7380 7381 idx = igb_find_vlvf_entry(hw, vid); 7382 if (!idx) 7383 return; 7384 7385 /* See if any other pools are set for this VLAN filter 7386 * entry other than the PF. 7387 */ 7388 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7389 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7390 bits &= rd32(E1000_VLVF(idx)); 7391 7392 /* Disable the filter so this falls into the default pool. */ 7393 if (!bits) { 7394 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7395 wr32(E1000_VLVF(idx), BIT(pf_id)); 7396 else 7397 wr32(E1000_VLVF(idx), 0); 7398 } 7399 } 7400 7401 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7402 bool add, u32 vf) 7403 { 7404 int pf_id = adapter->vfs_allocated_count; 7405 struct e1000_hw *hw = &adapter->hw; 7406 int err; 7407 7408 /* If VLAN overlaps with one the PF is currently monitoring make 7409 * sure that we are able to allocate a VLVF entry. This may be 7410 * redundant but it guarantees PF will maintain visibility to 7411 * the VLAN. 7412 */ 7413 if (add && test_bit(vid, adapter->active_vlans)) { 7414 err = igb_vfta_set(hw, vid, pf_id, true, false); 7415 if (err) 7416 return err; 7417 } 7418 7419 err = igb_vfta_set(hw, vid, vf, add, false); 7420 7421 if (add && !err) 7422 return err; 7423 7424 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7425 * we may need to drop the PF pool bit in order to allow us to free 7426 * up the VLVF resources. 7427 */ 7428 if (test_bit(vid, adapter->active_vlans) || 7429 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7430 igb_update_pf_vlvf(adapter, vid); 7431 7432 return err; 7433 } 7434 7435 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7436 { 7437 struct e1000_hw *hw = &adapter->hw; 7438 7439 if (vid) 7440 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7441 else 7442 wr32(E1000_VMVIR(vf), 0); 7443 } 7444 7445 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7446 u16 vlan, u8 qos) 7447 { 7448 int err; 7449 7450 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7451 if (err) 7452 return err; 7453 7454 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7455 igb_set_vmolr(adapter, vf, !vlan); 7456 7457 /* revoke access to previous VLAN */ 7458 if (vlan != adapter->vf_data[vf].pf_vlan) 7459 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7460 false, vf); 7461 7462 adapter->vf_data[vf].pf_vlan = vlan; 7463 adapter->vf_data[vf].pf_qos = qos; 7464 igb_set_vf_vlan_strip(adapter, vf, true); 7465 dev_info(&adapter->pdev->dev, 7466 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7467 if (test_bit(__IGB_DOWN, &adapter->state)) { 7468 dev_warn(&adapter->pdev->dev, 7469 "The VF VLAN has been set, but the PF device is not up.\n"); 7470 dev_warn(&adapter->pdev->dev, 7471 "Bring the PF device up before attempting to use the VF device.\n"); 7472 } 7473 7474 return err; 7475 } 7476 7477 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7478 { 7479 /* Restore tagless access via VLAN 0 */ 7480 igb_set_vf_vlan(adapter, 0, true, vf); 7481 7482 igb_set_vmvir(adapter, 0, vf); 7483 igb_set_vmolr(adapter, vf, true); 7484 7485 /* Remove any PF assigned VLAN */ 7486 if (adapter->vf_data[vf].pf_vlan) 7487 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7488 false, vf); 7489 7490 adapter->vf_data[vf].pf_vlan = 0; 7491 adapter->vf_data[vf].pf_qos = 0; 7492 igb_set_vf_vlan_strip(adapter, vf, false); 7493 7494 return 0; 7495 } 7496 7497 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7498 u16 vlan, u8 qos, __be16 vlan_proto) 7499 { 7500 struct igb_adapter *adapter = netdev_priv(netdev); 7501 7502 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7503 return -EINVAL; 7504 7505 if (vlan_proto != htons(ETH_P_8021Q)) 7506 return -EPROTONOSUPPORT; 7507 7508 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7509 igb_disable_port_vlan(adapter, vf); 7510 } 7511 7512 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7513 { 7514 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7515 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7516 int ret; 7517 7518 if (adapter->vf_data[vf].pf_vlan) 7519 return -1; 7520 7521 /* VLAN 0 is a special case, don't allow it to be removed */ 7522 if (!vid && !add) 7523 return 0; 7524 7525 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7526 if (!ret) 7527 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7528 return ret; 7529 } 7530 7531 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7532 { 7533 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7534 7535 /* clear flags - except flag that indicates PF has set the MAC */ 7536 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7537 vf_data->last_nack = jiffies; 7538 7539 /* reset vlans for device */ 7540 igb_clear_vf_vfta(adapter, vf); 7541 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7542 igb_set_vmvir(adapter, vf_data->pf_vlan | 7543 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7544 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7545 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7546 7547 /* reset multicast table array for vf */ 7548 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7549 7550 /* Flush and reset the mta with the new values */ 7551 igb_set_rx_mode(adapter->netdev); 7552 } 7553 7554 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7555 { 7556 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7557 7558 /* clear mac address as we were hotplug removed/added */ 7559 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7560 eth_zero_addr(vf_mac); 7561 7562 /* process remaining reset events */ 7563 igb_vf_reset(adapter, vf); 7564 } 7565 7566 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7567 { 7568 struct e1000_hw *hw = &adapter->hw; 7569 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7570 u32 reg, msgbuf[3] = {}; 7571 u8 *addr = (u8 *)(&msgbuf[1]); 7572 7573 /* process all the same items cleared in a function level reset */ 7574 igb_vf_reset(adapter, vf); 7575 7576 /* set vf mac address */ 7577 igb_set_vf_mac(adapter, vf, vf_mac); 7578 7579 /* enable transmit and receive for vf */ 7580 reg = rd32(E1000_VFTE); 7581 wr32(E1000_VFTE, reg | BIT(vf)); 7582 reg = rd32(E1000_VFRE); 7583 wr32(E1000_VFRE, reg | BIT(vf)); 7584 7585 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7586 7587 /* reply to reset with ack and vf mac address */ 7588 if (!is_zero_ether_addr(vf_mac)) { 7589 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7590 memcpy(addr, vf_mac, ETH_ALEN); 7591 } else { 7592 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7593 } 7594 igb_write_mbx(hw, msgbuf, 3, vf); 7595 } 7596 7597 static void igb_flush_mac_table(struct igb_adapter *adapter) 7598 { 7599 struct e1000_hw *hw = &adapter->hw; 7600 int i; 7601 7602 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7603 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7604 eth_zero_addr(adapter->mac_table[i].addr); 7605 adapter->mac_table[i].queue = 0; 7606 igb_rar_set_index(adapter, i); 7607 } 7608 } 7609 7610 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7611 { 7612 struct e1000_hw *hw = &adapter->hw; 7613 /* do not count rar entries reserved for VFs MAC addresses */ 7614 int rar_entries = hw->mac.rar_entry_count - 7615 adapter->vfs_allocated_count; 7616 int i, count = 0; 7617 7618 for (i = 0; i < rar_entries; i++) { 7619 /* do not count default entries */ 7620 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7621 continue; 7622 7623 /* do not count "in use" entries for different queues */ 7624 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7625 (adapter->mac_table[i].queue != queue)) 7626 continue; 7627 7628 count++; 7629 } 7630 7631 return count; 7632 } 7633 7634 /* Set default MAC address for the PF in the first RAR entry */ 7635 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7636 { 7637 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7638 7639 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7640 mac_table->queue = adapter->vfs_allocated_count; 7641 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7642 7643 igb_rar_set_index(adapter, 0); 7644 } 7645 7646 /* If the filter to be added and an already existing filter express 7647 * the same address and address type, it should be possible to only 7648 * override the other configurations, for example the queue to steer 7649 * traffic. 7650 */ 7651 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7652 const u8 *addr, const u8 flags) 7653 { 7654 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7655 return true; 7656 7657 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7658 (flags & IGB_MAC_STATE_SRC_ADDR)) 7659 return false; 7660 7661 if (!ether_addr_equal(addr, entry->addr)) 7662 return false; 7663 7664 return true; 7665 } 7666 7667 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7668 * 'flags' is used to indicate what kind of match is made, match is by 7669 * default for the destination address, if matching by source address 7670 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7671 */ 7672 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7673 const u8 *addr, const u8 queue, 7674 const u8 flags) 7675 { 7676 struct e1000_hw *hw = &adapter->hw; 7677 int rar_entries = hw->mac.rar_entry_count - 7678 adapter->vfs_allocated_count; 7679 int i; 7680 7681 if (is_zero_ether_addr(addr)) 7682 return -EINVAL; 7683 7684 /* Search for the first empty entry in the MAC table. 7685 * Do not touch entries at the end of the table reserved for the VF MAC 7686 * addresses. 7687 */ 7688 for (i = 0; i < rar_entries; i++) { 7689 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7690 addr, flags)) 7691 continue; 7692 7693 ether_addr_copy(adapter->mac_table[i].addr, addr); 7694 adapter->mac_table[i].queue = queue; 7695 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7696 7697 igb_rar_set_index(adapter, i); 7698 return i; 7699 } 7700 7701 return -ENOSPC; 7702 } 7703 7704 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7705 const u8 queue) 7706 { 7707 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7708 } 7709 7710 /* Remove a MAC filter for 'addr' directing matching traffic to 7711 * 'queue', 'flags' is used to indicate what kind of match need to be 7712 * removed, match is by default for the destination address, if 7713 * matching by source address is to be removed the flag 7714 * IGB_MAC_STATE_SRC_ADDR can be used. 7715 */ 7716 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7717 const u8 *addr, const u8 queue, 7718 const u8 flags) 7719 { 7720 struct e1000_hw *hw = &adapter->hw; 7721 int rar_entries = hw->mac.rar_entry_count - 7722 adapter->vfs_allocated_count; 7723 int i; 7724 7725 if (is_zero_ether_addr(addr)) 7726 return -EINVAL; 7727 7728 /* Search for matching entry in the MAC table based on given address 7729 * and queue. Do not touch entries at the end of the table reserved 7730 * for the VF MAC addresses. 7731 */ 7732 for (i = 0; i < rar_entries; i++) { 7733 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7734 continue; 7735 if ((adapter->mac_table[i].state & flags) != flags) 7736 continue; 7737 if (adapter->mac_table[i].queue != queue) 7738 continue; 7739 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7740 continue; 7741 7742 /* When a filter for the default address is "deleted", 7743 * we return it to its initial configuration 7744 */ 7745 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7746 adapter->mac_table[i].state = 7747 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7748 adapter->mac_table[i].queue = 7749 adapter->vfs_allocated_count; 7750 } else { 7751 adapter->mac_table[i].state = 0; 7752 adapter->mac_table[i].queue = 0; 7753 eth_zero_addr(adapter->mac_table[i].addr); 7754 } 7755 7756 igb_rar_set_index(adapter, i); 7757 return 0; 7758 } 7759 7760 return -ENOENT; 7761 } 7762 7763 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7764 const u8 queue) 7765 { 7766 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7767 } 7768 7769 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7770 const u8 *addr, u8 queue, u8 flags) 7771 { 7772 struct e1000_hw *hw = &adapter->hw; 7773 7774 /* In theory, this should be supported on 82575 as well, but 7775 * that part wasn't easily accessible during development. 7776 */ 7777 if (hw->mac.type != e1000_i210) 7778 return -EOPNOTSUPP; 7779 7780 return igb_add_mac_filter_flags(adapter, addr, queue, 7781 IGB_MAC_STATE_QUEUE_STEERING | flags); 7782 } 7783 7784 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7785 const u8 *addr, u8 queue, u8 flags) 7786 { 7787 return igb_del_mac_filter_flags(adapter, addr, queue, 7788 IGB_MAC_STATE_QUEUE_STEERING | flags); 7789 } 7790 7791 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7792 { 7793 struct igb_adapter *adapter = netdev_priv(netdev); 7794 int ret; 7795 7796 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7797 7798 return min_t(int, ret, 0); 7799 } 7800 7801 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7802 { 7803 struct igb_adapter *adapter = netdev_priv(netdev); 7804 7805 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7806 7807 return 0; 7808 } 7809 7810 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7811 const u32 info, const u8 *addr) 7812 { 7813 struct pci_dev *pdev = adapter->pdev; 7814 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7815 struct list_head *pos; 7816 struct vf_mac_filter *entry = NULL; 7817 int ret = 0; 7818 7819 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7820 !vf_data->trusted) { 7821 dev_warn(&pdev->dev, 7822 "VF %d requested MAC filter but is administratively denied\n", 7823 vf); 7824 return -EINVAL; 7825 } 7826 if (!is_valid_ether_addr(addr)) { 7827 dev_warn(&pdev->dev, 7828 "VF %d attempted to set invalid MAC filter\n", 7829 vf); 7830 return -EINVAL; 7831 } 7832 7833 switch (info) { 7834 case E1000_VF_MAC_FILTER_CLR: 7835 /* remove all unicast MAC filters related to the current VF */ 7836 list_for_each(pos, &adapter->vf_macs.l) { 7837 entry = list_entry(pos, struct vf_mac_filter, l); 7838 if (entry->vf == vf) { 7839 entry->vf = -1; 7840 entry->free = true; 7841 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7842 } 7843 } 7844 break; 7845 case E1000_VF_MAC_FILTER_ADD: 7846 /* try to find empty slot in the list */ 7847 list_for_each(pos, &adapter->vf_macs.l) { 7848 entry = list_entry(pos, struct vf_mac_filter, l); 7849 if (entry->free) 7850 break; 7851 } 7852 7853 if (entry && entry->free) { 7854 entry->free = false; 7855 entry->vf = vf; 7856 ether_addr_copy(entry->vf_mac, addr); 7857 7858 ret = igb_add_mac_filter(adapter, addr, vf); 7859 ret = min_t(int, ret, 0); 7860 } else { 7861 ret = -ENOSPC; 7862 } 7863 7864 if (ret == -ENOSPC) 7865 dev_warn(&pdev->dev, 7866 "VF %d has requested MAC filter but there is no space for it\n", 7867 vf); 7868 break; 7869 default: 7870 ret = -EINVAL; 7871 break; 7872 } 7873 7874 return ret; 7875 } 7876 7877 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7878 { 7879 struct pci_dev *pdev = adapter->pdev; 7880 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7881 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7882 7883 /* The VF MAC Address is stored in a packed array of bytes 7884 * starting at the second 32 bit word of the msg array 7885 */ 7886 unsigned char *addr = (unsigned char *)&msg[1]; 7887 int ret = 0; 7888 7889 if (!info) { 7890 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7891 !vf_data->trusted) { 7892 dev_warn(&pdev->dev, 7893 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7894 vf); 7895 return -EINVAL; 7896 } 7897 7898 if (!is_valid_ether_addr(addr)) { 7899 dev_warn(&pdev->dev, 7900 "VF %d attempted to set invalid MAC\n", 7901 vf); 7902 return -EINVAL; 7903 } 7904 7905 ret = igb_set_vf_mac(adapter, vf, addr); 7906 } else { 7907 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7908 } 7909 7910 return ret; 7911 } 7912 7913 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7914 { 7915 struct e1000_hw *hw = &adapter->hw; 7916 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7917 u32 msg = E1000_VT_MSGTYPE_NACK; 7918 7919 /* if device isn't clear to send it shouldn't be reading either */ 7920 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7921 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7922 igb_write_mbx(hw, &msg, 1, vf); 7923 vf_data->last_nack = jiffies; 7924 } 7925 } 7926 7927 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7928 { 7929 struct pci_dev *pdev = adapter->pdev; 7930 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7931 struct e1000_hw *hw = &adapter->hw; 7932 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7933 s32 retval; 7934 7935 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7936 7937 if (retval) { 7938 /* if receive failed revoke VF CTS stats and restart init */ 7939 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7940 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7941 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7942 goto unlock; 7943 goto out; 7944 } 7945 7946 /* this is a message we already processed, do nothing */ 7947 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7948 goto unlock; 7949 7950 /* until the vf completes a reset it should not be 7951 * allowed to start any configuration. 7952 */ 7953 if (msgbuf[0] == E1000_VF_RESET) { 7954 /* unlocks mailbox */ 7955 igb_vf_reset_msg(adapter, vf); 7956 return; 7957 } 7958 7959 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7960 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7961 goto unlock; 7962 retval = -1; 7963 goto out; 7964 } 7965 7966 switch ((msgbuf[0] & 0xFFFF)) { 7967 case E1000_VF_SET_MAC_ADDR: 7968 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7969 break; 7970 case E1000_VF_SET_PROMISC: 7971 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7972 break; 7973 case E1000_VF_SET_MULTICAST: 7974 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7975 break; 7976 case E1000_VF_SET_LPE: 7977 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7978 break; 7979 case E1000_VF_SET_VLAN: 7980 retval = -1; 7981 if (vf_data->pf_vlan) 7982 dev_warn(&pdev->dev, 7983 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7984 vf); 7985 else 7986 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7987 break; 7988 default: 7989 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7990 retval = -1; 7991 break; 7992 } 7993 7994 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7995 out: 7996 /* notify the VF of the results of what it sent us */ 7997 if (retval) 7998 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7999 else 8000 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8001 8002 /* unlocks mailbox */ 8003 igb_write_mbx(hw, msgbuf, 1, vf); 8004 return; 8005 8006 unlock: 8007 igb_unlock_mbx(hw, vf); 8008 } 8009 8010 static void igb_msg_task(struct igb_adapter *adapter) 8011 { 8012 struct e1000_hw *hw = &adapter->hw; 8013 unsigned long flags; 8014 u32 vf; 8015 8016 spin_lock_irqsave(&adapter->vfs_lock, flags); 8017 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8018 /* process any reset requests */ 8019 if (!igb_check_for_rst(hw, vf)) 8020 igb_vf_reset_event(adapter, vf); 8021 8022 /* process any messages pending */ 8023 if (!igb_check_for_msg(hw, vf)) 8024 igb_rcv_msg_from_vf(adapter, vf); 8025 8026 /* process any acks */ 8027 if (!igb_check_for_ack(hw, vf)) 8028 igb_rcv_ack_from_vf(adapter, vf); 8029 } 8030 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8031 } 8032 8033 /** 8034 * igb_set_uta - Set unicast filter table address 8035 * @adapter: board private structure 8036 * @set: boolean indicating if we are setting or clearing bits 8037 * 8038 * The unicast table address is a register array of 32-bit registers. 8039 * The table is meant to be used in a way similar to how the MTA is used 8040 * however due to certain limitations in the hardware it is necessary to 8041 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8042 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8043 **/ 8044 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8045 { 8046 struct e1000_hw *hw = &adapter->hw; 8047 u32 uta = set ? ~0 : 0; 8048 int i; 8049 8050 /* we only need to do this if VMDq is enabled */ 8051 if (!adapter->vfs_allocated_count) 8052 return; 8053 8054 for (i = hw->mac.uta_reg_count; i--;) 8055 array_wr32(E1000_UTA, i, uta); 8056 } 8057 8058 /** 8059 * igb_intr_msi - Interrupt Handler 8060 * @irq: interrupt number 8061 * @data: pointer to a network interface device structure 8062 **/ 8063 static irqreturn_t igb_intr_msi(int irq, void *data) 8064 { 8065 struct igb_adapter *adapter = data; 8066 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8067 struct e1000_hw *hw = &adapter->hw; 8068 /* read ICR disables interrupts using IAM */ 8069 u32 icr = rd32(E1000_ICR); 8070 8071 igb_write_itr(q_vector); 8072 8073 if (icr & E1000_ICR_DRSTA) 8074 schedule_work(&adapter->reset_task); 8075 8076 if (icr & E1000_ICR_DOUTSYNC) { 8077 /* HW is reporting DMA is out of sync */ 8078 adapter->stats.doosync++; 8079 } 8080 8081 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8082 hw->mac.get_link_status = 1; 8083 if (!test_bit(__IGB_DOWN, &adapter->state)) 8084 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8085 } 8086 8087 if (icr & E1000_ICR_TS) 8088 igb_tsync_interrupt(adapter); 8089 8090 napi_schedule(&q_vector->napi); 8091 8092 return IRQ_HANDLED; 8093 } 8094 8095 /** 8096 * igb_intr - Legacy Interrupt Handler 8097 * @irq: interrupt number 8098 * @data: pointer to a network interface device structure 8099 **/ 8100 static irqreturn_t igb_intr(int irq, void *data) 8101 { 8102 struct igb_adapter *adapter = data; 8103 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8104 struct e1000_hw *hw = &adapter->hw; 8105 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8106 * need for the IMC write 8107 */ 8108 u32 icr = rd32(E1000_ICR); 8109 8110 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8111 * not set, then the adapter didn't send an interrupt 8112 */ 8113 if (!(icr & E1000_ICR_INT_ASSERTED)) 8114 return IRQ_NONE; 8115 8116 igb_write_itr(q_vector); 8117 8118 if (icr & E1000_ICR_DRSTA) 8119 schedule_work(&adapter->reset_task); 8120 8121 if (icr & E1000_ICR_DOUTSYNC) { 8122 /* HW is reporting DMA is out of sync */ 8123 adapter->stats.doosync++; 8124 } 8125 8126 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8127 hw->mac.get_link_status = 1; 8128 /* guard against interrupt when we're going down */ 8129 if (!test_bit(__IGB_DOWN, &adapter->state)) 8130 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8131 } 8132 8133 if (icr & E1000_ICR_TS) 8134 igb_tsync_interrupt(adapter); 8135 8136 napi_schedule(&q_vector->napi); 8137 8138 return IRQ_HANDLED; 8139 } 8140 8141 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8142 { 8143 struct igb_adapter *adapter = q_vector->adapter; 8144 struct e1000_hw *hw = &adapter->hw; 8145 8146 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8147 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8148 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8149 igb_set_itr(q_vector); 8150 else 8151 igb_update_ring_itr(q_vector); 8152 } 8153 8154 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8155 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8156 wr32(E1000_EIMS, q_vector->eims_value); 8157 else 8158 igb_irq_enable(adapter); 8159 } 8160 } 8161 8162 /** 8163 * igb_poll - NAPI Rx polling callback 8164 * @napi: napi polling structure 8165 * @budget: count of how many packets we should handle 8166 **/ 8167 static int igb_poll(struct napi_struct *napi, int budget) 8168 { 8169 struct igb_q_vector *q_vector = container_of(napi, 8170 struct igb_q_vector, 8171 napi); 8172 bool clean_complete = true; 8173 int work_done = 0; 8174 8175 #ifdef CONFIG_IGB_DCA 8176 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8177 igb_update_dca(q_vector); 8178 #endif 8179 if (q_vector->tx.ring) 8180 clean_complete = igb_clean_tx_irq(q_vector, budget); 8181 8182 if (q_vector->rx.ring) { 8183 int cleaned = igb_clean_rx_irq(q_vector, budget); 8184 8185 work_done += cleaned; 8186 if (cleaned >= budget) 8187 clean_complete = false; 8188 } 8189 8190 /* If all work not completed, return budget and keep polling */ 8191 if (!clean_complete) 8192 return budget; 8193 8194 /* Exit the polling mode, but don't re-enable interrupts if stack might 8195 * poll us due to busy-polling 8196 */ 8197 if (likely(napi_complete_done(napi, work_done))) 8198 igb_ring_irq_enable(q_vector); 8199 8200 return work_done; 8201 } 8202 8203 /** 8204 * igb_clean_tx_irq - Reclaim resources after transmit completes 8205 * @q_vector: pointer to q_vector containing needed info 8206 * @napi_budget: Used to determine if we are in netpoll 8207 * 8208 * returns true if ring is completely cleaned 8209 **/ 8210 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8211 { 8212 struct igb_adapter *adapter = q_vector->adapter; 8213 struct igb_ring *tx_ring = q_vector->tx.ring; 8214 struct igb_tx_buffer *tx_buffer; 8215 union e1000_adv_tx_desc *tx_desc; 8216 unsigned int total_bytes = 0, total_packets = 0; 8217 unsigned int budget = q_vector->tx.work_limit; 8218 unsigned int i = tx_ring->next_to_clean; 8219 8220 if (test_bit(__IGB_DOWN, &adapter->state)) 8221 return true; 8222 8223 tx_buffer = &tx_ring->tx_buffer_info[i]; 8224 tx_desc = IGB_TX_DESC(tx_ring, i); 8225 i -= tx_ring->count; 8226 8227 do { 8228 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8229 8230 /* if next_to_watch is not set then there is no work pending */ 8231 if (!eop_desc) 8232 break; 8233 8234 /* prevent any other reads prior to eop_desc */ 8235 smp_rmb(); 8236 8237 /* if DD is not set pending work has not been completed */ 8238 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8239 break; 8240 8241 /* clear next_to_watch to prevent false hangs */ 8242 tx_buffer->next_to_watch = NULL; 8243 8244 /* update the statistics for this packet */ 8245 total_bytes += tx_buffer->bytecount; 8246 total_packets += tx_buffer->gso_segs; 8247 8248 /* free the skb */ 8249 if (tx_buffer->type == IGB_TYPE_SKB) 8250 napi_consume_skb(tx_buffer->skb, napi_budget); 8251 else 8252 xdp_return_frame(tx_buffer->xdpf); 8253 8254 /* unmap skb header data */ 8255 dma_unmap_single(tx_ring->dev, 8256 dma_unmap_addr(tx_buffer, dma), 8257 dma_unmap_len(tx_buffer, len), 8258 DMA_TO_DEVICE); 8259 8260 /* clear tx_buffer data */ 8261 dma_unmap_len_set(tx_buffer, len, 0); 8262 8263 /* clear last DMA location and unmap remaining buffers */ 8264 while (tx_desc != eop_desc) { 8265 tx_buffer++; 8266 tx_desc++; 8267 i++; 8268 if (unlikely(!i)) { 8269 i -= tx_ring->count; 8270 tx_buffer = tx_ring->tx_buffer_info; 8271 tx_desc = IGB_TX_DESC(tx_ring, 0); 8272 } 8273 8274 /* unmap any remaining paged data */ 8275 if (dma_unmap_len(tx_buffer, len)) { 8276 dma_unmap_page(tx_ring->dev, 8277 dma_unmap_addr(tx_buffer, dma), 8278 dma_unmap_len(tx_buffer, len), 8279 DMA_TO_DEVICE); 8280 dma_unmap_len_set(tx_buffer, len, 0); 8281 } 8282 } 8283 8284 /* move us one more past the eop_desc for start of next pkt */ 8285 tx_buffer++; 8286 tx_desc++; 8287 i++; 8288 if (unlikely(!i)) { 8289 i -= tx_ring->count; 8290 tx_buffer = tx_ring->tx_buffer_info; 8291 tx_desc = IGB_TX_DESC(tx_ring, 0); 8292 } 8293 8294 /* issue prefetch for next Tx descriptor */ 8295 prefetch(tx_desc); 8296 8297 /* update budget accounting */ 8298 budget--; 8299 } while (likely(budget)); 8300 8301 netdev_tx_completed_queue(txring_txq(tx_ring), 8302 total_packets, total_bytes); 8303 i += tx_ring->count; 8304 tx_ring->next_to_clean = i; 8305 u64_stats_update_begin(&tx_ring->tx_syncp); 8306 tx_ring->tx_stats.bytes += total_bytes; 8307 tx_ring->tx_stats.packets += total_packets; 8308 u64_stats_update_end(&tx_ring->tx_syncp); 8309 q_vector->tx.total_bytes += total_bytes; 8310 q_vector->tx.total_packets += total_packets; 8311 8312 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8313 struct e1000_hw *hw = &adapter->hw; 8314 8315 /* Detect a transmit hang in hardware, this serializes the 8316 * check with the clearing of time_stamp and movement of i 8317 */ 8318 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8319 if (tx_buffer->next_to_watch && 8320 time_after(jiffies, tx_buffer->time_stamp + 8321 (adapter->tx_timeout_factor * HZ)) && 8322 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8323 8324 /* detected Tx unit hang */ 8325 dev_err(tx_ring->dev, 8326 "Detected Tx Unit Hang\n" 8327 " Tx Queue <%d>\n" 8328 " TDH <%x>\n" 8329 " TDT <%x>\n" 8330 " next_to_use <%x>\n" 8331 " next_to_clean <%x>\n" 8332 "buffer_info[next_to_clean]\n" 8333 " time_stamp <%lx>\n" 8334 " next_to_watch <%p>\n" 8335 " jiffies <%lx>\n" 8336 " desc.status <%x>\n", 8337 tx_ring->queue_index, 8338 rd32(E1000_TDH(tx_ring->reg_idx)), 8339 readl(tx_ring->tail), 8340 tx_ring->next_to_use, 8341 tx_ring->next_to_clean, 8342 tx_buffer->time_stamp, 8343 tx_buffer->next_to_watch, 8344 jiffies, 8345 tx_buffer->next_to_watch->wb.status); 8346 netif_stop_subqueue(tx_ring->netdev, 8347 tx_ring->queue_index); 8348 8349 /* we are about to reset, no point in enabling stuff */ 8350 return true; 8351 } 8352 } 8353 8354 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8355 if (unlikely(total_packets && 8356 netif_carrier_ok(tx_ring->netdev) && 8357 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8358 /* Make sure that anybody stopping the queue after this 8359 * sees the new next_to_clean. 8360 */ 8361 smp_mb(); 8362 if (__netif_subqueue_stopped(tx_ring->netdev, 8363 tx_ring->queue_index) && 8364 !(test_bit(__IGB_DOWN, &adapter->state))) { 8365 netif_wake_subqueue(tx_ring->netdev, 8366 tx_ring->queue_index); 8367 8368 u64_stats_update_begin(&tx_ring->tx_syncp); 8369 tx_ring->tx_stats.restart_queue++; 8370 u64_stats_update_end(&tx_ring->tx_syncp); 8371 } 8372 } 8373 8374 return !!budget; 8375 } 8376 8377 /** 8378 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8379 * @rx_ring: rx descriptor ring to store buffers on 8380 * @old_buff: donor buffer to have page reused 8381 * 8382 * Synchronizes page for reuse by the adapter 8383 **/ 8384 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8385 struct igb_rx_buffer *old_buff) 8386 { 8387 struct igb_rx_buffer *new_buff; 8388 u16 nta = rx_ring->next_to_alloc; 8389 8390 new_buff = &rx_ring->rx_buffer_info[nta]; 8391 8392 /* update, and store next to alloc */ 8393 nta++; 8394 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8395 8396 /* Transfer page from old buffer to new buffer. 8397 * Move each member individually to avoid possible store 8398 * forwarding stalls. 8399 */ 8400 new_buff->dma = old_buff->dma; 8401 new_buff->page = old_buff->page; 8402 new_buff->page_offset = old_buff->page_offset; 8403 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8404 } 8405 8406 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8407 int rx_buf_pgcnt) 8408 { 8409 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8410 struct page *page = rx_buffer->page; 8411 8412 /* avoid re-using remote and pfmemalloc pages */ 8413 if (!dev_page_is_reusable(page)) 8414 return false; 8415 8416 #if (PAGE_SIZE < 8192) 8417 /* if we are only owner of page we can reuse it */ 8418 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8419 return false; 8420 #else 8421 #define IGB_LAST_OFFSET \ 8422 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8423 8424 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8425 return false; 8426 #endif 8427 8428 /* If we have drained the page fragment pool we need to update 8429 * the pagecnt_bias and page count so that we fully restock the 8430 * number of references the driver holds. 8431 */ 8432 if (unlikely(pagecnt_bias == 1)) { 8433 page_ref_add(page, USHRT_MAX - 1); 8434 rx_buffer->pagecnt_bias = USHRT_MAX; 8435 } 8436 8437 return true; 8438 } 8439 8440 /** 8441 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8442 * @rx_ring: rx descriptor ring to transact packets on 8443 * @rx_buffer: buffer containing page to add 8444 * @skb: sk_buff to place the data into 8445 * @size: size of buffer to be added 8446 * 8447 * This function will add the data contained in rx_buffer->page to the skb. 8448 **/ 8449 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8450 struct igb_rx_buffer *rx_buffer, 8451 struct sk_buff *skb, 8452 unsigned int size) 8453 { 8454 #if (PAGE_SIZE < 8192) 8455 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8456 #else 8457 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8458 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8459 SKB_DATA_ALIGN(size); 8460 #endif 8461 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8462 rx_buffer->page_offset, size, truesize); 8463 #if (PAGE_SIZE < 8192) 8464 rx_buffer->page_offset ^= truesize; 8465 #else 8466 rx_buffer->page_offset += truesize; 8467 #endif 8468 } 8469 8470 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8471 struct igb_rx_buffer *rx_buffer, 8472 struct xdp_buff *xdp, 8473 ktime_t timestamp) 8474 { 8475 #if (PAGE_SIZE < 8192) 8476 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8477 #else 8478 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8479 xdp->data_hard_start); 8480 #endif 8481 unsigned int size = xdp->data_end - xdp->data; 8482 unsigned int headlen; 8483 struct sk_buff *skb; 8484 8485 /* prefetch first cache line of first page */ 8486 net_prefetch(xdp->data); 8487 8488 /* allocate a skb to store the frags */ 8489 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8490 if (unlikely(!skb)) 8491 return NULL; 8492 8493 if (timestamp) 8494 skb_hwtstamps(skb)->hwtstamp = timestamp; 8495 8496 /* Determine available headroom for copy */ 8497 headlen = size; 8498 if (headlen > IGB_RX_HDR_LEN) 8499 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8500 8501 /* align pull length to size of long to optimize memcpy performance */ 8502 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8503 8504 /* update all of the pointers */ 8505 size -= headlen; 8506 if (size) { 8507 skb_add_rx_frag(skb, 0, rx_buffer->page, 8508 (xdp->data + headlen) - page_address(rx_buffer->page), 8509 size, truesize); 8510 #if (PAGE_SIZE < 8192) 8511 rx_buffer->page_offset ^= truesize; 8512 #else 8513 rx_buffer->page_offset += truesize; 8514 #endif 8515 } else { 8516 rx_buffer->pagecnt_bias++; 8517 } 8518 8519 return skb; 8520 } 8521 8522 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8523 struct igb_rx_buffer *rx_buffer, 8524 struct xdp_buff *xdp, 8525 ktime_t timestamp) 8526 { 8527 #if (PAGE_SIZE < 8192) 8528 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8529 #else 8530 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8531 SKB_DATA_ALIGN(xdp->data_end - 8532 xdp->data_hard_start); 8533 #endif 8534 unsigned int metasize = xdp->data - xdp->data_meta; 8535 struct sk_buff *skb; 8536 8537 /* prefetch first cache line of first page */ 8538 net_prefetch(xdp->data_meta); 8539 8540 /* build an skb around the page buffer */ 8541 skb = napi_build_skb(xdp->data_hard_start, truesize); 8542 if (unlikely(!skb)) 8543 return NULL; 8544 8545 /* update pointers within the skb to store the data */ 8546 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8547 __skb_put(skb, xdp->data_end - xdp->data); 8548 8549 if (metasize) 8550 skb_metadata_set(skb, metasize); 8551 8552 if (timestamp) 8553 skb_hwtstamps(skb)->hwtstamp = timestamp; 8554 8555 /* update buffer offset */ 8556 #if (PAGE_SIZE < 8192) 8557 rx_buffer->page_offset ^= truesize; 8558 #else 8559 rx_buffer->page_offset += truesize; 8560 #endif 8561 8562 return skb; 8563 } 8564 8565 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8566 struct igb_ring *rx_ring, 8567 struct xdp_buff *xdp) 8568 { 8569 int err, result = IGB_XDP_PASS; 8570 struct bpf_prog *xdp_prog; 8571 u32 act; 8572 8573 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8574 8575 if (!xdp_prog) 8576 goto xdp_out; 8577 8578 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8579 8580 act = bpf_prog_run_xdp(xdp_prog, xdp); 8581 switch (act) { 8582 case XDP_PASS: 8583 break; 8584 case XDP_TX: 8585 result = igb_xdp_xmit_back(adapter, xdp); 8586 if (result == IGB_XDP_CONSUMED) 8587 goto out_failure; 8588 break; 8589 case XDP_REDIRECT: 8590 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8591 if (err) 8592 goto out_failure; 8593 result = IGB_XDP_REDIR; 8594 break; 8595 default: 8596 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8597 fallthrough; 8598 case XDP_ABORTED: 8599 out_failure: 8600 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8601 fallthrough; 8602 case XDP_DROP: 8603 result = IGB_XDP_CONSUMED; 8604 break; 8605 } 8606 xdp_out: 8607 return ERR_PTR(-result); 8608 } 8609 8610 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8611 unsigned int size) 8612 { 8613 unsigned int truesize; 8614 8615 #if (PAGE_SIZE < 8192) 8616 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8617 #else 8618 truesize = ring_uses_build_skb(rx_ring) ? 8619 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8620 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8621 SKB_DATA_ALIGN(size); 8622 #endif 8623 return truesize; 8624 } 8625 8626 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8627 struct igb_rx_buffer *rx_buffer, 8628 unsigned int size) 8629 { 8630 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8631 #if (PAGE_SIZE < 8192) 8632 rx_buffer->page_offset ^= truesize; 8633 #else 8634 rx_buffer->page_offset += truesize; 8635 #endif 8636 } 8637 8638 static inline void igb_rx_checksum(struct igb_ring *ring, 8639 union e1000_adv_rx_desc *rx_desc, 8640 struct sk_buff *skb) 8641 { 8642 skb_checksum_none_assert(skb); 8643 8644 /* Ignore Checksum bit is set */ 8645 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8646 return; 8647 8648 /* Rx checksum disabled via ethtool */ 8649 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8650 return; 8651 8652 /* TCP/UDP checksum error bit is set */ 8653 if (igb_test_staterr(rx_desc, 8654 E1000_RXDEXT_STATERR_TCPE | 8655 E1000_RXDEXT_STATERR_IPE)) { 8656 /* work around errata with sctp packets where the TCPE aka 8657 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8658 * packets, (aka let the stack check the crc32c) 8659 */ 8660 if (!((skb->len == 60) && 8661 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8662 u64_stats_update_begin(&ring->rx_syncp); 8663 ring->rx_stats.csum_err++; 8664 u64_stats_update_end(&ring->rx_syncp); 8665 } 8666 /* let the stack verify checksum errors */ 8667 return; 8668 } 8669 /* It must be a TCP or UDP packet with a valid checksum */ 8670 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8671 E1000_RXD_STAT_UDPCS)) 8672 skb->ip_summed = CHECKSUM_UNNECESSARY; 8673 8674 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8675 le32_to_cpu(rx_desc->wb.upper.status_error)); 8676 } 8677 8678 static inline void igb_rx_hash(struct igb_ring *ring, 8679 union e1000_adv_rx_desc *rx_desc, 8680 struct sk_buff *skb) 8681 { 8682 if (ring->netdev->features & NETIF_F_RXHASH) 8683 skb_set_hash(skb, 8684 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8685 PKT_HASH_TYPE_L3); 8686 } 8687 8688 /** 8689 * igb_is_non_eop - process handling of non-EOP buffers 8690 * @rx_ring: Rx ring being processed 8691 * @rx_desc: Rx descriptor for current buffer 8692 * 8693 * This function updates next to clean. If the buffer is an EOP buffer 8694 * this function exits returning false, otherwise it will place the 8695 * sk_buff in the next buffer to be chained and return true indicating 8696 * that this is in fact a non-EOP buffer. 8697 **/ 8698 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8699 union e1000_adv_rx_desc *rx_desc) 8700 { 8701 u32 ntc = rx_ring->next_to_clean + 1; 8702 8703 /* fetch, update, and store next to clean */ 8704 ntc = (ntc < rx_ring->count) ? ntc : 0; 8705 rx_ring->next_to_clean = ntc; 8706 8707 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8708 8709 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8710 return false; 8711 8712 return true; 8713 } 8714 8715 /** 8716 * igb_cleanup_headers - Correct corrupted or empty headers 8717 * @rx_ring: rx descriptor ring packet is being transacted on 8718 * @rx_desc: pointer to the EOP Rx descriptor 8719 * @skb: pointer to current skb being fixed 8720 * 8721 * Address the case where we are pulling data in on pages only 8722 * and as such no data is present in the skb header. 8723 * 8724 * In addition if skb is not at least 60 bytes we need to pad it so that 8725 * it is large enough to qualify as a valid Ethernet frame. 8726 * 8727 * Returns true if an error was encountered and skb was freed. 8728 **/ 8729 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8730 union e1000_adv_rx_desc *rx_desc, 8731 struct sk_buff *skb) 8732 { 8733 /* XDP packets use error pointer so abort at this point */ 8734 if (IS_ERR(skb)) 8735 return true; 8736 8737 if (unlikely((igb_test_staterr(rx_desc, 8738 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8739 struct net_device *netdev = rx_ring->netdev; 8740 if (!(netdev->features & NETIF_F_RXALL)) { 8741 dev_kfree_skb_any(skb); 8742 return true; 8743 } 8744 } 8745 8746 /* if eth_skb_pad returns an error the skb was freed */ 8747 if (eth_skb_pad(skb)) 8748 return true; 8749 8750 return false; 8751 } 8752 8753 /** 8754 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8755 * @rx_ring: rx descriptor ring packet is being transacted on 8756 * @rx_desc: pointer to the EOP Rx descriptor 8757 * @skb: pointer to current skb being populated 8758 * 8759 * This function checks the ring, descriptor, and packet information in 8760 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8761 * other fields within the skb. 8762 **/ 8763 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8764 union e1000_adv_rx_desc *rx_desc, 8765 struct sk_buff *skb) 8766 { 8767 struct net_device *dev = rx_ring->netdev; 8768 8769 igb_rx_hash(rx_ring, rx_desc, skb); 8770 8771 igb_rx_checksum(rx_ring, rx_desc, skb); 8772 8773 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8774 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8775 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8776 8777 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8778 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8779 u16 vid; 8780 8781 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8782 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8783 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8784 else 8785 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8786 8787 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8788 } 8789 8790 skb_record_rx_queue(skb, rx_ring->queue_index); 8791 8792 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8793 } 8794 8795 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8796 { 8797 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8798 } 8799 8800 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8801 const unsigned int size, int *rx_buf_pgcnt) 8802 { 8803 struct igb_rx_buffer *rx_buffer; 8804 8805 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8806 *rx_buf_pgcnt = 8807 #if (PAGE_SIZE < 8192) 8808 page_count(rx_buffer->page); 8809 #else 8810 0; 8811 #endif 8812 prefetchw(rx_buffer->page); 8813 8814 /* we are reusing so sync this buffer for CPU use */ 8815 dma_sync_single_range_for_cpu(rx_ring->dev, 8816 rx_buffer->dma, 8817 rx_buffer->page_offset, 8818 size, 8819 DMA_FROM_DEVICE); 8820 8821 rx_buffer->pagecnt_bias--; 8822 8823 return rx_buffer; 8824 } 8825 8826 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8827 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8828 { 8829 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8830 /* hand second half of page back to the ring */ 8831 igb_reuse_rx_page(rx_ring, rx_buffer); 8832 } else { 8833 /* We are not reusing the buffer so unmap it and free 8834 * any references we are holding to it 8835 */ 8836 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8837 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8838 IGB_RX_DMA_ATTR); 8839 __page_frag_cache_drain(rx_buffer->page, 8840 rx_buffer->pagecnt_bias); 8841 } 8842 8843 /* clear contents of rx_buffer */ 8844 rx_buffer->page = NULL; 8845 } 8846 8847 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8848 { 8849 struct igb_adapter *adapter = q_vector->adapter; 8850 struct igb_ring *rx_ring = q_vector->rx.ring; 8851 struct sk_buff *skb = rx_ring->skb; 8852 unsigned int total_bytes = 0, total_packets = 0; 8853 u16 cleaned_count = igb_desc_unused(rx_ring); 8854 unsigned int xdp_xmit = 0; 8855 struct xdp_buff xdp; 8856 u32 frame_sz = 0; 8857 int rx_buf_pgcnt; 8858 8859 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8860 #if (PAGE_SIZE < 8192) 8861 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8862 #endif 8863 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8864 8865 while (likely(total_packets < budget)) { 8866 union e1000_adv_rx_desc *rx_desc; 8867 struct igb_rx_buffer *rx_buffer; 8868 ktime_t timestamp = 0; 8869 int pkt_offset = 0; 8870 unsigned int size; 8871 void *pktbuf; 8872 8873 /* return some buffers to hardware, one at a time is too slow */ 8874 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8875 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8876 cleaned_count = 0; 8877 } 8878 8879 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8880 size = le16_to_cpu(rx_desc->wb.upper.length); 8881 if (!size) 8882 break; 8883 8884 /* This memory barrier is needed to keep us from reading 8885 * any other fields out of the rx_desc until we know the 8886 * descriptor has been written back 8887 */ 8888 dma_rmb(); 8889 8890 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8891 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8892 8893 /* pull rx packet timestamp if available and valid */ 8894 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8895 int ts_hdr_len; 8896 8897 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8898 pktbuf, ×tamp); 8899 8900 pkt_offset += ts_hdr_len; 8901 size -= ts_hdr_len; 8902 } 8903 8904 /* retrieve a buffer from the ring */ 8905 if (!skb) { 8906 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8907 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8908 8909 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8910 xdp_buff_clear_frags_flag(&xdp); 8911 #if (PAGE_SIZE > 4096) 8912 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8913 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8914 #endif 8915 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8916 } 8917 8918 if (IS_ERR(skb)) { 8919 unsigned int xdp_res = -PTR_ERR(skb); 8920 8921 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8922 xdp_xmit |= xdp_res; 8923 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8924 } else { 8925 rx_buffer->pagecnt_bias++; 8926 } 8927 total_packets++; 8928 total_bytes += size; 8929 } else if (skb) 8930 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8931 else if (ring_uses_build_skb(rx_ring)) 8932 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8933 timestamp); 8934 else 8935 skb = igb_construct_skb(rx_ring, rx_buffer, 8936 &xdp, timestamp); 8937 8938 /* exit if we failed to retrieve a buffer */ 8939 if (!skb) { 8940 rx_ring->rx_stats.alloc_failed++; 8941 rx_buffer->pagecnt_bias++; 8942 break; 8943 } 8944 8945 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8946 cleaned_count++; 8947 8948 /* fetch next buffer in frame if non-eop */ 8949 if (igb_is_non_eop(rx_ring, rx_desc)) 8950 continue; 8951 8952 /* verify the packet layout is correct */ 8953 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8954 skb = NULL; 8955 continue; 8956 } 8957 8958 /* probably a little skewed due to removing CRC */ 8959 total_bytes += skb->len; 8960 8961 /* populate checksum, timestamp, VLAN, and protocol */ 8962 igb_process_skb_fields(rx_ring, rx_desc, skb); 8963 8964 napi_gro_receive(&q_vector->napi, skb); 8965 8966 /* reset skb pointer */ 8967 skb = NULL; 8968 8969 /* update budget accounting */ 8970 total_packets++; 8971 } 8972 8973 /* place incomplete frames back on ring for completion */ 8974 rx_ring->skb = skb; 8975 8976 if (xdp_xmit & IGB_XDP_REDIR) 8977 xdp_do_flush(); 8978 8979 if (xdp_xmit & IGB_XDP_TX) { 8980 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8981 8982 igb_xdp_ring_update_tail(tx_ring); 8983 } 8984 8985 u64_stats_update_begin(&rx_ring->rx_syncp); 8986 rx_ring->rx_stats.packets += total_packets; 8987 rx_ring->rx_stats.bytes += total_bytes; 8988 u64_stats_update_end(&rx_ring->rx_syncp); 8989 q_vector->rx.total_packets += total_packets; 8990 q_vector->rx.total_bytes += total_bytes; 8991 8992 if (cleaned_count) 8993 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8994 8995 return total_packets; 8996 } 8997 8998 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8999 struct igb_rx_buffer *bi) 9000 { 9001 struct page *page = bi->page; 9002 dma_addr_t dma; 9003 9004 /* since we are recycling buffers we should seldom need to alloc */ 9005 if (likely(page)) 9006 return true; 9007 9008 /* alloc new page for storage */ 9009 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9010 if (unlikely(!page)) { 9011 rx_ring->rx_stats.alloc_failed++; 9012 return false; 9013 } 9014 9015 /* map page for use */ 9016 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9017 igb_rx_pg_size(rx_ring), 9018 DMA_FROM_DEVICE, 9019 IGB_RX_DMA_ATTR); 9020 9021 /* if mapping failed free memory back to system since 9022 * there isn't much point in holding memory we can't use 9023 */ 9024 if (dma_mapping_error(rx_ring->dev, dma)) { 9025 __free_pages(page, igb_rx_pg_order(rx_ring)); 9026 9027 rx_ring->rx_stats.alloc_failed++; 9028 return false; 9029 } 9030 9031 bi->dma = dma; 9032 bi->page = page; 9033 bi->page_offset = igb_rx_offset(rx_ring); 9034 page_ref_add(page, USHRT_MAX - 1); 9035 bi->pagecnt_bias = USHRT_MAX; 9036 9037 return true; 9038 } 9039 9040 /** 9041 * igb_alloc_rx_buffers - Replace used receive buffers 9042 * @rx_ring: rx descriptor ring to allocate new receive buffers 9043 * @cleaned_count: count of buffers to allocate 9044 **/ 9045 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9046 { 9047 union e1000_adv_rx_desc *rx_desc; 9048 struct igb_rx_buffer *bi; 9049 u16 i = rx_ring->next_to_use; 9050 u16 bufsz; 9051 9052 /* nothing to do */ 9053 if (!cleaned_count) 9054 return; 9055 9056 rx_desc = IGB_RX_DESC(rx_ring, i); 9057 bi = &rx_ring->rx_buffer_info[i]; 9058 i -= rx_ring->count; 9059 9060 bufsz = igb_rx_bufsz(rx_ring); 9061 9062 do { 9063 if (!igb_alloc_mapped_page(rx_ring, bi)) 9064 break; 9065 9066 /* sync the buffer for use by the device */ 9067 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9068 bi->page_offset, bufsz, 9069 DMA_FROM_DEVICE); 9070 9071 /* Refresh the desc even if buffer_addrs didn't change 9072 * because each write-back erases this info. 9073 */ 9074 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9075 9076 rx_desc++; 9077 bi++; 9078 i++; 9079 if (unlikely(!i)) { 9080 rx_desc = IGB_RX_DESC(rx_ring, 0); 9081 bi = rx_ring->rx_buffer_info; 9082 i -= rx_ring->count; 9083 } 9084 9085 /* clear the length for the next_to_use descriptor */ 9086 rx_desc->wb.upper.length = 0; 9087 9088 cleaned_count--; 9089 } while (cleaned_count); 9090 9091 i += rx_ring->count; 9092 9093 if (rx_ring->next_to_use != i) { 9094 /* record the next descriptor to use */ 9095 rx_ring->next_to_use = i; 9096 9097 /* update next to alloc since we have filled the ring */ 9098 rx_ring->next_to_alloc = i; 9099 9100 /* Force memory writes to complete before letting h/w 9101 * know there are new descriptors to fetch. (Only 9102 * applicable for weak-ordered memory model archs, 9103 * such as IA-64). 9104 */ 9105 dma_wmb(); 9106 writel(i, rx_ring->tail); 9107 } 9108 } 9109 9110 /** 9111 * igb_mii_ioctl - 9112 * @netdev: pointer to netdev struct 9113 * @ifr: interface structure 9114 * @cmd: ioctl command to execute 9115 **/ 9116 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9117 { 9118 struct igb_adapter *adapter = netdev_priv(netdev); 9119 struct mii_ioctl_data *data = if_mii(ifr); 9120 9121 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9122 return -EOPNOTSUPP; 9123 9124 switch (cmd) { 9125 case SIOCGMIIPHY: 9126 data->phy_id = adapter->hw.phy.addr; 9127 break; 9128 case SIOCGMIIREG: 9129 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9130 &data->val_out)) 9131 return -EIO; 9132 break; 9133 case SIOCSMIIREG: 9134 default: 9135 return -EOPNOTSUPP; 9136 } 9137 return 0; 9138 } 9139 9140 /** 9141 * igb_ioctl - 9142 * @netdev: pointer to netdev struct 9143 * @ifr: interface structure 9144 * @cmd: ioctl command to execute 9145 **/ 9146 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9147 { 9148 switch (cmd) { 9149 case SIOCGMIIPHY: 9150 case SIOCGMIIREG: 9151 case SIOCSMIIREG: 9152 return igb_mii_ioctl(netdev, ifr, cmd); 9153 case SIOCGHWTSTAMP: 9154 return igb_ptp_get_ts_config(netdev, ifr); 9155 case SIOCSHWTSTAMP: 9156 return igb_ptp_set_ts_config(netdev, ifr); 9157 default: 9158 return -EOPNOTSUPP; 9159 } 9160 } 9161 9162 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9163 { 9164 struct igb_adapter *adapter = hw->back; 9165 9166 pci_read_config_word(adapter->pdev, reg, value); 9167 } 9168 9169 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9170 { 9171 struct igb_adapter *adapter = hw->back; 9172 9173 pci_write_config_word(adapter->pdev, reg, *value); 9174 } 9175 9176 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9177 { 9178 struct igb_adapter *adapter = hw->back; 9179 9180 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9181 return -E1000_ERR_CONFIG; 9182 9183 return 0; 9184 } 9185 9186 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9187 { 9188 struct igb_adapter *adapter = hw->back; 9189 9190 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9191 return -E1000_ERR_CONFIG; 9192 9193 return 0; 9194 } 9195 9196 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9197 { 9198 struct igb_adapter *adapter = netdev_priv(netdev); 9199 struct e1000_hw *hw = &adapter->hw; 9200 u32 ctrl, rctl; 9201 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9202 9203 if (enable) { 9204 /* enable VLAN tag insert/strip */ 9205 ctrl = rd32(E1000_CTRL); 9206 ctrl |= E1000_CTRL_VME; 9207 wr32(E1000_CTRL, ctrl); 9208 9209 /* Disable CFI check */ 9210 rctl = rd32(E1000_RCTL); 9211 rctl &= ~E1000_RCTL_CFIEN; 9212 wr32(E1000_RCTL, rctl); 9213 } else { 9214 /* disable VLAN tag insert/strip */ 9215 ctrl = rd32(E1000_CTRL); 9216 ctrl &= ~E1000_CTRL_VME; 9217 wr32(E1000_CTRL, ctrl); 9218 } 9219 9220 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9221 } 9222 9223 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9224 __be16 proto, u16 vid) 9225 { 9226 struct igb_adapter *adapter = netdev_priv(netdev); 9227 struct e1000_hw *hw = &adapter->hw; 9228 int pf_id = adapter->vfs_allocated_count; 9229 9230 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9231 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9232 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9233 9234 set_bit(vid, adapter->active_vlans); 9235 9236 return 0; 9237 } 9238 9239 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9240 __be16 proto, u16 vid) 9241 { 9242 struct igb_adapter *adapter = netdev_priv(netdev); 9243 int pf_id = adapter->vfs_allocated_count; 9244 struct e1000_hw *hw = &adapter->hw; 9245 9246 /* remove VID from filter table */ 9247 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9248 igb_vfta_set(hw, vid, pf_id, false, true); 9249 9250 clear_bit(vid, adapter->active_vlans); 9251 9252 return 0; 9253 } 9254 9255 static void igb_restore_vlan(struct igb_adapter *adapter) 9256 { 9257 u16 vid = 1; 9258 9259 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9260 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9261 9262 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9263 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9264 } 9265 9266 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9267 { 9268 struct pci_dev *pdev = adapter->pdev; 9269 struct e1000_mac_info *mac = &adapter->hw.mac; 9270 9271 mac->autoneg = 0; 9272 9273 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9274 * for the switch() below to work 9275 */ 9276 if ((spd & 1) || (dplx & ~1)) 9277 goto err_inval; 9278 9279 /* Fiber NIC's only allow 1000 gbps Full duplex 9280 * and 100Mbps Full duplex for 100baseFx sfp 9281 */ 9282 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9283 switch (spd + dplx) { 9284 case SPEED_10 + DUPLEX_HALF: 9285 case SPEED_10 + DUPLEX_FULL: 9286 case SPEED_100 + DUPLEX_HALF: 9287 goto err_inval; 9288 default: 9289 break; 9290 } 9291 } 9292 9293 switch (spd + dplx) { 9294 case SPEED_10 + DUPLEX_HALF: 9295 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9296 break; 9297 case SPEED_10 + DUPLEX_FULL: 9298 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9299 break; 9300 case SPEED_100 + DUPLEX_HALF: 9301 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9302 break; 9303 case SPEED_100 + DUPLEX_FULL: 9304 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9305 break; 9306 case SPEED_1000 + DUPLEX_FULL: 9307 mac->autoneg = 1; 9308 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9309 break; 9310 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9311 default: 9312 goto err_inval; 9313 } 9314 9315 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9316 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9317 9318 return 0; 9319 9320 err_inval: 9321 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9322 return -EINVAL; 9323 } 9324 9325 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9326 bool runtime) 9327 { 9328 struct net_device *netdev = pci_get_drvdata(pdev); 9329 struct igb_adapter *adapter = netdev_priv(netdev); 9330 struct e1000_hw *hw = &adapter->hw; 9331 u32 ctrl, rctl, status; 9332 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9333 bool wake; 9334 9335 rtnl_lock(); 9336 netif_device_detach(netdev); 9337 9338 if (netif_running(netdev)) 9339 __igb_close(netdev, true); 9340 9341 igb_ptp_suspend(adapter); 9342 9343 igb_clear_interrupt_scheme(adapter); 9344 rtnl_unlock(); 9345 9346 status = rd32(E1000_STATUS); 9347 if (status & E1000_STATUS_LU) 9348 wufc &= ~E1000_WUFC_LNKC; 9349 9350 if (wufc) { 9351 igb_setup_rctl(adapter); 9352 igb_set_rx_mode(netdev); 9353 9354 /* turn on all-multi mode if wake on multicast is enabled */ 9355 if (wufc & E1000_WUFC_MC) { 9356 rctl = rd32(E1000_RCTL); 9357 rctl |= E1000_RCTL_MPE; 9358 wr32(E1000_RCTL, rctl); 9359 } 9360 9361 ctrl = rd32(E1000_CTRL); 9362 ctrl |= E1000_CTRL_ADVD3WUC; 9363 wr32(E1000_CTRL, ctrl); 9364 9365 /* Allow time for pending master requests to run */ 9366 igb_disable_pcie_master(hw); 9367 9368 wr32(E1000_WUC, E1000_WUC_PME_EN); 9369 wr32(E1000_WUFC, wufc); 9370 } else { 9371 wr32(E1000_WUC, 0); 9372 wr32(E1000_WUFC, 0); 9373 } 9374 9375 wake = wufc || adapter->en_mng_pt; 9376 if (!wake) 9377 igb_power_down_link(adapter); 9378 else 9379 igb_power_up_link(adapter); 9380 9381 if (enable_wake) 9382 *enable_wake = wake; 9383 9384 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9385 * would have already happened in close and is redundant. 9386 */ 9387 igb_release_hw_control(adapter); 9388 9389 pci_disable_device(pdev); 9390 9391 return 0; 9392 } 9393 9394 static void igb_deliver_wake_packet(struct net_device *netdev) 9395 { 9396 struct igb_adapter *adapter = netdev_priv(netdev); 9397 struct e1000_hw *hw = &adapter->hw; 9398 struct sk_buff *skb; 9399 u32 wupl; 9400 9401 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9402 9403 /* WUPM stores only the first 128 bytes of the wake packet. 9404 * Read the packet only if we have the whole thing. 9405 */ 9406 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9407 return; 9408 9409 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9410 if (!skb) 9411 return; 9412 9413 skb_put(skb, wupl); 9414 9415 /* Ensure reads are 32-bit aligned */ 9416 wupl = roundup(wupl, 4); 9417 9418 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9419 9420 skb->protocol = eth_type_trans(skb, netdev); 9421 netif_rx(skb); 9422 } 9423 9424 static int __maybe_unused igb_suspend(struct device *dev) 9425 { 9426 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9427 } 9428 9429 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9430 { 9431 struct pci_dev *pdev = to_pci_dev(dev); 9432 struct net_device *netdev = pci_get_drvdata(pdev); 9433 struct igb_adapter *adapter = netdev_priv(netdev); 9434 struct e1000_hw *hw = &adapter->hw; 9435 u32 err, val; 9436 9437 pci_set_power_state(pdev, PCI_D0); 9438 pci_restore_state(pdev); 9439 pci_save_state(pdev); 9440 9441 if (!pci_device_is_present(pdev)) 9442 return -ENODEV; 9443 err = pci_enable_device_mem(pdev); 9444 if (err) { 9445 dev_err(&pdev->dev, 9446 "igb: Cannot enable PCI device from suspend\n"); 9447 return err; 9448 } 9449 pci_set_master(pdev); 9450 9451 pci_enable_wake(pdev, PCI_D3hot, 0); 9452 pci_enable_wake(pdev, PCI_D3cold, 0); 9453 9454 if (igb_init_interrupt_scheme(adapter, true)) { 9455 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9456 return -ENOMEM; 9457 } 9458 9459 igb_reset(adapter); 9460 9461 /* let the f/w know that the h/w is now under the control of the 9462 * driver. 9463 */ 9464 igb_get_hw_control(adapter); 9465 9466 val = rd32(E1000_WUS); 9467 if (val & WAKE_PKT_WUS) 9468 igb_deliver_wake_packet(netdev); 9469 9470 wr32(E1000_WUS, ~0); 9471 9472 if (!rpm) 9473 rtnl_lock(); 9474 if (!err && netif_running(netdev)) 9475 err = __igb_open(netdev, true); 9476 9477 if (!err) 9478 netif_device_attach(netdev); 9479 if (!rpm) 9480 rtnl_unlock(); 9481 9482 return err; 9483 } 9484 9485 static int __maybe_unused igb_resume(struct device *dev) 9486 { 9487 return __igb_resume(dev, false); 9488 } 9489 9490 static int __maybe_unused igb_runtime_idle(struct device *dev) 9491 { 9492 struct net_device *netdev = dev_get_drvdata(dev); 9493 struct igb_adapter *adapter = netdev_priv(netdev); 9494 9495 if (!igb_has_link(adapter)) 9496 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9497 9498 return -EBUSY; 9499 } 9500 9501 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9502 { 9503 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9504 } 9505 9506 static int __maybe_unused igb_runtime_resume(struct device *dev) 9507 { 9508 return __igb_resume(dev, true); 9509 } 9510 9511 static void igb_shutdown(struct pci_dev *pdev) 9512 { 9513 bool wake; 9514 9515 __igb_shutdown(pdev, &wake, 0); 9516 9517 if (system_state == SYSTEM_POWER_OFF) { 9518 pci_wake_from_d3(pdev, wake); 9519 pci_set_power_state(pdev, PCI_D3hot); 9520 } 9521 } 9522 9523 #ifdef CONFIG_PCI_IOV 9524 static int igb_sriov_reinit(struct pci_dev *dev) 9525 { 9526 struct net_device *netdev = pci_get_drvdata(dev); 9527 struct igb_adapter *adapter = netdev_priv(netdev); 9528 struct pci_dev *pdev = adapter->pdev; 9529 9530 rtnl_lock(); 9531 9532 if (netif_running(netdev)) 9533 igb_close(netdev); 9534 else 9535 igb_reset(adapter); 9536 9537 igb_clear_interrupt_scheme(adapter); 9538 9539 igb_init_queue_configuration(adapter); 9540 9541 if (igb_init_interrupt_scheme(adapter, true)) { 9542 rtnl_unlock(); 9543 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9544 return -ENOMEM; 9545 } 9546 9547 if (netif_running(netdev)) 9548 igb_open(netdev); 9549 9550 rtnl_unlock(); 9551 9552 return 0; 9553 } 9554 9555 static int igb_pci_disable_sriov(struct pci_dev *dev) 9556 { 9557 int err = igb_disable_sriov(dev); 9558 9559 if (!err) 9560 err = igb_sriov_reinit(dev); 9561 9562 return err; 9563 } 9564 9565 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9566 { 9567 int err = igb_enable_sriov(dev, num_vfs); 9568 9569 if (err) 9570 goto out; 9571 9572 err = igb_sriov_reinit(dev); 9573 if (!err) 9574 return num_vfs; 9575 9576 out: 9577 return err; 9578 } 9579 9580 #endif 9581 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9582 { 9583 #ifdef CONFIG_PCI_IOV 9584 if (num_vfs == 0) 9585 return igb_pci_disable_sriov(dev); 9586 else 9587 return igb_pci_enable_sriov(dev, num_vfs); 9588 #endif 9589 return 0; 9590 } 9591 9592 /** 9593 * igb_io_error_detected - called when PCI error is detected 9594 * @pdev: Pointer to PCI device 9595 * @state: The current pci connection state 9596 * 9597 * This function is called after a PCI bus error affecting 9598 * this device has been detected. 9599 **/ 9600 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9601 pci_channel_state_t state) 9602 { 9603 struct net_device *netdev = pci_get_drvdata(pdev); 9604 struct igb_adapter *adapter = netdev_priv(netdev); 9605 9606 netif_device_detach(netdev); 9607 9608 if (state == pci_channel_io_perm_failure) 9609 return PCI_ERS_RESULT_DISCONNECT; 9610 9611 if (netif_running(netdev)) 9612 igb_down(adapter); 9613 pci_disable_device(pdev); 9614 9615 /* Request a slot reset. */ 9616 return PCI_ERS_RESULT_NEED_RESET; 9617 } 9618 9619 /** 9620 * igb_io_slot_reset - called after the pci bus has been reset. 9621 * @pdev: Pointer to PCI device 9622 * 9623 * Restart the card from scratch, as if from a cold-boot. Implementation 9624 * resembles the first-half of the __igb_resume routine. 9625 **/ 9626 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9627 { 9628 struct net_device *netdev = pci_get_drvdata(pdev); 9629 struct igb_adapter *adapter = netdev_priv(netdev); 9630 struct e1000_hw *hw = &adapter->hw; 9631 pci_ers_result_t result; 9632 9633 if (pci_enable_device_mem(pdev)) { 9634 dev_err(&pdev->dev, 9635 "Cannot re-enable PCI device after reset.\n"); 9636 result = PCI_ERS_RESULT_DISCONNECT; 9637 } else { 9638 pci_set_master(pdev); 9639 pci_restore_state(pdev); 9640 pci_save_state(pdev); 9641 9642 pci_enable_wake(pdev, PCI_D3hot, 0); 9643 pci_enable_wake(pdev, PCI_D3cold, 0); 9644 9645 /* In case of PCI error, adapter lose its HW address 9646 * so we should re-assign it here. 9647 */ 9648 hw->hw_addr = adapter->io_addr; 9649 9650 igb_reset(adapter); 9651 wr32(E1000_WUS, ~0); 9652 result = PCI_ERS_RESULT_RECOVERED; 9653 } 9654 9655 return result; 9656 } 9657 9658 /** 9659 * igb_io_resume - called when traffic can start flowing again. 9660 * @pdev: Pointer to PCI device 9661 * 9662 * This callback is called when the error recovery driver tells us that 9663 * its OK to resume normal operation. Implementation resembles the 9664 * second-half of the __igb_resume routine. 9665 */ 9666 static void igb_io_resume(struct pci_dev *pdev) 9667 { 9668 struct net_device *netdev = pci_get_drvdata(pdev); 9669 struct igb_adapter *adapter = netdev_priv(netdev); 9670 9671 if (netif_running(netdev)) { 9672 if (igb_up(adapter)) { 9673 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9674 return; 9675 } 9676 } 9677 9678 netif_device_attach(netdev); 9679 9680 /* let the f/w know that the h/w is now under the control of the 9681 * driver. 9682 */ 9683 igb_get_hw_control(adapter); 9684 } 9685 9686 /** 9687 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9688 * @adapter: Pointer to adapter structure 9689 * @index: Index of the RAR entry which need to be synced with MAC table 9690 **/ 9691 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9692 { 9693 struct e1000_hw *hw = &adapter->hw; 9694 u32 rar_low, rar_high; 9695 u8 *addr = adapter->mac_table[index].addr; 9696 9697 /* HW expects these to be in network order when they are plugged 9698 * into the registers which are little endian. In order to guarantee 9699 * that ordering we need to do an leXX_to_cpup here in order to be 9700 * ready for the byteswap that occurs with writel 9701 */ 9702 rar_low = le32_to_cpup((__le32 *)(addr)); 9703 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9704 9705 /* Indicate to hardware the Address is Valid. */ 9706 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9707 if (is_valid_ether_addr(addr)) 9708 rar_high |= E1000_RAH_AV; 9709 9710 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9711 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9712 9713 switch (hw->mac.type) { 9714 case e1000_82575: 9715 case e1000_i210: 9716 if (adapter->mac_table[index].state & 9717 IGB_MAC_STATE_QUEUE_STEERING) 9718 rar_high |= E1000_RAH_QSEL_ENABLE; 9719 9720 rar_high |= E1000_RAH_POOL_1 * 9721 adapter->mac_table[index].queue; 9722 break; 9723 default: 9724 rar_high |= E1000_RAH_POOL_1 << 9725 adapter->mac_table[index].queue; 9726 break; 9727 } 9728 } 9729 9730 wr32(E1000_RAL(index), rar_low); 9731 wrfl(); 9732 wr32(E1000_RAH(index), rar_high); 9733 wrfl(); 9734 } 9735 9736 static int igb_set_vf_mac(struct igb_adapter *adapter, 9737 int vf, unsigned char *mac_addr) 9738 { 9739 struct e1000_hw *hw = &adapter->hw; 9740 /* VF MAC addresses start at end of receive addresses and moves 9741 * towards the first, as a result a collision should not be possible 9742 */ 9743 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9744 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9745 9746 ether_addr_copy(vf_mac_addr, mac_addr); 9747 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9748 adapter->mac_table[rar_entry].queue = vf; 9749 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9750 igb_rar_set_index(adapter, rar_entry); 9751 9752 return 0; 9753 } 9754 9755 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9756 { 9757 struct igb_adapter *adapter = netdev_priv(netdev); 9758 9759 if (vf >= adapter->vfs_allocated_count) 9760 return -EINVAL; 9761 9762 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9763 * flag and allows to overwrite the MAC via VF netdev. This 9764 * is necessary to allow libvirt a way to restore the original 9765 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9766 * down a VM. 9767 */ 9768 if (is_zero_ether_addr(mac)) { 9769 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9770 dev_info(&adapter->pdev->dev, 9771 "remove administratively set MAC on VF %d\n", 9772 vf); 9773 } else if (is_valid_ether_addr(mac)) { 9774 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9775 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9776 mac, vf); 9777 dev_info(&adapter->pdev->dev, 9778 "Reload the VF driver to make this change effective."); 9779 /* Generate additional warning if PF is down */ 9780 if (test_bit(__IGB_DOWN, &adapter->state)) { 9781 dev_warn(&adapter->pdev->dev, 9782 "The VF MAC address has been set, but the PF device is not up.\n"); 9783 dev_warn(&adapter->pdev->dev, 9784 "Bring the PF device up before attempting to use the VF device.\n"); 9785 } 9786 } else { 9787 return -EINVAL; 9788 } 9789 return igb_set_vf_mac(adapter, vf, mac); 9790 } 9791 9792 static int igb_link_mbps(int internal_link_speed) 9793 { 9794 switch (internal_link_speed) { 9795 case SPEED_100: 9796 return 100; 9797 case SPEED_1000: 9798 return 1000; 9799 default: 9800 return 0; 9801 } 9802 } 9803 9804 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9805 int link_speed) 9806 { 9807 int rf_dec, rf_int; 9808 u32 bcnrc_val; 9809 9810 if (tx_rate != 0) { 9811 /* Calculate the rate factor values to set */ 9812 rf_int = link_speed / tx_rate; 9813 rf_dec = (link_speed - (rf_int * tx_rate)); 9814 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9815 tx_rate; 9816 9817 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9818 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9819 E1000_RTTBCNRC_RF_INT_MASK); 9820 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9821 } else { 9822 bcnrc_val = 0; 9823 } 9824 9825 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9826 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9827 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9828 */ 9829 wr32(E1000_RTTBCNRM, 0x14); 9830 wr32(E1000_RTTBCNRC, bcnrc_val); 9831 } 9832 9833 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9834 { 9835 int actual_link_speed, i; 9836 bool reset_rate = false; 9837 9838 /* VF TX rate limit was not set or not supported */ 9839 if ((adapter->vf_rate_link_speed == 0) || 9840 (adapter->hw.mac.type != e1000_82576)) 9841 return; 9842 9843 actual_link_speed = igb_link_mbps(adapter->link_speed); 9844 if (actual_link_speed != adapter->vf_rate_link_speed) { 9845 reset_rate = true; 9846 adapter->vf_rate_link_speed = 0; 9847 dev_info(&adapter->pdev->dev, 9848 "Link speed has been changed. VF Transmit rate is disabled\n"); 9849 } 9850 9851 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9852 if (reset_rate) 9853 adapter->vf_data[i].tx_rate = 0; 9854 9855 igb_set_vf_rate_limit(&adapter->hw, i, 9856 adapter->vf_data[i].tx_rate, 9857 actual_link_speed); 9858 } 9859 } 9860 9861 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9862 int min_tx_rate, int max_tx_rate) 9863 { 9864 struct igb_adapter *adapter = netdev_priv(netdev); 9865 struct e1000_hw *hw = &adapter->hw; 9866 int actual_link_speed; 9867 9868 if (hw->mac.type != e1000_82576) 9869 return -EOPNOTSUPP; 9870 9871 if (min_tx_rate) 9872 return -EINVAL; 9873 9874 actual_link_speed = igb_link_mbps(adapter->link_speed); 9875 if ((vf >= adapter->vfs_allocated_count) || 9876 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9877 (max_tx_rate < 0) || 9878 (max_tx_rate > actual_link_speed)) 9879 return -EINVAL; 9880 9881 adapter->vf_rate_link_speed = actual_link_speed; 9882 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9883 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9884 9885 return 0; 9886 } 9887 9888 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9889 bool setting) 9890 { 9891 struct igb_adapter *adapter = netdev_priv(netdev); 9892 struct e1000_hw *hw = &adapter->hw; 9893 u32 reg_val, reg_offset; 9894 9895 if (!adapter->vfs_allocated_count) 9896 return -EOPNOTSUPP; 9897 9898 if (vf >= adapter->vfs_allocated_count) 9899 return -EINVAL; 9900 9901 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9902 reg_val = rd32(reg_offset); 9903 if (setting) 9904 reg_val |= (BIT(vf) | 9905 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9906 else 9907 reg_val &= ~(BIT(vf) | 9908 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9909 wr32(reg_offset, reg_val); 9910 9911 adapter->vf_data[vf].spoofchk_enabled = setting; 9912 return 0; 9913 } 9914 9915 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9916 { 9917 struct igb_adapter *adapter = netdev_priv(netdev); 9918 9919 if (vf >= adapter->vfs_allocated_count) 9920 return -EINVAL; 9921 if (adapter->vf_data[vf].trusted == setting) 9922 return 0; 9923 9924 adapter->vf_data[vf].trusted = setting; 9925 9926 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9927 vf, setting ? "" : "not "); 9928 return 0; 9929 } 9930 9931 static int igb_ndo_get_vf_config(struct net_device *netdev, 9932 int vf, struct ifla_vf_info *ivi) 9933 { 9934 struct igb_adapter *adapter = netdev_priv(netdev); 9935 if (vf >= adapter->vfs_allocated_count) 9936 return -EINVAL; 9937 ivi->vf = vf; 9938 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9939 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9940 ivi->min_tx_rate = 0; 9941 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9942 ivi->qos = adapter->vf_data[vf].pf_qos; 9943 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9944 ivi->trusted = adapter->vf_data[vf].trusted; 9945 return 0; 9946 } 9947 9948 static void igb_vmm_control(struct igb_adapter *adapter) 9949 { 9950 struct e1000_hw *hw = &adapter->hw; 9951 u32 reg; 9952 9953 switch (hw->mac.type) { 9954 case e1000_82575: 9955 case e1000_i210: 9956 case e1000_i211: 9957 case e1000_i354: 9958 default: 9959 /* replication is not supported for 82575 */ 9960 return; 9961 case e1000_82576: 9962 /* notify HW that the MAC is adding vlan tags */ 9963 reg = rd32(E1000_DTXCTL); 9964 reg |= E1000_DTXCTL_VLAN_ADDED; 9965 wr32(E1000_DTXCTL, reg); 9966 fallthrough; 9967 case e1000_82580: 9968 /* enable replication vlan tag stripping */ 9969 reg = rd32(E1000_RPLOLR); 9970 reg |= E1000_RPLOLR_STRVLAN; 9971 wr32(E1000_RPLOLR, reg); 9972 fallthrough; 9973 case e1000_i350: 9974 /* none of the above registers are supported by i350 */ 9975 break; 9976 } 9977 9978 if (adapter->vfs_allocated_count) { 9979 igb_vmdq_set_loopback_pf(hw, true); 9980 igb_vmdq_set_replication_pf(hw, true); 9981 igb_vmdq_set_anti_spoofing_pf(hw, true, 9982 adapter->vfs_allocated_count); 9983 } else { 9984 igb_vmdq_set_loopback_pf(hw, false); 9985 igb_vmdq_set_replication_pf(hw, false); 9986 } 9987 } 9988 9989 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9990 { 9991 struct e1000_hw *hw = &adapter->hw; 9992 u32 dmac_thr; 9993 u16 hwm; 9994 u32 reg; 9995 9996 if (hw->mac.type > e1000_82580) { 9997 if (adapter->flags & IGB_FLAG_DMAC) { 9998 /* force threshold to 0. */ 9999 wr32(E1000_DMCTXTH, 0); 10000 10001 /* DMA Coalescing high water mark needs to be greater 10002 * than the Rx threshold. Set hwm to PBA - max frame 10003 * size in 16B units, capping it at PBA - 6KB. 10004 */ 10005 hwm = 64 * (pba - 6); 10006 reg = rd32(E1000_FCRTC); 10007 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10008 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 10009 & E1000_FCRTC_RTH_COAL_MASK); 10010 wr32(E1000_FCRTC, reg); 10011 10012 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10013 * frame size, capping it at PBA - 10KB. 10014 */ 10015 dmac_thr = pba - 10; 10016 reg = rd32(E1000_DMACR); 10017 reg &= ~E1000_DMACR_DMACTHR_MASK; 10018 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 10019 & E1000_DMACR_DMACTHR_MASK); 10020 10021 /* transition to L0x or L1 if available..*/ 10022 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10023 10024 /* watchdog timer= +-1000 usec in 32usec intervals */ 10025 reg |= (1000 >> 5); 10026 10027 /* Disable BMC-to-OS Watchdog Enable */ 10028 if (hw->mac.type != e1000_i354) 10029 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10030 wr32(E1000_DMACR, reg); 10031 10032 /* no lower threshold to disable 10033 * coalescing(smart fifb)-UTRESH=0 10034 */ 10035 wr32(E1000_DMCRTRH, 0); 10036 10037 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10038 10039 wr32(E1000_DMCTLX, reg); 10040 10041 /* free space in tx packet buffer to wake from 10042 * DMA coal 10043 */ 10044 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10045 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10046 } 10047 10048 if (hw->mac.type >= e1000_i210 || 10049 (adapter->flags & IGB_FLAG_DMAC)) { 10050 reg = rd32(E1000_PCIEMISC); 10051 reg |= E1000_PCIEMISC_LX_DECISION; 10052 wr32(E1000_PCIEMISC, reg); 10053 } /* endif adapter->dmac is not disabled */ 10054 } else if (hw->mac.type == e1000_82580) { 10055 u32 reg = rd32(E1000_PCIEMISC); 10056 10057 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10058 wr32(E1000_DMACR, 0); 10059 } 10060 } 10061 10062 /** 10063 * igb_read_i2c_byte - Reads 8 bit word over I2C 10064 * @hw: pointer to hardware structure 10065 * @byte_offset: byte offset to read 10066 * @dev_addr: device address 10067 * @data: value read 10068 * 10069 * Performs byte read operation over I2C interface at 10070 * a specified device address. 10071 **/ 10072 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10073 u8 dev_addr, u8 *data) 10074 { 10075 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10076 struct i2c_client *this_client = adapter->i2c_client; 10077 s32 status; 10078 u16 swfw_mask = 0; 10079 10080 if (!this_client) 10081 return E1000_ERR_I2C; 10082 10083 swfw_mask = E1000_SWFW_PHY0_SM; 10084 10085 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10086 return E1000_ERR_SWFW_SYNC; 10087 10088 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10089 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10090 10091 if (status < 0) 10092 return E1000_ERR_I2C; 10093 else { 10094 *data = status; 10095 return 0; 10096 } 10097 } 10098 10099 /** 10100 * igb_write_i2c_byte - Writes 8 bit word over I2C 10101 * @hw: pointer to hardware structure 10102 * @byte_offset: byte offset to write 10103 * @dev_addr: device address 10104 * @data: value to write 10105 * 10106 * Performs byte write operation over I2C interface at 10107 * a specified device address. 10108 **/ 10109 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10110 u8 dev_addr, u8 data) 10111 { 10112 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10113 struct i2c_client *this_client = adapter->i2c_client; 10114 s32 status; 10115 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10116 10117 if (!this_client) 10118 return E1000_ERR_I2C; 10119 10120 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10121 return E1000_ERR_SWFW_SYNC; 10122 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10123 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10124 10125 if (status) 10126 return E1000_ERR_I2C; 10127 else 10128 return 0; 10129 10130 } 10131 10132 int igb_reinit_queues(struct igb_adapter *adapter) 10133 { 10134 struct net_device *netdev = adapter->netdev; 10135 struct pci_dev *pdev = adapter->pdev; 10136 int err = 0; 10137 10138 if (netif_running(netdev)) 10139 igb_close(netdev); 10140 10141 igb_reset_interrupt_capability(adapter); 10142 10143 if (igb_init_interrupt_scheme(adapter, true)) { 10144 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10145 return -ENOMEM; 10146 } 10147 10148 if (netif_running(netdev)) 10149 err = igb_open(netdev); 10150 10151 return err; 10152 } 10153 10154 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10155 { 10156 struct igb_nfc_filter *rule; 10157 10158 spin_lock(&adapter->nfc_lock); 10159 10160 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10161 igb_erase_filter(adapter, rule); 10162 10163 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10164 igb_erase_filter(adapter, rule); 10165 10166 spin_unlock(&adapter->nfc_lock); 10167 } 10168 10169 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10170 { 10171 struct igb_nfc_filter *rule; 10172 10173 spin_lock(&adapter->nfc_lock); 10174 10175 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10176 igb_add_filter(adapter, rule); 10177 10178 spin_unlock(&adapter->nfc_lock); 10179 } 10180 /* igb_main.c */ 10181