1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K 0x3100 24 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 25 26 /* Function pointers for the MAC. */ 27 struct igc_mac_operations { 28 s32 (*check_for_link)(struct igc_hw *hw); 29 s32 (*reset_hw)(struct igc_hw *hw); 30 s32 (*init_hw)(struct igc_hw *hw); 31 s32 (*setup_physical_interface)(struct igc_hw *hw); 32 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 33 s32 (*read_mac_addr)(struct igc_hw *hw); 34 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 35 u16 *duplex); 36 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 37 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 38 }; 39 40 enum igc_mac_type { 41 igc_undefined = 0, 42 igc_i225, 43 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 44 }; 45 46 enum igc_phy_type { 47 igc_phy_unknown = 0, 48 igc_phy_none, 49 igc_phy_i225, 50 }; 51 52 enum igc_media_type { 53 igc_media_type_unknown = 0, 54 igc_media_type_copper = 1, 55 igc_num_media_types 56 }; 57 58 enum igc_nvm_type { 59 igc_nvm_unknown = 0, 60 igc_nvm_eeprom_spi, 61 igc_nvm_flash_hw, 62 igc_nvm_invm, 63 }; 64 65 struct igc_info { 66 s32 (*get_invariants)(struct igc_hw *hw); 67 struct igc_mac_operations *mac_ops; 68 const struct igc_phy_operations *phy_ops; 69 struct igc_nvm_operations *nvm_ops; 70 }; 71 72 extern const struct igc_info igc_base_info; 73 74 struct igc_mac_info { 75 struct igc_mac_operations ops; 76 77 u8 addr[ETH_ALEN]; 78 u8 perm_addr[ETH_ALEN]; 79 80 enum igc_mac_type type; 81 82 u32 collision_delta; 83 u32 ledctl_default; 84 u32 ledctl_mode1; 85 u32 ledctl_mode2; 86 u32 mc_filter_type; 87 u32 tx_packet_delta; 88 u32 txcw; 89 90 u16 mta_reg_count; 91 u16 uta_reg_count; 92 93 u32 mta_shadow[MAX_MTA_REG]; 94 u16 rar_entry_count; 95 96 u8 forced_speed_duplex; 97 98 bool adaptive_ifs; 99 bool has_fwsm; 100 bool asf_firmware_present; 101 bool arc_subsystem_valid; 102 103 bool autoneg; 104 bool autoneg_failed; 105 bool get_link_status; 106 }; 107 108 struct igc_nvm_operations { 109 s32 (*acquire)(struct igc_hw *hw); 110 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 111 void (*release)(struct igc_hw *hw); 112 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 113 s32 (*update)(struct igc_hw *hw); 114 s32 (*validate)(struct igc_hw *hw); 115 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 116 }; 117 118 struct igc_phy_operations { 119 s32 (*acquire)(struct igc_hw *hw); 120 s32 (*check_reset_block)(struct igc_hw *hw); 121 s32 (*force_speed_duplex)(struct igc_hw *hw); 122 s32 (*get_phy_info)(struct igc_hw *hw); 123 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 124 void (*release)(struct igc_hw *hw); 125 s32 (*reset)(struct igc_hw *hw); 126 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 127 }; 128 129 struct igc_nvm_info { 130 struct igc_nvm_operations ops; 131 enum igc_nvm_type type; 132 133 u32 flash_bank_size; 134 u32 flash_base_addr; 135 136 u16 word_size; 137 u16 delay_usec; 138 u16 address_bits; 139 u16 opcode_bits; 140 u16 page_size; 141 }; 142 143 struct igc_phy_info { 144 struct igc_phy_operations ops; 145 146 enum igc_phy_type type; 147 148 u32 addr; 149 u32 id; 150 u32 reset_delay_us; /* in usec */ 151 u32 revision; 152 153 enum igc_media_type media_type; 154 155 u16 autoneg_advertised; 156 u16 autoneg_mask; 157 158 u8 mdix; 159 160 bool is_mdix; 161 bool reset_disable; 162 bool speed_downgraded; 163 bool autoneg_wait_to_complete; 164 }; 165 166 struct igc_bus_info { 167 u16 func; 168 u16 pci_cmd_word; 169 }; 170 171 enum igc_fc_mode { 172 igc_fc_none = 0, 173 igc_fc_rx_pause, 174 igc_fc_tx_pause, 175 igc_fc_full, 176 igc_fc_default = 0xFF 177 }; 178 179 struct igc_fc_info { 180 u32 high_water; /* Flow control high-water mark */ 181 u32 low_water; /* Flow control low-water mark */ 182 u16 pause_time; /* Flow control pause timer */ 183 bool send_xon; /* Flow control send XON */ 184 bool strict_ieee; /* Strict IEEE mode */ 185 enum igc_fc_mode current_mode; /* Type of flow control */ 186 enum igc_fc_mode requested_mode; 187 }; 188 189 struct igc_dev_spec_base { 190 bool clear_semaphore_once; 191 }; 192 193 struct igc_hw { 194 void *back; 195 196 u8 __iomem *hw_addr; 197 unsigned long io_base; 198 199 struct igc_mac_info mac; 200 struct igc_fc_info fc; 201 struct igc_nvm_info nvm; 202 struct igc_phy_info phy; 203 204 struct igc_bus_info bus; 205 206 union { 207 struct igc_dev_spec_base _base; 208 } dev_spec; 209 210 u16 device_id; 211 u16 subsystem_vendor_id; 212 u16 subsystem_device_id; 213 u16 vendor_id; 214 215 u8 revision_id; 216 }; 217 218 /* Statistics counters collected by the MAC */ 219 struct igc_hw_stats { 220 u64 crcerrs; 221 u64 algnerrc; 222 u64 symerrs; 223 u64 rxerrc; 224 u64 mpc; 225 u64 scc; 226 u64 ecol; 227 u64 mcc; 228 u64 latecol; 229 u64 colc; 230 u64 dc; 231 u64 tncrs; 232 u64 sec; 233 u64 cexterr; 234 u64 rlec; 235 u64 xonrxc; 236 u64 xontxc; 237 u64 xoffrxc; 238 u64 xofftxc; 239 u64 fcruc; 240 u64 prc64; 241 u64 prc127; 242 u64 prc255; 243 u64 prc511; 244 u64 prc1023; 245 u64 prc1522; 246 u64 gprc; 247 u64 bprc; 248 u64 mprc; 249 u64 gptc; 250 u64 gorc; 251 u64 gotc; 252 u64 rnbc; 253 u64 ruc; 254 u64 rfc; 255 u64 roc; 256 u64 rjc; 257 u64 mgprc; 258 u64 mgpdc; 259 u64 mgptc; 260 u64 tor; 261 u64 tot; 262 u64 tpr; 263 u64 tpt; 264 u64 ptc64; 265 u64 ptc127; 266 u64 ptc255; 267 u64 ptc511; 268 u64 ptc1023; 269 u64 ptc1522; 270 u64 mptc; 271 u64 bptc; 272 u64 tsctc; 273 u64 tsctfc; 274 u64 iac; 275 u64 icrxptc; 276 u64 icrxatc; 277 u64 ictxptc; 278 u64 ictxatc; 279 u64 ictxqec; 280 u64 ictxqmtc; 281 u64 icrxdmtc; 282 u64 icrxoc; 283 u64 cbtmpc; 284 u64 htdpmc; 285 u64 cbrdpc; 286 u64 cbrmpc; 287 u64 rpthc; 288 u64 hgptc; 289 u64 htcbdpc; 290 u64 hgorc; 291 u64 hgotc; 292 u64 lenerrs; 293 u64 scvpc; 294 u64 hrmpc; 295 u64 doosync; 296 u64 o2bgptc; 297 u64 o2bspc; 298 u64 b2ospc; 299 u64 b2ogprc; 300 }; 301 302 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 303 #define hw_dbg(format, arg...) \ 304 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 305 306 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 307 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 308 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 309 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 310 311 #endif /* _IGC_HW_H_ */ 312