1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* ethtool support for ixgbe */ 5 6 #include <linux/interrupt.h> 7 #include <linux/types.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/netdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/vmalloc.h> 14 #include <linux/highmem.h> 15 #include <linux/uaccess.h> 16 17 #include "ixgbe.h" 18 #include "ixgbe_phy.h" 19 20 21 enum {NETDEV_STATS, IXGBE_STATS}; 22 23 struct ixgbe_stats { 24 char stat_string[ETH_GSTRING_LEN]; 25 int type; 26 int sizeof_stat; 27 int stat_offset; 28 }; 29 30 #define IXGBE_STAT(m) IXGBE_STATS, \ 31 sizeof(((struct ixgbe_adapter *)0)->m), \ 32 offsetof(struct ixgbe_adapter, m) 33 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 34 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 35 offsetof(struct rtnl_link_stats64, m) 36 37 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 38 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 39 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 40 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 41 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 42 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 43 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 44 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 45 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 46 {"lsc_int", IXGBE_STAT(lsc_int)}, 47 {"tx_busy", IXGBE_STAT(tx_busy)}, 48 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 49 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 50 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 51 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 52 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 53 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 54 {"broadcast", IXGBE_STAT(stats.bprc)}, 55 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 56 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 57 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 58 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 59 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 60 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 61 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 62 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 63 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 64 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 65 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 66 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 67 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 68 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 69 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 70 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 71 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 72 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 73 {"rx_length_errors", IXGBE_STAT(stats.rlec)}, 74 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 75 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 76 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 77 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 78 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 79 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 80 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 81 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)}, 82 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 83 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 84 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 85 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 86 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 87 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 88 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 89 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)}, 90 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)}, 91 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)}, 92 {"tx_ipsec", IXGBE_STAT(tx_ipsec)}, 93 {"rx_ipsec", IXGBE_STAT(rx_ipsec)}, 94 #ifdef IXGBE_FCOE 95 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 96 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 97 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 98 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 99 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 100 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 101 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 102 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 103 #endif /* IXGBE_FCOE */ 104 }; 105 106 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 107 * we set the num_rx_queues to evaluate to num_tx_queues. This is 108 * used because we do not have a good way to get the max number of 109 * rx queues with CONFIG_RPS disabled. 110 */ 111 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 112 113 #define IXGBE_QUEUE_STATS_LEN ( \ 114 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 115 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 116 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 117 #define IXGBE_PB_STATS_LEN ( \ 118 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 119 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 120 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 121 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 122 / sizeof(u64)) 123 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 124 IXGBE_PB_STATS_LEN + \ 125 IXGBE_QUEUE_STATS_LEN) 126 127 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 128 "Register test (offline)", "Eeprom test (offline)", 129 "Interrupt test (offline)", "Loopback test (offline)", 130 "Link test (on/offline)" 131 }; 132 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 133 134 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 135 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 136 "legacy-rx", 137 #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) 138 "vf-ipsec", 139 #define IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF BIT(2) 140 "mdd-disable-vf", 141 }; 142 143 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 144 145 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 146 147 static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw, 148 struct ethtool_link_ksettings *cmd) 149 { 150 if (!ixgbe_isbackplane(hw->phy.media_type)) { 151 ethtool_link_ksettings_add_link_mode(cmd, supported, 152 10000baseT_Full); 153 return; 154 } 155 156 switch (hw->device_id) { 157 case IXGBE_DEV_ID_82598: 158 case IXGBE_DEV_ID_82599_KX4: 159 case IXGBE_DEV_ID_82599_KX4_MEZZ: 160 case IXGBE_DEV_ID_X550EM_X_KX4: 161 ethtool_link_ksettings_add_link_mode 162 (cmd, supported, 10000baseKX4_Full); 163 break; 164 case IXGBE_DEV_ID_82598_BX: 165 case IXGBE_DEV_ID_82599_KR: 166 case IXGBE_DEV_ID_X550EM_X_KR: 167 case IXGBE_DEV_ID_X550EM_X_XFI: 168 ethtool_link_ksettings_add_link_mode 169 (cmd, supported, 10000baseKR_Full); 170 break; 171 default: 172 ethtool_link_ksettings_add_link_mode 173 (cmd, supported, 10000baseKX4_Full); 174 ethtool_link_ksettings_add_link_mode 175 (cmd, supported, 10000baseKR_Full); 176 break; 177 } 178 } 179 180 static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw, 181 struct ethtool_link_ksettings *cmd) 182 { 183 if (!ixgbe_isbackplane(hw->phy.media_type)) { 184 ethtool_link_ksettings_add_link_mode(cmd, advertising, 185 10000baseT_Full); 186 return; 187 } 188 189 switch (hw->device_id) { 190 case IXGBE_DEV_ID_82598: 191 case IXGBE_DEV_ID_82599_KX4: 192 case IXGBE_DEV_ID_82599_KX4_MEZZ: 193 case IXGBE_DEV_ID_X550EM_X_KX4: 194 ethtool_link_ksettings_add_link_mode 195 (cmd, advertising, 10000baseKX4_Full); 196 break; 197 case IXGBE_DEV_ID_82598_BX: 198 case IXGBE_DEV_ID_82599_KR: 199 case IXGBE_DEV_ID_X550EM_X_KR: 200 case IXGBE_DEV_ID_X550EM_X_XFI: 201 ethtool_link_ksettings_add_link_mode 202 (cmd, advertising, 10000baseKR_Full); 203 break; 204 default: 205 ethtool_link_ksettings_add_link_mode 206 (cmd, advertising, 10000baseKX4_Full); 207 ethtool_link_ksettings_add_link_mode 208 (cmd, advertising, 10000baseKR_Full); 209 break; 210 } 211 } 212 213 static int ixgbe_get_link_ksettings(struct net_device *netdev, 214 struct ethtool_link_ksettings *cmd) 215 { 216 struct ixgbe_adapter *adapter = netdev_priv(netdev); 217 struct ixgbe_hw *hw = &adapter->hw; 218 ixgbe_link_speed supported_link; 219 bool autoneg = false; 220 221 ethtool_link_ksettings_zero_link_mode(cmd, supported); 222 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 223 224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 225 226 /* set the supported link speeds */ 227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) { 228 ixgbe_set_supported_10gtypes(hw, cmd); 229 ixgbe_set_advertising_10gtypes(hw, cmd); 230 } 231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL) 232 ethtool_link_ksettings_add_link_mode(cmd, supported, 233 5000baseT_Full); 234 235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL) 236 ethtool_link_ksettings_add_link_mode(cmd, supported, 237 2500baseT_Full); 238 239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) { 240 if (ixgbe_isbackplane(hw->phy.media_type)) { 241 ethtool_link_ksettings_add_link_mode(cmd, supported, 242 1000baseKX_Full); 243 ethtool_link_ksettings_add_link_mode(cmd, advertising, 244 1000baseKX_Full); 245 } else { 246 ethtool_link_ksettings_add_link_mode(cmd, supported, 247 1000baseT_Full); 248 ethtool_link_ksettings_add_link_mode(cmd, advertising, 249 1000baseT_Full); 250 } 251 } 252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) { 253 ethtool_link_ksettings_add_link_mode(cmd, supported, 254 100baseT_Full); 255 ethtool_link_ksettings_add_link_mode(cmd, advertising, 256 100baseT_Full); 257 } 258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) { 259 ethtool_link_ksettings_add_link_mode(cmd, supported, 260 10baseT_Full); 261 ethtool_link_ksettings_add_link_mode(cmd, advertising, 262 10baseT_Full); 263 } 264 265 /* set the advertised speeds */ 266 if (hw->phy.autoneg_advertised) { 267 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 269 ethtool_link_ksettings_add_link_mode(cmd, advertising, 270 10baseT_Full); 271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 272 ethtool_link_ksettings_add_link_mode(cmd, advertising, 273 100baseT_Full); 274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 275 ixgbe_set_advertising_10gtypes(hw, cmd); 276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 277 if (ethtool_link_ksettings_test_link_mode 278 (cmd, supported, 1000baseKX_Full)) 279 ethtool_link_ksettings_add_link_mode 280 (cmd, advertising, 1000baseKX_Full); 281 else 282 ethtool_link_ksettings_add_link_mode 283 (cmd, advertising, 1000baseT_Full); 284 } 285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) 286 ethtool_link_ksettings_add_link_mode(cmd, advertising, 287 5000baseT_Full); 288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 289 ethtool_link_ksettings_add_link_mode(cmd, advertising, 290 2500baseT_Full); 291 } else { 292 if (hw->phy.multispeed_fiber && !autoneg) { 293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 294 ethtool_link_ksettings_add_link_mode 295 (cmd, advertising, 10000baseT_Full); 296 } 297 } 298 299 if (autoneg) { 300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 302 cmd->base.autoneg = AUTONEG_ENABLE; 303 } else 304 cmd->base.autoneg = AUTONEG_DISABLE; 305 306 /* Determine the remaining settings based on the PHY type. */ 307 switch (adapter->hw.phy.type) { 308 case ixgbe_phy_tn: 309 case ixgbe_phy_aq: 310 case ixgbe_phy_x550em_ext_t: 311 case ixgbe_phy_fw: 312 case ixgbe_phy_cu_unknown: 313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP); 314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); 315 cmd->base.port = PORT_TP; 316 break; 317 case ixgbe_phy_qt: 318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE); 320 cmd->base.port = PORT_FIBRE; 321 break; 322 case ixgbe_phy_nl: 323 case ixgbe_phy_sfp_passive_tyco: 324 case ixgbe_phy_sfp_passive_unknown: 325 case ixgbe_phy_sfp_ftl: 326 case ixgbe_phy_sfp_avago: 327 case ixgbe_phy_sfp_intel: 328 case ixgbe_phy_sfp_unknown: 329 case ixgbe_phy_qsfp_passive_unknown: 330 case ixgbe_phy_qsfp_active_unknown: 331 case ixgbe_phy_qsfp_intel: 332 case ixgbe_phy_qsfp_unknown: 333 /* SFP+ devices, further checking needed */ 334 switch (adapter->hw.phy.sfp_type) { 335 case ixgbe_sfp_type_da_cu: 336 case ixgbe_sfp_type_da_cu_core0: 337 case ixgbe_sfp_type_da_cu_core1: 338 ethtool_link_ksettings_add_link_mode(cmd, supported, 339 FIBRE); 340 ethtool_link_ksettings_add_link_mode(cmd, advertising, 341 FIBRE); 342 cmd->base.port = PORT_DA; 343 break; 344 case ixgbe_sfp_type_sr: 345 case ixgbe_sfp_type_lr: 346 case ixgbe_sfp_type_srlr_core0: 347 case ixgbe_sfp_type_srlr_core1: 348 case ixgbe_sfp_type_1g_sx_core0: 349 case ixgbe_sfp_type_1g_sx_core1: 350 case ixgbe_sfp_type_1g_lx_core0: 351 case ixgbe_sfp_type_1g_lx_core1: 352 ethtool_link_ksettings_add_link_mode(cmd, supported, 353 FIBRE); 354 ethtool_link_ksettings_add_link_mode(cmd, advertising, 355 FIBRE); 356 cmd->base.port = PORT_FIBRE; 357 break; 358 case ixgbe_sfp_type_not_present: 359 ethtool_link_ksettings_add_link_mode(cmd, supported, 360 FIBRE); 361 ethtool_link_ksettings_add_link_mode(cmd, advertising, 362 FIBRE); 363 cmd->base.port = PORT_NONE; 364 break; 365 case ixgbe_sfp_type_1g_cu_core0: 366 case ixgbe_sfp_type_1g_cu_core1: 367 ethtool_link_ksettings_add_link_mode(cmd, supported, 368 TP); 369 ethtool_link_ksettings_add_link_mode(cmd, advertising, 370 TP); 371 cmd->base.port = PORT_TP; 372 break; 373 case ixgbe_sfp_type_unknown: 374 default: 375 ethtool_link_ksettings_add_link_mode(cmd, supported, 376 FIBRE); 377 ethtool_link_ksettings_add_link_mode(cmd, advertising, 378 FIBRE); 379 cmd->base.port = PORT_OTHER; 380 break; 381 } 382 break; 383 case ixgbe_phy_xaui: 384 ethtool_link_ksettings_add_link_mode(cmd, supported, 385 FIBRE); 386 ethtool_link_ksettings_add_link_mode(cmd, advertising, 387 FIBRE); 388 cmd->base.port = PORT_NONE; 389 break; 390 case ixgbe_phy_unknown: 391 case ixgbe_phy_generic: 392 case ixgbe_phy_sfp_unsupported: 393 default: 394 ethtool_link_ksettings_add_link_mode(cmd, supported, 395 FIBRE); 396 ethtool_link_ksettings_add_link_mode(cmd, advertising, 397 FIBRE); 398 cmd->base.port = PORT_OTHER; 399 break; 400 } 401 402 /* Indicate pause support */ 403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 404 405 switch (hw->fc.requested_mode) { 406 case ixgbe_fc_full: 407 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 408 break; 409 case ixgbe_fc_rx_pause: 410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 411 ethtool_link_ksettings_add_link_mode(cmd, advertising, 412 Asym_Pause); 413 break; 414 case ixgbe_fc_tx_pause: 415 ethtool_link_ksettings_add_link_mode(cmd, advertising, 416 Asym_Pause); 417 break; 418 default: 419 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause); 420 ethtool_link_ksettings_del_link_mode(cmd, advertising, 421 Asym_Pause); 422 } 423 424 if (netif_carrier_ok(netdev)) { 425 switch (adapter->link_speed) { 426 case IXGBE_LINK_SPEED_10GB_FULL: 427 cmd->base.speed = SPEED_10000; 428 break; 429 case IXGBE_LINK_SPEED_5GB_FULL: 430 cmd->base.speed = SPEED_5000; 431 break; 432 case IXGBE_LINK_SPEED_2_5GB_FULL: 433 cmd->base.speed = SPEED_2500; 434 break; 435 case IXGBE_LINK_SPEED_1GB_FULL: 436 cmd->base.speed = SPEED_1000; 437 break; 438 case IXGBE_LINK_SPEED_100_FULL: 439 cmd->base.speed = SPEED_100; 440 break; 441 case IXGBE_LINK_SPEED_10_FULL: 442 cmd->base.speed = SPEED_10; 443 break; 444 default: 445 break; 446 } 447 cmd->base.duplex = DUPLEX_FULL; 448 } else { 449 cmd->base.speed = SPEED_UNKNOWN; 450 cmd->base.duplex = DUPLEX_UNKNOWN; 451 } 452 453 return 0; 454 } 455 456 static int ixgbe_set_link_ksettings(struct net_device *netdev, 457 const struct ethtool_link_ksettings *cmd) 458 { 459 struct ixgbe_adapter *adapter = netdev_priv(netdev); 460 struct ixgbe_hw *hw = &adapter->hw; 461 u32 advertised, old; 462 s32 err = 0; 463 464 if ((hw->phy.media_type == ixgbe_media_type_copper) || 465 (hw->phy.multispeed_fiber)) { 466 /* 467 * this function does not support duplex forcing, but can 468 * limit the advertising of the adapter to the specified speed 469 */ 470 if (!linkmode_subset(cmd->link_modes.advertising, 471 cmd->link_modes.supported)) 472 return -EINVAL; 473 474 /* only allow one speed at a time if no autoneg */ 475 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 476 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 477 10000baseT_Full) && 478 ethtool_link_ksettings_test_link_mode(cmd, advertising, 479 1000baseT_Full)) 480 return -EINVAL; 481 } 482 483 old = hw->phy.autoneg_advertised; 484 advertised = 0; 485 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 486 10000baseT_Full)) 487 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 488 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 489 5000baseT_Full)) 490 advertised |= IXGBE_LINK_SPEED_5GB_FULL; 491 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 492 2500baseT_Full)) 493 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 494 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 495 1000baseT_Full)) 496 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 497 498 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 499 100baseT_Full)) 500 advertised |= IXGBE_LINK_SPEED_100_FULL; 501 502 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 503 10baseT_Full)) 504 advertised |= IXGBE_LINK_SPEED_10_FULL; 505 506 if (old == advertised) 507 return err; 508 /* this sets the link speed and restarts auto-neg */ 509 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 510 usleep_range(1000, 2000); 511 512 hw->mac.autotry_restart = true; 513 err = hw->mac.ops.setup_link(hw, advertised, true); 514 if (err) { 515 e_info(probe, "setup link failed with code %d\n", err); 516 hw->mac.ops.setup_link(hw, old, true); 517 } 518 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 519 } else { 520 /* in this case we currently only support 10Gb/FULL */ 521 u32 speed = cmd->base.speed; 522 523 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 524 (!ethtool_link_ksettings_test_link_mode(cmd, advertising, 525 10000baseT_Full)) || 526 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 527 return -EINVAL; 528 } 529 530 return err; 531 } 532 533 static void ixgbe_get_pause_stats(struct net_device *netdev, 534 struct ethtool_pause_stats *stats) 535 { 536 struct ixgbe_adapter *adapter = netdev_priv(netdev); 537 struct ixgbe_hw_stats *hwstats = &adapter->stats; 538 539 stats->tx_pause_frames = hwstats->lxontxc + hwstats->lxofftxc; 540 stats->rx_pause_frames = hwstats->lxonrxc + hwstats->lxoffrxc; 541 } 542 543 static void ixgbe_get_pauseparam(struct net_device *netdev, 544 struct ethtool_pauseparam *pause) 545 { 546 struct ixgbe_adapter *adapter = netdev_priv(netdev); 547 struct ixgbe_hw *hw = &adapter->hw; 548 549 if (ixgbe_device_supports_autoneg_fc(hw) && 550 !hw->fc.disable_fc_autoneg) 551 pause->autoneg = 1; 552 else 553 pause->autoneg = 0; 554 555 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 556 pause->rx_pause = 1; 557 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 558 pause->tx_pause = 1; 559 } else if (hw->fc.current_mode == ixgbe_fc_full) { 560 pause->rx_pause = 1; 561 pause->tx_pause = 1; 562 } 563 } 564 565 static int ixgbe_set_pauseparam(struct net_device *netdev, 566 struct ethtool_pauseparam *pause) 567 { 568 struct ixgbe_adapter *adapter = netdev_priv(netdev); 569 struct ixgbe_hw *hw = &adapter->hw; 570 struct ixgbe_fc_info fc = hw->fc; 571 572 /* 82598 does no support link flow control with DCB enabled */ 573 if ((hw->mac.type == ixgbe_mac_82598EB) && 574 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 575 return -EINVAL; 576 577 /* some devices do not support autoneg of link flow control */ 578 if ((pause->autoneg == AUTONEG_ENABLE) && 579 !ixgbe_device_supports_autoneg_fc(hw)) 580 return -EINVAL; 581 582 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 583 584 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 585 fc.requested_mode = ixgbe_fc_full; 586 else if (pause->rx_pause && !pause->tx_pause) 587 fc.requested_mode = ixgbe_fc_rx_pause; 588 else if (!pause->rx_pause && pause->tx_pause) 589 fc.requested_mode = ixgbe_fc_tx_pause; 590 else 591 fc.requested_mode = ixgbe_fc_none; 592 593 /* if the thing changed then we'll update and use new autoneg */ 594 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 595 hw->fc = fc; 596 if (netif_running(netdev)) 597 ixgbe_reinit_locked(adapter); 598 else 599 ixgbe_reset(adapter); 600 } 601 602 return 0; 603 } 604 605 static u32 ixgbe_get_msglevel(struct net_device *netdev) 606 { 607 struct ixgbe_adapter *adapter = netdev_priv(netdev); 608 return adapter->msg_enable; 609 } 610 611 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 612 { 613 struct ixgbe_adapter *adapter = netdev_priv(netdev); 614 adapter->msg_enable = data; 615 } 616 617 static int ixgbe_get_regs_len(struct net_device *netdev) 618 { 619 #define IXGBE_REGS_LEN 1145 620 return IXGBE_REGS_LEN * sizeof(u32); 621 } 622 623 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 624 625 static void ixgbe_get_regs(struct net_device *netdev, 626 struct ethtool_regs *regs, void *p) 627 { 628 struct ixgbe_adapter *adapter = netdev_priv(netdev); 629 struct ixgbe_hw *hw = &adapter->hw; 630 u32 *regs_buff = p; 631 u8 i; 632 633 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 634 635 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 636 hw->device_id; 637 638 /* General Registers */ 639 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 640 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 641 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 642 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 643 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 644 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 645 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 646 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 647 648 /* NVM Register */ 649 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 650 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 651 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 652 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 653 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 654 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 655 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 656 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 657 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 658 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 659 660 /* Interrupt */ 661 /* don't read EICR because it can clear interrupt causes, instead 662 * read EICS which is a shadow but doesn't clear EICR */ 663 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 664 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 665 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 666 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 667 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 668 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 669 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 670 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 671 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 672 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 673 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 674 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 675 676 /* Flow Control */ 677 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 678 for (i = 0; i < 4; i++) 679 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 680 for (i = 0; i < 8; i++) { 681 switch (hw->mac.type) { 682 case ixgbe_mac_82598EB: 683 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 684 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 685 break; 686 case ixgbe_mac_82599EB: 687 case ixgbe_mac_X540: 688 case ixgbe_mac_X550: 689 case ixgbe_mac_X550EM_x: 690 case ixgbe_mac_x550em_a: 691 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 692 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 693 break; 694 default: 695 break; 696 } 697 } 698 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 699 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 700 701 /* Receive DMA */ 702 for (i = 0; i < 64; i++) 703 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 704 for (i = 0; i < 64; i++) 705 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 706 for (i = 0; i < 64; i++) 707 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 708 for (i = 0; i < 64; i++) 709 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 710 for (i = 0; i < 64; i++) 711 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 712 for (i = 0; i < 64; i++) 713 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 714 for (i = 0; i < 16; i++) 715 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 716 for (i = 0; i < 16; i++) 717 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 718 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 719 for (i = 0; i < 8; i++) 720 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 721 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 722 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 723 724 /* Receive */ 725 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 726 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 727 for (i = 0; i < 16; i++) 728 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 729 for (i = 0; i < 16; i++) 730 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 731 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 732 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 733 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 734 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 735 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 736 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 737 for (i = 0; i < 8; i++) 738 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 739 for (i = 0; i < 8; i++) 740 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 741 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 742 743 /* Transmit */ 744 for (i = 0; i < 32; i++) 745 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 746 for (i = 0; i < 32; i++) 747 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 748 for (i = 0; i < 32; i++) 749 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 750 for (i = 0; i < 32; i++) 751 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 752 for (i = 0; i < 32; i++) 753 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 754 for (i = 0; i < 32; i++) 755 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 756 for (i = 0; i < 32; i++) 757 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 758 for (i = 0; i < 32; i++) 759 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 760 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 761 for (i = 0; i < 16; i++) 762 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 763 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 764 for (i = 0; i < 8; i++) 765 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 766 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 767 768 /* Wake Up */ 769 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 770 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 771 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 772 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 773 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 774 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 775 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 776 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 777 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 778 779 /* DCB */ 780 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 781 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 782 783 switch (hw->mac.type) { 784 case ixgbe_mac_82598EB: 785 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 786 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 787 for (i = 0; i < 8; i++) 788 regs_buff[833 + i] = 789 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 790 for (i = 0; i < 8; i++) 791 regs_buff[841 + i] = 792 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 793 for (i = 0; i < 8; i++) 794 regs_buff[849 + i] = 795 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 796 for (i = 0; i < 8; i++) 797 regs_buff[857 + i] = 798 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 799 break; 800 case ixgbe_mac_82599EB: 801 case ixgbe_mac_X540: 802 case ixgbe_mac_X550: 803 case ixgbe_mac_X550EM_x: 804 case ixgbe_mac_x550em_a: 805 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 806 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 807 for (i = 0; i < 8; i++) 808 regs_buff[833 + i] = 809 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 810 for (i = 0; i < 8; i++) 811 regs_buff[841 + i] = 812 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 813 for (i = 0; i < 8; i++) 814 regs_buff[849 + i] = 815 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 816 for (i = 0; i < 8; i++) 817 regs_buff[857 + i] = 818 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 819 break; 820 default: 821 break; 822 } 823 824 for (i = 0; i < 8; i++) 825 regs_buff[865 + i] = 826 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 827 for (i = 0; i < 8; i++) 828 regs_buff[873 + i] = 829 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 830 831 /* Statistics */ 832 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 833 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 834 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 835 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 836 for (i = 0; i < 8; i++) 837 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 838 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 839 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 840 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 841 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 842 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 843 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 844 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 845 for (i = 0; i < 8; i++) 846 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 847 for (i = 0; i < 8; i++) 848 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 849 for (i = 0; i < 8; i++) 850 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 851 for (i = 0; i < 8; i++) 852 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 853 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 854 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 855 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 856 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 857 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 858 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 859 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 860 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 861 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 862 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 863 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 864 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 865 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 866 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 867 for (i = 0; i < 8; i++) 868 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 869 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 870 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 871 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 872 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 873 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 874 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 875 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 876 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 877 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 878 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 879 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 880 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 881 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 882 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 883 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 884 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 885 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 886 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 887 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 888 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 889 for (i = 0; i < 16; i++) 890 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 891 for (i = 0; i < 16; i++) 892 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 893 for (i = 0; i < 16; i++) 894 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 895 for (i = 0; i < 16; i++) 896 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 897 898 /* MAC */ 899 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 900 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 901 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 902 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 903 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 904 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 905 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 906 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 907 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 908 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 909 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 910 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 911 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 912 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 913 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 914 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 915 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 916 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 917 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 918 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 919 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 920 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 921 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 922 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 923 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 924 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 925 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 926 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 927 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 928 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 929 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 930 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 931 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 932 933 /* Diagnostic */ 934 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 935 for (i = 0; i < 8; i++) 936 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 937 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 938 for (i = 0; i < 4; i++) 939 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 940 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 941 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 942 for (i = 0; i < 8; i++) 943 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 944 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 945 for (i = 0; i < 4; i++) 946 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 947 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 948 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 949 for (i = 0; i < 4; i++) 950 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 951 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 952 for (i = 0; i < 4; i++) 953 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 954 for (i = 0; i < 8; i++) 955 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 956 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 957 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 958 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 959 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 960 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 961 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 962 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 963 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 964 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 965 966 /* 82599 X540 specific registers */ 967 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 968 969 /* 82599 X540 specific DCB registers */ 970 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 971 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 972 for (i = 0; i < 4; i++) 973 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 974 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 975 /* same as RTTQCNRM */ 976 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 977 /* same as RTTQCNRR */ 978 979 /* X540 specific DCB registers */ 980 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 981 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 982 983 /* Security config registers */ 984 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 985 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 986 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); 987 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 988 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 989 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 990 } 991 992 static int ixgbe_get_eeprom_len(struct net_device *netdev) 993 { 994 struct ixgbe_adapter *adapter = netdev_priv(netdev); 995 return adapter->hw.eeprom.word_size * 2; 996 } 997 998 static int ixgbe_get_eeprom(struct net_device *netdev, 999 struct ethtool_eeprom *eeprom, u8 *bytes) 1000 { 1001 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1002 struct ixgbe_hw *hw = &adapter->hw; 1003 u16 *eeprom_buff; 1004 int first_word, last_word, eeprom_len; 1005 int ret_val = 0; 1006 u16 i; 1007 1008 if (eeprom->len == 0) 1009 return -EINVAL; 1010 1011 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1012 1013 first_word = eeprom->offset >> 1; 1014 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1015 eeprom_len = last_word - first_word + 1; 1016 1017 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL); 1018 if (!eeprom_buff) 1019 return -ENOMEM; 1020 1021 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 1022 eeprom_buff); 1023 1024 /* Device's eeprom is always little-endian, word addressable */ 1025 for (i = 0; i < eeprom_len; i++) 1026 le16_to_cpus(&eeprom_buff[i]); 1027 1028 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 1029 kfree(eeprom_buff); 1030 1031 return ret_val; 1032 } 1033 1034 static int ixgbe_set_eeprom(struct net_device *netdev, 1035 struct ethtool_eeprom *eeprom, u8 *bytes) 1036 { 1037 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1038 struct ixgbe_hw *hw = &adapter->hw; 1039 u16 *eeprom_buff; 1040 void *ptr; 1041 int max_len, first_word, last_word, ret_val = 0; 1042 u16 i; 1043 1044 if (eeprom->len == 0) 1045 return -EINVAL; 1046 1047 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1048 return -EINVAL; 1049 1050 max_len = hw->eeprom.word_size * 2; 1051 1052 first_word = eeprom->offset >> 1; 1053 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1054 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1055 if (!eeprom_buff) 1056 return -ENOMEM; 1057 1058 ptr = eeprom_buff; 1059 1060 if (eeprom->offset & 1) { 1061 /* 1062 * need read/modify/write of first changed EEPROM word 1063 * only the second byte of the word is being modified 1064 */ 1065 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 1066 if (ret_val) 1067 goto err; 1068 1069 ptr++; 1070 } 1071 if ((eeprom->offset + eeprom->len) & 1) { 1072 /* 1073 * need read/modify/write of last changed EEPROM word 1074 * only the first byte of the word is being modified 1075 */ 1076 ret_val = hw->eeprom.ops.read(hw, last_word, 1077 &eeprom_buff[last_word - first_word]); 1078 if (ret_val) 1079 goto err; 1080 } 1081 1082 /* Device's eeprom is always little-endian, word addressable */ 1083 for (i = 0; i < last_word - first_word + 1; i++) 1084 le16_to_cpus(&eeprom_buff[i]); 1085 1086 memcpy(ptr, bytes, eeprom->len); 1087 1088 for (i = 0; i < last_word - first_word + 1; i++) 1089 cpu_to_le16s(&eeprom_buff[i]); 1090 1091 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 1092 last_word - first_word + 1, 1093 eeprom_buff); 1094 1095 /* Update the checksum */ 1096 if (ret_val == 0) 1097 hw->eeprom.ops.update_checksum(hw); 1098 1099 err: 1100 kfree(eeprom_buff); 1101 return ret_val; 1102 } 1103 1104 static void ixgbe_get_drvinfo(struct net_device *netdev, 1105 struct ethtool_drvinfo *drvinfo) 1106 { 1107 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1108 1109 strscpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1110 1111 strscpy(drvinfo->fw_version, adapter->eeprom_id, 1112 sizeof(drvinfo->fw_version)); 1113 1114 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 1115 sizeof(drvinfo->bus_info)); 1116 1117 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1118 } 1119 1120 static void ixgbe_get_ringparam(struct net_device *netdev, 1121 struct ethtool_ringparam *ring, 1122 struct kernel_ethtool_ringparam *kernel_ring, 1123 struct netlink_ext_ack *extack) 1124 { 1125 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1126 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1127 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1128 1129 ring->rx_max_pending = IXGBE_MAX_RXD; 1130 ring->tx_max_pending = IXGBE_MAX_TXD; 1131 ring->rx_pending = rx_ring->count; 1132 ring->tx_pending = tx_ring->count; 1133 } 1134 1135 static int ixgbe_set_ringparam(struct net_device *netdev, 1136 struct ethtool_ringparam *ring, 1137 struct kernel_ethtool_ringparam *kernel_ring, 1138 struct netlink_ext_ack *extack) 1139 { 1140 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1141 struct ixgbe_ring *temp_ring; 1142 int i, j, err = 0; 1143 u32 new_rx_count, new_tx_count; 1144 1145 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1146 return -EINVAL; 1147 1148 new_tx_count = clamp_t(u32, ring->tx_pending, 1149 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1150 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1151 1152 new_rx_count = clamp_t(u32, ring->rx_pending, 1153 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1154 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1155 1156 if ((new_tx_count == adapter->tx_ring_count) && 1157 (new_rx_count == adapter->rx_ring_count)) { 1158 /* nothing to do */ 1159 return 0; 1160 } 1161 1162 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1163 usleep_range(1000, 2000); 1164 1165 if (!netif_running(adapter->netdev)) { 1166 for (i = 0; i < adapter->num_tx_queues; i++) 1167 adapter->tx_ring[i]->count = new_tx_count; 1168 for (i = 0; i < adapter->num_xdp_queues; i++) 1169 adapter->xdp_ring[i]->count = new_tx_count; 1170 for (i = 0; i < adapter->num_rx_queues; i++) 1171 adapter->rx_ring[i]->count = new_rx_count; 1172 adapter->tx_ring_count = new_tx_count; 1173 adapter->xdp_ring_count = new_tx_count; 1174 adapter->rx_ring_count = new_rx_count; 1175 goto clear_reset; 1176 } 1177 1178 /* allocate temporary buffer to store rings in */ 1179 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues, 1180 adapter->num_rx_queues); 1181 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring))); 1182 1183 if (!temp_ring) { 1184 err = -ENOMEM; 1185 goto clear_reset; 1186 } 1187 1188 ixgbe_down(adapter); 1189 1190 /* 1191 * Setup new Tx resources and free the old Tx resources in that order. 1192 * We can then assign the new resources to the rings via a memcpy. 1193 * The advantage to this approach is that we are guaranteed to still 1194 * have resources even in the case of an allocation failure. 1195 */ 1196 if (new_tx_count != adapter->tx_ring_count) { 1197 for (i = 0; i < adapter->num_tx_queues; i++) { 1198 memcpy(&temp_ring[i], adapter->tx_ring[i], 1199 sizeof(struct ixgbe_ring)); 1200 1201 temp_ring[i].count = new_tx_count; 1202 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1203 if (err) { 1204 while (i) { 1205 i--; 1206 ixgbe_free_tx_resources(&temp_ring[i]); 1207 } 1208 goto err_setup; 1209 } 1210 } 1211 1212 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1213 memcpy(&temp_ring[i], adapter->xdp_ring[j], 1214 sizeof(struct ixgbe_ring)); 1215 1216 temp_ring[i].count = new_tx_count; 1217 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1218 if (err) { 1219 while (i) { 1220 i--; 1221 ixgbe_free_tx_resources(&temp_ring[i]); 1222 } 1223 goto err_setup; 1224 } 1225 } 1226 1227 for (i = 0; i < adapter->num_tx_queues; i++) { 1228 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1229 1230 memcpy(adapter->tx_ring[i], &temp_ring[i], 1231 sizeof(struct ixgbe_ring)); 1232 } 1233 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1234 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 1235 1236 memcpy(adapter->xdp_ring[j], &temp_ring[i], 1237 sizeof(struct ixgbe_ring)); 1238 } 1239 1240 adapter->tx_ring_count = new_tx_count; 1241 } 1242 1243 /* Repeat the process for the Rx rings if needed */ 1244 if (new_rx_count != adapter->rx_ring_count) { 1245 for (i = 0; i < adapter->num_rx_queues; i++) { 1246 memcpy(&temp_ring[i], adapter->rx_ring[i], 1247 sizeof(struct ixgbe_ring)); 1248 1249 /* Clear copied XDP RX-queue info */ 1250 memset(&temp_ring[i].xdp_rxq, 0, 1251 sizeof(temp_ring[i].xdp_rxq)); 1252 1253 temp_ring[i].count = new_rx_count; 1254 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1255 if (err) { 1256 while (i) { 1257 i--; 1258 ixgbe_free_rx_resources(&temp_ring[i]); 1259 } 1260 goto err_setup; 1261 } 1262 1263 } 1264 1265 for (i = 0; i < adapter->num_rx_queues; i++) { 1266 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1267 1268 memcpy(adapter->rx_ring[i], &temp_ring[i], 1269 sizeof(struct ixgbe_ring)); 1270 } 1271 1272 adapter->rx_ring_count = new_rx_count; 1273 } 1274 1275 err_setup: 1276 ixgbe_up(adapter); 1277 vfree(temp_ring); 1278 clear_reset: 1279 clear_bit(__IXGBE_RESETTING, &adapter->state); 1280 return err; 1281 } 1282 1283 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1284 { 1285 switch (sset) { 1286 case ETH_SS_TEST: 1287 return IXGBE_TEST_LEN; 1288 case ETH_SS_STATS: 1289 return IXGBE_STATS_LEN; 1290 case ETH_SS_PRIV_FLAGS: 1291 return IXGBE_PRIV_FLAGS_STR_LEN; 1292 default: 1293 return -EOPNOTSUPP; 1294 } 1295 } 1296 1297 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1298 struct ethtool_stats *stats, u64 *data) 1299 { 1300 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1301 struct rtnl_link_stats64 temp; 1302 const struct rtnl_link_stats64 *net_stats; 1303 unsigned int start; 1304 struct ixgbe_ring *ring; 1305 int i, j; 1306 char *p = NULL; 1307 1308 ixgbe_update_stats(adapter); 1309 net_stats = dev_get_stats(netdev, &temp); 1310 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1311 switch (ixgbe_gstrings_stats[i].type) { 1312 case NETDEV_STATS: 1313 p = (char *) net_stats + 1314 ixgbe_gstrings_stats[i].stat_offset; 1315 break; 1316 case IXGBE_STATS: 1317 p = (char *) adapter + 1318 ixgbe_gstrings_stats[i].stat_offset; 1319 break; 1320 default: 1321 data[i] = 0; 1322 continue; 1323 } 1324 1325 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1326 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1327 } 1328 for (j = 0; j < netdev->num_tx_queues; j++) { 1329 ring = adapter->tx_ring[j]; 1330 if (!ring) { 1331 data[i] = 0; 1332 data[i+1] = 0; 1333 i += 2; 1334 continue; 1335 } 1336 1337 do { 1338 start = u64_stats_fetch_begin_irq(&ring->syncp); 1339 data[i] = ring->stats.packets; 1340 data[i+1] = ring->stats.bytes; 1341 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1342 i += 2; 1343 } 1344 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1345 ring = adapter->rx_ring[j]; 1346 if (!ring) { 1347 data[i] = 0; 1348 data[i+1] = 0; 1349 i += 2; 1350 continue; 1351 } 1352 1353 do { 1354 start = u64_stats_fetch_begin_irq(&ring->syncp); 1355 data[i] = ring->stats.packets; 1356 data[i+1] = ring->stats.bytes; 1357 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1358 i += 2; 1359 } 1360 1361 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1362 data[i++] = adapter->stats.pxontxc[j]; 1363 data[i++] = adapter->stats.pxofftxc[j]; 1364 } 1365 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1366 data[i++] = adapter->stats.pxonrxc[j]; 1367 data[i++] = adapter->stats.pxoffrxc[j]; 1368 } 1369 } 1370 1371 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1372 u8 *data) 1373 { 1374 unsigned int i; 1375 u8 *p = data; 1376 1377 switch (stringset) { 1378 case ETH_SS_TEST: 1379 for (i = 0; i < IXGBE_TEST_LEN; i++) 1380 ethtool_sprintf(&p, ixgbe_gstrings_test[i]); 1381 break; 1382 case ETH_SS_STATS: 1383 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) 1384 ethtool_sprintf(&p, 1385 ixgbe_gstrings_stats[i].stat_string); 1386 for (i = 0; i < netdev->num_tx_queues; i++) { 1387 ethtool_sprintf(&p, "tx_queue_%u_packets", i); 1388 ethtool_sprintf(&p, "tx_queue_%u_bytes", i); 1389 } 1390 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1391 ethtool_sprintf(&p, "rx_queue_%u_packets", i); 1392 ethtool_sprintf(&p, "rx_queue_%u_bytes", i); 1393 } 1394 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1395 ethtool_sprintf(&p, "tx_pb_%u_pxon", i); 1396 ethtool_sprintf(&p, "tx_pb_%u_pxoff", i); 1397 } 1398 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1399 ethtool_sprintf(&p, "rx_pb_%u_pxon", i); 1400 ethtool_sprintf(&p, "rx_pb_%u_pxoff", i); 1401 } 1402 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1403 break; 1404 case ETH_SS_PRIV_FLAGS: 1405 memcpy(data, ixgbe_priv_flags_strings, 1406 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1407 } 1408 } 1409 1410 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1411 { 1412 struct ixgbe_hw *hw = &adapter->hw; 1413 bool link_up; 1414 u32 link_speed = 0; 1415 1416 if (ixgbe_removed(hw->hw_addr)) { 1417 *data = 1; 1418 return 1; 1419 } 1420 *data = 0; 1421 1422 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1423 if (link_up) 1424 return *data; 1425 else 1426 *data = 1; 1427 return *data; 1428 } 1429 1430 /* ethtool register test data */ 1431 struct ixgbe_reg_test { 1432 u16 reg; 1433 u8 array_len; 1434 u8 test_type; 1435 u32 mask; 1436 u32 write; 1437 }; 1438 1439 /* In the hardware, registers are laid out either singly, in arrays 1440 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1441 * most tests take place on arrays or single registers (handled 1442 * as a single-element array) and special-case the tables. 1443 * Table tests are always pattern tests. 1444 * 1445 * We also make provision for some required setup steps by specifying 1446 * registers to be written without any read-back testing. 1447 */ 1448 1449 #define PATTERN_TEST 1 1450 #define SET_READ_TEST 2 1451 #define WRITE_NO_TEST 3 1452 #define TABLE32_TEST 4 1453 #define TABLE64_TEST_LO 5 1454 #define TABLE64_TEST_HI 6 1455 1456 /* default 82599 register test */ 1457 static const struct ixgbe_reg_test reg_test_82599[] = { 1458 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1459 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1460 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1461 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1462 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1463 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1464 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1465 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1466 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1467 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1468 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1469 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1470 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1471 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1472 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1473 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1474 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1475 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1476 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1477 { .reg = 0 } 1478 }; 1479 1480 /* default 82598 register test */ 1481 static const struct ixgbe_reg_test reg_test_82598[] = { 1482 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1483 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1484 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1485 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1486 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1487 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1488 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1489 /* Enable all four RX queues before testing. */ 1490 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1491 /* RDH is read-only for 82598, only test RDT. */ 1492 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1493 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1494 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1495 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1496 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1497 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1498 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1499 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1500 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1501 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1502 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1503 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1504 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1505 { .reg = 0 } 1506 }; 1507 1508 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1509 u32 mask, u32 write) 1510 { 1511 u32 pat, val, before; 1512 static const u32 test_pattern[] = { 1513 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1514 1515 if (ixgbe_removed(adapter->hw.hw_addr)) { 1516 *data = 1; 1517 return true; 1518 } 1519 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1520 before = ixgbe_read_reg(&adapter->hw, reg); 1521 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1522 val = ixgbe_read_reg(&adapter->hw, reg); 1523 if (val != (test_pattern[pat] & write & mask)) { 1524 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1525 reg, val, (test_pattern[pat] & write & mask)); 1526 *data = reg; 1527 ixgbe_write_reg(&adapter->hw, reg, before); 1528 return true; 1529 } 1530 ixgbe_write_reg(&adapter->hw, reg, before); 1531 } 1532 return false; 1533 } 1534 1535 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1536 u32 mask, u32 write) 1537 { 1538 u32 val, before; 1539 1540 if (ixgbe_removed(adapter->hw.hw_addr)) { 1541 *data = 1; 1542 return true; 1543 } 1544 before = ixgbe_read_reg(&adapter->hw, reg); 1545 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1546 val = ixgbe_read_reg(&adapter->hw, reg); 1547 if ((write & mask) != (val & mask)) { 1548 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1549 reg, (val & mask), (write & mask)); 1550 *data = reg; 1551 ixgbe_write_reg(&adapter->hw, reg, before); 1552 return true; 1553 } 1554 ixgbe_write_reg(&adapter->hw, reg, before); 1555 return false; 1556 } 1557 1558 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1559 { 1560 const struct ixgbe_reg_test *test; 1561 u32 value, before, after; 1562 u32 i, toggle; 1563 1564 if (ixgbe_removed(adapter->hw.hw_addr)) { 1565 e_err(drv, "Adapter removed - register test blocked\n"); 1566 *data = 1; 1567 return 1; 1568 } 1569 switch (adapter->hw.mac.type) { 1570 case ixgbe_mac_82598EB: 1571 toggle = 0x7FFFF3FF; 1572 test = reg_test_82598; 1573 break; 1574 case ixgbe_mac_82599EB: 1575 case ixgbe_mac_X540: 1576 case ixgbe_mac_X550: 1577 case ixgbe_mac_X550EM_x: 1578 case ixgbe_mac_x550em_a: 1579 toggle = 0x7FFFF30F; 1580 test = reg_test_82599; 1581 break; 1582 default: 1583 *data = 1; 1584 return 1; 1585 } 1586 1587 /* 1588 * Because the status register is such a special case, 1589 * we handle it separately from the rest of the register 1590 * tests. Some bits are read-only, some toggle, and some 1591 * are writeable on newer MACs. 1592 */ 1593 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1594 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1595 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1596 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1597 if (value != after) { 1598 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1599 after, value); 1600 *data = 1; 1601 return 1; 1602 } 1603 /* restore previous status */ 1604 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1605 1606 /* 1607 * Perform the remainder of the register test, looping through 1608 * the test table until we either fail or reach the null entry. 1609 */ 1610 while (test->reg) { 1611 for (i = 0; i < test->array_len; i++) { 1612 bool b = false; 1613 1614 switch (test->test_type) { 1615 case PATTERN_TEST: 1616 b = reg_pattern_test(adapter, data, 1617 test->reg + (i * 0x40), 1618 test->mask, 1619 test->write); 1620 break; 1621 case SET_READ_TEST: 1622 b = reg_set_and_check(adapter, data, 1623 test->reg + (i * 0x40), 1624 test->mask, 1625 test->write); 1626 break; 1627 case WRITE_NO_TEST: 1628 ixgbe_write_reg(&adapter->hw, 1629 test->reg + (i * 0x40), 1630 test->write); 1631 break; 1632 case TABLE32_TEST: 1633 b = reg_pattern_test(adapter, data, 1634 test->reg + (i * 4), 1635 test->mask, 1636 test->write); 1637 break; 1638 case TABLE64_TEST_LO: 1639 b = reg_pattern_test(adapter, data, 1640 test->reg + (i * 8), 1641 test->mask, 1642 test->write); 1643 break; 1644 case TABLE64_TEST_HI: 1645 b = reg_pattern_test(adapter, data, 1646 (test->reg + 4) + (i * 8), 1647 test->mask, 1648 test->write); 1649 break; 1650 } 1651 if (b) 1652 return 1; 1653 } 1654 test++; 1655 } 1656 1657 *data = 0; 1658 return 0; 1659 } 1660 1661 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1662 { 1663 struct ixgbe_hw *hw = &adapter->hw; 1664 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1665 *data = 1; 1666 else 1667 *data = 0; 1668 return *data; 1669 } 1670 1671 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1672 { 1673 struct net_device *netdev = (struct net_device *) data; 1674 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1675 1676 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1677 1678 return IRQ_HANDLED; 1679 } 1680 1681 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1682 { 1683 struct net_device *netdev = adapter->netdev; 1684 u32 mask, i = 0, shared_int = true; 1685 u32 irq = adapter->pdev->irq; 1686 1687 *data = 0; 1688 1689 /* Hook up test interrupt handler just for this test */ 1690 if (adapter->msix_entries) { 1691 /* NOTE: we don't test MSI-X interrupts here, yet */ 1692 return 0; 1693 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1694 shared_int = false; 1695 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1696 netdev)) { 1697 *data = 1; 1698 return -1; 1699 } 1700 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1701 netdev->name, netdev)) { 1702 shared_int = false; 1703 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1704 netdev->name, netdev)) { 1705 *data = 1; 1706 return -1; 1707 } 1708 e_info(hw, "testing %s interrupt\n", shared_int ? 1709 "shared" : "unshared"); 1710 1711 /* Disable all the interrupts */ 1712 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1713 IXGBE_WRITE_FLUSH(&adapter->hw); 1714 usleep_range(10000, 20000); 1715 1716 /* Test each interrupt */ 1717 for (; i < 10; i++) { 1718 /* Interrupt to test */ 1719 mask = BIT(i); 1720 1721 if (!shared_int) { 1722 /* 1723 * Disable the interrupts to be reported in 1724 * the cause register and then force the same 1725 * interrupt and see if one gets posted. If 1726 * an interrupt was posted to the bus, the 1727 * test failed. 1728 */ 1729 adapter->test_icr = 0; 1730 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1731 ~mask & 0x00007FFF); 1732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1733 ~mask & 0x00007FFF); 1734 IXGBE_WRITE_FLUSH(&adapter->hw); 1735 usleep_range(10000, 20000); 1736 1737 if (adapter->test_icr & mask) { 1738 *data = 3; 1739 break; 1740 } 1741 } 1742 1743 /* 1744 * Enable the interrupt to be reported in the cause 1745 * register and then force the same interrupt and see 1746 * if one gets posted. If an interrupt was not posted 1747 * to the bus, the test failed. 1748 */ 1749 adapter->test_icr = 0; 1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1751 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1752 IXGBE_WRITE_FLUSH(&adapter->hw); 1753 usleep_range(10000, 20000); 1754 1755 if (!(adapter->test_icr & mask)) { 1756 *data = 4; 1757 break; 1758 } 1759 1760 if (!shared_int) { 1761 /* 1762 * Disable the other interrupts to be reported in 1763 * the cause register and then force the other 1764 * interrupts and see if any get posted. If 1765 * an interrupt was posted to the bus, the 1766 * test failed. 1767 */ 1768 adapter->test_icr = 0; 1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1770 ~mask & 0x00007FFF); 1771 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1772 ~mask & 0x00007FFF); 1773 IXGBE_WRITE_FLUSH(&adapter->hw); 1774 usleep_range(10000, 20000); 1775 1776 if (adapter->test_icr) { 1777 *data = 5; 1778 break; 1779 } 1780 } 1781 } 1782 1783 /* Disable all the interrupts */ 1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1785 IXGBE_WRITE_FLUSH(&adapter->hw); 1786 usleep_range(10000, 20000); 1787 1788 /* Unhook test interrupt handler */ 1789 free_irq(irq, netdev); 1790 1791 return *data; 1792 } 1793 1794 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1795 { 1796 /* Shut down the DMA engines now so they can be reinitialized later, 1797 * since the test rings and normally used rings should overlap on 1798 * queue 0 we can just use the standard disable Rx/Tx calls and they 1799 * will take care of disabling the test rings for us. 1800 */ 1801 1802 /* first Rx */ 1803 ixgbe_disable_rx(adapter); 1804 1805 /* now Tx */ 1806 ixgbe_disable_tx(adapter); 1807 1808 ixgbe_reset(adapter); 1809 1810 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1811 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1812 } 1813 1814 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1815 { 1816 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1817 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1818 struct ixgbe_hw *hw = &adapter->hw; 1819 u32 rctl, reg_data; 1820 int ret_val; 1821 int err; 1822 1823 /* Setup Tx descriptor ring and Tx buffers */ 1824 tx_ring->count = IXGBE_DEFAULT_TXD; 1825 tx_ring->queue_index = 0; 1826 tx_ring->dev = &adapter->pdev->dev; 1827 tx_ring->netdev = adapter->netdev; 1828 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1829 1830 err = ixgbe_setup_tx_resources(tx_ring); 1831 if (err) 1832 return 1; 1833 1834 switch (adapter->hw.mac.type) { 1835 case ixgbe_mac_82599EB: 1836 case ixgbe_mac_X540: 1837 case ixgbe_mac_X550: 1838 case ixgbe_mac_X550EM_x: 1839 case ixgbe_mac_x550em_a: 1840 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1841 reg_data |= IXGBE_DMATXCTL_TE; 1842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1843 break; 1844 default: 1845 break; 1846 } 1847 1848 ixgbe_configure_tx_ring(adapter, tx_ring); 1849 1850 /* Setup Rx Descriptor ring and Rx buffers */ 1851 rx_ring->count = IXGBE_DEFAULT_RXD; 1852 rx_ring->queue_index = 0; 1853 rx_ring->dev = &adapter->pdev->dev; 1854 rx_ring->netdev = adapter->netdev; 1855 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1856 1857 err = ixgbe_setup_rx_resources(adapter, rx_ring); 1858 if (err) { 1859 ret_val = 4; 1860 goto err_nomem; 1861 } 1862 1863 hw->mac.ops.disable_rx(hw); 1864 1865 ixgbe_configure_rx_ring(adapter, rx_ring); 1866 1867 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1868 rctl |= IXGBE_RXCTRL_DMBYPS; 1869 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1870 1871 hw->mac.ops.enable_rx(hw); 1872 1873 return 0; 1874 1875 err_nomem: 1876 ixgbe_free_desc_rings(adapter); 1877 return ret_val; 1878 } 1879 1880 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1881 { 1882 struct ixgbe_hw *hw = &adapter->hw; 1883 u32 reg_data; 1884 1885 1886 /* Setup MAC loopback */ 1887 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1888 reg_data |= IXGBE_HLREG0_LPBK; 1889 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1890 1891 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1892 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1893 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1894 1895 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1896 switch (adapter->hw.mac.type) { 1897 case ixgbe_mac_X540: 1898 case ixgbe_mac_X550: 1899 case ixgbe_mac_X550EM_x: 1900 case ixgbe_mac_x550em_a: 1901 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1902 reg_data |= IXGBE_MACC_FLU; 1903 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1904 break; 1905 default: 1906 if (hw->mac.orig_autoc) { 1907 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1908 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1909 } else { 1910 return 10; 1911 } 1912 } 1913 IXGBE_WRITE_FLUSH(hw); 1914 usleep_range(10000, 20000); 1915 1916 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1917 if (hw->mac.type == ixgbe_mac_82598EB) { 1918 u8 atlas; 1919 1920 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1921 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1922 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1923 1924 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1925 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1926 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1927 1928 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1929 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1930 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1931 1932 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1933 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1934 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1935 } 1936 1937 return 0; 1938 } 1939 1940 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1941 { 1942 u32 reg_data; 1943 1944 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1945 reg_data &= ~IXGBE_HLREG0_LPBK; 1946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1947 } 1948 1949 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1950 unsigned int frame_size) 1951 { 1952 memset(skb->data, 0xFF, frame_size); 1953 frame_size >>= 1; 1954 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1955 skb->data[frame_size + 10] = 0xBE; 1956 skb->data[frame_size + 12] = 0xAF; 1957 } 1958 1959 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1960 unsigned int frame_size) 1961 { 1962 unsigned char *data; 1963 bool match = true; 1964 1965 frame_size >>= 1; 1966 1967 data = page_address(rx_buffer->page) + rx_buffer->page_offset; 1968 1969 if (data[3] != 0xFF || 1970 data[frame_size + 10] != 0xBE || 1971 data[frame_size + 12] != 0xAF) 1972 match = false; 1973 1974 return match; 1975 } 1976 1977 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1978 struct ixgbe_ring *tx_ring, 1979 unsigned int size) 1980 { 1981 union ixgbe_adv_rx_desc *rx_desc; 1982 u16 rx_ntc, tx_ntc, count = 0; 1983 1984 /* initialize next to clean and descriptor values */ 1985 rx_ntc = rx_ring->next_to_clean; 1986 tx_ntc = tx_ring->next_to_clean; 1987 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1988 1989 while (tx_ntc != tx_ring->next_to_use) { 1990 union ixgbe_adv_tx_desc *tx_desc; 1991 struct ixgbe_tx_buffer *tx_buffer; 1992 1993 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc); 1994 1995 /* if DD is not set transmit has not completed */ 1996 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1997 return count; 1998 1999 /* unmap buffer on Tx side */ 2000 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 2001 2002 /* Free all the Tx ring sk_buffs */ 2003 dev_kfree_skb_any(tx_buffer->skb); 2004 2005 /* unmap skb header data */ 2006 dma_unmap_single(tx_ring->dev, 2007 dma_unmap_addr(tx_buffer, dma), 2008 dma_unmap_len(tx_buffer, len), 2009 DMA_TO_DEVICE); 2010 dma_unmap_len_set(tx_buffer, len, 0); 2011 2012 /* increment Tx next to clean counter */ 2013 tx_ntc++; 2014 if (tx_ntc == tx_ring->count) 2015 tx_ntc = 0; 2016 } 2017 2018 while (rx_desc->wb.upper.length) { 2019 struct ixgbe_rx_buffer *rx_buffer; 2020 2021 /* check Rx buffer */ 2022 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 2023 2024 /* sync Rx buffer for CPU read */ 2025 dma_sync_single_for_cpu(rx_ring->dev, 2026 rx_buffer->dma, 2027 ixgbe_rx_bufsz(rx_ring), 2028 DMA_FROM_DEVICE); 2029 2030 /* verify contents of skb */ 2031 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 2032 count++; 2033 else 2034 break; 2035 2036 /* sync Rx buffer for device write */ 2037 dma_sync_single_for_device(rx_ring->dev, 2038 rx_buffer->dma, 2039 ixgbe_rx_bufsz(rx_ring), 2040 DMA_FROM_DEVICE); 2041 2042 /* increment Rx next to clean counter */ 2043 rx_ntc++; 2044 if (rx_ntc == rx_ring->count) 2045 rx_ntc = 0; 2046 2047 /* fetch next descriptor */ 2048 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 2049 } 2050 2051 netdev_tx_reset_queue(txring_txq(tx_ring)); 2052 2053 /* re-map buffers to ring, store next to clean values */ 2054 ixgbe_alloc_rx_buffers(rx_ring, count); 2055 rx_ring->next_to_clean = rx_ntc; 2056 tx_ring->next_to_clean = tx_ntc; 2057 2058 return count; 2059 } 2060 2061 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 2062 { 2063 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 2064 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 2065 int i, j, lc, good_cnt, ret_val = 0; 2066 unsigned int size = 1024; 2067 netdev_tx_t tx_ret_val; 2068 struct sk_buff *skb; 2069 u32 flags_orig = adapter->flags; 2070 2071 /* DCB can modify the frames on Tx */ 2072 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 2073 2074 /* allocate test skb */ 2075 skb = alloc_skb(size, GFP_KERNEL); 2076 if (!skb) 2077 return 11; 2078 2079 /* place data into test skb */ 2080 ixgbe_create_lbtest_frame(skb, size); 2081 skb_put(skb, size); 2082 2083 /* 2084 * Calculate the loop count based on the largest descriptor ring 2085 * The idea is to wrap the largest ring a number of times using 64 2086 * send/receive pairs during each loop 2087 */ 2088 2089 if (rx_ring->count <= tx_ring->count) 2090 lc = ((tx_ring->count / 64) * 2) + 1; 2091 else 2092 lc = ((rx_ring->count / 64) * 2) + 1; 2093 2094 for (j = 0; j <= lc; j++) { 2095 /* reset count of good packets */ 2096 good_cnt = 0; 2097 2098 /* place 64 packets on the transmit queue*/ 2099 for (i = 0; i < 64; i++) { 2100 skb_get(skb); 2101 tx_ret_val = ixgbe_xmit_frame_ring(skb, 2102 adapter, 2103 tx_ring); 2104 if (tx_ret_val == NETDEV_TX_OK) 2105 good_cnt++; 2106 } 2107 2108 if (good_cnt != 64) { 2109 ret_val = 12; 2110 break; 2111 } 2112 2113 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2114 msleep(200); 2115 2116 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2117 if (good_cnt != 64) { 2118 ret_val = 13; 2119 break; 2120 } 2121 } 2122 2123 /* free the original skb */ 2124 kfree_skb(skb); 2125 adapter->flags = flags_orig; 2126 2127 return ret_val; 2128 } 2129 2130 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2131 { 2132 *data = ixgbe_setup_desc_rings(adapter); 2133 if (*data) 2134 goto out; 2135 *data = ixgbe_setup_loopback_test(adapter); 2136 if (*data) 2137 goto err_loopback; 2138 *data = ixgbe_run_loopback_test(adapter); 2139 ixgbe_loopback_cleanup(adapter); 2140 2141 err_loopback: 2142 ixgbe_free_desc_rings(adapter); 2143 out: 2144 return *data; 2145 } 2146 2147 static void ixgbe_diag_test(struct net_device *netdev, 2148 struct ethtool_test *eth_test, u64 *data) 2149 { 2150 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2151 bool if_running = netif_running(netdev); 2152 2153 if (ixgbe_removed(adapter->hw.hw_addr)) { 2154 e_err(hw, "Adapter removed - test blocked\n"); 2155 data[0] = 1; 2156 data[1] = 1; 2157 data[2] = 1; 2158 data[3] = 1; 2159 data[4] = 1; 2160 eth_test->flags |= ETH_TEST_FL_FAILED; 2161 return; 2162 } 2163 set_bit(__IXGBE_TESTING, &adapter->state); 2164 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2165 struct ixgbe_hw *hw = &adapter->hw; 2166 2167 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2168 int i; 2169 for (i = 0; i < adapter->num_vfs; i++) { 2170 if (adapter->vfinfo[i].clear_to_send) { 2171 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2172 data[0] = 1; 2173 data[1] = 1; 2174 data[2] = 1; 2175 data[3] = 1; 2176 data[4] = 1; 2177 eth_test->flags |= ETH_TEST_FL_FAILED; 2178 clear_bit(__IXGBE_TESTING, 2179 &adapter->state); 2180 return; 2181 } 2182 } 2183 } 2184 2185 /* Offline tests */ 2186 e_info(hw, "offline testing starting\n"); 2187 2188 /* Link test performed before hardware reset so autoneg doesn't 2189 * interfere with test result 2190 */ 2191 if (ixgbe_link_test(adapter, &data[4])) 2192 eth_test->flags |= ETH_TEST_FL_FAILED; 2193 2194 if (if_running) 2195 /* indicate we're in test mode */ 2196 ixgbe_close(netdev); 2197 else 2198 ixgbe_reset(adapter); 2199 2200 e_info(hw, "register testing starting\n"); 2201 if (ixgbe_reg_test(adapter, &data[0])) 2202 eth_test->flags |= ETH_TEST_FL_FAILED; 2203 2204 ixgbe_reset(adapter); 2205 e_info(hw, "eeprom testing starting\n"); 2206 if (ixgbe_eeprom_test(adapter, &data[1])) 2207 eth_test->flags |= ETH_TEST_FL_FAILED; 2208 2209 ixgbe_reset(adapter); 2210 e_info(hw, "interrupt testing starting\n"); 2211 if (ixgbe_intr_test(adapter, &data[2])) 2212 eth_test->flags |= ETH_TEST_FL_FAILED; 2213 2214 /* If SRIOV or VMDq is enabled then skip MAC 2215 * loopback diagnostic. */ 2216 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2217 IXGBE_FLAG_VMDQ_ENABLED)) { 2218 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2219 data[3] = 0; 2220 goto skip_loopback; 2221 } 2222 2223 ixgbe_reset(adapter); 2224 e_info(hw, "loopback testing starting\n"); 2225 if (ixgbe_loopback_test(adapter, &data[3])) 2226 eth_test->flags |= ETH_TEST_FL_FAILED; 2227 2228 skip_loopback: 2229 ixgbe_reset(adapter); 2230 2231 /* clear testing bit and return adapter to previous state */ 2232 clear_bit(__IXGBE_TESTING, &adapter->state); 2233 if (if_running) 2234 ixgbe_open(netdev); 2235 else if (hw->mac.ops.disable_tx_laser) 2236 hw->mac.ops.disable_tx_laser(hw); 2237 } else { 2238 e_info(hw, "online testing starting\n"); 2239 2240 /* Online tests */ 2241 if (ixgbe_link_test(adapter, &data[4])) 2242 eth_test->flags |= ETH_TEST_FL_FAILED; 2243 2244 /* Offline tests aren't run; pass by default */ 2245 data[0] = 0; 2246 data[1] = 0; 2247 data[2] = 0; 2248 data[3] = 0; 2249 2250 clear_bit(__IXGBE_TESTING, &adapter->state); 2251 } 2252 } 2253 2254 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2255 struct ethtool_wolinfo *wol) 2256 { 2257 struct ixgbe_hw *hw = &adapter->hw; 2258 int retval = 0; 2259 2260 /* WOL not supported for all devices */ 2261 if (!ixgbe_wol_supported(adapter, hw->device_id, 2262 hw->subsystem_device_id)) { 2263 retval = 1; 2264 wol->supported = 0; 2265 } 2266 2267 return retval; 2268 } 2269 2270 static void ixgbe_get_wol(struct net_device *netdev, 2271 struct ethtool_wolinfo *wol) 2272 { 2273 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2274 2275 wol->supported = WAKE_UCAST | WAKE_MCAST | 2276 WAKE_BCAST | WAKE_MAGIC; 2277 wol->wolopts = 0; 2278 2279 if (ixgbe_wol_exclusion(adapter, wol) || 2280 !device_can_wakeup(&adapter->pdev->dev)) 2281 return; 2282 2283 if (adapter->wol & IXGBE_WUFC_EX) 2284 wol->wolopts |= WAKE_UCAST; 2285 if (adapter->wol & IXGBE_WUFC_MC) 2286 wol->wolopts |= WAKE_MCAST; 2287 if (adapter->wol & IXGBE_WUFC_BC) 2288 wol->wolopts |= WAKE_BCAST; 2289 if (adapter->wol & IXGBE_WUFC_MAG) 2290 wol->wolopts |= WAKE_MAGIC; 2291 } 2292 2293 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2294 { 2295 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2296 2297 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE | 2298 WAKE_FILTER)) 2299 return -EOPNOTSUPP; 2300 2301 if (ixgbe_wol_exclusion(adapter, wol)) 2302 return wol->wolopts ? -EOPNOTSUPP : 0; 2303 2304 adapter->wol = 0; 2305 2306 if (wol->wolopts & WAKE_UCAST) 2307 adapter->wol |= IXGBE_WUFC_EX; 2308 if (wol->wolopts & WAKE_MCAST) 2309 adapter->wol |= IXGBE_WUFC_MC; 2310 if (wol->wolopts & WAKE_BCAST) 2311 adapter->wol |= IXGBE_WUFC_BC; 2312 if (wol->wolopts & WAKE_MAGIC) 2313 adapter->wol |= IXGBE_WUFC_MAG; 2314 2315 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2316 2317 return 0; 2318 } 2319 2320 static int ixgbe_nway_reset(struct net_device *netdev) 2321 { 2322 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2323 2324 if (netif_running(netdev)) 2325 ixgbe_reinit_locked(adapter); 2326 2327 return 0; 2328 } 2329 2330 static int ixgbe_set_phys_id(struct net_device *netdev, 2331 enum ethtool_phys_id_state state) 2332 { 2333 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2334 struct ixgbe_hw *hw = &adapter->hw; 2335 2336 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off) 2337 return -EOPNOTSUPP; 2338 2339 switch (state) { 2340 case ETHTOOL_ID_ACTIVE: 2341 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2342 return 2; 2343 2344 case ETHTOOL_ID_ON: 2345 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2346 break; 2347 2348 case ETHTOOL_ID_OFF: 2349 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2350 break; 2351 2352 case ETHTOOL_ID_INACTIVE: 2353 /* Restore LED settings */ 2354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2355 break; 2356 } 2357 2358 return 0; 2359 } 2360 2361 static int ixgbe_get_coalesce(struct net_device *netdev, 2362 struct ethtool_coalesce *ec, 2363 struct kernel_ethtool_coalesce *kernel_coal, 2364 struct netlink_ext_ack *extack) 2365 { 2366 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2367 2368 /* only valid if in constant ITR mode */ 2369 if (adapter->rx_itr_setting <= 1) 2370 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2371 else 2372 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2373 2374 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2375 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2376 return 0; 2377 2378 /* only valid if in constant ITR mode */ 2379 if (adapter->tx_itr_setting <= 1) 2380 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2381 else 2382 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2383 2384 return 0; 2385 } 2386 2387 /* 2388 * this function must be called before setting the new value of 2389 * rx_itr_setting 2390 */ 2391 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2392 { 2393 struct net_device *netdev = adapter->netdev; 2394 2395 /* nothing to do if LRO or RSC are not enabled */ 2396 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2397 !(netdev->features & NETIF_F_LRO)) 2398 return false; 2399 2400 /* check the feature flag value and enable RSC if necessary */ 2401 if (adapter->rx_itr_setting == 1 || 2402 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2403 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2404 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2405 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2406 return true; 2407 } 2408 /* if interrupt rate is too high then disable RSC */ 2409 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2410 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2411 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2412 return true; 2413 } 2414 return false; 2415 } 2416 2417 static int ixgbe_set_coalesce(struct net_device *netdev, 2418 struct ethtool_coalesce *ec, 2419 struct kernel_ethtool_coalesce *kernel_coal, 2420 struct netlink_ext_ack *extack) 2421 { 2422 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2423 struct ixgbe_q_vector *q_vector; 2424 int i; 2425 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2426 bool need_reset = false; 2427 2428 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2429 /* reject Tx specific changes in case of mixed RxTx vectors */ 2430 if (ec->tx_coalesce_usecs) 2431 return -EINVAL; 2432 tx_itr_prev = adapter->rx_itr_setting; 2433 } else { 2434 tx_itr_prev = adapter->tx_itr_setting; 2435 } 2436 2437 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2438 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2439 return -EINVAL; 2440 2441 if (ec->rx_coalesce_usecs > 1) 2442 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2443 else 2444 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2445 2446 if (adapter->rx_itr_setting == 1) 2447 rx_itr_param = IXGBE_20K_ITR; 2448 else 2449 rx_itr_param = adapter->rx_itr_setting; 2450 2451 if (ec->tx_coalesce_usecs > 1) 2452 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2453 else 2454 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2455 2456 if (adapter->tx_itr_setting == 1) 2457 tx_itr_param = IXGBE_12K_ITR; 2458 else 2459 tx_itr_param = adapter->tx_itr_setting; 2460 2461 /* mixed Rx/Tx */ 2462 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2463 adapter->tx_itr_setting = adapter->rx_itr_setting; 2464 2465 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2466 if ((adapter->tx_itr_setting != 1) && 2467 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2468 if ((tx_itr_prev == 1) || 2469 (tx_itr_prev >= IXGBE_100K_ITR)) 2470 need_reset = true; 2471 } else { 2472 if ((tx_itr_prev != 1) && 2473 (tx_itr_prev < IXGBE_100K_ITR)) 2474 need_reset = true; 2475 } 2476 2477 /* check the old value and enable RSC if necessary */ 2478 need_reset |= ixgbe_update_rsc(adapter); 2479 2480 for (i = 0; i < adapter->num_q_vectors; i++) { 2481 q_vector = adapter->q_vector[i]; 2482 if (q_vector->tx.count && !q_vector->rx.count) 2483 /* tx only */ 2484 q_vector->itr = tx_itr_param; 2485 else 2486 /* rx only or mixed */ 2487 q_vector->itr = rx_itr_param; 2488 ixgbe_write_eitr(q_vector); 2489 } 2490 2491 /* 2492 * do reset here at the end to make sure EITR==0 case is handled 2493 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2494 * also locks in RSC enable/disable which requires reset 2495 */ 2496 if (need_reset) 2497 ixgbe_do_reset(netdev); 2498 2499 return 0; 2500 } 2501 2502 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2503 struct ethtool_rxnfc *cmd) 2504 { 2505 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2506 struct ethtool_rx_flow_spec *fsp = 2507 (struct ethtool_rx_flow_spec *)&cmd->fs; 2508 struct hlist_node *node2; 2509 struct ixgbe_fdir_filter *rule = NULL; 2510 2511 /* report total rule count */ 2512 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2513 2514 hlist_for_each_entry_safe(rule, node2, 2515 &adapter->fdir_filter_list, fdir_node) { 2516 if (fsp->location <= rule->sw_idx) 2517 break; 2518 } 2519 2520 if (!rule || fsp->location != rule->sw_idx) 2521 return -EINVAL; 2522 2523 /* fill out the flow spec entry */ 2524 2525 /* set flow type field */ 2526 switch (rule->filter.formatted.flow_type) { 2527 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2528 fsp->flow_type = TCP_V4_FLOW; 2529 break; 2530 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2531 fsp->flow_type = UDP_V4_FLOW; 2532 break; 2533 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2534 fsp->flow_type = SCTP_V4_FLOW; 2535 break; 2536 case IXGBE_ATR_FLOW_TYPE_IPV4: 2537 fsp->flow_type = IP_USER_FLOW; 2538 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2539 fsp->h_u.usr_ip4_spec.proto = 0; 2540 fsp->m_u.usr_ip4_spec.proto = 0; 2541 break; 2542 default: 2543 return -EINVAL; 2544 } 2545 2546 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2547 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2548 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2549 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2550 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2551 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2552 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2553 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2554 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2555 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2556 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2557 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2558 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2559 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2560 fsp->flow_type |= FLOW_EXT; 2561 2562 /* record action */ 2563 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2564 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2565 else 2566 fsp->ring_cookie = rule->action; 2567 2568 return 0; 2569 } 2570 2571 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2572 struct ethtool_rxnfc *cmd, 2573 u32 *rule_locs) 2574 { 2575 struct hlist_node *node2; 2576 struct ixgbe_fdir_filter *rule; 2577 int cnt = 0; 2578 2579 /* report total rule count */ 2580 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2581 2582 hlist_for_each_entry_safe(rule, node2, 2583 &adapter->fdir_filter_list, fdir_node) { 2584 if (cnt == cmd->rule_cnt) 2585 return -EMSGSIZE; 2586 rule_locs[cnt] = rule->sw_idx; 2587 cnt++; 2588 } 2589 2590 cmd->rule_cnt = cnt; 2591 2592 return 0; 2593 } 2594 2595 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2596 struct ethtool_rxnfc *cmd) 2597 { 2598 cmd->data = 0; 2599 2600 /* Report default options for RSS on ixgbe */ 2601 switch (cmd->flow_type) { 2602 case TCP_V4_FLOW: 2603 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2604 fallthrough; 2605 case UDP_V4_FLOW: 2606 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2607 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2608 fallthrough; 2609 case SCTP_V4_FLOW: 2610 case AH_ESP_V4_FLOW: 2611 case AH_V4_FLOW: 2612 case ESP_V4_FLOW: 2613 case IPV4_FLOW: 2614 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2615 break; 2616 case TCP_V6_FLOW: 2617 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2618 fallthrough; 2619 case UDP_V6_FLOW: 2620 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2621 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2622 fallthrough; 2623 case SCTP_V6_FLOW: 2624 case AH_ESP_V6_FLOW: 2625 case AH_V6_FLOW: 2626 case ESP_V6_FLOW: 2627 case IPV6_FLOW: 2628 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2629 break; 2630 default: 2631 return -EINVAL; 2632 } 2633 2634 return 0; 2635 } 2636 2637 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2638 u32 *rule_locs) 2639 { 2640 struct ixgbe_adapter *adapter = netdev_priv(dev); 2641 int ret = -EOPNOTSUPP; 2642 2643 switch (cmd->cmd) { 2644 case ETHTOOL_GRXRINGS: 2645 cmd->data = adapter->num_rx_queues; 2646 ret = 0; 2647 break; 2648 case ETHTOOL_GRXCLSRLCNT: 2649 cmd->rule_cnt = adapter->fdir_filter_count; 2650 ret = 0; 2651 break; 2652 case ETHTOOL_GRXCLSRULE: 2653 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2654 break; 2655 case ETHTOOL_GRXCLSRLALL: 2656 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2657 break; 2658 case ETHTOOL_GRXFH: 2659 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2660 break; 2661 default: 2662 break; 2663 } 2664 2665 return ret; 2666 } 2667 2668 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2669 struct ixgbe_fdir_filter *input, 2670 u16 sw_idx) 2671 { 2672 struct ixgbe_hw *hw = &adapter->hw; 2673 struct hlist_node *node2; 2674 struct ixgbe_fdir_filter *rule, *parent; 2675 int err = -EINVAL; 2676 2677 parent = NULL; 2678 rule = NULL; 2679 2680 hlist_for_each_entry_safe(rule, node2, 2681 &adapter->fdir_filter_list, fdir_node) { 2682 /* hash found, or no matching entry */ 2683 if (rule->sw_idx >= sw_idx) 2684 break; 2685 parent = rule; 2686 } 2687 2688 /* if there is an old rule occupying our place remove it */ 2689 if (rule && (rule->sw_idx == sw_idx)) { 2690 if (!input || (rule->filter.formatted.bkt_hash != 2691 input->filter.formatted.bkt_hash)) { 2692 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2693 &rule->filter, 2694 sw_idx); 2695 } 2696 2697 hlist_del(&rule->fdir_node); 2698 kfree(rule); 2699 adapter->fdir_filter_count--; 2700 } 2701 2702 /* 2703 * If no input this was a delete, err should be 0 if a rule was 2704 * successfully found and removed from the list else -EINVAL 2705 */ 2706 if (!input) 2707 return err; 2708 2709 /* initialize node and set software index */ 2710 INIT_HLIST_NODE(&input->fdir_node); 2711 2712 /* add filter to the list */ 2713 if (parent) 2714 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2715 else 2716 hlist_add_head(&input->fdir_node, 2717 &adapter->fdir_filter_list); 2718 2719 /* update counts */ 2720 adapter->fdir_filter_count++; 2721 2722 return 0; 2723 } 2724 2725 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2726 u8 *flow_type) 2727 { 2728 switch (fsp->flow_type & ~FLOW_EXT) { 2729 case TCP_V4_FLOW: 2730 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2731 break; 2732 case UDP_V4_FLOW: 2733 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2734 break; 2735 case SCTP_V4_FLOW: 2736 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2737 break; 2738 case IP_USER_FLOW: 2739 switch (fsp->h_u.usr_ip4_spec.proto) { 2740 case IPPROTO_TCP: 2741 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2742 break; 2743 case IPPROTO_UDP: 2744 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2745 break; 2746 case IPPROTO_SCTP: 2747 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2748 break; 2749 case 0: 2750 if (!fsp->m_u.usr_ip4_spec.proto) { 2751 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2752 break; 2753 } 2754 fallthrough; 2755 default: 2756 return 0; 2757 } 2758 break; 2759 default: 2760 return 0; 2761 } 2762 2763 return 1; 2764 } 2765 2766 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2767 struct ethtool_rxnfc *cmd) 2768 { 2769 struct ethtool_rx_flow_spec *fsp = 2770 (struct ethtool_rx_flow_spec *)&cmd->fs; 2771 struct ixgbe_hw *hw = &adapter->hw; 2772 struct ixgbe_fdir_filter *input; 2773 union ixgbe_atr_input mask; 2774 u8 queue; 2775 int err; 2776 2777 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2778 return -EOPNOTSUPP; 2779 2780 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2781 * we use the drop index. 2782 */ 2783 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2784 queue = IXGBE_FDIR_DROP_QUEUE; 2785 } else { 2786 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2787 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2788 2789 if (!vf && (ring >= adapter->num_rx_queues)) 2790 return -EINVAL; 2791 else if (vf && 2792 ((vf > adapter->num_vfs) || 2793 ring >= adapter->num_rx_queues_per_pool)) 2794 return -EINVAL; 2795 2796 /* Map the ring onto the absolute queue index */ 2797 if (!vf) 2798 queue = adapter->rx_ring[ring]->reg_idx; 2799 else 2800 queue = ((vf - 1) * 2801 adapter->num_rx_queues_per_pool) + ring; 2802 } 2803 2804 /* Don't allow indexes to exist outside of available space */ 2805 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2806 e_err(drv, "Location out of range\n"); 2807 return -EINVAL; 2808 } 2809 2810 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2811 if (!input) 2812 return -ENOMEM; 2813 2814 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2815 2816 /* set SW index */ 2817 input->sw_idx = fsp->location; 2818 2819 /* record flow type */ 2820 if (!ixgbe_flowspec_to_flow_type(fsp, 2821 &input->filter.formatted.flow_type)) { 2822 e_err(drv, "Unrecognized flow type\n"); 2823 goto err_out; 2824 } 2825 2826 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2827 IXGBE_ATR_L4TYPE_MASK; 2828 2829 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2830 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2831 2832 /* Copy input into formatted structures */ 2833 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2834 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2835 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2836 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2837 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2838 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2839 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2840 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2841 2842 if (fsp->flow_type & FLOW_EXT) { 2843 input->filter.formatted.vm_pool = 2844 (unsigned char)ntohl(fsp->h_ext.data[1]); 2845 mask.formatted.vm_pool = 2846 (unsigned char)ntohl(fsp->m_ext.data[1]); 2847 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2848 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2849 input->filter.formatted.flex_bytes = 2850 fsp->h_ext.vlan_etype; 2851 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2852 } 2853 2854 /* determine if we need to drop or route the packet */ 2855 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2856 input->action = IXGBE_FDIR_DROP_QUEUE; 2857 else 2858 input->action = fsp->ring_cookie; 2859 2860 spin_lock(&adapter->fdir_perfect_lock); 2861 2862 if (hlist_empty(&adapter->fdir_filter_list)) { 2863 /* save mask and program input mask into HW */ 2864 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2865 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2866 if (err) { 2867 e_err(drv, "Error writing mask\n"); 2868 goto err_out_w_lock; 2869 } 2870 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2871 e_err(drv, "Only one mask supported per port\n"); 2872 goto err_out_w_lock; 2873 } 2874 2875 /* apply mask and compute/store hash */ 2876 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2877 2878 /* program filters to filter memory */ 2879 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2880 &input->filter, input->sw_idx, queue); 2881 if (err) 2882 goto err_out_w_lock; 2883 2884 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2885 2886 spin_unlock(&adapter->fdir_perfect_lock); 2887 2888 return err; 2889 err_out_w_lock: 2890 spin_unlock(&adapter->fdir_perfect_lock); 2891 err_out: 2892 kfree(input); 2893 return -EINVAL; 2894 } 2895 2896 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2897 struct ethtool_rxnfc *cmd) 2898 { 2899 struct ethtool_rx_flow_spec *fsp = 2900 (struct ethtool_rx_flow_spec *)&cmd->fs; 2901 int err; 2902 2903 spin_lock(&adapter->fdir_perfect_lock); 2904 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2905 spin_unlock(&adapter->fdir_perfect_lock); 2906 2907 return err; 2908 } 2909 2910 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2911 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2912 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2913 struct ethtool_rxnfc *nfc) 2914 { 2915 u32 flags2 = adapter->flags2; 2916 2917 /* 2918 * RSS does not support anything other than hashing 2919 * to queues on src and dst IPs and ports 2920 */ 2921 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2922 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2923 return -EINVAL; 2924 2925 switch (nfc->flow_type) { 2926 case TCP_V4_FLOW: 2927 case TCP_V6_FLOW: 2928 if (!(nfc->data & RXH_IP_SRC) || 2929 !(nfc->data & RXH_IP_DST) || 2930 !(nfc->data & RXH_L4_B_0_1) || 2931 !(nfc->data & RXH_L4_B_2_3)) 2932 return -EINVAL; 2933 break; 2934 case UDP_V4_FLOW: 2935 if (!(nfc->data & RXH_IP_SRC) || 2936 !(nfc->data & RXH_IP_DST)) 2937 return -EINVAL; 2938 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2939 case 0: 2940 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2941 break; 2942 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2943 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2944 break; 2945 default: 2946 return -EINVAL; 2947 } 2948 break; 2949 case UDP_V6_FLOW: 2950 if (!(nfc->data & RXH_IP_SRC) || 2951 !(nfc->data & RXH_IP_DST)) 2952 return -EINVAL; 2953 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2954 case 0: 2955 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2956 break; 2957 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2958 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2959 break; 2960 default: 2961 return -EINVAL; 2962 } 2963 break; 2964 case AH_ESP_V4_FLOW: 2965 case AH_V4_FLOW: 2966 case ESP_V4_FLOW: 2967 case SCTP_V4_FLOW: 2968 case AH_ESP_V6_FLOW: 2969 case AH_V6_FLOW: 2970 case ESP_V6_FLOW: 2971 case SCTP_V6_FLOW: 2972 if (!(nfc->data & RXH_IP_SRC) || 2973 !(nfc->data & RXH_IP_DST) || 2974 (nfc->data & RXH_L4_B_0_1) || 2975 (nfc->data & RXH_L4_B_2_3)) 2976 return -EINVAL; 2977 break; 2978 default: 2979 return -EINVAL; 2980 } 2981 2982 /* if we changed something we need to update flags */ 2983 if (flags2 != adapter->flags2) { 2984 struct ixgbe_hw *hw = &adapter->hw; 2985 u32 mrqc; 2986 unsigned int pf_pool = adapter->num_vfs; 2987 2988 if ((hw->mac.type >= ixgbe_mac_X550) && 2989 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2990 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2991 else 2992 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2993 2994 if ((flags2 & UDP_RSS_FLAGS) && 2995 !(adapter->flags2 & UDP_RSS_FLAGS)) 2996 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2997 2998 adapter->flags2 = flags2; 2999 3000 /* Perform hash on these packet types */ 3001 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 3002 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 3003 | IXGBE_MRQC_RSS_FIELD_IPV6 3004 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3005 3006 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 3007 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 3008 3009 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3010 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3011 3012 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3013 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3014 3015 if ((hw->mac.type >= ixgbe_mac_X550) && 3016 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3017 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 3018 else 3019 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3020 } 3021 3022 return 0; 3023 } 3024 3025 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3026 { 3027 struct ixgbe_adapter *adapter = netdev_priv(dev); 3028 int ret = -EOPNOTSUPP; 3029 3030 switch (cmd->cmd) { 3031 case ETHTOOL_SRXCLSRLINS: 3032 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 3033 break; 3034 case ETHTOOL_SRXCLSRLDEL: 3035 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 3036 break; 3037 case ETHTOOL_SRXFH: 3038 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 3039 break; 3040 default: 3041 break; 3042 } 3043 3044 return ret; 3045 } 3046 3047 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 3048 { 3049 if (adapter->hw.mac.type < ixgbe_mac_X550) 3050 return 16; 3051 else 3052 return 64; 3053 } 3054 3055 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 3056 { 3057 return IXGBE_RSS_KEY_SIZE; 3058 } 3059 3060 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 3061 { 3062 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3063 3064 return ixgbe_rss_indir_tbl_entries(adapter); 3065 } 3066 3067 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 3068 { 3069 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 3070 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 3071 3072 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3073 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 3074 3075 for (i = 0; i < reta_size; i++) 3076 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 3077 } 3078 3079 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3080 u8 *hfunc) 3081 { 3082 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3083 3084 if (hfunc) 3085 *hfunc = ETH_RSS_HASH_TOP; 3086 3087 if (indir) 3088 ixgbe_get_reta(adapter, indir); 3089 3090 if (key) 3091 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 3092 3093 return 0; 3094 } 3095 3096 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, 3097 const u8 *key, const u8 hfunc) 3098 { 3099 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3100 int i; 3101 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3102 3103 if (hfunc) 3104 return -EINVAL; 3105 3106 /* Fill out the redirection table */ 3107 if (indir) { 3108 int max_queues = min_t(int, adapter->num_rx_queues, 3109 ixgbe_rss_indir_tbl_max(adapter)); 3110 3111 /*Allow at least 2 queues w/ SR-IOV.*/ 3112 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3113 (max_queues < 2)) 3114 max_queues = 2; 3115 3116 /* Verify user input. */ 3117 for (i = 0; i < reta_entries; i++) 3118 if (indir[i] >= max_queues) 3119 return -EINVAL; 3120 3121 for (i = 0; i < reta_entries; i++) 3122 adapter->rss_indir_tbl[i] = indir[i]; 3123 3124 ixgbe_store_reta(adapter); 3125 } 3126 3127 /* Fill out the rss hash key */ 3128 if (key) { 3129 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev)); 3130 ixgbe_store_key(adapter); 3131 } 3132 3133 return 0; 3134 } 3135 3136 static int ixgbe_get_ts_info(struct net_device *dev, 3137 struct ethtool_ts_info *info) 3138 { 3139 struct ixgbe_adapter *adapter = netdev_priv(dev); 3140 3141 /* we always support timestamping disabled */ 3142 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3143 3144 switch (adapter->hw.mac.type) { 3145 case ixgbe_mac_X550: 3146 case ixgbe_mac_X550EM_x: 3147 case ixgbe_mac_x550em_a: 3148 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3149 break; 3150 case ixgbe_mac_X540: 3151 case ixgbe_mac_82599EB: 3152 info->rx_filters |= 3153 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3154 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3155 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3156 break; 3157 default: 3158 return ethtool_op_get_ts_info(dev, info); 3159 } 3160 3161 info->so_timestamping = 3162 SOF_TIMESTAMPING_TX_SOFTWARE | 3163 SOF_TIMESTAMPING_RX_SOFTWARE | 3164 SOF_TIMESTAMPING_SOFTWARE | 3165 SOF_TIMESTAMPING_TX_HARDWARE | 3166 SOF_TIMESTAMPING_RX_HARDWARE | 3167 SOF_TIMESTAMPING_RAW_HARDWARE; 3168 3169 if (adapter->ptp_clock) 3170 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3171 else 3172 info->phc_index = -1; 3173 3174 info->tx_types = 3175 BIT(HWTSTAMP_TX_OFF) | 3176 BIT(HWTSTAMP_TX_ON); 3177 3178 return 0; 3179 } 3180 3181 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3182 { 3183 unsigned int max_combined; 3184 u8 tcs = adapter->hw_tcs; 3185 3186 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3187 /* We only support one q_vector without MSI-X */ 3188 max_combined = 1; 3189 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3190 /* Limit value based on the queue mask */ 3191 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3192 } else if (tcs > 1) { 3193 /* For DCB report channels per traffic class */ 3194 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3195 /* 8 TC w/ 4 queues per TC */ 3196 max_combined = 4; 3197 } else if (tcs > 4) { 3198 /* 8 TC w/ 8 queues per TC */ 3199 max_combined = 8; 3200 } else { 3201 /* 4 TC w/ 16 queues per TC */ 3202 max_combined = 16; 3203 } 3204 } else if (adapter->atr_sample_rate) { 3205 /* support up to 64 queues with ATR */ 3206 max_combined = IXGBE_MAX_FDIR_INDICES; 3207 } else { 3208 /* support up to 16 queues with RSS */ 3209 max_combined = ixgbe_max_rss_indices(adapter); 3210 } 3211 3212 return min_t(int, max_combined, num_online_cpus()); 3213 } 3214 3215 static void ixgbe_get_channels(struct net_device *dev, 3216 struct ethtool_channels *ch) 3217 { 3218 struct ixgbe_adapter *adapter = netdev_priv(dev); 3219 3220 /* report maximum channels */ 3221 ch->max_combined = ixgbe_max_channels(adapter); 3222 3223 /* report info for other vector */ 3224 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3225 ch->max_other = NON_Q_VECTORS; 3226 ch->other_count = NON_Q_VECTORS; 3227 } 3228 3229 /* record RSS queues */ 3230 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3231 3232 /* nothing else to report if RSS is disabled */ 3233 if (ch->combined_count == 1) 3234 return; 3235 3236 /* we do not support ATR queueing if SR-IOV is enabled */ 3237 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3238 return; 3239 3240 /* same thing goes for being DCB enabled */ 3241 if (adapter->hw_tcs > 1) 3242 return; 3243 3244 /* if ATR is disabled we can exit */ 3245 if (!adapter->atr_sample_rate) 3246 return; 3247 3248 /* report flow director queues as maximum channels */ 3249 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3250 } 3251 3252 static int ixgbe_set_channels(struct net_device *dev, 3253 struct ethtool_channels *ch) 3254 { 3255 struct ixgbe_adapter *adapter = netdev_priv(dev); 3256 unsigned int count = ch->combined_count; 3257 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3258 3259 /* verify they are not requesting separate vectors */ 3260 if (!count || ch->rx_count || ch->tx_count) 3261 return -EINVAL; 3262 3263 /* verify other_count has not changed */ 3264 if (ch->other_count != NON_Q_VECTORS) 3265 return -EINVAL; 3266 3267 /* verify the number of channels does not exceed hardware limits */ 3268 if (count > ixgbe_max_channels(adapter)) 3269 return -EINVAL; 3270 3271 /* update feature limits from largest to smallest supported values */ 3272 adapter->ring_feature[RING_F_FDIR].limit = count; 3273 3274 /* cap RSS limit */ 3275 if (count > max_rss_indices) 3276 count = max_rss_indices; 3277 adapter->ring_feature[RING_F_RSS].limit = count; 3278 3279 #ifdef IXGBE_FCOE 3280 /* cap FCoE limit at 8 */ 3281 if (count > IXGBE_FCRETA_SIZE) 3282 count = IXGBE_FCRETA_SIZE; 3283 adapter->ring_feature[RING_F_FCOE].limit = count; 3284 3285 #endif 3286 /* use setup TC to update any traffic class queue mapping */ 3287 return ixgbe_setup_tc(dev, adapter->hw_tcs); 3288 } 3289 3290 static int ixgbe_get_module_info(struct net_device *dev, 3291 struct ethtool_modinfo *modinfo) 3292 { 3293 struct ixgbe_adapter *adapter = netdev_priv(dev); 3294 struct ixgbe_hw *hw = &adapter->hw; 3295 s32 status; 3296 u8 sff8472_rev, addr_mode; 3297 bool page_swap = false; 3298 3299 if (hw->phy.type == ixgbe_phy_fw) 3300 return -ENXIO; 3301 3302 /* Check whether we support SFF-8472 or not */ 3303 status = hw->phy.ops.read_i2c_eeprom(hw, 3304 IXGBE_SFF_SFF_8472_COMP, 3305 &sff8472_rev); 3306 if (status) 3307 return -EIO; 3308 3309 /* addressing mode is not supported */ 3310 status = hw->phy.ops.read_i2c_eeprom(hw, 3311 IXGBE_SFF_SFF_8472_SWAP, 3312 &addr_mode); 3313 if (status) 3314 return -EIO; 3315 3316 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3317 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3318 page_swap = true; 3319 } 3320 3321 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap || 3322 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) { 3323 /* We have a SFP, but it does not support SFF-8472 */ 3324 modinfo->type = ETH_MODULE_SFF_8079; 3325 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3326 } else { 3327 /* We have a SFP which supports a revision of SFF-8472. */ 3328 modinfo->type = ETH_MODULE_SFF_8472; 3329 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3330 } 3331 3332 return 0; 3333 } 3334 3335 static int ixgbe_get_module_eeprom(struct net_device *dev, 3336 struct ethtool_eeprom *ee, 3337 u8 *data) 3338 { 3339 struct ixgbe_adapter *adapter = netdev_priv(dev); 3340 struct ixgbe_hw *hw = &adapter->hw; 3341 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3342 u8 databyte = 0xFF; 3343 int i = 0; 3344 3345 if (ee->len == 0) 3346 return -EINVAL; 3347 3348 if (hw->phy.type == ixgbe_phy_fw) 3349 return -ENXIO; 3350 3351 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3352 /* I2C reads can take long time */ 3353 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3354 return -EBUSY; 3355 3356 if (i < ETH_MODULE_SFF_8079_LEN) 3357 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3358 else 3359 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3360 3361 if (status) 3362 return -EIO; 3363 3364 data[i - ee->offset] = databyte; 3365 } 3366 3367 return 0; 3368 } 3369 3370 static const struct { 3371 ixgbe_link_speed mac_speed; 3372 u32 supported; 3373 } ixgbe_ls_map[] = { 3374 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full }, 3375 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full }, 3376 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full }, 3377 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full }, 3378 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full }, 3379 }; 3380 3381 static const struct { 3382 u32 lp_advertised; 3383 u32 mac_speed; 3384 } ixgbe_lp_map[] = { 3385 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full }, 3386 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full }, 3387 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full }, 3388 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full }, 3389 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full }, 3390 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full}, 3391 }; 3392 3393 static int 3394 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata) 3395 { 3396 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3397 struct ixgbe_hw *hw = &adapter->hw; 3398 s32 rc; 3399 u16 i; 3400 3401 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3402 if (rc) 3403 return rc; 3404 3405 edata->lp_advertised = 0; 3406 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3407 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3408 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed; 3409 } 3410 3411 edata->supported = 0; 3412 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3413 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3414 edata->supported |= ixgbe_ls_map[i].supported; 3415 } 3416 3417 edata->advertised = 0; 3418 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3419 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3420 edata->advertised |= ixgbe_ls_map[i].supported; 3421 } 3422 3423 edata->eee_enabled = !!edata->advertised; 3424 edata->tx_lpi_enabled = edata->eee_enabled; 3425 if (edata->advertised & edata->lp_advertised) 3426 edata->eee_active = true; 3427 3428 return 0; 3429 } 3430 3431 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3432 { 3433 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3434 struct ixgbe_hw *hw = &adapter->hw; 3435 3436 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3437 return -EOPNOTSUPP; 3438 3439 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3440 return ixgbe_get_eee_fw(adapter, edata); 3441 3442 return -EOPNOTSUPP; 3443 } 3444 3445 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata) 3446 { 3447 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3448 struct ixgbe_hw *hw = &adapter->hw; 3449 struct ethtool_eee eee_data; 3450 s32 ret_val; 3451 3452 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3453 return -EOPNOTSUPP; 3454 3455 memset(&eee_data, 0, sizeof(struct ethtool_eee)); 3456 3457 ret_val = ixgbe_get_eee(netdev, &eee_data); 3458 if (ret_val) 3459 return ret_val; 3460 3461 if (eee_data.eee_enabled && !edata->eee_enabled) { 3462 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3463 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3464 return -EINVAL; 3465 } 3466 3467 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3468 e_err(drv, 3469 "Setting EEE Tx LPI timer is not supported\n"); 3470 return -EINVAL; 3471 } 3472 3473 if (eee_data.advertised != edata->advertised) { 3474 e_err(drv, 3475 "Setting EEE advertised speeds is not supported\n"); 3476 return -EINVAL; 3477 } 3478 } 3479 3480 if (eee_data.eee_enabled != edata->eee_enabled) { 3481 if (edata->eee_enabled) { 3482 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3483 hw->phy.eee_speeds_advertised = 3484 hw->phy.eee_speeds_supported; 3485 } else { 3486 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3487 hw->phy.eee_speeds_advertised = 0; 3488 } 3489 3490 /* reset link */ 3491 if (netif_running(netdev)) 3492 ixgbe_reinit_locked(adapter); 3493 else 3494 ixgbe_reset(adapter); 3495 } 3496 3497 return 0; 3498 } 3499 3500 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3501 { 3502 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3503 u32 priv_flags = 0; 3504 3505 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3506 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3507 3508 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED) 3509 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN; 3510 3511 if (adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) 3512 priv_flags |= IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF; 3513 3514 return priv_flags; 3515 } 3516 3517 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3518 { 3519 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3520 unsigned int flags2 = adapter->flags2; 3521 unsigned int i; 3522 3523 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3524 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3525 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3526 3527 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED; 3528 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN) 3529 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED; 3530 3531 flags2 &= ~IXGBE_FLAG2_AUTO_DISABLE_VF; 3532 if (priv_flags & IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF) { 3533 if (adapter->hw.mac.type == ixgbe_mac_82599EB) { 3534 /* Reset primary abort counter */ 3535 for (i = 0; i < adapter->num_vfs; i++) 3536 adapter->vfinfo[i].primary_abort_count = 0; 3537 3538 flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 3539 } else { 3540 e_info(probe, 3541 "Cannot set private flags: Operation not supported\n"); 3542 return -EOPNOTSUPP; 3543 } 3544 } 3545 3546 if (flags2 != adapter->flags2) { 3547 adapter->flags2 = flags2; 3548 3549 /* reset interface to repopulate queues */ 3550 if (netif_running(netdev)) 3551 ixgbe_reinit_locked(adapter); 3552 } 3553 3554 return 0; 3555 } 3556 3557 static const struct ethtool_ops ixgbe_ethtool_ops = { 3558 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3559 .get_drvinfo = ixgbe_get_drvinfo, 3560 .get_regs_len = ixgbe_get_regs_len, 3561 .get_regs = ixgbe_get_regs, 3562 .get_wol = ixgbe_get_wol, 3563 .set_wol = ixgbe_set_wol, 3564 .nway_reset = ixgbe_nway_reset, 3565 .get_link = ethtool_op_get_link, 3566 .get_eeprom_len = ixgbe_get_eeprom_len, 3567 .get_eeprom = ixgbe_get_eeprom, 3568 .set_eeprom = ixgbe_set_eeprom, 3569 .get_ringparam = ixgbe_get_ringparam, 3570 .set_ringparam = ixgbe_set_ringparam, 3571 .get_pause_stats = ixgbe_get_pause_stats, 3572 .get_pauseparam = ixgbe_get_pauseparam, 3573 .set_pauseparam = ixgbe_set_pauseparam, 3574 .get_msglevel = ixgbe_get_msglevel, 3575 .set_msglevel = ixgbe_set_msglevel, 3576 .self_test = ixgbe_diag_test, 3577 .get_strings = ixgbe_get_strings, 3578 .set_phys_id = ixgbe_set_phys_id, 3579 .get_sset_count = ixgbe_get_sset_count, 3580 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3581 .get_coalesce = ixgbe_get_coalesce, 3582 .set_coalesce = ixgbe_set_coalesce, 3583 .get_rxnfc = ixgbe_get_rxnfc, 3584 .set_rxnfc = ixgbe_set_rxnfc, 3585 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3586 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3587 .get_rxfh = ixgbe_get_rxfh, 3588 .set_rxfh = ixgbe_set_rxfh, 3589 .get_eee = ixgbe_get_eee, 3590 .set_eee = ixgbe_set_eee, 3591 .get_channels = ixgbe_get_channels, 3592 .set_channels = ixgbe_set_channels, 3593 .get_priv_flags = ixgbe_get_priv_flags, 3594 .set_priv_flags = ixgbe_set_priv_flags, 3595 .get_ts_info = ixgbe_get_ts_info, 3596 .get_module_info = ixgbe_get_module_info, 3597 .get_module_eeprom = ixgbe_get_module_eeprom, 3598 .get_link_ksettings = ixgbe_get_link_ksettings, 3599 .set_link_ksettings = ixgbe_set_link_ksettings, 3600 }; 3601 3602 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3603 { 3604 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3605 } 3606