1cde29af9SShinas Rasheed /* SPDX-License-Identifier: GPL-2.0 */ 2cde29af9SShinas Rasheed /* Marvell Octeon EP (EndPoint) Ethernet Driver 3cde29af9SShinas Rasheed * 4cde29af9SShinas Rasheed * Copyright (C) 2020 Marvell. 5cde29af9SShinas Rasheed * 6cde29af9SShinas Rasheed */ 7cde29af9SShinas Rasheed 8cde29af9SShinas Rasheed #ifndef _OCTEP_PFVF_MBOX_H_ 9cde29af9SShinas Rasheed #define _OCTEP_PFVF_MBOX_H_ 10cde29af9SShinas Rasheed 11cde29af9SShinas Rasheed /* VF flags */ 12cde29af9SShinas Rasheed #define OCTEON_PFVF_FLAG_MAC_SET_BY_PF BIT_ULL(0) /* PF has set VF MAC address */ 13cde29af9SShinas Rasheed #define OCTEON_SDP_16K_HW_FRS 16380UL 14cde29af9SShinas Rasheed #define OCTEON_SDP_64K_HW_FRS 65531UL 15cde29af9SShinas Rasheed 16c130e589SShinas Rasheed /* When a new command is implemented,PF Mbox version should be bumped. 17c130e589SShinas Rasheed */ 18cde29af9SShinas Rasheed enum octep_pfvf_mbox_version { 19cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_VERSION_V0, 20cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_VERSION_V1, 21e28db8cbSShinas Rasheed OCTEP_PFVF_MBOX_VERSION_V2, 22cde29af9SShinas Rasheed }; 23cde29af9SShinas Rasheed 24e28db8cbSShinas Rasheed #define OCTEP_PFVF_MBOX_VERSION_CURRENT OCTEP_PFVF_MBOX_VERSION_V2 25c130e589SShinas Rasheed 26cde29af9SShinas Rasheed enum octep_pfvf_mbox_opcode { 27cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_VERSION, 28cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_SET_MTU, 29cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_SET_MAC_ADDR, 30cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_MAC_ADDR, 31cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_LINK_INFO, 32cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_STATS, 33cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_SET_RX_STATE, 34cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_SET_LINK_STATUS, 35cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_LINK_STATUS, 36cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_MTU, 37cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_DEV_REMOVE, 38e28db8cbSShinas Rasheed OCTEP_PFVF_MBOX_CMD_GET_FW_INFO, 39e28db8cbSShinas Rasheed OCTEP_PFVF_MBOX_CMD_SET_OFFLOADS, 40*4ebb86a9SShinas Rasheed OCTEP_PFVF_MBOX_NOTIF_LINK_STATUS, 41cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_MAX, 42cde29af9SShinas Rasheed }; 43cde29af9SShinas Rasheed 44cde29af9SShinas Rasheed enum octep_pfvf_mbox_word_type { 45cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_TYPE_CMD, 46cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_TYPE_RSP_ACK, 47cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_TYPE_RSP_NACK, 48cde29af9SShinas Rasheed }; 49cde29af9SShinas Rasheed 50cde29af9SShinas Rasheed enum octep_pfvf_mbox_cmd_status { 51cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_STATUS_NOT_SETUP = 1, 52cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_STATUS_TIMEDOUT = 2, 53cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_STATUS_NACK = 3, 54cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_CMD_STATUS_BUSY = 4 55cde29af9SShinas Rasheed }; 56cde29af9SShinas Rasheed 57cde29af9SShinas Rasheed enum octep_pfvf_mbox_state { 58cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_STATE_IDLE = 0, 59cde29af9SShinas Rasheed OCTEP_PFVF_MBOX_STATE_BUSY = 1, 60cde29af9SShinas Rasheed }; 61cde29af9SShinas Rasheed 62cde29af9SShinas Rasheed enum octep_pfvf_link_status { 63cde29af9SShinas Rasheed OCTEP_PFVF_LINK_STATUS_DOWN, 64cde29af9SShinas Rasheed OCTEP_PFVF_LINK_STATUS_UP, 65cde29af9SShinas Rasheed }; 66cde29af9SShinas Rasheed 67cde29af9SShinas Rasheed enum octep_pfvf_link_speed { 68cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_NONE, 69cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_1000, 70cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_10000, 71cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_25000, 72cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_40000, 73cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_50000, 74cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_100000, 75cde29af9SShinas Rasheed OCTEP_PFVF_LINK_SPEED_LAST, 76cde29af9SShinas Rasheed }; 77cde29af9SShinas Rasheed 78cde29af9SShinas Rasheed enum octep_pfvf_link_duplex { 79cde29af9SShinas Rasheed OCTEP_PFVF_LINK_HALF_DUPLEX, 80cde29af9SShinas Rasheed OCTEP_PFVF_LINK_FULL_DUPLEX, 81cde29af9SShinas Rasheed }; 82cde29af9SShinas Rasheed 83cde29af9SShinas Rasheed enum octep_pfvf_link_autoneg { 84cde29af9SShinas Rasheed OCTEP_PFVF_LINK_AUTONEG, 85cde29af9SShinas Rasheed OCTEP_PFVF_LINK_FIXED, 86cde29af9SShinas Rasheed }; 87cde29af9SShinas Rasheed 88cde29af9SShinas Rasheed #define OCTEP_PFVF_MBOX_TIMEOUT_MS 500 89cde29af9SShinas Rasheed #define OCTEP_PFVF_MBOX_MAX_RETRIES 2 90cde29af9SShinas Rasheed #define OCTEP_PFVF_MBOX_MAX_DATA_SIZE 6 91cde29af9SShinas Rasheed #define OCTEP_PFVF_MBOX_MORE_FRAG_FLAG 1 92cde29af9SShinas Rasheed #define OCTEP_PFVF_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1) 93cde29af9SShinas Rasheed 94cde29af9SShinas Rasheed union octep_pfvf_mbox_word { 95cde29af9SShinas Rasheed u64 u64; 96cde29af9SShinas Rasheed struct { 97cde29af9SShinas Rasheed u64 opcode:8; 98cde29af9SShinas Rasheed u64 type:2; 99cde29af9SShinas Rasheed u64 rsvd:6; 100cde29af9SShinas Rasheed u64 data:48; 101cde29af9SShinas Rasheed } s; 102cde29af9SShinas Rasheed struct { 103cde29af9SShinas Rasheed u64 opcode:8; 104cde29af9SShinas Rasheed u64 type:2; 105cde29af9SShinas Rasheed u64 frag:1; 106cde29af9SShinas Rasheed u64 rsvd:5; 107cde29af9SShinas Rasheed u8 data[6]; 108cde29af9SShinas Rasheed } s_data; 109cde29af9SShinas Rasheed struct { 110cde29af9SShinas Rasheed u64 opcode:8; 111cde29af9SShinas Rasheed u64 type:2; 112cde29af9SShinas Rasheed u64 rsvd:6; 113cde29af9SShinas Rasheed u64 version:48; 114cde29af9SShinas Rasheed } s_version; 115cde29af9SShinas Rasheed struct { 116cde29af9SShinas Rasheed u64 opcode:8; 117cde29af9SShinas Rasheed u64 type:2; 118cde29af9SShinas Rasheed u64 rsvd:6; 119cde29af9SShinas Rasheed u8 mac_addr[6]; 120cde29af9SShinas Rasheed } s_set_mac; 121cde29af9SShinas Rasheed struct { 122cde29af9SShinas Rasheed u64 opcode:8; 123cde29af9SShinas Rasheed u64 type:2; 124cde29af9SShinas Rasheed u64 rsvd:6; 125cde29af9SShinas Rasheed u64 mtu:48; 126cde29af9SShinas Rasheed } s_set_mtu; 127cde29af9SShinas Rasheed struct { 128cde29af9SShinas Rasheed u64 opcode:8; 129cde29af9SShinas Rasheed u64 type:2; 130cde29af9SShinas Rasheed u64 rsvd:6; 131cde29af9SShinas Rasheed u64 mtu:48; 132cde29af9SShinas Rasheed } s_get_mtu; 133cde29af9SShinas Rasheed struct { 134cde29af9SShinas Rasheed u64 opcode:8; 135cde29af9SShinas Rasheed u64 type:2; 136cde29af9SShinas Rasheed u64 state:1; 137cde29af9SShinas Rasheed u64 rsvd:53; 138cde29af9SShinas Rasheed } s_link_state; 139cde29af9SShinas Rasheed struct { 140cde29af9SShinas Rasheed u64 opcode:8; 141cde29af9SShinas Rasheed u64 type:2; 142cde29af9SShinas Rasheed u64 status:1; 143cde29af9SShinas Rasheed u64 rsvd:53; 144cde29af9SShinas Rasheed } s_link_status; 145e28db8cbSShinas Rasheed struct { 146e28db8cbSShinas Rasheed u64 opcode:8; 147e28db8cbSShinas Rasheed u64 type:2; 148e28db8cbSShinas Rasheed u64 pkind:8; 149e28db8cbSShinas Rasheed u64 fsz:8; 150e28db8cbSShinas Rasheed u64 rx_ol_flags:16; 151e28db8cbSShinas Rasheed u64 tx_ol_flags:16; 152e28db8cbSShinas Rasheed u64 rsvd:6; 153e28db8cbSShinas Rasheed } s_fw_info; 154e28db8cbSShinas Rasheed struct { 155e28db8cbSShinas Rasheed u64 opcode:8; 156e28db8cbSShinas Rasheed u64 type:2; 157e28db8cbSShinas Rasheed u64 rsvd:22; 158e28db8cbSShinas Rasheed u64 rx_ol_flags:16; 159e28db8cbSShinas Rasheed u64 tx_ol_flags:16; 160e28db8cbSShinas Rasheed } s_offloads; 161cde29af9SShinas Rasheed } __packed; 162cde29af9SShinas Rasheed 163cde29af9SShinas Rasheed void octep_pfvf_mbox_work(struct work_struct *work); 164cde29af9SShinas Rasheed int octep_setup_pfvf_mbox(struct octep_device *oct); 165cde29af9SShinas Rasheed void octep_delete_pfvf_mbox(struct octep_device *oct); 166*4ebb86a9SShinas Rasheed void octep_pfvf_notify(struct octep_device *oct, struct octep_ctrl_mbox_msg *msg); 167cde29af9SShinas Rasheed #endif 168