1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 106 int size, int size_rsp); 107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 108 struct mbox_msghdr *msg); 109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 111 u16 pcifunc, u16 id); 112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 113 const char *otx2_mbox_id2name(u16 id); 114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 115 int devid, int size) 116 { 117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 118 } 119 120 /* Mailbox message types */ 121 #define MBOX_MSG_MASK 0xFFFF 122 #define MBOX_MSG_INVALID 0xFFFE 123 #define MBOX_MSG_MAX 0xFFFF 124 125 #define MBOX_MESSAGES \ 126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 136 msg_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 160 cgx_mac_addr_add_rsp) \ 161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 162 msg_rsp) \ 163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 164 cgx_max_dmac_entries_get_rsp) \ 165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 167 cgx_set_link_mode_rsp) \ 168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 170 cgx_features_info_msg) \ 171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 173 msg_rsp) \ 174 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 175 cgx_mac_addr_update_rsp) \ 176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 177 cgx_pfc_rsp) \ 178 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 179 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 180 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 182 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 185 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 188 msg_rsp) \ 189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 191 cpt_rd_wr_reg_msg) \ 192 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 193 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 194 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 195 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 196 msg_rsp) \ 197 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 198 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 199 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 200 cpt_flt_eng_info_rsp) \ 201 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 202 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 203 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 204 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 205 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 206 npc_mcam_alloc_entry_rsp) \ 207 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 208 npc_mcam_free_entry_req, msg_rsp) \ 209 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 210 npc_mcam_write_entry_req, msg_rsp) \ 211 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 212 npc_mcam_ena_dis_entry_req, msg_rsp) \ 213 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 214 npc_mcam_ena_dis_entry_req, msg_rsp) \ 215 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 216 npc_mcam_shift_entry_rsp) \ 217 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 218 npc_mcam_alloc_counter_req, \ 219 npc_mcam_alloc_counter_rsp) \ 220 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 221 npc_mcam_oper_counter_req, msg_rsp) \ 222 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 223 npc_mcam_unmap_counter_req, msg_rsp) \ 224 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 225 npc_mcam_oper_counter_req, msg_rsp) \ 226 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 227 npc_mcam_oper_counter_req, \ 228 npc_mcam_oper_counter_rsp) \ 229 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 230 npc_mcam_alloc_and_write_entry_req, \ 231 npc_mcam_alloc_and_write_entry_rsp) \ 232 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 233 msg_req, npc_get_kex_cfg_rsp) \ 234 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 235 npc_install_flow_req, npc_install_flow_rsp) \ 236 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 237 npc_delete_flow_req, msg_rsp) \ 238 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 239 npc_mcam_read_entry_req, \ 240 npc_mcam_read_entry_rsp) \ 241 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 242 npc_set_pkind, msg_rsp) \ 243 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 244 msg_req, npc_mcam_read_base_rule_rsp) \ 245 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 246 npc_mcam_get_stats_req, \ 247 npc_mcam_get_stats_rsp) \ 248 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key, \ 249 npc_get_secret_key_req, \ 250 npc_get_secret_key_rsp) \ 251 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 252 npc_get_field_status_req, \ 253 npc_get_field_status_rsp) \ 254 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 255 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 256 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 257 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 258 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 259 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 260 hwctx_disable_req, msg_rsp) \ 261 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 262 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 263 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 264 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 265 nix_txschq_config) \ 266 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 267 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 268 nix_vtag_config_rsp) \ 269 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 270 nix_rss_flowkey_cfg, \ 271 nix_rss_flowkey_cfg_rsp) \ 272 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 273 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 274 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 275 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 276 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 277 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 278 nix_mark_format_cfg, \ 279 nix_mark_format_cfg_rsp) \ 280 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 281 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 282 nix_lso_format_cfg, \ 283 nix_lso_format_cfg_rsp) \ 284 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 285 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 286 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 287 nix_bp_cfg_rsp) \ 288 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 289 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 290 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 291 nix_inline_ipsec_cfg, msg_rsp) \ 292 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 293 nix_inline_ipsec_lf_cfg, msg_rsp) \ 294 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 295 nix_cn10k_aq_enq_rsp) \ 296 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 297 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 298 nix_bandprof_alloc_rsp) \ 299 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 300 msg_rsp) \ 301 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 302 nix_bandprof_get_hwinfo_rsp) \ 303 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 304 msg_req, nix_inline_ipsec_cfg) \ 305 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 306 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 307 mcs_alloc_rsrc_rsp) \ 308 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 309 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 310 msg_rsp) \ 311 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 312 msg_rsp) \ 313 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 314 msg_rsp) \ 315 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 316 msg_rsp) \ 317 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 318 msg_rsp) \ 319 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 320 msg_rsp) \ 321 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 322 msg_rsp) \ 323 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 324 msg_rsp) \ 325 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 326 msg_rsp) \ 327 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 328 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 329 mcs_flowid_stats) \ 330 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 331 mcs_secy_stats) \ 332 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 333 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 334 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 335 mcs_port_stats) \ 336 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 337 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 338 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 339 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 340 msg_rsp) \ 341 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 342 mcs_alloc_ctrl_pkt_rule_req, \ 343 mcs_alloc_ctrl_pkt_rule_rsp) \ 344 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 345 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 346 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 347 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 348 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 349 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 350 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 351 mcs_port_cfg_get_rsp) \ 352 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 353 mcs_custom_tag_cfg_get_req, \ 354 mcs_custom_tag_cfg_get_rsp) 355 356 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 357 #define MBOX_UP_CGX_MESSAGES \ 358 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 359 360 #define MBOX_UP_CPT_MESSAGES \ 361 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 362 363 #define MBOX_UP_MCS_MESSAGES \ 364 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 365 366 enum { 367 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 368 MBOX_MESSAGES 369 MBOX_UP_CGX_MESSAGES 370 MBOX_UP_CPT_MESSAGES 371 MBOX_UP_MCS_MESSAGES 372 #undef M 373 }; 374 375 /* Mailbox message formats */ 376 377 #define RVU_DEFAULT_PF_FUNC 0xFFFF 378 379 /* Generic request msg used for those mbox messages which 380 * don't send any data in the request. 381 */ 382 struct msg_req { 383 struct mbox_msghdr hdr; 384 }; 385 386 /* Generic response msg used an ack or response for those mbox 387 * messages which don't have a specific rsp msg format. 388 */ 389 struct msg_rsp { 390 struct mbox_msghdr hdr; 391 }; 392 393 /* RVU mailbox error codes 394 * Range 256 - 300. 395 */ 396 enum rvu_af_status { 397 RVU_INVALID_VF_ID = -256, 398 }; 399 400 struct ready_msg_rsp { 401 struct mbox_msghdr hdr; 402 u16 sclk_freq; /* SCLK frequency (in MHz) */ 403 u16 rclk_freq; /* RCLK frequency (in MHz) */ 404 }; 405 406 /* Structure for requesting resource provisioning. 407 * 'modify' flag to be used when either requesting more 408 * or to detach partial of a certain resource type. 409 * Rest of the fields specify how many of what type to 410 * be attached. 411 * To request LFs from two blocks of same type this mailbox 412 * can be sent twice as below: 413 * struct rsrc_attach *attach; 414 * .. Allocate memory for message .. 415 * attach->cptlfs = 3; <3 LFs from CPT0> 416 * .. Send message .. 417 * .. Allocate memory for message .. 418 * attach->modify = 1; 419 * attach->cpt_blkaddr = BLKADDR_CPT1; 420 * attach->cptlfs = 2; <2 LFs from CPT1> 421 * .. Send message .. 422 */ 423 struct rsrc_attach { 424 struct mbox_msghdr hdr; 425 u8 modify:1; 426 u8 npalf:1; 427 u8 nixlf:1; 428 u16 sso; 429 u16 ssow; 430 u16 timlfs; 431 u16 cptlfs; 432 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 433 }; 434 435 /* Structure for relinquishing resources. 436 * 'partial' flag to be used when relinquishing all resources 437 * but only of a certain type. If not set, all resources of all 438 * types provisioned to the RVU function will be detached. 439 */ 440 struct rsrc_detach { 441 struct mbox_msghdr hdr; 442 u8 partial:1; 443 u8 npalf:1; 444 u8 nixlf:1; 445 u8 sso:1; 446 u8 ssow:1; 447 u8 timlfs:1; 448 u8 cptlfs:1; 449 }; 450 451 /* Number of resources available to the caller. 452 * In reply to MBOX_MSG_FREE_RSRC_CNT. 453 */ 454 struct free_rsrcs_rsp { 455 struct mbox_msghdr hdr; 456 u16 schq[NIX_TXSCH_LVL_CNT]; 457 u16 sso; 458 u16 tim; 459 u16 ssow; 460 u16 cpt; 461 u8 npa; 462 u8 nix; 463 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 464 u8 nix1; 465 u8 cpt1; 466 u8 ree0; 467 u8 ree1; 468 }; 469 470 #define MSIX_VECTOR_INVALID 0xFFFF 471 #define MAX_RVU_BLKLF_CNT 256 472 473 struct msix_offset_rsp { 474 struct mbox_msghdr hdr; 475 u16 npa_msixoff; 476 u16 nix_msixoff; 477 u16 sso; 478 u16 ssow; 479 u16 timlfs; 480 u16 cptlfs; 481 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 482 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 483 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 484 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 485 u16 cpt1_lfs; 486 u16 ree0_lfs; 487 u16 ree1_lfs; 488 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 489 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 490 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 491 }; 492 493 struct get_hw_cap_rsp { 494 struct mbox_msghdr hdr; 495 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 496 u8 nix_shaping; /* Is shaping and coloring supported */ 497 u8 npc_hash_extract; /* Is hash extract supported */ 498 }; 499 500 /* CGX mbox message formats */ 501 502 struct cgx_stats_rsp { 503 struct mbox_msghdr hdr; 504 #define CGX_RX_STATS_COUNT 9 505 #define CGX_TX_STATS_COUNT 18 506 u64 rx_stats[CGX_RX_STATS_COUNT]; 507 u64 tx_stats[CGX_TX_STATS_COUNT]; 508 }; 509 510 struct cgx_fec_stats_rsp { 511 struct mbox_msghdr hdr; 512 u64 fec_corr_blks; 513 u64 fec_uncorr_blks; 514 }; 515 /* Structure for requesting the operation for 516 * setting/getting mac address in the CGX interface 517 */ 518 struct cgx_mac_addr_set_or_get { 519 struct mbox_msghdr hdr; 520 u8 mac_addr[ETH_ALEN]; 521 u32 index; 522 }; 523 524 /* Structure for requesting the operation to 525 * add DMAC filter entry into CGX interface 526 */ 527 struct cgx_mac_addr_add_req { 528 struct mbox_msghdr hdr; 529 u8 mac_addr[ETH_ALEN]; 530 }; 531 532 /* Structure for response against the operation to 533 * add DMAC filter entry into CGX interface 534 */ 535 struct cgx_mac_addr_add_rsp { 536 struct mbox_msghdr hdr; 537 u32 index; 538 }; 539 540 /* Structure for requesting the operation to 541 * delete DMAC filter entry from CGX interface 542 */ 543 struct cgx_mac_addr_del_req { 544 struct mbox_msghdr hdr; 545 u32 index; 546 }; 547 548 /* Structure for response against the operation to 549 * get maximum supported DMAC filter entries 550 */ 551 struct cgx_max_dmac_entries_get_rsp { 552 struct mbox_msghdr hdr; 553 u32 max_dmac_filters; 554 }; 555 556 struct cgx_link_user_info { 557 uint64_t link_up:1; 558 uint64_t full_duplex:1; 559 uint64_t lmac_type_id:4; 560 uint64_t speed:20; /* speed in Mbps */ 561 uint64_t an:1; /* AN supported or not */ 562 uint64_t fec:2; /* FEC type if enabled else 0 */ 563 #define LMACTYPE_STR_LEN 16 564 char lmac_type[LMACTYPE_STR_LEN]; 565 }; 566 567 struct cgx_link_info_msg { 568 struct mbox_msghdr hdr; 569 struct cgx_link_user_info link_info; 570 }; 571 572 struct cgx_pause_frm_cfg { 573 struct mbox_msghdr hdr; 574 u8 set; 575 /* set = 1 if the request is to config pause frames */ 576 /* set = 0 if the request is to fetch pause frames config */ 577 u8 rx_pause; 578 u8 tx_pause; 579 }; 580 581 enum fec_type { 582 OTX2_FEC_NONE, 583 OTX2_FEC_BASER, 584 OTX2_FEC_RS, 585 OTX2_FEC_STATS_CNT = 2, 586 OTX2_FEC_OFF, 587 }; 588 589 struct fec_mode { 590 struct mbox_msghdr hdr; 591 int fec; 592 }; 593 594 struct sfp_eeprom_s { 595 #define SFP_EEPROM_SIZE 256 596 u16 sff_id; 597 u8 buf[SFP_EEPROM_SIZE]; 598 u64 reserved; 599 }; 600 601 struct phy_s { 602 struct { 603 u64 can_change_mod_type:1; 604 u64 mod_type:1; 605 u64 has_fec_stats:1; 606 } misc; 607 struct fec_stats_s { 608 u32 rsfec_corr_cws; 609 u32 rsfec_uncorr_cws; 610 u32 brfec_corr_blks; 611 u32 brfec_uncorr_blks; 612 } fec_stats; 613 }; 614 615 struct cgx_lmac_fwdata_s { 616 u16 rw_valid; 617 u64 supported_fec; 618 u64 supported_an; 619 u64 supported_link_modes; 620 /* only applicable if AN is supported */ 621 u64 advertised_fec; 622 u64 advertised_link_modes; 623 /* Only applicable if SFP/QSFP slot is present */ 624 struct sfp_eeprom_s sfp_eeprom; 625 struct phy_s phy; 626 #define LMAC_FWDATA_RESERVED_MEM 1021 627 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 628 }; 629 630 struct cgx_fw_data { 631 struct mbox_msghdr hdr; 632 struct cgx_lmac_fwdata_s fwdata; 633 }; 634 635 struct cgx_set_link_mode_args { 636 u32 speed; 637 u8 duplex; 638 u8 an; 639 u8 ports; 640 u64 mode; 641 }; 642 643 struct cgx_set_link_mode_req { 644 #define AUTONEG_UNKNOWN 0xff 645 struct mbox_msghdr hdr; 646 struct cgx_set_link_mode_args args; 647 }; 648 649 struct cgx_set_link_mode_rsp { 650 struct mbox_msghdr hdr; 651 int status; 652 }; 653 654 struct cgx_mac_addr_reset_req { 655 struct mbox_msghdr hdr; 656 u32 index; 657 }; 658 659 struct cgx_mac_addr_update_req { 660 struct mbox_msghdr hdr; 661 u8 mac_addr[ETH_ALEN]; 662 u32 index; 663 }; 664 665 struct cgx_mac_addr_update_rsp { 666 struct mbox_msghdr hdr; 667 u32 index; 668 }; 669 670 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 671 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 672 /* flow control from physical link higig2 messages */ 673 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 674 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 675 #define RVU_MAC_VERSION BIT_ULL(4) 676 #define RVU_MAC_CGX BIT_ULL(5) 677 #define RVU_MAC_RPM BIT_ULL(6) 678 679 struct cgx_features_info_msg { 680 struct mbox_msghdr hdr; 681 u64 lmac_features; 682 }; 683 684 struct rpm_stats_rsp { 685 struct mbox_msghdr hdr; 686 #define RPM_RX_STATS_COUNT 43 687 #define RPM_TX_STATS_COUNT 34 688 u64 rx_stats[RPM_RX_STATS_COUNT]; 689 u64 tx_stats[RPM_TX_STATS_COUNT]; 690 }; 691 692 struct cgx_pfc_cfg { 693 struct mbox_msghdr hdr; 694 u8 rx_pause; 695 u8 tx_pause; 696 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 697 }; 698 699 struct cgx_pfc_rsp { 700 struct mbox_msghdr hdr; 701 u8 rx_pause; 702 u8 tx_pause; 703 }; 704 705 /* NPA mbox message formats */ 706 707 struct npc_set_pkind { 708 struct mbox_msghdr hdr; 709 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 710 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 711 u64 mode; 712 #define PKIND_TX BIT_ULL(0) 713 #define PKIND_RX BIT_ULL(1) 714 u8 dir; 715 u8 pkind; /* valid only in case custom flag */ 716 u8 var_len_off; /* Offset of custom header length field. 717 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 718 */ 719 u8 var_len_off_mask; /* Mask for length with in offset */ 720 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 721 }; 722 723 /* NPA mbox message formats */ 724 725 /* NPA mailbox error codes 726 * Range 301 - 400. 727 */ 728 enum npa_af_status { 729 NPA_AF_ERR_PARAM = -301, 730 NPA_AF_ERR_AQ_FULL = -302, 731 NPA_AF_ERR_AQ_ENQUEUE = -303, 732 NPA_AF_ERR_AF_LF_INVALID = -304, 733 NPA_AF_ERR_AF_LF_ALLOC = -305, 734 NPA_AF_ERR_LF_RESET = -306, 735 }; 736 737 /* For NPA LF context alloc and init */ 738 struct npa_lf_alloc_req { 739 struct mbox_msghdr hdr; 740 int node; 741 int aura_sz; /* No of auras */ 742 u32 nr_pools; /* No of pools */ 743 u64 way_mask; 744 }; 745 746 struct npa_lf_alloc_rsp { 747 struct mbox_msghdr hdr; 748 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 749 u32 stack_pg_bytes; /* Size of stack page */ 750 u16 qints; /* NPA_AF_CONST::QINTS */ 751 u8 cache_lines; /*BATCH ALLOC DMA */ 752 }; 753 754 /* NPA AQ enqueue msg */ 755 struct npa_aq_enq_req { 756 struct mbox_msghdr hdr; 757 u32 aura_id; 758 u8 ctype; 759 u8 op; 760 union { 761 /* Valid when op == WRITE/INIT and ctype == AURA. 762 * LF fills the pool_id in aura.pool_addr. AF will translate 763 * the pool_id to pool context pointer. 764 */ 765 struct npa_aura_s aura; 766 /* Valid when op == WRITE/INIT and ctype == POOL */ 767 struct npa_pool_s pool; 768 }; 769 /* Mask data when op == WRITE (1=write, 0=don't write) */ 770 union { 771 /* Valid when op == WRITE and ctype == AURA */ 772 struct npa_aura_s aura_mask; 773 /* Valid when op == WRITE and ctype == POOL */ 774 struct npa_pool_s pool_mask; 775 }; 776 }; 777 778 struct npa_aq_enq_rsp { 779 struct mbox_msghdr hdr; 780 union { 781 /* Valid when op == READ and ctype == AURA */ 782 struct npa_aura_s aura; 783 /* Valid when op == READ and ctype == POOL */ 784 struct npa_pool_s pool; 785 }; 786 }; 787 788 /* Disable all contexts of type 'ctype' */ 789 struct hwctx_disable_req { 790 struct mbox_msghdr hdr; 791 u8 ctype; 792 }; 793 794 /* NIX mbox message formats */ 795 796 /* NIX mailbox error codes 797 * Range 401 - 500. 798 */ 799 enum nix_af_status { 800 NIX_AF_ERR_PARAM = -401, 801 NIX_AF_ERR_AQ_FULL = -402, 802 NIX_AF_ERR_AQ_ENQUEUE = -403, 803 NIX_AF_ERR_AF_LF_INVALID = -404, 804 NIX_AF_ERR_AF_LF_ALLOC = -405, 805 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 806 NIX_AF_ERR_TLX_INVALID = -407, 807 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 808 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 809 NIX_AF_ERR_FRS_INVALID = -410, 810 NIX_AF_ERR_RX_LINK_INVALID = -411, 811 NIX_AF_INVAL_TXSCHQ_CFG = -412, 812 NIX_AF_SMQ_FLUSH_FAILED = -413, 813 NIX_AF_ERR_LF_RESET = -414, 814 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 815 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 816 NIX_AF_ERR_MARK_CFG_FAIL = -417, 817 NIX_AF_ERR_LSO_CFG_FAIL = -418, 818 NIX_AF_INVAL_NPA_PF_FUNC = -419, 819 NIX_AF_INVAL_SSO_PF_FUNC = -420, 820 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 821 NIX_AF_ERR_RX_VTAG_INUSE = -422, 822 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 823 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 824 NIX_AF_ERR_INVALID_NIXBLK = -425, 825 NIX_AF_ERR_INVALID_BANDPROF = -426, 826 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 827 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 828 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 829 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 830 NIX_AF_ERR_LINK_CREDITS = -431, 831 }; 832 833 /* For NIX RX vtag action */ 834 enum nix_rx_vtag0_type { 835 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 836 NIX_AF_LFX_RX_VTAG_TYPE1, 837 NIX_AF_LFX_RX_VTAG_TYPE2, 838 NIX_AF_LFX_RX_VTAG_TYPE3, 839 NIX_AF_LFX_RX_VTAG_TYPE4, 840 NIX_AF_LFX_RX_VTAG_TYPE5, 841 NIX_AF_LFX_RX_VTAG_TYPE6, 842 NIX_AF_LFX_RX_VTAG_TYPE7, 843 }; 844 845 /* For NIX LF context alloc and init */ 846 struct nix_lf_alloc_req { 847 struct mbox_msghdr hdr; 848 int node; 849 u32 rq_cnt; /* No of receive queues */ 850 u32 sq_cnt; /* No of send queues */ 851 u32 cq_cnt; /* No of completion queues */ 852 u8 xqe_sz; 853 u16 rss_sz; 854 u8 rss_grps; 855 u16 npa_func; 856 u16 sso_func; 857 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 858 u64 way_mask; 859 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 860 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 861 u64 flags; 862 }; 863 864 struct nix_lf_alloc_rsp { 865 struct mbox_msghdr hdr; 866 u16 sqb_size; 867 u16 rx_chan_base; 868 u16 tx_chan_base; 869 u8 rx_chan_cnt; /* total number of RX channels */ 870 u8 tx_chan_cnt; /* total number of TX channels */ 871 u8 lso_tsov4_idx; 872 u8 lso_tsov6_idx; 873 u8 mac_addr[ETH_ALEN]; 874 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 875 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 876 u16 cints; /* NIX_AF_CONST2::CINTS */ 877 u16 qints; /* NIX_AF_CONST2::QINTS */ 878 u8 cgx_links; /* No. of CGX links present in HW */ 879 u8 lbk_links; /* No. of LBK links present in HW */ 880 u8 sdp_links; /* No. of SDP links present in HW */ 881 u8 tx_link; /* Transmit channel link number */ 882 }; 883 884 struct nix_lf_free_req { 885 struct mbox_msghdr hdr; 886 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 887 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 888 u64 flags; 889 }; 890 891 /* CN10K NIX AQ enqueue msg */ 892 struct nix_cn10k_aq_enq_req { 893 struct mbox_msghdr hdr; 894 u32 qidx; 895 u8 ctype; 896 u8 op; 897 union { 898 struct nix_cn10k_rq_ctx_s rq; 899 struct nix_cn10k_sq_ctx_s sq; 900 struct nix_cq_ctx_s cq; 901 struct nix_rsse_s rss; 902 struct nix_rx_mce_s mce; 903 struct nix_bandprof_s prof; 904 }; 905 union { 906 struct nix_cn10k_rq_ctx_s rq_mask; 907 struct nix_cn10k_sq_ctx_s sq_mask; 908 struct nix_cq_ctx_s cq_mask; 909 struct nix_rsse_s rss_mask; 910 struct nix_rx_mce_s mce_mask; 911 struct nix_bandprof_s prof_mask; 912 }; 913 }; 914 915 struct nix_cn10k_aq_enq_rsp { 916 struct mbox_msghdr hdr; 917 union { 918 struct nix_cn10k_rq_ctx_s rq; 919 struct nix_cn10k_sq_ctx_s sq; 920 struct nix_cq_ctx_s cq; 921 struct nix_rsse_s rss; 922 struct nix_rx_mce_s mce; 923 struct nix_bandprof_s prof; 924 }; 925 }; 926 927 /* NIX AQ enqueue msg */ 928 struct nix_aq_enq_req { 929 struct mbox_msghdr hdr; 930 u32 qidx; 931 u8 ctype; 932 u8 op; 933 union { 934 struct nix_rq_ctx_s rq; 935 struct nix_sq_ctx_s sq; 936 struct nix_cq_ctx_s cq; 937 struct nix_rsse_s rss; 938 struct nix_rx_mce_s mce; 939 u64 prof; 940 }; 941 union { 942 struct nix_rq_ctx_s rq_mask; 943 struct nix_sq_ctx_s sq_mask; 944 struct nix_cq_ctx_s cq_mask; 945 struct nix_rsse_s rss_mask; 946 struct nix_rx_mce_s mce_mask; 947 u64 prof_mask; 948 }; 949 }; 950 951 struct nix_aq_enq_rsp { 952 struct mbox_msghdr hdr; 953 union { 954 struct nix_rq_ctx_s rq; 955 struct nix_sq_ctx_s sq; 956 struct nix_cq_ctx_s cq; 957 struct nix_rsse_s rss; 958 struct nix_rx_mce_s mce; 959 struct nix_bandprof_s prof; 960 }; 961 }; 962 963 /* Tx scheduler/shaper mailbox messages */ 964 965 #define MAX_TXSCHQ_PER_FUNC 128 966 967 struct nix_txsch_alloc_req { 968 struct mbox_msghdr hdr; 969 /* Scheduler queue count request at each level */ 970 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 971 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 972 }; 973 974 struct nix_txsch_alloc_rsp { 975 struct mbox_msghdr hdr; 976 /* Scheduler queue count allocated at each level */ 977 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 978 u16 schq[NIX_TXSCH_LVL_CNT]; 979 /* Scheduler queue list allocated at each level */ 980 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 981 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 982 u8 aggr_level; /* Traffic aggregation scheduler level */ 983 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 984 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 985 }; 986 987 struct nix_txsch_free_req { 988 struct mbox_msghdr hdr; 989 #define TXSCHQ_FREE_ALL BIT_ULL(0) 990 u16 flags; 991 /* Scheduler queue level to be freed */ 992 u16 schq_lvl; 993 /* List of scheduler queues to be freed */ 994 u16 schq; 995 }; 996 997 struct nix_txschq_config { 998 struct mbox_msghdr hdr; 999 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1000 u8 read; 1001 #define TXSCHQ_IDX_SHIFT 16 1002 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1003 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1004 u8 num_regs; 1005 #define MAX_REGS_PER_MBOX_MSG 20 1006 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1007 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1008 /* All 0's => overwrite with new value */ 1009 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1010 }; 1011 1012 struct nix_vtag_config { 1013 struct mbox_msghdr hdr; 1014 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1015 u8 vtag_size; 1016 /* cfg_type is '0' for tx vlan cfg 1017 * cfg_type is '1' for rx vlan cfg 1018 */ 1019 u8 cfg_type; 1020 union { 1021 /* valid when cfg_type is '0' */ 1022 struct { 1023 u64 vtag0; 1024 u64 vtag1; 1025 1026 /* cfg_vtag0 & cfg_vtag1 fields are valid 1027 * when free_vtag0 & free_vtag1 are '0's. 1028 */ 1029 /* cfg_vtag0 = 1 to configure vtag0 */ 1030 u8 cfg_vtag0 :1; 1031 /* cfg_vtag1 = 1 to configure vtag1 */ 1032 u8 cfg_vtag1 :1; 1033 1034 /* vtag0_idx & vtag1_idx are only valid when 1035 * both cfg_vtag0 & cfg_vtag1 are '0's, 1036 * these fields are used along with free_vtag0 1037 * & free_vtag1 to free the nix lf's tx_vlan 1038 * configuration. 1039 * 1040 * Denotes the indices of tx_vtag def registers 1041 * that needs to be cleared and freed. 1042 */ 1043 int vtag0_idx; 1044 int vtag1_idx; 1045 1046 /* free_vtag0 & free_vtag1 fields are valid 1047 * when cfg_vtag0 & cfg_vtag1 are '0's. 1048 */ 1049 /* free_vtag0 = 1 clears vtag0 configuration 1050 * vtag0_idx denotes the index to be cleared. 1051 */ 1052 u8 free_vtag0 :1; 1053 /* free_vtag1 = 1 clears vtag1 configuration 1054 * vtag1_idx denotes the index to be cleared. 1055 */ 1056 u8 free_vtag1 :1; 1057 } tx; 1058 1059 /* valid when cfg_type is '1' */ 1060 struct { 1061 /* rx vtag type index, valid values are in 0..7 range */ 1062 u8 vtag_type; 1063 /* rx vtag strip */ 1064 u8 strip_vtag :1; 1065 /* rx vtag capture */ 1066 u8 capture_vtag :1; 1067 } rx; 1068 }; 1069 }; 1070 1071 struct nix_vtag_config_rsp { 1072 struct mbox_msghdr hdr; 1073 int vtag0_idx; 1074 int vtag1_idx; 1075 /* Indices of tx_vtag def registers used to configure 1076 * tx vtag0 & vtag1 headers, these indices are valid 1077 * when nix_vtag_config mbox requested for vtag0 and/ 1078 * or vtag1 configuration. 1079 */ 1080 }; 1081 1082 struct nix_rss_flowkey_cfg { 1083 struct mbox_msghdr hdr; 1084 int mcam_index; /* MCAM entry index to modify */ 1085 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1086 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1087 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1088 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1089 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1090 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1091 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1092 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1093 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1094 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1095 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1096 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1097 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1098 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1099 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1100 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1101 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1102 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1103 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1104 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1105 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1106 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1107 u32 flowkey_cfg; /* Flowkey types selected */ 1108 u8 group; /* RSS context or group */ 1109 }; 1110 1111 struct nix_rss_flowkey_cfg_rsp { 1112 struct mbox_msghdr hdr; 1113 u8 alg_idx; /* Selected algo index */ 1114 }; 1115 1116 struct nix_set_mac_addr { 1117 struct mbox_msghdr hdr; 1118 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1119 }; 1120 1121 struct nix_get_mac_addr_rsp { 1122 struct mbox_msghdr hdr; 1123 u8 mac_addr[ETH_ALEN]; 1124 }; 1125 1126 struct nix_mark_format_cfg { 1127 struct mbox_msghdr hdr; 1128 u8 offset; 1129 u8 y_mask; 1130 u8 y_val; 1131 u8 r_mask; 1132 u8 r_val; 1133 }; 1134 1135 struct nix_mark_format_cfg_rsp { 1136 struct mbox_msghdr hdr; 1137 u8 mark_format_idx; 1138 }; 1139 1140 struct nix_rx_mode { 1141 struct mbox_msghdr hdr; 1142 #define NIX_RX_MODE_UCAST BIT(0) 1143 #define NIX_RX_MODE_PROMISC BIT(1) 1144 #define NIX_RX_MODE_ALLMULTI BIT(2) 1145 #define NIX_RX_MODE_USE_MCE BIT(3) 1146 u16 mode; 1147 }; 1148 1149 struct nix_rx_cfg { 1150 struct mbox_msghdr hdr; 1151 #define NIX_RX_OL3_VERIFY BIT(0) 1152 #define NIX_RX_OL4_VERIFY BIT(1) 1153 u8 len_verify; /* Outer L3/L4 len check */ 1154 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1155 u8 csum_verify; /* Outer L4 checksum verification */ 1156 }; 1157 1158 struct nix_frs_cfg { 1159 struct mbox_msghdr hdr; 1160 u8 update_smq; /* Update SMQ's min/max lens */ 1161 u8 update_minlen; /* Set minlen also */ 1162 u8 sdp_link; /* Set SDP RX link */ 1163 u16 maxlen; 1164 u16 minlen; 1165 }; 1166 1167 struct nix_lso_format_cfg { 1168 struct mbox_msghdr hdr; 1169 u64 field_mask; 1170 #define NIX_LSO_FIELD_MAX 8 1171 u64 fields[NIX_LSO_FIELD_MAX]; 1172 }; 1173 1174 struct nix_lso_format_cfg_rsp { 1175 struct mbox_msghdr hdr; 1176 u8 lso_format_idx; 1177 }; 1178 1179 struct nix_bp_cfg_req { 1180 struct mbox_msghdr hdr; 1181 u16 chan_base; /* Starting channel number */ 1182 u8 chan_cnt; /* Number of channels */ 1183 u8 bpid_per_chan; 1184 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1185 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1186 }; 1187 1188 /* PF can be mapped to either CGX or LBK interface, 1189 * so maximum 64 channels are possible. 1190 */ 1191 #define NIX_MAX_BPID_CHAN 64 1192 struct nix_bp_cfg_rsp { 1193 struct mbox_msghdr hdr; 1194 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1195 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1196 }; 1197 1198 /* Global NIX inline IPSec configuration */ 1199 struct nix_inline_ipsec_cfg { 1200 struct mbox_msghdr hdr; 1201 u32 cpt_credit; 1202 struct { 1203 u8 egrp; 1204 u16 opcode; 1205 u16 param1; 1206 u16 param2; 1207 } gen_cfg; 1208 struct { 1209 u16 cpt_pf_func; 1210 u8 cpt_slot; 1211 } inst_qsel; 1212 u8 enable; 1213 u16 bpid; 1214 u32 credit_th; 1215 }; 1216 1217 /* Per NIX LF inline IPSec configuration */ 1218 struct nix_inline_ipsec_lf_cfg { 1219 struct mbox_msghdr hdr; 1220 u64 sa_base_addr; 1221 struct { 1222 u32 tag_const; 1223 u16 lenm1_max; 1224 u8 sa_pow2_size; 1225 u8 tt; 1226 } ipsec_cfg0; 1227 struct { 1228 u32 sa_idx_max; 1229 u8 sa_idx_w; 1230 } ipsec_cfg1; 1231 u8 enable; 1232 }; 1233 1234 struct nix_hw_info { 1235 struct mbox_msghdr hdr; 1236 u16 rsvs16; 1237 u16 max_mtu; 1238 u16 min_mtu; 1239 u32 rpm_dwrr_mtu; 1240 u32 sdp_dwrr_mtu; 1241 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1242 }; 1243 1244 struct nix_bandprof_alloc_req { 1245 struct mbox_msghdr hdr; 1246 /* Count of profiles needed per layer */ 1247 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1248 }; 1249 1250 struct nix_bandprof_alloc_rsp { 1251 struct mbox_msghdr hdr; 1252 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1253 1254 /* There is no need to allocate morethan 1 bandwidth profile 1255 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1256 * profiles to 64 per PF_FUNC. 1257 */ 1258 #define MAX_BANDPROF_PER_PFFUNC 64 1259 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1260 }; 1261 1262 struct nix_bandprof_free_req { 1263 struct mbox_msghdr hdr; 1264 u8 free_all; 1265 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1266 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1267 }; 1268 1269 struct nix_bandprof_get_hwinfo_rsp { 1270 struct mbox_msghdr hdr; 1271 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1272 u32 policer_timeunit; 1273 }; 1274 1275 /* NPC mbox message structs */ 1276 1277 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1278 #define NPC_MCAM_INVALID_MAP 0xFFFF 1279 1280 /* NPC mailbox error codes 1281 * Range 701 - 800. 1282 */ 1283 enum npc_af_status { 1284 NPC_MCAM_INVALID_REQ = -701, 1285 NPC_MCAM_ALLOC_DENIED = -702, 1286 NPC_MCAM_ALLOC_FAILED = -703, 1287 NPC_MCAM_PERM_DENIED = -704, 1288 NPC_FLOW_INTF_INVALID = -707, 1289 NPC_FLOW_CHAN_INVALID = -708, 1290 NPC_FLOW_NO_NIXLF = -709, 1291 NPC_FLOW_NOT_SUPPORTED = -710, 1292 NPC_FLOW_VF_PERM_DENIED = -711, 1293 NPC_FLOW_VF_NOT_INIT = -712, 1294 NPC_FLOW_VF_OVERLAP = -713, 1295 }; 1296 1297 struct npc_mcam_alloc_entry_req { 1298 struct mbox_msghdr hdr; 1299 #define NPC_MAX_NONCONTIG_ENTRIES 256 1300 u8 contig; /* Contiguous entries ? */ 1301 #define NPC_MCAM_ANY_PRIO 0 1302 #define NPC_MCAM_LOWER_PRIO 1 1303 #define NPC_MCAM_HIGHER_PRIO 2 1304 u8 priority; /* Lower or higher w.r.t ref_entry */ 1305 u16 ref_entry; 1306 u16 count; /* Number of entries requested */ 1307 }; 1308 1309 struct npc_mcam_alloc_entry_rsp { 1310 struct mbox_msghdr hdr; 1311 u16 entry; /* Entry allocated or start index if contiguous. 1312 * Invalid incase of non-contiguous. 1313 */ 1314 u16 count; /* Number of entries allocated */ 1315 u16 free_count; /* Number of entries available */ 1316 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1317 }; 1318 1319 struct npc_mcam_free_entry_req { 1320 struct mbox_msghdr hdr; 1321 u16 entry; /* Entry index to be freed */ 1322 u8 all; /* If all entries allocated to this PFVF to be freed */ 1323 }; 1324 1325 struct mcam_entry { 1326 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1327 u64 kw[NPC_MAX_KWS_IN_KEY]; 1328 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1329 u64 action; 1330 u64 vtag_action; 1331 }; 1332 1333 struct npc_mcam_write_entry_req { 1334 struct mbox_msghdr hdr; 1335 struct mcam_entry entry_data; 1336 u16 entry; /* MCAM entry to write this match key */ 1337 u16 cntr; /* Counter for this MCAM entry */ 1338 u8 intf; /* Rx or Tx interface */ 1339 u8 enable_entry;/* Enable this MCAM entry ? */ 1340 u8 set_cntr; /* Set counter for this entry ? */ 1341 }; 1342 1343 /* Enable/Disable a given entry */ 1344 struct npc_mcam_ena_dis_entry_req { 1345 struct mbox_msghdr hdr; 1346 u16 entry; 1347 }; 1348 1349 struct npc_mcam_shift_entry_req { 1350 struct mbox_msghdr hdr; 1351 #define NPC_MCAM_MAX_SHIFTS 64 1352 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1353 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1354 u16 shift_count; /* Number of entries to shift */ 1355 }; 1356 1357 struct npc_mcam_shift_entry_rsp { 1358 struct mbox_msghdr hdr; 1359 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1360 }; 1361 1362 struct npc_mcam_alloc_counter_req { 1363 struct mbox_msghdr hdr; 1364 u8 contig; /* Contiguous counters ? */ 1365 #define NPC_MAX_NONCONTIG_COUNTERS 64 1366 u16 count; /* Number of counters requested */ 1367 }; 1368 1369 struct npc_mcam_alloc_counter_rsp { 1370 struct mbox_msghdr hdr; 1371 u16 cntr; /* Counter allocated or start index if contiguous. 1372 * Invalid incase of non-contiguous. 1373 */ 1374 u16 count; /* Number of counters allocated */ 1375 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1376 }; 1377 1378 struct npc_mcam_oper_counter_req { 1379 struct mbox_msghdr hdr; 1380 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1381 }; 1382 1383 struct npc_mcam_oper_counter_rsp { 1384 struct mbox_msghdr hdr; 1385 u64 stat; /* valid only while fetching counter's stats */ 1386 }; 1387 1388 struct npc_mcam_unmap_counter_req { 1389 struct mbox_msghdr hdr; 1390 u16 cntr; 1391 u16 entry; /* Entry and counter to be unmapped */ 1392 u8 all; /* Unmap all entries using this counter ? */ 1393 }; 1394 1395 struct npc_mcam_alloc_and_write_entry_req { 1396 struct mbox_msghdr hdr; 1397 struct mcam_entry entry_data; 1398 u16 ref_entry; 1399 u8 priority; /* Lower or higher w.r.t ref_entry */ 1400 u8 intf; /* Rx or Tx interface */ 1401 u8 enable_entry;/* Enable this MCAM entry ? */ 1402 u8 alloc_cntr; /* Allocate counter and map ? */ 1403 }; 1404 1405 struct npc_mcam_alloc_and_write_entry_rsp { 1406 struct mbox_msghdr hdr; 1407 u16 entry; 1408 u16 cntr; 1409 }; 1410 1411 struct npc_get_kex_cfg_rsp { 1412 struct mbox_msghdr hdr; 1413 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1414 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1415 #define NPC_MAX_INTF 2 1416 #define NPC_MAX_LID 8 1417 #define NPC_MAX_LT 16 1418 #define NPC_MAX_LD 2 1419 #define NPC_MAX_LFL 16 1420 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1421 u64 kex_ld_flags[NPC_MAX_LD]; 1422 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1423 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1424 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1425 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1426 #define MKEX_NAME_LEN 128 1427 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1428 }; 1429 1430 struct flow_msg { 1431 unsigned char dmac[6]; 1432 unsigned char smac[6]; 1433 __be16 etype; 1434 __be16 vlan_etype; 1435 __be16 vlan_tci; 1436 union { 1437 __be32 ip4src; 1438 __be32 ip6src[4]; 1439 }; 1440 union { 1441 __be32 ip4dst; 1442 __be32 ip6dst[4]; 1443 }; 1444 u8 tos; 1445 u8 ip_ver; 1446 u8 ip_proto; 1447 u8 tc; 1448 __be16 sport; 1449 __be16 dport; 1450 union { 1451 u8 ip_flag; 1452 u8 next_header; 1453 }; 1454 }; 1455 1456 struct npc_install_flow_req { 1457 struct mbox_msghdr hdr; 1458 struct flow_msg packet; 1459 struct flow_msg mask; 1460 u64 features; 1461 u16 entry; 1462 u16 channel; 1463 u16 chan_mask; 1464 u8 intf; 1465 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1466 u8 default_rule; 1467 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1468 u16 vf; 1469 /* action */ 1470 u32 index; 1471 u16 match_id; 1472 u8 flow_key_alg; 1473 u8 op; 1474 /* vtag rx action */ 1475 u8 vtag0_type; 1476 u8 vtag0_valid; 1477 u8 vtag1_type; 1478 u8 vtag1_valid; 1479 /* vtag tx action */ 1480 u16 vtag0_def; 1481 u8 vtag0_op; 1482 u16 vtag1_def; 1483 u8 vtag1_op; 1484 }; 1485 1486 struct npc_install_flow_rsp { 1487 struct mbox_msghdr hdr; 1488 int counter; /* negative if no counter else counter number */ 1489 }; 1490 1491 struct npc_delete_flow_req { 1492 struct mbox_msghdr hdr; 1493 u16 entry; 1494 u16 start;/*Disable range of entries */ 1495 u16 end; 1496 u8 all; /* PF + VFs */ 1497 }; 1498 1499 struct npc_mcam_read_entry_req { 1500 struct mbox_msghdr hdr; 1501 u16 entry; /* MCAM entry to read */ 1502 }; 1503 1504 struct npc_mcam_read_entry_rsp { 1505 struct mbox_msghdr hdr; 1506 struct mcam_entry entry_data; 1507 u8 intf; 1508 u8 enable; 1509 }; 1510 1511 struct npc_mcam_read_base_rule_rsp { 1512 struct mbox_msghdr hdr; 1513 struct mcam_entry entry; 1514 }; 1515 1516 struct npc_mcam_get_stats_req { 1517 struct mbox_msghdr hdr; 1518 u16 entry; /* mcam entry */ 1519 }; 1520 1521 struct npc_mcam_get_stats_rsp { 1522 struct mbox_msghdr hdr; 1523 u64 stat; /* counter stats */ 1524 u8 stat_ena; /* enabled */ 1525 }; 1526 1527 struct npc_get_secret_key_req { 1528 struct mbox_msghdr hdr; 1529 u8 intf; 1530 }; 1531 1532 struct npc_get_secret_key_rsp { 1533 struct mbox_msghdr hdr; 1534 u64 secret_key[3]; 1535 }; 1536 1537 enum ptp_op { 1538 PTP_OP_ADJFINE = 0, 1539 PTP_OP_GET_CLOCK = 1, 1540 PTP_OP_GET_TSTMP = 2, 1541 PTP_OP_SET_THRESH = 3, 1542 PTP_OP_EXTTS_ON = 4, 1543 }; 1544 1545 struct ptp_req { 1546 struct mbox_msghdr hdr; 1547 u8 op; 1548 s64 scaled_ppm; 1549 u64 thresh; 1550 int extts_on; 1551 }; 1552 1553 struct ptp_rsp { 1554 struct mbox_msghdr hdr; 1555 u64 clk; 1556 }; 1557 1558 struct npc_get_field_status_req { 1559 struct mbox_msghdr hdr; 1560 u8 intf; 1561 u8 field; 1562 }; 1563 1564 struct npc_get_field_status_rsp { 1565 struct mbox_msghdr hdr; 1566 u8 enable; 1567 }; 1568 1569 struct set_vf_perm { 1570 struct mbox_msghdr hdr; 1571 u16 vf; 1572 #define RESET_VF_PERM BIT_ULL(0) 1573 #define VF_TRUSTED BIT_ULL(1) 1574 u64 flags; 1575 }; 1576 1577 struct lmtst_tbl_setup_req { 1578 struct mbox_msghdr hdr; 1579 u64 dis_sched_early_comp :1; 1580 u64 sch_ena :1; 1581 u64 dis_line_pref :1; 1582 u64 ssow_pf_func :13; 1583 u16 base_pcifunc; 1584 u8 use_local_lmt_region; 1585 u64 lmt_iova; 1586 u64 rsvd[4]; 1587 }; 1588 1589 /* CPT mailbox error codes 1590 * Range 901 - 1000. 1591 */ 1592 enum cpt_af_status { 1593 CPT_AF_ERR_PARAM = -901, 1594 CPT_AF_ERR_GRP_INVALID = -902, 1595 CPT_AF_ERR_LF_INVALID = -903, 1596 CPT_AF_ERR_ACCESS_DENIED = -904, 1597 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1598 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1599 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1600 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1601 }; 1602 1603 /* CPT mbox message formats */ 1604 struct cpt_rd_wr_reg_msg { 1605 struct mbox_msghdr hdr; 1606 u64 reg_offset; 1607 u64 *ret_val; 1608 u64 val; 1609 u8 is_write; 1610 int blkaddr; 1611 }; 1612 1613 struct cpt_lf_alloc_req_msg { 1614 struct mbox_msghdr hdr; 1615 u16 nix_pf_func; 1616 u16 sso_pf_func; 1617 u16 eng_grpmsk; 1618 int blkaddr; 1619 u8 ctx_ilen_valid : 1; 1620 u8 ctx_ilen : 7; 1621 }; 1622 1623 #define CPT_INLINE_INBOUND 0 1624 #define CPT_INLINE_OUTBOUND 1 1625 1626 /* Mailbox message request format for CPT IPsec 1627 * inline inbound and outbound configuration. 1628 */ 1629 struct cpt_inline_ipsec_cfg_msg { 1630 struct mbox_msghdr hdr; 1631 u8 enable; 1632 u8 slot; 1633 u8 dir; 1634 u8 sso_pf_func_ovrd; 1635 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1636 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1637 }; 1638 1639 /* Mailbox message request and response format for CPT stats. */ 1640 struct cpt_sts_req { 1641 struct mbox_msghdr hdr; 1642 u8 blkaddr; 1643 }; 1644 1645 struct cpt_sts_rsp { 1646 struct mbox_msghdr hdr; 1647 u64 inst_req_pc; 1648 u64 inst_lat_pc; 1649 u64 rd_req_pc; 1650 u64 rd_lat_pc; 1651 u64 rd_uc_pc; 1652 u64 active_cycles_pc; 1653 u64 ctx_mis_pc; 1654 u64 ctx_hit_pc; 1655 u64 ctx_aop_pc; 1656 u64 ctx_aop_lat_pc; 1657 u64 ctx_ifetch_pc; 1658 u64 ctx_ifetch_lat_pc; 1659 u64 ctx_ffetch_pc; 1660 u64 ctx_ffetch_lat_pc; 1661 u64 ctx_wback_pc; 1662 u64 ctx_wback_lat_pc; 1663 u64 ctx_psh_pc; 1664 u64 ctx_psh_lat_pc; 1665 u64 ctx_err; 1666 u64 ctx_enc_id; 1667 u64 ctx_flush_timer; 1668 u64 rxc_time; 1669 u64 rxc_time_cfg; 1670 u64 rxc_active_sts; 1671 u64 rxc_zombie_sts; 1672 u64 busy_sts_ae; 1673 u64 free_sts_ae; 1674 u64 busy_sts_se; 1675 u64 free_sts_se; 1676 u64 busy_sts_ie; 1677 u64 free_sts_ie; 1678 u64 exe_err_info; 1679 u64 cptclk_cnt; 1680 u64 diag; 1681 u64 rxc_dfrg; 1682 u64 x2p_link_cfg0; 1683 u64 x2p_link_cfg1; 1684 }; 1685 1686 /* Mailbox message request format to configure reassembly timeout. */ 1687 struct cpt_rxc_time_cfg_req { 1688 struct mbox_msghdr hdr; 1689 int blkaddr; 1690 u32 step; 1691 u16 zombie_thres; 1692 u16 zombie_limit; 1693 u16 active_thres; 1694 u16 active_limit; 1695 }; 1696 1697 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1698 struct cpt_inst_lmtst_req { 1699 struct mbox_msghdr hdr; 1700 u64 inst[8]; 1701 u64 rsvd; 1702 }; 1703 1704 /* Mailbox message format to request for CPT LF reset */ 1705 struct cpt_lf_rst_req { 1706 struct mbox_msghdr hdr; 1707 u32 slot; 1708 u32 rsvd; 1709 }; 1710 1711 /* Mailbox message format to request for CPT faulted engines */ 1712 struct cpt_flt_eng_info_req { 1713 struct mbox_msghdr hdr; 1714 int blkaddr; 1715 bool reset; 1716 u32 rsvd; 1717 }; 1718 1719 struct cpt_flt_eng_info_rsp { 1720 struct mbox_msghdr hdr; 1721 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1722 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1723 u64 rsvd; 1724 }; 1725 1726 struct sdp_node_info { 1727 /* Node to which this PF belons to */ 1728 u8 node_id; 1729 u8 max_vfs; 1730 u8 num_pf_rings; 1731 u8 pf_srn; 1732 #define SDP_MAX_VFS 128 1733 u8 vf_rings[SDP_MAX_VFS]; 1734 }; 1735 1736 struct sdp_chan_info_msg { 1737 struct mbox_msghdr hdr; 1738 struct sdp_node_info info; 1739 }; 1740 1741 struct sdp_get_chan_info_msg { 1742 struct mbox_msghdr hdr; 1743 u16 chan_base; 1744 u16 num_chan; 1745 }; 1746 1747 /* CGX mailbox error codes 1748 * Range 1101 - 1200. 1749 */ 1750 enum cgx_af_status { 1751 LMAC_AF_ERR_INVALID_PARAM = -1101, 1752 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1753 LMAC_AF_ERR_PERM_DENIED = -1103, 1754 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1755 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1756 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1757 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1758 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1759 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1760 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1761 }; 1762 1763 enum mcs_direction { 1764 MCS_RX, 1765 MCS_TX, 1766 }; 1767 1768 enum mcs_rsrc_type { 1769 MCS_RSRC_TYPE_FLOWID, 1770 MCS_RSRC_TYPE_SECY, 1771 MCS_RSRC_TYPE_SC, 1772 MCS_RSRC_TYPE_SA, 1773 }; 1774 1775 struct mcs_alloc_rsrc_req { 1776 struct mbox_msghdr hdr; 1777 u8 rsrc_type; 1778 u8 rsrc_cnt; /* Resources count */ 1779 u8 mcs_id; /* MCS block ID */ 1780 u8 dir; /* Macsec ingress or egress side */ 1781 u8 all; /* Allocate all resource type one each */ 1782 u64 rsvd; 1783 }; 1784 1785 struct mcs_alloc_rsrc_rsp { 1786 struct mbox_msghdr hdr; 1787 u8 flow_ids[128]; /* Index of reserved entries */ 1788 u8 secy_ids[128]; 1789 u8 sc_ids[128]; 1790 u8 sa_ids[256]; 1791 u8 rsrc_type; 1792 u8 rsrc_cnt; /* No of entries reserved */ 1793 u8 mcs_id; 1794 u8 dir; 1795 u8 all; 1796 u8 rsvd[256]; /* reserved fields for future expansion */ 1797 }; 1798 1799 struct mcs_free_rsrc_req { 1800 struct mbox_msghdr hdr; 1801 u8 rsrc_id; /* Index of the entry to be freed */ 1802 u8 rsrc_type; 1803 u8 mcs_id; 1804 u8 dir; 1805 u8 all; /* Free all the cam resources */ 1806 u64 rsvd; 1807 }; 1808 1809 struct mcs_flowid_entry_write_req { 1810 struct mbox_msghdr hdr; 1811 u64 data[4]; 1812 u64 mask[4]; 1813 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1814 u8 flow_id; 1815 u8 secy_id; /* secyid for which flowid is mapped */ 1816 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1817 u8 ena; /* Enable tcam entry */ 1818 u8 ctrl_pkt; 1819 u8 mcs_id; 1820 u8 dir; 1821 u64 rsvd; 1822 }; 1823 1824 struct mcs_secy_plcy_write_req { 1825 struct mbox_msghdr hdr; 1826 u64 plcy; 1827 u8 secy_id; 1828 u8 mcs_id; 1829 u8 dir; 1830 u64 rsvd; 1831 }; 1832 1833 /* RX SC_CAM mapping */ 1834 struct mcs_rx_sc_cam_write_req { 1835 struct mbox_msghdr hdr; 1836 u64 sci; /* SCI */ 1837 u64 secy_id; /* secy index mapped to SC */ 1838 u8 sc_id; /* SC CAM entry index */ 1839 u8 mcs_id; 1840 u64 rsvd; 1841 }; 1842 1843 struct mcs_sa_plcy_write_req { 1844 struct mbox_msghdr hdr; 1845 u64 plcy[2][9]; /* Support 2 SA policy */ 1846 u8 sa_index[2]; 1847 u8 sa_cnt; 1848 u8 mcs_id; 1849 u8 dir; 1850 u64 rsvd; 1851 }; 1852 1853 struct mcs_tx_sc_sa_map { 1854 struct mbox_msghdr hdr; 1855 u8 sa_index0; 1856 u8 sa_index1; 1857 u8 rekey_ena; 1858 u8 sa_index0_vld; 1859 u8 sa_index1_vld; 1860 u8 tx_sa_active; 1861 u64 sectag_sci; 1862 u8 sc_id; /* used as index for SA_MEM_MAP */ 1863 u8 mcs_id; 1864 u64 rsvd; 1865 }; 1866 1867 struct mcs_rx_sc_sa_map { 1868 struct mbox_msghdr hdr; 1869 u8 sa_index; 1870 u8 sa_in_use; 1871 u8 sc_id; 1872 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1873 u8 mcs_id; 1874 u64 rsvd; 1875 }; 1876 1877 struct mcs_flowid_ena_dis_entry { 1878 struct mbox_msghdr hdr; 1879 u8 flow_id; 1880 u8 ena; 1881 u8 mcs_id; 1882 u8 dir; 1883 u64 rsvd; 1884 }; 1885 1886 struct mcs_pn_table_write_req { 1887 struct mbox_msghdr hdr; 1888 u64 next_pn; 1889 u8 pn_id; 1890 u8 mcs_id; 1891 u8 dir; 1892 u64 rsvd; 1893 }; 1894 1895 struct mcs_hw_info { 1896 struct mbox_msghdr hdr; 1897 u8 num_mcs_blks; /* Number of MCS blocks */ 1898 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1899 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1900 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1901 u8 sa_entries; /* PN table entries = SA entries */ 1902 u64 rsvd[16]; 1903 }; 1904 1905 struct mcs_set_active_lmac { 1906 struct mbox_msghdr hdr; 1907 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1908 u8 mcs_id; 1909 u16 chan_base; /* MCS channel base */ 1910 u64 rsvd; 1911 }; 1912 1913 struct mcs_set_lmac_mode { 1914 struct mbox_msghdr hdr; 1915 u8 mode; /* 1:Bypass 0:Operational */ 1916 u8 lmac_id; 1917 u8 mcs_id; 1918 u64 rsvd; 1919 }; 1920 1921 struct mcs_port_reset_req { 1922 struct mbox_msghdr hdr; 1923 u8 reset; 1924 u8 mcs_id; 1925 u8 port_id; 1926 u64 rsvd; 1927 }; 1928 1929 struct mcs_port_cfg_set_req { 1930 struct mbox_msghdr hdr; 1931 u8 cstm_tag_rel_mode_sel; 1932 u8 custom_hdr_enb; 1933 u8 fifo_skid; 1934 u8 port_mode; 1935 u8 port_id; 1936 u8 mcs_id; 1937 u64 rsvd; 1938 }; 1939 1940 struct mcs_port_cfg_get_req { 1941 struct mbox_msghdr hdr; 1942 u8 port_id; 1943 u8 mcs_id; 1944 u64 rsvd; 1945 }; 1946 1947 struct mcs_port_cfg_get_rsp { 1948 struct mbox_msghdr hdr; 1949 u8 cstm_tag_rel_mode_sel; 1950 u8 custom_hdr_enb; 1951 u8 fifo_skid; 1952 u8 port_mode; 1953 u8 port_id; 1954 u8 mcs_id; 1955 u64 rsvd; 1956 }; 1957 1958 struct mcs_custom_tag_cfg_get_req { 1959 struct mbox_msghdr hdr; 1960 u8 mcs_id; 1961 u8 dir; 1962 u64 rsvd; 1963 }; 1964 1965 struct mcs_custom_tag_cfg_get_rsp { 1966 struct mbox_msghdr hdr; 1967 u16 cstm_etype[8]; 1968 u8 cstm_indx[8]; 1969 u8 cstm_etype_en; 1970 u8 mcs_id; 1971 u8 dir; 1972 u64 rsvd; 1973 }; 1974 1975 /* MCS mailbox error codes 1976 * Range 1201 - 1300. 1977 */ 1978 enum mcs_af_status { 1979 MCS_AF_ERR_INVALID_MCSID = -1201, 1980 MCS_AF_ERR_NOT_MAPPED = -1202, 1981 }; 1982 1983 struct mcs_set_pn_threshold { 1984 struct mbox_msghdr hdr; 1985 u64 threshold; 1986 u8 xpn; /* '1' for setting xpn threshold */ 1987 u8 mcs_id; 1988 u8 dir; 1989 u64 rsvd; 1990 }; 1991 1992 enum mcs_ctrl_pkt_rulew_type { 1993 MCS_CTRL_PKT_RULE_TYPE_ETH, 1994 MCS_CTRL_PKT_RULE_TYPE_DA, 1995 MCS_CTRL_PKT_RULE_TYPE_RANGE, 1996 MCS_CTRL_PKT_RULE_TYPE_COMBO, 1997 MCS_CTRL_PKT_RULE_TYPE_MAC, 1998 }; 1999 2000 struct mcs_alloc_ctrl_pkt_rule_req { 2001 struct mbox_msghdr hdr; 2002 u8 rule_type; 2003 u8 mcs_id; /* MCS block ID */ 2004 u8 dir; /* Macsec ingress or egress side */ 2005 u64 rsvd; 2006 }; 2007 2008 struct mcs_alloc_ctrl_pkt_rule_rsp { 2009 struct mbox_msghdr hdr; 2010 u8 rule_idx; 2011 u8 rule_type; 2012 u8 mcs_id; 2013 u8 dir; 2014 u64 rsvd; 2015 }; 2016 2017 struct mcs_free_ctrl_pkt_rule_req { 2018 struct mbox_msghdr hdr; 2019 u8 rule_idx; 2020 u8 rule_type; 2021 u8 mcs_id; 2022 u8 dir; 2023 u8 all; 2024 u64 rsvd; 2025 }; 2026 2027 struct mcs_ctrl_pkt_rule_write_req { 2028 struct mbox_msghdr hdr; 2029 u64 data0; 2030 u64 data1; 2031 u64 data2; 2032 u8 rule_idx; 2033 u8 rule_type; 2034 u8 mcs_id; 2035 u8 dir; 2036 u64 rsvd; 2037 }; 2038 2039 struct mcs_stats_req { 2040 struct mbox_msghdr hdr; 2041 u8 id; 2042 u8 mcs_id; 2043 u8 dir; 2044 u64 rsvd; 2045 }; 2046 2047 struct mcs_flowid_stats { 2048 struct mbox_msghdr hdr; 2049 u64 tcam_hit_cnt; 2050 u64 rsvd; 2051 }; 2052 2053 struct mcs_secy_stats { 2054 struct mbox_msghdr hdr; 2055 u64 ctl_pkt_bcast_cnt; 2056 u64 ctl_pkt_mcast_cnt; 2057 u64 ctl_pkt_ucast_cnt; 2058 u64 ctl_octet_cnt; 2059 u64 unctl_pkt_bcast_cnt; 2060 u64 unctl_pkt_mcast_cnt; 2061 u64 unctl_pkt_ucast_cnt; 2062 u64 unctl_octet_cnt; 2063 /* Valid only for RX */ 2064 u64 octet_decrypted_cnt; 2065 u64 octet_validated_cnt; 2066 u64 pkt_port_disabled_cnt; 2067 u64 pkt_badtag_cnt; 2068 u64 pkt_nosa_cnt; 2069 u64 pkt_nosaerror_cnt; 2070 u64 pkt_tagged_ctl_cnt; 2071 u64 pkt_untaged_cnt; 2072 u64 pkt_ctl_cnt; /* CN10K-B */ 2073 u64 pkt_notag_cnt; /* CNF10K-B */ 2074 /* Valid only for TX */ 2075 u64 octet_encrypted_cnt; 2076 u64 octet_protected_cnt; 2077 u64 pkt_noactivesa_cnt; 2078 u64 pkt_toolong_cnt; 2079 u64 pkt_untagged_cnt; 2080 u64 rsvd[4]; 2081 }; 2082 2083 struct mcs_port_stats { 2084 struct mbox_msghdr hdr; 2085 u64 tcam_miss_cnt; 2086 u64 parser_err_cnt; 2087 u64 preempt_err_cnt; /* CNF10K-B */ 2088 u64 sectag_insert_err_cnt; 2089 u64 rsvd[4]; 2090 }; 2091 2092 /* Only for CN10K-B */ 2093 struct mcs_sa_stats { 2094 struct mbox_msghdr hdr; 2095 /* RX */ 2096 u64 pkt_invalid_cnt; 2097 u64 pkt_nosaerror_cnt; 2098 u64 pkt_notvalid_cnt; 2099 u64 pkt_ok_cnt; 2100 u64 pkt_nosa_cnt; 2101 /* TX */ 2102 u64 pkt_encrypt_cnt; 2103 u64 pkt_protected_cnt; 2104 u64 rsvd[4]; 2105 }; 2106 2107 struct mcs_sc_stats { 2108 struct mbox_msghdr hdr; 2109 /* RX */ 2110 u64 hit_cnt; 2111 u64 pkt_invalid_cnt; 2112 u64 pkt_late_cnt; 2113 u64 pkt_notvalid_cnt; 2114 u64 pkt_unchecked_cnt; 2115 u64 pkt_delay_cnt; /* CNF10K-B */ 2116 u64 pkt_ok_cnt; /* CNF10K-B */ 2117 u64 octet_decrypt_cnt; /* CN10K-B */ 2118 u64 octet_validate_cnt; /* CN10K-B */ 2119 /* TX */ 2120 u64 pkt_encrypt_cnt; 2121 u64 pkt_protected_cnt; 2122 u64 octet_encrypt_cnt; /* CN10K-B */ 2123 u64 octet_protected_cnt; /* CN10K-B */ 2124 u64 rsvd[4]; 2125 }; 2126 2127 struct mcs_clear_stats { 2128 struct mbox_msghdr hdr; 2129 #define MCS_FLOWID_STATS 0 2130 #define MCS_SECY_STATS 1 2131 #define MCS_SC_STATS 2 2132 #define MCS_SA_STATS 3 2133 #define MCS_PORT_STATS 4 2134 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2135 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2136 u8 mcs_id; 2137 u8 dir; 2138 u8 all; /* All resources stats mapped to PF are cleared */ 2139 }; 2140 2141 struct mcs_intr_cfg { 2142 struct mbox_msghdr hdr; 2143 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2144 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2145 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2146 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2147 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2148 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2149 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2150 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2151 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2152 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2153 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2154 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2155 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2156 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2157 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2158 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2159 u64 intr_mask; /* Interrupt enable mask */ 2160 u8 mcs_id; 2161 u8 lmac_id; 2162 u64 rsvd; 2163 }; 2164 2165 struct mcs_intr_info { 2166 struct mbox_msghdr hdr; 2167 u64 intr_mask; 2168 int sa_id; 2169 u8 mcs_id; 2170 u8 lmac_id; 2171 u64 rsvd; 2172 }; 2173 2174 #endif /* MBOX_H */ 2175