1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 106 int size, int size_rsp); 107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 108 struct mbox_msghdr *msg); 109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 111 u16 pcifunc, u16 id); 112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 113 const char *otx2_mbox_id2name(u16 id); 114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 115 int devid, int size) 116 { 117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 118 } 119 120 /* Mailbox message types */ 121 #define MBOX_MSG_MASK 0xFFFF 122 #define MBOX_MSG_INVALID 0xFFFE 123 #define MBOX_MSG_MAX 0xFFFF 124 125 #define MBOX_MESSAGES \ 126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 136 msg_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 160 cgx_mac_addr_add_rsp) \ 161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 162 msg_rsp) \ 163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 164 cgx_max_dmac_entries_get_rsp) \ 165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 167 cgx_set_link_mode_rsp) \ 168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 170 cgx_features_info_msg) \ 171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 173 msg_rsp) \ 174 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 175 cgx_mac_addr_update_rsp) \ 176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 177 cgx_pfc_rsp) \ 178 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 179 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 180 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 182 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 185 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 188 msg_rsp) \ 189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 191 cpt_rd_wr_reg_msg) \ 192 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 193 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 194 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 195 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 196 msg_rsp) \ 197 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 198 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 199 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 200 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 202 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 203 npc_mcam_alloc_entry_rsp) \ 204 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 205 npc_mcam_free_entry_req, msg_rsp) \ 206 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 207 npc_mcam_write_entry_req, msg_rsp) \ 208 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 209 npc_mcam_ena_dis_entry_req, msg_rsp) \ 210 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 211 npc_mcam_ena_dis_entry_req, msg_rsp) \ 212 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 213 npc_mcam_shift_entry_rsp) \ 214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 215 npc_mcam_alloc_counter_req, \ 216 npc_mcam_alloc_counter_rsp) \ 217 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 218 npc_mcam_oper_counter_req, msg_rsp) \ 219 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 220 npc_mcam_unmap_counter_req, msg_rsp) \ 221 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 222 npc_mcam_oper_counter_req, msg_rsp) \ 223 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 224 npc_mcam_oper_counter_req, \ 225 npc_mcam_oper_counter_rsp) \ 226 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 227 npc_mcam_alloc_and_write_entry_req, \ 228 npc_mcam_alloc_and_write_entry_rsp) \ 229 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 230 msg_req, npc_get_kex_cfg_rsp) \ 231 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 232 npc_install_flow_req, npc_install_flow_rsp) \ 233 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 234 npc_delete_flow_req, msg_rsp) \ 235 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 236 npc_mcam_read_entry_req, \ 237 npc_mcam_read_entry_rsp) \ 238 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 239 npc_set_pkind, msg_rsp) \ 240 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 241 msg_req, npc_mcam_read_base_rule_rsp) \ 242 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 243 npc_mcam_get_stats_req, \ 244 npc_mcam_get_stats_rsp) \ 245 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key, \ 246 npc_get_secret_key_req, \ 247 npc_get_secret_key_rsp) \ 248 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 249 npc_get_field_status_req, \ 250 npc_get_field_status_rsp) \ 251 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 252 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 253 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 254 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 255 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 256 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 257 hwctx_disable_req, msg_rsp) \ 258 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 259 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 260 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 261 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 262 nix_txschq_config) \ 263 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 264 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 265 nix_vtag_config_rsp) \ 266 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 267 nix_rss_flowkey_cfg, \ 268 nix_rss_flowkey_cfg_rsp) \ 269 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 270 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 271 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 272 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 273 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 274 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 275 nix_mark_format_cfg, \ 276 nix_mark_format_cfg_rsp) \ 277 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 278 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 279 nix_lso_format_cfg, \ 280 nix_lso_format_cfg_rsp) \ 281 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 282 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 283 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 284 nix_bp_cfg_rsp) \ 285 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 286 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 287 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 288 nix_inline_ipsec_cfg, msg_rsp) \ 289 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 290 nix_inline_ipsec_lf_cfg, msg_rsp) \ 291 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 292 nix_cn10k_aq_enq_rsp) \ 293 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 294 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 295 nix_bandprof_alloc_rsp) \ 296 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 297 msg_rsp) \ 298 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 299 nix_bandprof_get_hwinfo_rsp) \ 300 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 301 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 302 mcs_alloc_rsrc_rsp) \ 303 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 304 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 305 msg_rsp) \ 306 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 307 msg_rsp) \ 308 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 309 msg_rsp) \ 310 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 311 msg_rsp) \ 312 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 313 msg_rsp) \ 314 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 315 msg_rsp) \ 316 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 317 msg_rsp) \ 318 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 319 msg_rsp) \ 320 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 321 msg_rsp) \ 322 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 323 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 324 mcs_flowid_stats) \ 325 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 326 mcs_secy_stats) \ 327 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 328 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 329 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 330 mcs_port_stats) \ 331 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 332 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 333 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 334 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 335 msg_rsp) \ 336 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 337 mcs_alloc_ctrl_pkt_rule_req, \ 338 mcs_alloc_ctrl_pkt_rule_rsp) \ 339 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 340 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 341 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 342 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 343 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 344 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 345 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 346 mcs_port_cfg_get_rsp) \ 347 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 348 mcs_custom_tag_cfg_get_req, \ 349 mcs_custom_tag_cfg_get_rsp) 350 351 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 352 #define MBOX_UP_CGX_MESSAGES \ 353 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 354 355 #define MBOX_UP_CPT_MESSAGES \ 356 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 357 358 #define MBOX_UP_MCS_MESSAGES \ 359 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 360 361 enum { 362 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 363 MBOX_MESSAGES 364 MBOX_UP_CGX_MESSAGES 365 MBOX_UP_CPT_MESSAGES 366 MBOX_UP_MCS_MESSAGES 367 #undef M 368 }; 369 370 /* Mailbox message formats */ 371 372 #define RVU_DEFAULT_PF_FUNC 0xFFFF 373 374 /* Generic request msg used for those mbox messages which 375 * don't send any data in the request. 376 */ 377 struct msg_req { 378 struct mbox_msghdr hdr; 379 }; 380 381 /* Generic response msg used an ack or response for those mbox 382 * messages which don't have a specific rsp msg format. 383 */ 384 struct msg_rsp { 385 struct mbox_msghdr hdr; 386 }; 387 388 /* RVU mailbox error codes 389 * Range 256 - 300. 390 */ 391 enum rvu_af_status { 392 RVU_INVALID_VF_ID = -256, 393 }; 394 395 struct ready_msg_rsp { 396 struct mbox_msghdr hdr; 397 u16 sclk_freq; /* SCLK frequency (in MHz) */ 398 u16 rclk_freq; /* RCLK frequency (in MHz) */ 399 }; 400 401 /* Structure for requesting resource provisioning. 402 * 'modify' flag to be used when either requesting more 403 * or to detach partial of a certain resource type. 404 * Rest of the fields specify how many of what type to 405 * be attached. 406 * To request LFs from two blocks of same type this mailbox 407 * can be sent twice as below: 408 * struct rsrc_attach *attach; 409 * .. Allocate memory for message .. 410 * attach->cptlfs = 3; <3 LFs from CPT0> 411 * .. Send message .. 412 * .. Allocate memory for message .. 413 * attach->modify = 1; 414 * attach->cpt_blkaddr = BLKADDR_CPT1; 415 * attach->cptlfs = 2; <2 LFs from CPT1> 416 * .. Send message .. 417 */ 418 struct rsrc_attach { 419 struct mbox_msghdr hdr; 420 u8 modify:1; 421 u8 npalf:1; 422 u8 nixlf:1; 423 u16 sso; 424 u16 ssow; 425 u16 timlfs; 426 u16 cptlfs; 427 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 428 }; 429 430 /* Structure for relinquishing resources. 431 * 'partial' flag to be used when relinquishing all resources 432 * but only of a certain type. If not set, all resources of all 433 * types provisioned to the RVU function will be detached. 434 */ 435 struct rsrc_detach { 436 struct mbox_msghdr hdr; 437 u8 partial:1; 438 u8 npalf:1; 439 u8 nixlf:1; 440 u8 sso:1; 441 u8 ssow:1; 442 u8 timlfs:1; 443 u8 cptlfs:1; 444 }; 445 446 /* Number of resources available to the caller. 447 * In reply to MBOX_MSG_FREE_RSRC_CNT. 448 */ 449 struct free_rsrcs_rsp { 450 struct mbox_msghdr hdr; 451 u16 schq[NIX_TXSCH_LVL_CNT]; 452 u16 sso; 453 u16 tim; 454 u16 ssow; 455 u16 cpt; 456 u8 npa; 457 u8 nix; 458 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 459 u8 nix1; 460 u8 cpt1; 461 u8 ree0; 462 u8 ree1; 463 }; 464 465 #define MSIX_VECTOR_INVALID 0xFFFF 466 #define MAX_RVU_BLKLF_CNT 256 467 468 struct msix_offset_rsp { 469 struct mbox_msghdr hdr; 470 u16 npa_msixoff; 471 u16 nix_msixoff; 472 u16 sso; 473 u16 ssow; 474 u16 timlfs; 475 u16 cptlfs; 476 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 477 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 478 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 479 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 480 u16 cpt1_lfs; 481 u16 ree0_lfs; 482 u16 ree1_lfs; 483 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 484 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 485 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 486 }; 487 488 struct get_hw_cap_rsp { 489 struct mbox_msghdr hdr; 490 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 491 u8 nix_shaping; /* Is shaping and coloring supported */ 492 u8 npc_hash_extract; /* Is hash extract supported */ 493 }; 494 495 /* CGX mbox message formats */ 496 497 struct cgx_stats_rsp { 498 struct mbox_msghdr hdr; 499 #define CGX_RX_STATS_COUNT 9 500 #define CGX_TX_STATS_COUNT 18 501 u64 rx_stats[CGX_RX_STATS_COUNT]; 502 u64 tx_stats[CGX_TX_STATS_COUNT]; 503 }; 504 505 struct cgx_fec_stats_rsp { 506 struct mbox_msghdr hdr; 507 u64 fec_corr_blks; 508 u64 fec_uncorr_blks; 509 }; 510 /* Structure for requesting the operation for 511 * setting/getting mac address in the CGX interface 512 */ 513 struct cgx_mac_addr_set_or_get { 514 struct mbox_msghdr hdr; 515 u8 mac_addr[ETH_ALEN]; 516 u32 index; 517 }; 518 519 /* Structure for requesting the operation to 520 * add DMAC filter entry into CGX interface 521 */ 522 struct cgx_mac_addr_add_req { 523 struct mbox_msghdr hdr; 524 u8 mac_addr[ETH_ALEN]; 525 }; 526 527 /* Structure for response against the operation to 528 * add DMAC filter entry into CGX interface 529 */ 530 struct cgx_mac_addr_add_rsp { 531 struct mbox_msghdr hdr; 532 u32 index; 533 }; 534 535 /* Structure for requesting the operation to 536 * delete DMAC filter entry from CGX interface 537 */ 538 struct cgx_mac_addr_del_req { 539 struct mbox_msghdr hdr; 540 u32 index; 541 }; 542 543 /* Structure for response against the operation to 544 * get maximum supported DMAC filter entries 545 */ 546 struct cgx_max_dmac_entries_get_rsp { 547 struct mbox_msghdr hdr; 548 u32 max_dmac_filters; 549 }; 550 551 struct cgx_link_user_info { 552 uint64_t link_up:1; 553 uint64_t full_duplex:1; 554 uint64_t lmac_type_id:4; 555 uint64_t speed:20; /* speed in Mbps */ 556 uint64_t an:1; /* AN supported or not */ 557 uint64_t fec:2; /* FEC type if enabled else 0 */ 558 #define LMACTYPE_STR_LEN 16 559 char lmac_type[LMACTYPE_STR_LEN]; 560 }; 561 562 struct cgx_link_info_msg { 563 struct mbox_msghdr hdr; 564 struct cgx_link_user_info link_info; 565 }; 566 567 struct cgx_pause_frm_cfg { 568 struct mbox_msghdr hdr; 569 u8 set; 570 /* set = 1 if the request is to config pause frames */ 571 /* set = 0 if the request is to fetch pause frames config */ 572 u8 rx_pause; 573 u8 tx_pause; 574 }; 575 576 enum fec_type { 577 OTX2_FEC_NONE, 578 OTX2_FEC_BASER, 579 OTX2_FEC_RS, 580 OTX2_FEC_STATS_CNT = 2, 581 OTX2_FEC_OFF, 582 }; 583 584 struct fec_mode { 585 struct mbox_msghdr hdr; 586 int fec; 587 }; 588 589 struct sfp_eeprom_s { 590 #define SFP_EEPROM_SIZE 256 591 u16 sff_id; 592 u8 buf[SFP_EEPROM_SIZE]; 593 u64 reserved; 594 }; 595 596 struct phy_s { 597 struct { 598 u64 can_change_mod_type:1; 599 u64 mod_type:1; 600 u64 has_fec_stats:1; 601 } misc; 602 struct fec_stats_s { 603 u32 rsfec_corr_cws; 604 u32 rsfec_uncorr_cws; 605 u32 brfec_corr_blks; 606 u32 brfec_uncorr_blks; 607 } fec_stats; 608 }; 609 610 struct cgx_lmac_fwdata_s { 611 u16 rw_valid; 612 u64 supported_fec; 613 u64 supported_an; 614 u64 supported_link_modes; 615 /* only applicable if AN is supported */ 616 u64 advertised_fec; 617 u64 advertised_link_modes; 618 /* Only applicable if SFP/QSFP slot is present */ 619 struct sfp_eeprom_s sfp_eeprom; 620 struct phy_s phy; 621 #define LMAC_FWDATA_RESERVED_MEM 1021 622 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 623 }; 624 625 struct cgx_fw_data { 626 struct mbox_msghdr hdr; 627 struct cgx_lmac_fwdata_s fwdata; 628 }; 629 630 struct cgx_set_link_mode_args { 631 u32 speed; 632 u8 duplex; 633 u8 an; 634 u8 ports; 635 u64 mode; 636 }; 637 638 struct cgx_set_link_mode_req { 639 #define AUTONEG_UNKNOWN 0xff 640 struct mbox_msghdr hdr; 641 struct cgx_set_link_mode_args args; 642 }; 643 644 struct cgx_set_link_mode_rsp { 645 struct mbox_msghdr hdr; 646 int status; 647 }; 648 649 struct cgx_mac_addr_reset_req { 650 struct mbox_msghdr hdr; 651 u32 index; 652 }; 653 654 struct cgx_mac_addr_update_req { 655 struct mbox_msghdr hdr; 656 u8 mac_addr[ETH_ALEN]; 657 u32 index; 658 }; 659 660 struct cgx_mac_addr_update_rsp { 661 struct mbox_msghdr hdr; 662 u32 index; 663 }; 664 665 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 666 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 667 /* flow control from physical link higig2 messages */ 668 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 669 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 670 #define RVU_MAC_VERSION BIT_ULL(4) 671 #define RVU_MAC_CGX BIT_ULL(5) 672 #define RVU_MAC_RPM BIT_ULL(6) 673 674 struct cgx_features_info_msg { 675 struct mbox_msghdr hdr; 676 u64 lmac_features; 677 }; 678 679 struct rpm_stats_rsp { 680 struct mbox_msghdr hdr; 681 #define RPM_RX_STATS_COUNT 43 682 #define RPM_TX_STATS_COUNT 34 683 u64 rx_stats[RPM_RX_STATS_COUNT]; 684 u64 tx_stats[RPM_TX_STATS_COUNT]; 685 }; 686 687 struct cgx_pfc_cfg { 688 struct mbox_msghdr hdr; 689 u8 rx_pause; 690 u8 tx_pause; 691 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 692 }; 693 694 struct cgx_pfc_rsp { 695 struct mbox_msghdr hdr; 696 u8 rx_pause; 697 u8 tx_pause; 698 }; 699 700 /* NPA mbox message formats */ 701 702 struct npc_set_pkind { 703 struct mbox_msghdr hdr; 704 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 705 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 706 u64 mode; 707 #define PKIND_TX BIT_ULL(0) 708 #define PKIND_RX BIT_ULL(1) 709 u8 dir; 710 u8 pkind; /* valid only in case custom flag */ 711 u8 var_len_off; /* Offset of custom header length field. 712 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 713 */ 714 u8 var_len_off_mask; /* Mask for length with in offset */ 715 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 716 }; 717 718 /* NPA mbox message formats */ 719 720 /* NPA mailbox error codes 721 * Range 301 - 400. 722 */ 723 enum npa_af_status { 724 NPA_AF_ERR_PARAM = -301, 725 NPA_AF_ERR_AQ_FULL = -302, 726 NPA_AF_ERR_AQ_ENQUEUE = -303, 727 NPA_AF_ERR_AF_LF_INVALID = -304, 728 NPA_AF_ERR_AF_LF_ALLOC = -305, 729 NPA_AF_ERR_LF_RESET = -306, 730 }; 731 732 /* For NPA LF context alloc and init */ 733 struct npa_lf_alloc_req { 734 struct mbox_msghdr hdr; 735 int node; 736 int aura_sz; /* No of auras */ 737 u32 nr_pools; /* No of pools */ 738 u64 way_mask; 739 }; 740 741 struct npa_lf_alloc_rsp { 742 struct mbox_msghdr hdr; 743 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 744 u32 stack_pg_bytes; /* Size of stack page */ 745 u16 qints; /* NPA_AF_CONST::QINTS */ 746 u8 cache_lines; /*BATCH ALLOC DMA */ 747 }; 748 749 /* NPA AQ enqueue msg */ 750 struct npa_aq_enq_req { 751 struct mbox_msghdr hdr; 752 u32 aura_id; 753 u8 ctype; 754 u8 op; 755 union { 756 /* Valid when op == WRITE/INIT and ctype == AURA. 757 * LF fills the pool_id in aura.pool_addr. AF will translate 758 * the pool_id to pool context pointer. 759 */ 760 struct npa_aura_s aura; 761 /* Valid when op == WRITE/INIT and ctype == POOL */ 762 struct npa_pool_s pool; 763 }; 764 /* Mask data when op == WRITE (1=write, 0=don't write) */ 765 union { 766 /* Valid when op == WRITE and ctype == AURA */ 767 struct npa_aura_s aura_mask; 768 /* Valid when op == WRITE and ctype == POOL */ 769 struct npa_pool_s pool_mask; 770 }; 771 }; 772 773 struct npa_aq_enq_rsp { 774 struct mbox_msghdr hdr; 775 union { 776 /* Valid when op == READ and ctype == AURA */ 777 struct npa_aura_s aura; 778 /* Valid when op == READ and ctype == POOL */ 779 struct npa_pool_s pool; 780 }; 781 }; 782 783 /* Disable all contexts of type 'ctype' */ 784 struct hwctx_disable_req { 785 struct mbox_msghdr hdr; 786 u8 ctype; 787 }; 788 789 /* NIX mbox message formats */ 790 791 /* NIX mailbox error codes 792 * Range 401 - 500. 793 */ 794 enum nix_af_status { 795 NIX_AF_ERR_PARAM = -401, 796 NIX_AF_ERR_AQ_FULL = -402, 797 NIX_AF_ERR_AQ_ENQUEUE = -403, 798 NIX_AF_ERR_AF_LF_INVALID = -404, 799 NIX_AF_ERR_AF_LF_ALLOC = -405, 800 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 801 NIX_AF_ERR_TLX_INVALID = -407, 802 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 803 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 804 NIX_AF_ERR_FRS_INVALID = -410, 805 NIX_AF_ERR_RX_LINK_INVALID = -411, 806 NIX_AF_INVAL_TXSCHQ_CFG = -412, 807 NIX_AF_SMQ_FLUSH_FAILED = -413, 808 NIX_AF_ERR_LF_RESET = -414, 809 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 810 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 811 NIX_AF_ERR_MARK_CFG_FAIL = -417, 812 NIX_AF_ERR_LSO_CFG_FAIL = -418, 813 NIX_AF_INVAL_NPA_PF_FUNC = -419, 814 NIX_AF_INVAL_SSO_PF_FUNC = -420, 815 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 816 NIX_AF_ERR_RX_VTAG_INUSE = -422, 817 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 818 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 819 NIX_AF_ERR_INVALID_NIXBLK = -425, 820 NIX_AF_ERR_INVALID_BANDPROF = -426, 821 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 822 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 823 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 824 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 825 NIX_AF_ERR_LINK_CREDITS = -431, 826 }; 827 828 /* For NIX RX vtag action */ 829 enum nix_rx_vtag0_type { 830 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 831 NIX_AF_LFX_RX_VTAG_TYPE1, 832 NIX_AF_LFX_RX_VTAG_TYPE2, 833 NIX_AF_LFX_RX_VTAG_TYPE3, 834 NIX_AF_LFX_RX_VTAG_TYPE4, 835 NIX_AF_LFX_RX_VTAG_TYPE5, 836 NIX_AF_LFX_RX_VTAG_TYPE6, 837 NIX_AF_LFX_RX_VTAG_TYPE7, 838 }; 839 840 /* For NIX LF context alloc and init */ 841 struct nix_lf_alloc_req { 842 struct mbox_msghdr hdr; 843 int node; 844 u32 rq_cnt; /* No of receive queues */ 845 u32 sq_cnt; /* No of send queues */ 846 u32 cq_cnt; /* No of completion queues */ 847 u8 xqe_sz; 848 u16 rss_sz; 849 u8 rss_grps; 850 u16 npa_func; 851 u16 sso_func; 852 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 853 u64 way_mask; 854 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 855 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 856 u64 flags; 857 }; 858 859 struct nix_lf_alloc_rsp { 860 struct mbox_msghdr hdr; 861 u16 sqb_size; 862 u16 rx_chan_base; 863 u16 tx_chan_base; 864 u8 rx_chan_cnt; /* total number of RX channels */ 865 u8 tx_chan_cnt; /* total number of TX channels */ 866 u8 lso_tsov4_idx; 867 u8 lso_tsov6_idx; 868 u8 mac_addr[ETH_ALEN]; 869 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 870 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 871 u16 cints; /* NIX_AF_CONST2::CINTS */ 872 u16 qints; /* NIX_AF_CONST2::QINTS */ 873 u8 cgx_links; /* No. of CGX links present in HW */ 874 u8 lbk_links; /* No. of LBK links present in HW */ 875 u8 sdp_links; /* No. of SDP links present in HW */ 876 u8 tx_link; /* Transmit channel link number */ 877 }; 878 879 struct nix_lf_free_req { 880 struct mbox_msghdr hdr; 881 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 882 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 883 u64 flags; 884 }; 885 886 /* CN10K NIX AQ enqueue msg */ 887 struct nix_cn10k_aq_enq_req { 888 struct mbox_msghdr hdr; 889 u32 qidx; 890 u8 ctype; 891 u8 op; 892 union { 893 struct nix_cn10k_rq_ctx_s rq; 894 struct nix_cn10k_sq_ctx_s sq; 895 struct nix_cq_ctx_s cq; 896 struct nix_rsse_s rss; 897 struct nix_rx_mce_s mce; 898 struct nix_bandprof_s prof; 899 }; 900 union { 901 struct nix_cn10k_rq_ctx_s rq_mask; 902 struct nix_cn10k_sq_ctx_s sq_mask; 903 struct nix_cq_ctx_s cq_mask; 904 struct nix_rsse_s rss_mask; 905 struct nix_rx_mce_s mce_mask; 906 struct nix_bandprof_s prof_mask; 907 }; 908 }; 909 910 struct nix_cn10k_aq_enq_rsp { 911 struct mbox_msghdr hdr; 912 union { 913 struct nix_cn10k_rq_ctx_s rq; 914 struct nix_cn10k_sq_ctx_s sq; 915 struct nix_cq_ctx_s cq; 916 struct nix_rsse_s rss; 917 struct nix_rx_mce_s mce; 918 struct nix_bandprof_s prof; 919 }; 920 }; 921 922 /* NIX AQ enqueue msg */ 923 struct nix_aq_enq_req { 924 struct mbox_msghdr hdr; 925 u32 qidx; 926 u8 ctype; 927 u8 op; 928 union { 929 struct nix_rq_ctx_s rq; 930 struct nix_sq_ctx_s sq; 931 struct nix_cq_ctx_s cq; 932 struct nix_rsse_s rss; 933 struct nix_rx_mce_s mce; 934 u64 prof; 935 }; 936 union { 937 struct nix_rq_ctx_s rq_mask; 938 struct nix_sq_ctx_s sq_mask; 939 struct nix_cq_ctx_s cq_mask; 940 struct nix_rsse_s rss_mask; 941 struct nix_rx_mce_s mce_mask; 942 u64 prof_mask; 943 }; 944 }; 945 946 struct nix_aq_enq_rsp { 947 struct mbox_msghdr hdr; 948 union { 949 struct nix_rq_ctx_s rq; 950 struct nix_sq_ctx_s sq; 951 struct nix_cq_ctx_s cq; 952 struct nix_rsse_s rss; 953 struct nix_rx_mce_s mce; 954 struct nix_bandprof_s prof; 955 }; 956 }; 957 958 /* Tx scheduler/shaper mailbox messages */ 959 960 #define MAX_TXSCHQ_PER_FUNC 128 961 962 struct nix_txsch_alloc_req { 963 struct mbox_msghdr hdr; 964 /* Scheduler queue count request at each level */ 965 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 966 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 967 }; 968 969 struct nix_txsch_alloc_rsp { 970 struct mbox_msghdr hdr; 971 /* Scheduler queue count allocated at each level */ 972 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 973 u16 schq[NIX_TXSCH_LVL_CNT]; 974 /* Scheduler queue list allocated at each level */ 975 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 976 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 977 u8 aggr_level; /* Traffic aggregation scheduler level */ 978 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 979 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 980 }; 981 982 struct nix_txsch_free_req { 983 struct mbox_msghdr hdr; 984 #define TXSCHQ_FREE_ALL BIT_ULL(0) 985 u16 flags; 986 /* Scheduler queue level to be freed */ 987 u16 schq_lvl; 988 /* List of scheduler queues to be freed */ 989 u16 schq; 990 }; 991 992 struct nix_txschq_config { 993 struct mbox_msghdr hdr; 994 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 995 u8 read; 996 #define TXSCHQ_IDX_SHIFT 16 997 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 998 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 999 u8 num_regs; 1000 #define MAX_REGS_PER_MBOX_MSG 20 1001 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1002 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1003 /* All 0's => overwrite with new value */ 1004 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1005 }; 1006 1007 struct nix_vtag_config { 1008 struct mbox_msghdr hdr; 1009 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1010 u8 vtag_size; 1011 /* cfg_type is '0' for tx vlan cfg 1012 * cfg_type is '1' for rx vlan cfg 1013 */ 1014 u8 cfg_type; 1015 union { 1016 /* valid when cfg_type is '0' */ 1017 struct { 1018 u64 vtag0; 1019 u64 vtag1; 1020 1021 /* cfg_vtag0 & cfg_vtag1 fields are valid 1022 * when free_vtag0 & free_vtag1 are '0's. 1023 */ 1024 /* cfg_vtag0 = 1 to configure vtag0 */ 1025 u8 cfg_vtag0 :1; 1026 /* cfg_vtag1 = 1 to configure vtag1 */ 1027 u8 cfg_vtag1 :1; 1028 1029 /* vtag0_idx & vtag1_idx are only valid when 1030 * both cfg_vtag0 & cfg_vtag1 are '0's, 1031 * these fields are used along with free_vtag0 1032 * & free_vtag1 to free the nix lf's tx_vlan 1033 * configuration. 1034 * 1035 * Denotes the indices of tx_vtag def registers 1036 * that needs to be cleared and freed. 1037 */ 1038 int vtag0_idx; 1039 int vtag1_idx; 1040 1041 /* free_vtag0 & free_vtag1 fields are valid 1042 * when cfg_vtag0 & cfg_vtag1 are '0's. 1043 */ 1044 /* free_vtag0 = 1 clears vtag0 configuration 1045 * vtag0_idx denotes the index to be cleared. 1046 */ 1047 u8 free_vtag0 :1; 1048 /* free_vtag1 = 1 clears vtag1 configuration 1049 * vtag1_idx denotes the index to be cleared. 1050 */ 1051 u8 free_vtag1 :1; 1052 } tx; 1053 1054 /* valid when cfg_type is '1' */ 1055 struct { 1056 /* rx vtag type index, valid values are in 0..7 range */ 1057 u8 vtag_type; 1058 /* rx vtag strip */ 1059 u8 strip_vtag :1; 1060 /* rx vtag capture */ 1061 u8 capture_vtag :1; 1062 } rx; 1063 }; 1064 }; 1065 1066 struct nix_vtag_config_rsp { 1067 struct mbox_msghdr hdr; 1068 int vtag0_idx; 1069 int vtag1_idx; 1070 /* Indices of tx_vtag def registers used to configure 1071 * tx vtag0 & vtag1 headers, these indices are valid 1072 * when nix_vtag_config mbox requested for vtag0 and/ 1073 * or vtag1 configuration. 1074 */ 1075 }; 1076 1077 struct nix_rss_flowkey_cfg { 1078 struct mbox_msghdr hdr; 1079 int mcam_index; /* MCAM entry index to modify */ 1080 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1081 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1082 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1083 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1084 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1085 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1086 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1087 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1088 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1089 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1090 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1091 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1092 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1093 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1094 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1095 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1096 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1097 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1098 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1099 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1100 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1101 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1102 u32 flowkey_cfg; /* Flowkey types selected */ 1103 u8 group; /* RSS context or group */ 1104 }; 1105 1106 struct nix_rss_flowkey_cfg_rsp { 1107 struct mbox_msghdr hdr; 1108 u8 alg_idx; /* Selected algo index */ 1109 }; 1110 1111 struct nix_set_mac_addr { 1112 struct mbox_msghdr hdr; 1113 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1114 }; 1115 1116 struct nix_get_mac_addr_rsp { 1117 struct mbox_msghdr hdr; 1118 u8 mac_addr[ETH_ALEN]; 1119 }; 1120 1121 struct nix_mark_format_cfg { 1122 struct mbox_msghdr hdr; 1123 u8 offset; 1124 u8 y_mask; 1125 u8 y_val; 1126 u8 r_mask; 1127 u8 r_val; 1128 }; 1129 1130 struct nix_mark_format_cfg_rsp { 1131 struct mbox_msghdr hdr; 1132 u8 mark_format_idx; 1133 }; 1134 1135 struct nix_rx_mode { 1136 struct mbox_msghdr hdr; 1137 #define NIX_RX_MODE_UCAST BIT(0) 1138 #define NIX_RX_MODE_PROMISC BIT(1) 1139 #define NIX_RX_MODE_ALLMULTI BIT(2) 1140 #define NIX_RX_MODE_USE_MCE BIT(3) 1141 u16 mode; 1142 }; 1143 1144 struct nix_rx_cfg { 1145 struct mbox_msghdr hdr; 1146 #define NIX_RX_OL3_VERIFY BIT(0) 1147 #define NIX_RX_OL4_VERIFY BIT(1) 1148 u8 len_verify; /* Outer L3/L4 len check */ 1149 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1150 u8 csum_verify; /* Outer L4 checksum verification */ 1151 }; 1152 1153 struct nix_frs_cfg { 1154 struct mbox_msghdr hdr; 1155 u8 update_smq; /* Update SMQ's min/max lens */ 1156 u8 update_minlen; /* Set minlen also */ 1157 u8 sdp_link; /* Set SDP RX link */ 1158 u16 maxlen; 1159 u16 minlen; 1160 }; 1161 1162 struct nix_lso_format_cfg { 1163 struct mbox_msghdr hdr; 1164 u64 field_mask; 1165 #define NIX_LSO_FIELD_MAX 8 1166 u64 fields[NIX_LSO_FIELD_MAX]; 1167 }; 1168 1169 struct nix_lso_format_cfg_rsp { 1170 struct mbox_msghdr hdr; 1171 u8 lso_format_idx; 1172 }; 1173 1174 struct nix_bp_cfg_req { 1175 struct mbox_msghdr hdr; 1176 u16 chan_base; /* Starting channel number */ 1177 u8 chan_cnt; /* Number of channels */ 1178 u8 bpid_per_chan; 1179 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1180 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1181 }; 1182 1183 /* PF can be mapped to either CGX or LBK interface, 1184 * so maximum 64 channels are possible. 1185 */ 1186 #define NIX_MAX_BPID_CHAN 64 1187 struct nix_bp_cfg_rsp { 1188 struct mbox_msghdr hdr; 1189 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1190 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1191 }; 1192 1193 /* Global NIX inline IPSec configuration */ 1194 struct nix_inline_ipsec_cfg { 1195 struct mbox_msghdr hdr; 1196 u32 cpt_credit; 1197 struct { 1198 u8 egrp; 1199 u8 opcode; 1200 u16 param1; 1201 u16 param2; 1202 } gen_cfg; 1203 struct { 1204 u16 cpt_pf_func; 1205 u8 cpt_slot; 1206 } inst_qsel; 1207 u8 enable; 1208 }; 1209 1210 /* Per NIX LF inline IPSec configuration */ 1211 struct nix_inline_ipsec_lf_cfg { 1212 struct mbox_msghdr hdr; 1213 u64 sa_base_addr; 1214 struct { 1215 u32 tag_const; 1216 u16 lenm1_max; 1217 u8 sa_pow2_size; 1218 u8 tt; 1219 } ipsec_cfg0; 1220 struct { 1221 u32 sa_idx_max; 1222 u8 sa_idx_w; 1223 } ipsec_cfg1; 1224 u8 enable; 1225 }; 1226 1227 struct nix_hw_info { 1228 struct mbox_msghdr hdr; 1229 u16 rsvs16; 1230 u16 max_mtu; 1231 u16 min_mtu; 1232 u32 rpm_dwrr_mtu; 1233 u32 sdp_dwrr_mtu; 1234 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1235 }; 1236 1237 struct nix_bandprof_alloc_req { 1238 struct mbox_msghdr hdr; 1239 /* Count of profiles needed per layer */ 1240 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1241 }; 1242 1243 struct nix_bandprof_alloc_rsp { 1244 struct mbox_msghdr hdr; 1245 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1246 1247 /* There is no need to allocate morethan 1 bandwidth profile 1248 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1249 * profiles to 64 per PF_FUNC. 1250 */ 1251 #define MAX_BANDPROF_PER_PFFUNC 64 1252 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1253 }; 1254 1255 struct nix_bandprof_free_req { 1256 struct mbox_msghdr hdr; 1257 u8 free_all; 1258 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1259 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1260 }; 1261 1262 struct nix_bandprof_get_hwinfo_rsp { 1263 struct mbox_msghdr hdr; 1264 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1265 u32 policer_timeunit; 1266 }; 1267 1268 /* NPC mbox message structs */ 1269 1270 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1271 #define NPC_MCAM_INVALID_MAP 0xFFFF 1272 1273 /* NPC mailbox error codes 1274 * Range 701 - 800. 1275 */ 1276 enum npc_af_status { 1277 NPC_MCAM_INVALID_REQ = -701, 1278 NPC_MCAM_ALLOC_DENIED = -702, 1279 NPC_MCAM_ALLOC_FAILED = -703, 1280 NPC_MCAM_PERM_DENIED = -704, 1281 NPC_FLOW_INTF_INVALID = -707, 1282 NPC_FLOW_CHAN_INVALID = -708, 1283 NPC_FLOW_NO_NIXLF = -709, 1284 NPC_FLOW_NOT_SUPPORTED = -710, 1285 NPC_FLOW_VF_PERM_DENIED = -711, 1286 NPC_FLOW_VF_NOT_INIT = -712, 1287 NPC_FLOW_VF_OVERLAP = -713, 1288 }; 1289 1290 struct npc_mcam_alloc_entry_req { 1291 struct mbox_msghdr hdr; 1292 #define NPC_MAX_NONCONTIG_ENTRIES 256 1293 u8 contig; /* Contiguous entries ? */ 1294 #define NPC_MCAM_ANY_PRIO 0 1295 #define NPC_MCAM_LOWER_PRIO 1 1296 #define NPC_MCAM_HIGHER_PRIO 2 1297 u8 priority; /* Lower or higher w.r.t ref_entry */ 1298 u16 ref_entry; 1299 u16 count; /* Number of entries requested */ 1300 }; 1301 1302 struct npc_mcam_alloc_entry_rsp { 1303 struct mbox_msghdr hdr; 1304 u16 entry; /* Entry allocated or start index if contiguous. 1305 * Invalid incase of non-contiguous. 1306 */ 1307 u16 count; /* Number of entries allocated */ 1308 u16 free_count; /* Number of entries available */ 1309 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1310 }; 1311 1312 struct npc_mcam_free_entry_req { 1313 struct mbox_msghdr hdr; 1314 u16 entry; /* Entry index to be freed */ 1315 u8 all; /* If all entries allocated to this PFVF to be freed */ 1316 }; 1317 1318 struct mcam_entry { 1319 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1320 u64 kw[NPC_MAX_KWS_IN_KEY]; 1321 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1322 u64 action; 1323 u64 vtag_action; 1324 }; 1325 1326 struct npc_mcam_write_entry_req { 1327 struct mbox_msghdr hdr; 1328 struct mcam_entry entry_data; 1329 u16 entry; /* MCAM entry to write this match key */ 1330 u16 cntr; /* Counter for this MCAM entry */ 1331 u8 intf; /* Rx or Tx interface */ 1332 u8 enable_entry;/* Enable this MCAM entry ? */ 1333 u8 set_cntr; /* Set counter for this entry ? */ 1334 }; 1335 1336 /* Enable/Disable a given entry */ 1337 struct npc_mcam_ena_dis_entry_req { 1338 struct mbox_msghdr hdr; 1339 u16 entry; 1340 }; 1341 1342 struct npc_mcam_shift_entry_req { 1343 struct mbox_msghdr hdr; 1344 #define NPC_MCAM_MAX_SHIFTS 64 1345 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1346 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1347 u16 shift_count; /* Number of entries to shift */ 1348 }; 1349 1350 struct npc_mcam_shift_entry_rsp { 1351 struct mbox_msghdr hdr; 1352 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1353 }; 1354 1355 struct npc_mcam_alloc_counter_req { 1356 struct mbox_msghdr hdr; 1357 u8 contig; /* Contiguous counters ? */ 1358 #define NPC_MAX_NONCONTIG_COUNTERS 64 1359 u16 count; /* Number of counters requested */ 1360 }; 1361 1362 struct npc_mcam_alloc_counter_rsp { 1363 struct mbox_msghdr hdr; 1364 u16 cntr; /* Counter allocated or start index if contiguous. 1365 * Invalid incase of non-contiguous. 1366 */ 1367 u16 count; /* Number of counters allocated */ 1368 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1369 }; 1370 1371 struct npc_mcam_oper_counter_req { 1372 struct mbox_msghdr hdr; 1373 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1374 }; 1375 1376 struct npc_mcam_oper_counter_rsp { 1377 struct mbox_msghdr hdr; 1378 u64 stat; /* valid only while fetching counter's stats */ 1379 }; 1380 1381 struct npc_mcam_unmap_counter_req { 1382 struct mbox_msghdr hdr; 1383 u16 cntr; 1384 u16 entry; /* Entry and counter to be unmapped */ 1385 u8 all; /* Unmap all entries using this counter ? */ 1386 }; 1387 1388 struct npc_mcam_alloc_and_write_entry_req { 1389 struct mbox_msghdr hdr; 1390 struct mcam_entry entry_data; 1391 u16 ref_entry; 1392 u8 priority; /* Lower or higher w.r.t ref_entry */ 1393 u8 intf; /* Rx or Tx interface */ 1394 u8 enable_entry;/* Enable this MCAM entry ? */ 1395 u8 alloc_cntr; /* Allocate counter and map ? */ 1396 }; 1397 1398 struct npc_mcam_alloc_and_write_entry_rsp { 1399 struct mbox_msghdr hdr; 1400 u16 entry; 1401 u16 cntr; 1402 }; 1403 1404 struct npc_get_kex_cfg_rsp { 1405 struct mbox_msghdr hdr; 1406 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1407 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1408 #define NPC_MAX_INTF 2 1409 #define NPC_MAX_LID 8 1410 #define NPC_MAX_LT 16 1411 #define NPC_MAX_LD 2 1412 #define NPC_MAX_LFL 16 1413 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1414 u64 kex_ld_flags[NPC_MAX_LD]; 1415 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1416 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1417 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1418 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1419 #define MKEX_NAME_LEN 128 1420 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1421 }; 1422 1423 struct flow_msg { 1424 unsigned char dmac[6]; 1425 unsigned char smac[6]; 1426 __be16 etype; 1427 __be16 vlan_etype; 1428 __be16 vlan_tci; 1429 union { 1430 __be32 ip4src; 1431 __be32 ip6src[4]; 1432 }; 1433 union { 1434 __be32 ip4dst; 1435 __be32 ip6dst[4]; 1436 }; 1437 u8 tos; 1438 u8 ip_ver; 1439 u8 ip_proto; 1440 u8 tc; 1441 __be16 sport; 1442 __be16 dport; 1443 union { 1444 u8 ip_flag; 1445 u8 next_header; 1446 }; 1447 }; 1448 1449 struct npc_install_flow_req { 1450 struct mbox_msghdr hdr; 1451 struct flow_msg packet; 1452 struct flow_msg mask; 1453 u64 features; 1454 u16 entry; 1455 u16 channel; 1456 u16 chan_mask; 1457 u8 intf; 1458 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1459 u8 default_rule; 1460 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1461 u16 vf; 1462 /* action */ 1463 u32 index; 1464 u16 match_id; 1465 u8 flow_key_alg; 1466 u8 op; 1467 /* vtag rx action */ 1468 u8 vtag0_type; 1469 u8 vtag0_valid; 1470 u8 vtag1_type; 1471 u8 vtag1_valid; 1472 /* vtag tx action */ 1473 u16 vtag0_def; 1474 u8 vtag0_op; 1475 u16 vtag1_def; 1476 u8 vtag1_op; 1477 }; 1478 1479 struct npc_install_flow_rsp { 1480 struct mbox_msghdr hdr; 1481 int counter; /* negative if no counter else counter number */ 1482 }; 1483 1484 struct npc_delete_flow_req { 1485 struct mbox_msghdr hdr; 1486 u16 entry; 1487 u16 start;/*Disable range of entries */ 1488 u16 end; 1489 u8 all; /* PF + VFs */ 1490 }; 1491 1492 struct npc_mcam_read_entry_req { 1493 struct mbox_msghdr hdr; 1494 u16 entry; /* MCAM entry to read */ 1495 }; 1496 1497 struct npc_mcam_read_entry_rsp { 1498 struct mbox_msghdr hdr; 1499 struct mcam_entry entry_data; 1500 u8 intf; 1501 u8 enable; 1502 }; 1503 1504 struct npc_mcam_read_base_rule_rsp { 1505 struct mbox_msghdr hdr; 1506 struct mcam_entry entry; 1507 }; 1508 1509 struct npc_mcam_get_stats_req { 1510 struct mbox_msghdr hdr; 1511 u16 entry; /* mcam entry */ 1512 }; 1513 1514 struct npc_mcam_get_stats_rsp { 1515 struct mbox_msghdr hdr; 1516 u64 stat; /* counter stats */ 1517 u8 stat_ena; /* enabled */ 1518 }; 1519 1520 struct npc_get_secret_key_req { 1521 struct mbox_msghdr hdr; 1522 u8 intf; 1523 }; 1524 1525 struct npc_get_secret_key_rsp { 1526 struct mbox_msghdr hdr; 1527 u64 secret_key[3]; 1528 }; 1529 1530 enum ptp_op { 1531 PTP_OP_ADJFINE = 0, 1532 PTP_OP_GET_CLOCK = 1, 1533 PTP_OP_GET_TSTMP = 2, 1534 PTP_OP_SET_THRESH = 3, 1535 PTP_OP_EXTTS_ON = 4, 1536 }; 1537 1538 struct ptp_req { 1539 struct mbox_msghdr hdr; 1540 u8 op; 1541 s64 scaled_ppm; 1542 u64 thresh; 1543 int extts_on; 1544 }; 1545 1546 struct ptp_rsp { 1547 struct mbox_msghdr hdr; 1548 u64 clk; 1549 }; 1550 1551 struct npc_get_field_status_req { 1552 struct mbox_msghdr hdr; 1553 u8 intf; 1554 u8 field; 1555 }; 1556 1557 struct npc_get_field_status_rsp { 1558 struct mbox_msghdr hdr; 1559 u8 enable; 1560 }; 1561 1562 struct set_vf_perm { 1563 struct mbox_msghdr hdr; 1564 u16 vf; 1565 #define RESET_VF_PERM BIT_ULL(0) 1566 #define VF_TRUSTED BIT_ULL(1) 1567 u64 flags; 1568 }; 1569 1570 struct lmtst_tbl_setup_req { 1571 struct mbox_msghdr hdr; 1572 u64 dis_sched_early_comp :1; 1573 u64 sch_ena :1; 1574 u64 dis_line_pref :1; 1575 u64 ssow_pf_func :13; 1576 u16 base_pcifunc; 1577 u8 use_local_lmt_region; 1578 u64 lmt_iova; 1579 u64 rsvd[4]; 1580 }; 1581 1582 /* CPT mailbox error codes 1583 * Range 901 - 1000. 1584 */ 1585 enum cpt_af_status { 1586 CPT_AF_ERR_PARAM = -901, 1587 CPT_AF_ERR_GRP_INVALID = -902, 1588 CPT_AF_ERR_LF_INVALID = -903, 1589 CPT_AF_ERR_ACCESS_DENIED = -904, 1590 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1591 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1592 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1593 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1594 }; 1595 1596 /* CPT mbox message formats */ 1597 struct cpt_rd_wr_reg_msg { 1598 struct mbox_msghdr hdr; 1599 u64 reg_offset; 1600 u64 *ret_val; 1601 u64 val; 1602 u8 is_write; 1603 int blkaddr; 1604 }; 1605 1606 struct cpt_lf_alloc_req_msg { 1607 struct mbox_msghdr hdr; 1608 u16 nix_pf_func; 1609 u16 sso_pf_func; 1610 u16 eng_grpmsk; 1611 int blkaddr; 1612 }; 1613 1614 #define CPT_INLINE_INBOUND 0 1615 #define CPT_INLINE_OUTBOUND 1 1616 1617 /* Mailbox message request format for CPT IPsec 1618 * inline inbound and outbound configuration. 1619 */ 1620 struct cpt_inline_ipsec_cfg_msg { 1621 struct mbox_msghdr hdr; 1622 u8 enable; 1623 u8 slot; 1624 u8 dir; 1625 u8 sso_pf_func_ovrd; 1626 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1627 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1628 }; 1629 1630 /* Mailbox message request and response format for CPT stats. */ 1631 struct cpt_sts_req { 1632 struct mbox_msghdr hdr; 1633 u8 blkaddr; 1634 }; 1635 1636 struct cpt_sts_rsp { 1637 struct mbox_msghdr hdr; 1638 u64 inst_req_pc; 1639 u64 inst_lat_pc; 1640 u64 rd_req_pc; 1641 u64 rd_lat_pc; 1642 u64 rd_uc_pc; 1643 u64 active_cycles_pc; 1644 u64 ctx_mis_pc; 1645 u64 ctx_hit_pc; 1646 u64 ctx_aop_pc; 1647 u64 ctx_aop_lat_pc; 1648 u64 ctx_ifetch_pc; 1649 u64 ctx_ifetch_lat_pc; 1650 u64 ctx_ffetch_pc; 1651 u64 ctx_ffetch_lat_pc; 1652 u64 ctx_wback_pc; 1653 u64 ctx_wback_lat_pc; 1654 u64 ctx_psh_pc; 1655 u64 ctx_psh_lat_pc; 1656 u64 ctx_err; 1657 u64 ctx_enc_id; 1658 u64 ctx_flush_timer; 1659 u64 rxc_time; 1660 u64 rxc_time_cfg; 1661 u64 rxc_active_sts; 1662 u64 rxc_zombie_sts; 1663 u64 busy_sts_ae; 1664 u64 free_sts_ae; 1665 u64 busy_sts_se; 1666 u64 free_sts_se; 1667 u64 busy_sts_ie; 1668 u64 free_sts_ie; 1669 u64 exe_err_info; 1670 u64 cptclk_cnt; 1671 u64 diag; 1672 u64 rxc_dfrg; 1673 u64 x2p_link_cfg0; 1674 u64 x2p_link_cfg1; 1675 }; 1676 1677 /* Mailbox message request format to configure reassembly timeout. */ 1678 struct cpt_rxc_time_cfg_req { 1679 struct mbox_msghdr hdr; 1680 int blkaddr; 1681 u32 step; 1682 u16 zombie_thres; 1683 u16 zombie_limit; 1684 u16 active_thres; 1685 u16 active_limit; 1686 }; 1687 1688 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1689 struct cpt_inst_lmtst_req { 1690 struct mbox_msghdr hdr; 1691 u64 inst[8]; 1692 u64 rsvd; 1693 }; 1694 1695 struct sdp_node_info { 1696 /* Node to which this PF belons to */ 1697 u8 node_id; 1698 u8 max_vfs; 1699 u8 num_pf_rings; 1700 u8 pf_srn; 1701 #define SDP_MAX_VFS 128 1702 u8 vf_rings[SDP_MAX_VFS]; 1703 }; 1704 1705 struct sdp_chan_info_msg { 1706 struct mbox_msghdr hdr; 1707 struct sdp_node_info info; 1708 }; 1709 1710 struct sdp_get_chan_info_msg { 1711 struct mbox_msghdr hdr; 1712 u16 chan_base; 1713 u16 num_chan; 1714 }; 1715 1716 /* CGX mailbox error codes 1717 * Range 1101 - 1200. 1718 */ 1719 enum cgx_af_status { 1720 LMAC_AF_ERR_INVALID_PARAM = -1101, 1721 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1722 LMAC_AF_ERR_PERM_DENIED = -1103, 1723 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1724 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1725 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1726 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1727 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1728 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1729 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1730 }; 1731 1732 enum mcs_direction { 1733 MCS_RX, 1734 MCS_TX, 1735 }; 1736 1737 enum mcs_rsrc_type { 1738 MCS_RSRC_TYPE_FLOWID, 1739 MCS_RSRC_TYPE_SECY, 1740 MCS_RSRC_TYPE_SC, 1741 MCS_RSRC_TYPE_SA, 1742 }; 1743 1744 struct mcs_alloc_rsrc_req { 1745 struct mbox_msghdr hdr; 1746 u8 rsrc_type; 1747 u8 rsrc_cnt; /* Resources count */ 1748 u8 mcs_id; /* MCS block ID */ 1749 u8 dir; /* Macsec ingress or egress side */ 1750 u8 all; /* Allocate all resource type one each */ 1751 u64 rsvd; 1752 }; 1753 1754 struct mcs_alloc_rsrc_rsp { 1755 struct mbox_msghdr hdr; 1756 u8 flow_ids[128]; /* Index of reserved entries */ 1757 u8 secy_ids[128]; 1758 u8 sc_ids[128]; 1759 u8 sa_ids[256]; 1760 u8 rsrc_type; 1761 u8 rsrc_cnt; /* No of entries reserved */ 1762 u8 mcs_id; 1763 u8 dir; 1764 u8 all; 1765 u8 rsvd[256]; /* reserved fields for future expansion */ 1766 }; 1767 1768 struct mcs_free_rsrc_req { 1769 struct mbox_msghdr hdr; 1770 u8 rsrc_id; /* Index of the entry to be freed */ 1771 u8 rsrc_type; 1772 u8 mcs_id; 1773 u8 dir; 1774 u8 all; /* Free all the cam resources */ 1775 u64 rsvd; 1776 }; 1777 1778 struct mcs_flowid_entry_write_req { 1779 struct mbox_msghdr hdr; 1780 u64 data[4]; 1781 u64 mask[4]; 1782 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1783 u8 flow_id; 1784 u8 secy_id; /* secyid for which flowid is mapped */ 1785 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1786 u8 ena; /* Enable tcam entry */ 1787 u8 ctrl_pkt; 1788 u8 mcs_id; 1789 u8 dir; 1790 u64 rsvd; 1791 }; 1792 1793 struct mcs_secy_plcy_write_req { 1794 struct mbox_msghdr hdr; 1795 u64 plcy; 1796 u8 secy_id; 1797 u8 mcs_id; 1798 u8 dir; 1799 u64 rsvd; 1800 }; 1801 1802 /* RX SC_CAM mapping */ 1803 struct mcs_rx_sc_cam_write_req { 1804 struct mbox_msghdr hdr; 1805 u64 sci; /* SCI */ 1806 u64 secy_id; /* secy index mapped to SC */ 1807 u8 sc_id; /* SC CAM entry index */ 1808 u8 mcs_id; 1809 u64 rsvd; 1810 }; 1811 1812 struct mcs_sa_plcy_write_req { 1813 struct mbox_msghdr hdr; 1814 u64 plcy[2][9]; /* Support 2 SA policy */ 1815 u8 sa_index[2]; 1816 u8 sa_cnt; 1817 u8 mcs_id; 1818 u8 dir; 1819 u64 rsvd; 1820 }; 1821 1822 struct mcs_tx_sc_sa_map { 1823 struct mbox_msghdr hdr; 1824 u8 sa_index0; 1825 u8 sa_index1; 1826 u8 rekey_ena; 1827 u8 sa_index0_vld; 1828 u8 sa_index1_vld; 1829 u8 tx_sa_active; 1830 u64 sectag_sci; 1831 u8 sc_id; /* used as index for SA_MEM_MAP */ 1832 u8 mcs_id; 1833 u64 rsvd; 1834 }; 1835 1836 struct mcs_rx_sc_sa_map { 1837 struct mbox_msghdr hdr; 1838 u8 sa_index; 1839 u8 sa_in_use; 1840 u8 sc_id; 1841 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1842 u8 mcs_id; 1843 u64 rsvd; 1844 }; 1845 1846 struct mcs_flowid_ena_dis_entry { 1847 struct mbox_msghdr hdr; 1848 u8 flow_id; 1849 u8 ena; 1850 u8 mcs_id; 1851 u8 dir; 1852 u64 rsvd; 1853 }; 1854 1855 struct mcs_pn_table_write_req { 1856 struct mbox_msghdr hdr; 1857 u64 next_pn; 1858 u8 pn_id; 1859 u8 mcs_id; 1860 u8 dir; 1861 u64 rsvd; 1862 }; 1863 1864 struct mcs_hw_info { 1865 struct mbox_msghdr hdr; 1866 u8 num_mcs_blks; /* Number of MCS blocks */ 1867 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1868 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1869 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1870 u8 sa_entries; /* PN table entries = SA entries */ 1871 u64 rsvd[16]; 1872 }; 1873 1874 struct mcs_set_active_lmac { 1875 struct mbox_msghdr hdr; 1876 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1877 u8 mcs_id; 1878 u16 chan_base; /* MCS channel base */ 1879 u64 rsvd; 1880 }; 1881 1882 struct mcs_set_lmac_mode { 1883 struct mbox_msghdr hdr; 1884 u8 mode; /* 1:Bypass 0:Operational */ 1885 u8 lmac_id; 1886 u8 mcs_id; 1887 u64 rsvd; 1888 }; 1889 1890 struct mcs_port_reset_req { 1891 struct mbox_msghdr hdr; 1892 u8 reset; 1893 u8 mcs_id; 1894 u8 port_id; 1895 u64 rsvd; 1896 }; 1897 1898 struct mcs_port_cfg_set_req { 1899 struct mbox_msghdr hdr; 1900 u8 cstm_tag_rel_mode_sel; 1901 u8 custom_hdr_enb; 1902 u8 fifo_skid; 1903 u8 port_mode; 1904 u8 port_id; 1905 u8 mcs_id; 1906 u64 rsvd; 1907 }; 1908 1909 struct mcs_port_cfg_get_req { 1910 struct mbox_msghdr hdr; 1911 u8 port_id; 1912 u8 mcs_id; 1913 u64 rsvd; 1914 }; 1915 1916 struct mcs_port_cfg_get_rsp { 1917 struct mbox_msghdr hdr; 1918 u8 cstm_tag_rel_mode_sel; 1919 u8 custom_hdr_enb; 1920 u8 fifo_skid; 1921 u8 port_mode; 1922 u8 port_id; 1923 u8 mcs_id; 1924 u64 rsvd; 1925 }; 1926 1927 struct mcs_custom_tag_cfg_get_req { 1928 struct mbox_msghdr hdr; 1929 u8 mcs_id; 1930 u8 dir; 1931 u64 rsvd; 1932 }; 1933 1934 struct mcs_custom_tag_cfg_get_rsp { 1935 struct mbox_msghdr hdr; 1936 u16 cstm_etype[8]; 1937 u8 cstm_indx[8]; 1938 u8 cstm_etype_en; 1939 u8 mcs_id; 1940 u8 dir; 1941 u64 rsvd; 1942 }; 1943 1944 /* MCS mailbox error codes 1945 * Range 1201 - 1300. 1946 */ 1947 enum mcs_af_status { 1948 MCS_AF_ERR_INVALID_MCSID = -1201, 1949 MCS_AF_ERR_NOT_MAPPED = -1202, 1950 }; 1951 1952 struct mcs_set_pn_threshold { 1953 struct mbox_msghdr hdr; 1954 u64 threshold; 1955 u8 xpn; /* '1' for setting xpn threshold */ 1956 u8 mcs_id; 1957 u8 dir; 1958 u64 rsvd; 1959 }; 1960 1961 enum mcs_ctrl_pkt_rulew_type { 1962 MCS_CTRL_PKT_RULE_TYPE_ETH, 1963 MCS_CTRL_PKT_RULE_TYPE_DA, 1964 MCS_CTRL_PKT_RULE_TYPE_RANGE, 1965 MCS_CTRL_PKT_RULE_TYPE_COMBO, 1966 MCS_CTRL_PKT_RULE_TYPE_MAC, 1967 }; 1968 1969 struct mcs_alloc_ctrl_pkt_rule_req { 1970 struct mbox_msghdr hdr; 1971 u8 rule_type; 1972 u8 mcs_id; /* MCS block ID */ 1973 u8 dir; /* Macsec ingress or egress side */ 1974 u64 rsvd; 1975 }; 1976 1977 struct mcs_alloc_ctrl_pkt_rule_rsp { 1978 struct mbox_msghdr hdr; 1979 u8 rule_idx; 1980 u8 rule_type; 1981 u8 mcs_id; 1982 u8 dir; 1983 u64 rsvd; 1984 }; 1985 1986 struct mcs_free_ctrl_pkt_rule_req { 1987 struct mbox_msghdr hdr; 1988 u8 rule_idx; 1989 u8 rule_type; 1990 u8 mcs_id; 1991 u8 dir; 1992 u8 all; 1993 u64 rsvd; 1994 }; 1995 1996 struct mcs_ctrl_pkt_rule_write_req { 1997 struct mbox_msghdr hdr; 1998 u64 data0; 1999 u64 data1; 2000 u64 data2; 2001 u8 rule_idx; 2002 u8 rule_type; 2003 u8 mcs_id; 2004 u8 dir; 2005 u64 rsvd; 2006 }; 2007 2008 struct mcs_stats_req { 2009 struct mbox_msghdr hdr; 2010 u8 id; 2011 u8 mcs_id; 2012 u8 dir; 2013 u64 rsvd; 2014 }; 2015 2016 struct mcs_flowid_stats { 2017 struct mbox_msghdr hdr; 2018 u64 tcam_hit_cnt; 2019 u64 rsvd; 2020 }; 2021 2022 struct mcs_secy_stats { 2023 struct mbox_msghdr hdr; 2024 u64 ctl_pkt_bcast_cnt; 2025 u64 ctl_pkt_mcast_cnt; 2026 u64 ctl_pkt_ucast_cnt; 2027 u64 ctl_octet_cnt; 2028 u64 unctl_pkt_bcast_cnt; 2029 u64 unctl_pkt_mcast_cnt; 2030 u64 unctl_pkt_ucast_cnt; 2031 u64 unctl_octet_cnt; 2032 /* Valid only for RX */ 2033 u64 octet_decrypted_cnt; 2034 u64 octet_validated_cnt; 2035 u64 pkt_port_disabled_cnt; 2036 u64 pkt_badtag_cnt; 2037 u64 pkt_nosa_cnt; 2038 u64 pkt_nosaerror_cnt; 2039 u64 pkt_tagged_ctl_cnt; 2040 u64 pkt_untaged_cnt; 2041 u64 pkt_ctl_cnt; /* CN10K-B */ 2042 u64 pkt_notag_cnt; /* CNF10K-B */ 2043 /* Valid only for TX */ 2044 u64 octet_encrypted_cnt; 2045 u64 octet_protected_cnt; 2046 u64 pkt_noactivesa_cnt; 2047 u64 pkt_toolong_cnt; 2048 u64 pkt_untagged_cnt; 2049 u64 rsvd[4]; 2050 }; 2051 2052 struct mcs_port_stats { 2053 struct mbox_msghdr hdr; 2054 u64 tcam_miss_cnt; 2055 u64 parser_err_cnt; 2056 u64 preempt_err_cnt; /* CNF10K-B */ 2057 u64 sectag_insert_err_cnt; 2058 u64 rsvd[4]; 2059 }; 2060 2061 /* Only for CN10K-B */ 2062 struct mcs_sa_stats { 2063 struct mbox_msghdr hdr; 2064 /* RX */ 2065 u64 pkt_invalid_cnt; 2066 u64 pkt_nosaerror_cnt; 2067 u64 pkt_notvalid_cnt; 2068 u64 pkt_ok_cnt; 2069 u64 pkt_nosa_cnt; 2070 /* TX */ 2071 u64 pkt_encrypt_cnt; 2072 u64 pkt_protected_cnt; 2073 u64 rsvd[4]; 2074 }; 2075 2076 struct mcs_sc_stats { 2077 struct mbox_msghdr hdr; 2078 /* RX */ 2079 u64 hit_cnt; 2080 u64 pkt_invalid_cnt; 2081 u64 pkt_late_cnt; 2082 u64 pkt_notvalid_cnt; 2083 u64 pkt_unchecked_cnt; 2084 u64 pkt_delay_cnt; /* CNF10K-B */ 2085 u64 pkt_ok_cnt; /* CNF10K-B */ 2086 u64 octet_decrypt_cnt; /* CN10K-B */ 2087 u64 octet_validate_cnt; /* CN10K-B */ 2088 /* TX */ 2089 u64 pkt_encrypt_cnt; 2090 u64 pkt_protected_cnt; 2091 u64 octet_encrypt_cnt; /* CN10K-B */ 2092 u64 octet_protected_cnt; /* CN10K-B */ 2093 u64 rsvd[4]; 2094 }; 2095 2096 struct mcs_clear_stats { 2097 struct mbox_msghdr hdr; 2098 #define MCS_FLOWID_STATS 0 2099 #define MCS_SECY_STATS 1 2100 #define MCS_SC_STATS 2 2101 #define MCS_SA_STATS 3 2102 #define MCS_PORT_STATS 4 2103 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2104 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2105 u8 mcs_id; 2106 u8 dir; 2107 u8 all; /* All resources stats mapped to PF are cleared */ 2108 }; 2109 2110 struct mcs_intr_cfg { 2111 struct mbox_msghdr hdr; 2112 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2113 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2114 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2115 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2116 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2117 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2118 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2119 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2120 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2121 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2122 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2123 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2124 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2125 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2126 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2127 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2128 u64 intr_mask; /* Interrupt enable mask */ 2129 u8 mcs_id; 2130 u8 lmac_id; 2131 u64 rsvd; 2132 }; 2133 2134 struct mcs_intr_info { 2135 struct mbox_msghdr hdr; 2136 u64 intr_mask; 2137 int sa_id; 2138 u8 mcs_id; 2139 u8 lmac_id; 2140 u64 rsvd; 2141 }; 2142 2143 #endif /* MBOX_H */ 2144