1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell MCS driver 3 * 4 * Copyright (C) 2022 Marvell. 5 */ 6 7 #ifndef MCS_REG_H 8 #define MCS_REG_H 9 10 #include <linux/bits.h> 11 12 /* Registers */ 13 #define MCSX_IP_MODE 0x900c8ull 14 #define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({ \ 15 u64 offset; \ 16 \ 17 offset = 0x408ull; \ 18 if (mcs->hw->mcs_blks > 1) \ 19 offset = 0xa28ull; \ 20 offset += (a) * 0x8ull; \ 21 offset; }) 22 23 24 #define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({ \ 25 u64 offset; \ 26 \ 27 offset = 0x808ull; \ 28 if (mcs->hw->mcs_blks > 1) \ 29 offset = 0xa68ull; \ 30 offset += (a) * 0x8ull; \ 31 offset; }) 32 33 #define MCSX_MIL_GLOBAL ({ \ 34 u64 offset; \ 35 \ 36 offset = 0x80000ull; \ 37 if (mcs->hw->mcs_blks > 1) \ 38 offset = 0x60000ull; \ 39 offset; }) 40 41 #define MCSX_MIL_RX_LMACX_CFG(a) ({ \ 42 u64 offset; \ 43 \ 44 offset = 0x900a8ull; \ 45 if (mcs->hw->mcs_blks > 1) \ 46 offset = 0x700a8ull; \ 47 offset += (a) * 0x800ull; \ 48 offset; }) 49 50 #define MCSX_HIL_GLOBAL ({ \ 51 u64 offset; \ 52 \ 53 offset = 0xc0000ull; \ 54 if (mcs->hw->mcs_blks > 1) \ 55 offset = 0xa0000ull; \ 56 offset; }) 57 58 #define MCSX_LINK_LMACX_CFG(a) ({ \ 59 u64 offset; \ 60 \ 61 offset = 0x90000ull; \ 62 if (mcs->hw->mcs_blks > 1) \ 63 offset = 0x70000ull; \ 64 offset += (a) * 0x800ull; \ 65 offset; }) 66 67 #define MCSX_MIL_RX_GBL_STATUS ({ \ 68 u64 offset; \ 69 \ 70 offset = 0x800c8ull; \ 71 if (mcs->hw->mcs_blks > 1) \ 72 offset = 0x600c8ull; \ 73 offset; }) 74 75 #define MCSX_MIL_IP_GBL_STATUS ({ \ 76 u64 offset; \ 77 \ 78 offset = 0x800d0ull; \ 79 if (mcs->hw->mcs_blks > 1) \ 80 offset = 0x600d0ull; \ 81 offset; }) 82 83 /* PAB */ 84 #define MCSX_PAB_RX_SLAVE_PORT_CFGX(a) ({ \ 85 u64 offset; \ 86 \ 87 offset = 0x1718ull; \ 88 if (mcs->hw->mcs_blks > 1) \ 89 offset = 0x280ull; \ 90 offset += (a) * 0x40ull; \ 91 offset; }) 92 93 #define MCSX_PAB_TX_SLAVE_PORT_CFGX(a) (0x2930ull + (a) * 0x40ull) 94 95 /* PEX registers */ 96 #define MCSX_PEX_RX_SLAVE_VLAN_CFGX(a) (0x3b58ull + (a) * 0x8ull) 97 #define MCSX_PEX_TX_SLAVE_VLAN_CFGX(a) (0x46f8ull + (a) * 0x8ull) 98 #define MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(a) (0x788ull + (a) * 0x8ull) 99 #define MCSX_PEX_TX_SLAVE_PORT_CONFIG(a) (0x4738ull + (a) * 0x8ull) 100 #define MCSX_PEX_RX_SLAVE_RULE_ETYPE_CFGX(a) ({ \ 101 u64 offset; \ 102 \ 103 offset = 0x3fc0ull; \ 104 if (mcs->hw->mcs_blks > 1) \ 105 offset = 0x558ull; \ 106 offset += (a) * 0x8ull; \ 107 offset; }) 108 109 #define MCSX_PEX_RX_SLAVE_RULE_DAX(a) ({ \ 110 u64 offset; \ 111 \ 112 offset = 0x4000ull; \ 113 if (mcs->hw->mcs_blks > 1) \ 114 offset = 0x598ull; \ 115 offset += (a) * 0x8ull; \ 116 offset; }) 117 118 #define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MINX(a) ({ \ 119 u64 offset; \ 120 \ 121 offset = 0x4040ull; \ 122 if (mcs->hw->mcs_blks > 1) \ 123 offset = 0x5d8ull; \ 124 offset += (a) * 0x8ull; \ 125 offset; }) 126 127 #define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MAXX(a) ({ \ 128 u64 offset; \ 129 \ 130 offset = 0x4048ull; \ 131 if (mcs->hw->mcs_blks > 1) \ 132 offset = 0x5e0ull; \ 133 offset += (a) * 0x8ull; \ 134 offset; }) 135 136 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_MINX(a) ({ \ 137 u64 offset; \ 138 \ 139 offset = 0x4080ull; \ 140 if (mcs->hw->mcs_blks > 1) \ 141 offset = 0x648ull; \ 142 offset += (a) * 0x8ull; \ 143 offset; }) 144 145 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_MAXX(a) ({ \ 146 u64 offset; \ 147 \ 148 offset = 0x4088ull; \ 149 if (mcs->hw->mcs_blks > 1) \ 150 offset = 0x650ull; \ 151 offset += (a) * 0x8ull; \ 152 offset; }) 153 154 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_ETX(a) ({ \ 155 u64 offset; \ 156 \ 157 offset = 0x4090ull; \ 158 if (mcs->hw->mcs_blks > 1) \ 159 offset = 0x658ull; \ 160 offset += (a) * 0x8ull; \ 161 offset; }) 162 163 #define MCSX_PEX_RX_SLAVE_RULE_MAC ({ \ 164 u64 offset; \ 165 \ 166 offset = 0x40e0ull; \ 167 if (mcs->hw->mcs_blks > 1) \ 168 offset = 0x6d8ull; \ 169 offset; }) 170 171 #define MCSX_PEX_RX_SLAVE_RULE_ENABLE ({ \ 172 u64 offset; \ 173 \ 174 offset = 0x40e8ull; \ 175 if (mcs->hw->mcs_blks > 1) \ 176 offset = 0x6e0ull; \ 177 offset; }) 178 179 #define MCSX_PEX_TX_SLAVE_RULE_ETYPE_CFGX(a) ({ \ 180 u64 offset; \ 181 \ 182 offset = 0x4b60ull; \ 183 if (mcs->hw->mcs_blks > 1) \ 184 offset = 0x7d8ull; \ 185 offset += (a) * 0x8ull; \ 186 offset; }) 187 188 #define MCSX_PEX_TX_SLAVE_RULE_DAX(a) ({ \ 189 u64 offset; \ 190 \ 191 offset = 0x4ba0ull; \ 192 if (mcs->hw->mcs_blks > 1) \ 193 offset = 0x818ull; \ 194 offset += (a) * 0x8ull; \ 195 offset; }) 196 197 #define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MINX(a) ({ \ 198 u64 offset; \ 199 \ 200 offset = 0x4be0ull; \ 201 if (mcs->hw->mcs_blks > 1) \ 202 offset = 0x858ull; \ 203 offset += (a) * 0x8ull; \ 204 offset; }) 205 206 #define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MAXX(a) ({ \ 207 u64 offset; \ 208 \ 209 offset = 0x4be8ull; \ 210 if (mcs->hw->mcs_blks > 1) \ 211 offset = 0x860ull; \ 212 offset += (a) * 0x8ull; \ 213 offset; }) 214 215 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_MINX(a) ({ \ 216 u64 offset; \ 217 \ 218 offset = 0x4c20ull; \ 219 if (mcs->hw->mcs_blks > 1) \ 220 offset = 0x8c8ull; \ 221 offset += (a) * 0x8ull; \ 222 offset; }) 223 224 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_MAXX(a) ({ \ 225 u64 offset; \ 226 \ 227 offset = 0x4c28ull; \ 228 if (mcs->hw->mcs_blks > 1) \ 229 offset = 0x8d0ull; \ 230 offset += (a) * 0x8ull; \ 231 offset; }) 232 233 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_ETX(a) ({ \ 234 u64 offset; \ 235 \ 236 offset = 0x4c30ull; \ 237 if (mcs->hw->mcs_blks > 1) \ 238 offset = 0x8d8ull; \ 239 offset += (a) * 0x8ull; \ 240 offset; }) 241 242 #define MCSX_PEX_TX_SLAVE_RULE_MAC ({ \ 243 u64 offset; \ 244 \ 245 offset = 0x4c80ull; \ 246 if (mcs->hw->mcs_blks > 1) \ 247 offset = 0x958ull; \ 248 offset; }) 249 250 #define MCSX_PEX_TX_SLAVE_RULE_ENABLE ({ \ 251 u64 offset; \ 252 \ 253 offset = 0x4c88ull; \ 254 if (mcs->hw->mcs_blks > 1) \ 255 offset = 0x960ull; \ 256 offset; }) 257 258 #define MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION ({ \ 259 u64 offset; \ 260 \ 261 offset = 0x3b50ull; \ 262 if (mcs->hw->mcs_blks > 1) \ 263 offset = 0x4c0ull; \ 264 offset; }) 265 266 /* CNF10K-B */ 267 #define MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(a) (0x4c8ull + (a) * 0x8ull) 268 #define MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(a) (0x748ull + (a) * 0x8ull) 269 #define MCSX_PEX_RX_SLAVE_ETYPE_ENABLE 0x6e8ull 270 #define MCSX_PEX_TX_SLAVE_ETYPE_ENABLE 0x968ull 271 272 /* BEE */ 273 #define MCSX_BBE_RX_SLAVE_PADDING_CTL 0xe08ull 274 #define MCSX_BBE_TX_SLAVE_PADDING_CTL 0x12f8ull 275 #define MCSX_BBE_RX_SLAVE_CAL_ENTRY 0x180ull 276 #define MCSX_BBE_RX_SLAVE_CAL_LEN 0x188ull 277 #define MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(a) (0x290ull + (a) * 0x40ull) 278 279 #define MCSX_BBE_RX_SLAVE_BBE_INT ({ \ 280 u64 offset; \ 281 \ 282 offset = 0xe00ull; \ 283 if (mcs->hw->mcs_blks > 1) \ 284 offset = 0x160ull; \ 285 offset; }) 286 287 #define MCSX_BBE_RX_SLAVE_BBE_INT_ENB ({ \ 288 u64 offset; \ 289 \ 290 offset = 0xe08ull; \ 291 if (mcs->hw->mcs_blks > 1) \ 292 offset = 0x168ull; \ 293 offset; }) 294 295 #define MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW ({ \ 296 u64 offset; \ 297 \ 298 offset = 0xe08ull; \ 299 if (mcs->hw->mcs_blks > 1) \ 300 offset = 0x178ull; \ 301 offset; }) 302 303 #define MCSX_BBE_TX_SLAVE_BBE_INT ({ \ 304 u64 offset; \ 305 \ 306 offset = 0x1278ull; \ 307 if (mcs->hw->mcs_blks > 1) \ 308 offset = 0x1e0ull; \ 309 offset; }) 310 311 #define MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW ({ \ 312 u64 offset; \ 313 \ 314 offset = 0x1278ull; \ 315 if (mcs->hw->mcs_blks > 1) \ 316 offset = 0x1f8ull; \ 317 offset; }) 318 319 #define MCSX_BBE_TX_SLAVE_BBE_INT_ENB ({ \ 320 u64 offset; \ 321 \ 322 offset = 0x1280ull; \ 323 if (mcs->hw->mcs_blks > 1) \ 324 offset = 0x1e8ull; \ 325 offset; }) 326 327 #define MCSX_PAB_RX_SLAVE_PAB_INT ({ \ 328 u64 offset; \ 329 \ 330 offset = 0x16f0ull; \ 331 if (mcs->hw->mcs_blks > 1) \ 332 offset = 0x260ull; \ 333 offset; }) 334 335 #define MCSX_PAB_RX_SLAVE_PAB_INT_ENB ({ \ 336 u64 offset; \ 337 \ 338 offset = 0x16f8ull; \ 339 if (mcs->hw->mcs_blks > 1) \ 340 offset = 0x268ull; \ 341 offset; }) 342 343 #define MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW ({ \ 344 u64 offset; \ 345 \ 346 offset = 0x16f8ull; \ 347 if (mcs->hw->mcs_blks > 1) \ 348 offset = 0x278ull; \ 349 offset; }) 350 351 #define MCSX_PAB_TX_SLAVE_PAB_INT ({ \ 352 u64 offset; \ 353 \ 354 offset = 0x2908ull; \ 355 if (mcs->hw->mcs_blks > 1) \ 356 offset = 0x380ull; \ 357 offset; }) 358 359 #define MCSX_PAB_TX_SLAVE_PAB_INT_ENB ({ \ 360 u64 offset; \ 361 \ 362 offset = 0x2910ull; \ 363 if (mcs->hw->mcs_blks > 1) \ 364 offset = 0x388ull; \ 365 offset; }) 366 367 #define MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW ({ \ 368 u64 offset; \ 369 \ 370 offset = 0x16f8ull; \ 371 if (mcs->hw->mcs_blks > 1) \ 372 offset = 0x398ull; \ 373 offset; }) 374 375 /* CPM registers */ 376 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({ \ 377 u64 offset; \ 378 \ 379 offset = 0x30740ull; \ 380 if (mcs->hw->mcs_blks > 1) \ 381 offset = 0x3bf8ull; \ 382 offset += (a) * 0x8ull + (b) * 0x20ull; \ 383 offset; }) 384 385 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({ \ 386 u64 offset; \ 387 \ 388 offset = 0x34740ull; \ 389 if (mcs->hw->mcs_blks > 1) \ 390 offset = 0x43f8ull; \ 391 offset += (a) * 0x8ull + (b) * 0x20ull; \ 392 offset; }) 393 394 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_0 ({ \ 395 u64 offset; \ 396 \ 397 offset = 0x30700ull; \ 398 if (mcs->hw->mcs_blks > 1) \ 399 offset = 0x3bd8ull; \ 400 offset; }) 401 402 #define MCSX_CPM_RX_SLAVE_SC_CAMX(a, b) ({ \ 403 u64 offset; \ 404 \ 405 offset = 0x38780ull; \ 406 if (mcs->hw->mcs_blks > 1) \ 407 offset = 0x4c08ull; \ 408 offset += (a) * 0x8ull + (b) * 0x10ull; \ 409 offset; }) 410 411 #define MCSX_CPM_RX_SLAVE_SC_CAM_ENA(a) ({ \ 412 u64 offset; \ 413 \ 414 offset = 0x38740ull + (a) * 0x8ull; \ 415 if (mcs->hw->mcs_blks > 1) \ 416 offset = 0x4bf8ull; \ 417 offset; }) 418 419 #define MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(a) ({ \ 420 u64 offset; \ 421 \ 422 offset = 0x23ee0ull; \ 423 if (mcs->hw->mcs_blks > 1) \ 424 offset = 0xbd0ull; \ 425 offset += (a) * 0x8ull; \ 426 offset; }) 427 428 #define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_0X(a) ({ \ 429 u64 offset; \ 430 \ 431 offset = (0x246e0ull + (a) * 0x10ull); \ 432 if (mcs->hw->mcs_blks > 1) \ 433 offset = (0xdd0ull + (a) * 0x8ull); \ 434 offset; }) 435 436 #define MCSX_CPM_RX_SLAVE_SA_KEY_LOCKOUTX(a) ({ \ 437 u64 offset; \ 438 \ 439 offset = 0x23E90ull; \ 440 if (mcs->hw->mcs_blks > 1) \ 441 offset = 0xbb0ull; \ 442 offset += (a) * 0x8ull; \ 443 offset; }) 444 445 #define MCSX_CPM_RX_SLAVE_SA_MAP_MEMX(a) ({ \ 446 u64 offset; \ 447 \ 448 offset = 0x256e0ull; \ 449 if (mcs->hw->mcs_blks > 1) \ 450 offset = 0xfd0ull; \ 451 offset += (a) * 0x8ull; \ 452 offset; }) 453 454 #define MCSX_CPM_RX_SLAVE_SA_PLCY_MEMX(a, b) ({ \ 455 u64 offset; \ 456 \ 457 offset = 0x27700ull; \ 458 if (mcs->hw->mcs_blks > 1) \ 459 offset = 0x17d8ull; \ 460 offset += (a) * 0x8ull + (b) * 0x40ull; \ 461 offset; }) 462 463 #define MCSX_CPM_RX_SLAVE_SA_PN_TABLE_MEMX(a) ({ \ 464 u64 offset; \ 465 \ 466 offset = 0x2f700ull; \ 467 if (mcs->hw->mcs_blks > 1) \ 468 offset = 0x37d8; \ 469 offset += (a) * 0x8ull; \ 470 offset; }) 471 472 #define MCSX_CPM_RX_SLAVE_XPN_THRESHOLD ({ \ 473 u64 offset; \ 474 \ 475 offset = 0x23e40ull; \ 476 if (mcs->hw->mcs_blks > 1) \ 477 offset = 0xb90ull; \ 478 offset; }) 479 480 #define MCSX_CPM_RX_SLAVE_PN_THRESHOLD ({ \ 481 u64 offset; \ 482 \ 483 offset = 0x23e48ull; \ 484 if (mcs->hw->mcs_blks > 1) \ 485 offset = 0xb98ull; \ 486 offset; }) 487 488 #define MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(a) ({ \ 489 u64 offset; \ 490 \ 491 offset = 0x23e50ull; \ 492 if (mcs->hw->mcs_blks > 1) \ 493 offset = 0xba0ull; \ 494 offset += (a) * 0x8ull; \ 495 offset; }) 496 497 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_1 0x30708ull 498 #define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(a) (0x246e8ull + (a) * 0x10ull) 499 500 /* TX registers */ 501 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({ \ 502 u64 offset; \ 503 \ 504 offset = 0x51d50ull; \ 505 if (mcs->hw->mcs_blks > 1) \ 506 offset = 0xa7c0ull; \ 507 offset += (a) * 0x8ull + (b) * 0x20ull; \ 508 offset; }) 509 510 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({ \ 511 u64 offset; \ 512 \ 513 offset = 0x55d50ull; \ 514 if (mcs->hw->mcs_blks > 1) \ 515 offset = 0xafc0ull; \ 516 offset += (a) * 0x8ull + (b) * 0x20ull; \ 517 offset; }) 518 519 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_0 ({ \ 520 u64 offset; \ 521 \ 522 offset = 0x51d10ull; \ 523 if (mcs->hw->mcs_blks > 1) \ 524 offset = 0xa7a0ull; \ 525 offset; }) 526 527 #define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(a) ({ \ 528 u64 offset; \ 529 \ 530 offset = 0x3e508ull + (a) * 0x8ull; \ 531 if (mcs->hw->mcs_blks > 1) \ 532 offset = 0x5550ull + (a) * 0x10ull; \ 533 offset; }) 534 535 #define MCSX_CPM_TX_SLAVE_SECY_PLCY_MEMX(a) ({ \ 536 u64 offset; \ 537 \ 538 offset = 0x3ed08ull; \ 539 if (mcs->hw->mcs_blks > 1) \ 540 offset = 0x5950ull; \ 541 offset += (a) * 0x8ull; \ 542 offset; }) 543 544 #define MCSX_CPM_TX_SLAVE_SA_KEY_LOCKOUTX(a) ({ \ 545 u64 offset; \ 546 \ 547 offset = 0x3e4c0ull; \ 548 if (mcs->hw->mcs_blks > 1) \ 549 offset = 0x5538ull; \ 550 offset += (a) * 0x8ull; \ 551 offset; }) 552 553 #define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(a) ({ \ 554 u64 offset; \ 555 \ 556 offset = 0x3fd10ull + (a) * 0x10ull; \ 557 if (mcs->hw->mcs_blks > 1) \ 558 offset = 0x6150ull + (a) * 0x8ull; \ 559 offset; }) 560 561 #define MCSX_CPM_TX_SLAVE_SA_PLCY_MEMX(a, b) ({ \ 562 u64 offset; \ 563 \ 564 offset = 0x40d10ull; \ 565 if (mcs->hw->mcs_blks > 1) \ 566 offset = 0x63a0ull; \ 567 offset += (a) * 0x8ull + (b) * 0x80ull; \ 568 offset; }) 569 570 #define MCSX_CPM_TX_SLAVE_SA_PN_TABLE_MEMX(a) ({ \ 571 u64 offset; \ 572 \ 573 offset = 0x50d10ull; \ 574 if (mcs->hw->mcs_blks > 1) \ 575 offset = 0xa3a0ull; \ 576 offset += (a) * 0x8ull; \ 577 offset; }) 578 579 #define MCSX_CPM_TX_SLAVE_XPN_THRESHOLD ({ \ 580 u64 offset; \ 581 \ 582 offset = 0x3e4b0ull; \ 583 if (mcs->hw->mcs_blks > 1) \ 584 offset = 0x5528ull; \ 585 offset; }) 586 587 #define MCSX_CPM_TX_SLAVE_PN_THRESHOLD ({ \ 588 u64 offset; \ 589 \ 590 offset = 0x3e4b8ull; \ 591 if (mcs->hw->mcs_blks > 1) \ 592 offset = 0x5530ull; \ 593 offset; }) 594 595 #define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_1X(a) (0x3fd18ull + (a) * 0x10ull) 596 #define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(a) (0x5558ull + (a) * 0x10ull) 597 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_1 0x51d18ull 598 #define MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(a) (0x5b50 + (a) * 0x8ull) 599 #define MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(a) (0x5d50 + (a) * 0x8ull) 600 #define MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(a) (0x5f50 + (a) * 0x8ull) 601 #define MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0 0x5500ull 602 603 /* CSE */ 604 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLBCPKTSX(a) ({ \ 605 u64 offset; \ 606 \ 607 offset = 0x9e80ull; \ 608 if (mcs->hw->mcs_blks > 1) \ 609 offset = 0xc218ull; \ 610 offset += (a) * 0x8ull; \ 611 offset; }) 612 613 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLMCPKTSX(a) ({ \ 614 u64 offset; \ 615 \ 616 offset = 0x9680ull; \ 617 if (mcs->hw->mcs_blks > 1) \ 618 offset = 0xc018ull; \ 619 offset += (a) * 0x8ull; \ 620 offset; }) 621 622 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLOCTETSX(a) ({ \ 623 u64 offset; \ 624 \ 625 offset = 0x6e80ull; \ 626 if (mcs->hw->mcs_blks > 1) \ 627 offset = 0xbc18ull; \ 628 offset += (a) * 0x8ull; \ 629 offset; }) 630 631 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLUCPKTSX(a) ({ \ 632 u64 offset; \ 633 \ 634 offset = 0x8e80ull; \ 635 if (mcs->hw->mcs_blks > 1) \ 636 offset = 0xbe18ull; \ 637 offset += (a) * 0x8ull; \ 638 offset; }) 639 640 #define MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLBCPKTSX(a) ({ \ 641 u64 offset; \ 642 \ 643 offset = 0x8680ull; \ 644 if (mcs->hw->mcs_blks > 1) \ 645 offset = 0xca18ull; \ 646 offset += (a) * 0x8ull; \ 647 offset; }) 648 649 #define MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLMCPKTSX(a) ({ \ 650 u64 offset; \ 651 \ 652 offset = 0x7e80ull; \ 653 if (mcs->hw->mcs_blks > 1) \ 654 offset = 0xc818ull; \ 655 offset += (a) * 0x8ull; \ 656 offset; }) 657 658 #define MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLOCTETSX(a) ({ \ 659 u64 offset; \ 660 \ 661 offset = 0x6680ull; \ 662 if (mcs->hw->mcs_blks > 1) \ 663 offset = 0xc418ull; \ 664 offset += (a) * 0x8ull; \ 665 offset; }) 666 667 #define MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLUCPKTSX(a) ({ \ 668 u64 offset; \ 669 \ 670 offset = 0x7680ull; \ 671 if (mcs->hw->mcs_blks > 1) \ 672 offset = 0xc618ull; \ 673 offset += (a) * 0x8ull; \ 674 offset; }) 675 676 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYDECRYPTEDX(a) ({ \ 677 u64 offset; \ 678 \ 679 offset = 0x5e80ull; \ 680 if (mcs->hw->mcs_blks > 1) \ 681 offset = 0xdc18ull; \ 682 offset += (a) * 0x8ull; \ 683 offset; }) 684 685 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYVALIDATEX(a)({ \ 686 u64 offset; \ 687 \ 688 offset = 0x5680ull; \ 689 if (mcs->hw->mcs_blks > 1) \ 690 offset = 0xda18ull; \ 691 offset += (a) * 0x8ull; \ 692 offset; }) 693 694 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSCTRLPORTDISABLEDX(a) ({ \ 695 u64 offset; \ 696 \ 697 offset = 0xd680ull; \ 698 if (mcs->hw->mcs_blks > 1) \ 699 offset = 0xce18ull; \ 700 offset += (a) * 0x8ull; \ 701 offset; }) 702 703 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMHITX(a) ({ \ 704 u64 offset; \ 705 \ 706 offset = 0x16a80ull; \ 707 if (mcs->hw->mcs_blks > 1) \ 708 offset = 0xec78ull; \ 709 offset += (a) * 0x8ull; \ 710 offset; }) 711 712 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMMISSX(a) ({ \ 713 u64 offset; \ 714 \ 715 offset = 0x16680ull; \ 716 if (mcs->hw->mcs_blks > 1) \ 717 offset = 0xec38ull; \ 718 offset += (a) * 0x8ull; \ 719 offset; }) 720 721 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSPARSEERRX(a) ({ \ 722 u64 offset; \ 723 \ 724 offset = 0x16880ull; \ 725 if (mcs->hw->mcs_blks > 1) \ 726 offset = 0xec18ull; \ 727 offset += (a) * 0x8ull; \ 728 offset; }) 729 730 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCCAMHITX(a) ({ \ 731 u64 offset; \ 732 \ 733 offset = 0xfe80ull; \ 734 if (mcs->hw->mcs_blks > 1) \ 735 offset = 0xde18ull; \ 736 offset += (a) * 0x8ull; \ 737 offset; }) 738 739 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCINVALIDX(a) ({ \ 740 u64 offset; \ 741 \ 742 offset = 0x10680ull; \ 743 if (mcs->hw->mcs_blks > 1) \ 744 offset = 0xe418ull; \ 745 offset += (a) * 0x8ull; \ 746 offset; }) 747 748 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(a) ({ \ 749 u64 offset; \ 750 \ 751 offset = 0x10e80ull; \ 752 if (mcs->hw->mcs_blks > 1) \ 753 offset = 0xe218ull; \ 754 offset += (a) * 0x8ull; \ 755 offset; }) 756 757 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYBADTAGX(a) ({ \ 758 u64 offset; \ 759 \ 760 offset = 0xae80ull; \ 761 if (mcs->hw->mcs_blks > 1) \ 762 offset = 0xd418ull; \ 763 offset += (a) * 0x8ull; \ 764 offset; }) 765 766 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAX(a) ({ \ 767 u64 offset; \ 768 \ 769 offset = 0xc680ull; \ 770 if (mcs->hw->mcs_blks > 1) \ 771 offset = 0xd618ull; \ 772 offset += (a) * 0x8ull; \ 773 offset; }) 774 775 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAERRORX(a) ({ \ 776 u64 offset; \ 777 \ 778 offset = 0xce80ull; \ 779 if (mcs->hw->mcs_blks > 1) \ 780 offset = 0xd818ull; \ 781 offset += (a) * 0x8ull; \ 782 offset; }) 783 784 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(a) ({ \ 785 u64 offset; \ 786 \ 787 offset = 0xbe80ull; \ 788 if (mcs->hw->mcs_blks > 1) \ 789 offset = 0xcc18ull; \ 790 offset += (a) * 0x8ull; \ 791 offset; }) 792 793 #define MCSX_CSE_RX_SLAVE_CTRL ({ \ 794 u64 offset; \ 795 \ 796 offset = 0x52a0ull; \ 797 if (mcs->hw->mcs_blks > 1) \ 798 offset = 0x9c0ull; \ 799 offset; }) 800 801 #define MCSX_CSE_RX_SLAVE_STATS_CLEAR ({ \ 802 u64 offset; \ 803 \ 804 offset = 0x52b8ull; \ 805 if (mcs->hw->mcs_blks > 1) \ 806 offset = 0x9d8ull; \ 807 offset; }) 808 809 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a) (0xe680ull + (a) * 0x8ull) 810 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a) (0xde80ull + (a) * 0x8ull) 811 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(a) (0xa680ull + (a) * 0x8ull) 812 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a) (0xd218 + (a) * 0x8ull) 813 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) (0xd018ull + (a) * 0x8ull) 814 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(a) (0xee80ull + (a) * 0x8ull) 815 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a) (0xb680ull + (a) * 0x8ull) 816 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) (0xf680ull + (a) * 0x8ull) 817 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a) (0x12680ull + (a) * 0x8ull) 818 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a) * 0x8ull) 819 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a) (0x13680ull + (a) * 0x8ull) 820 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAOKX(a) (0x11680ull + (a) * 0x8ull) 821 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAUNUSEDSAX(a) (0x14680ull + (a) * 0x8ull) 822 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSEARLYPREEMPTERRX(a) (0xec58ull + (a) * 0x8ull) 823 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCOKX(a) (0xea18ull + (a) * 0x8ull) 824 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCDELAYEDX(a) (0xe618ull + (a) * 0x8ull) 825 826 /* CSE TX */ 827 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCOMMONOCTETSX(a) (0x18440ull + (a) * 0x8ull) 828 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLBCPKTSX(a) ({ \ 829 u64 offset; \ 830 \ 831 offset = 0x1c440ull; \ 832 if (mcs->hw->mcs_blks > 1) \ 833 offset = 0xf478ull; \ 834 offset += (a) * 0x8ull; \ 835 offset; }) 836 837 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLMCPKTSX(a) ({ \ 838 u64 offset; \ 839 \ 840 offset = 0x1bc40ull; \ 841 if (mcs->hw->mcs_blks > 1) \ 842 offset = 0xf278ull; \ 843 offset += (a) * 0x8ull; \ 844 offset; }) 845 846 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLOCTETSX(a) ({ \ 847 u64 offset; \ 848 \ 849 offset = 0x19440ull; \ 850 if (mcs->hw->mcs_blks > 1) \ 851 offset = 0xee78ull; \ 852 offset += (a) * 0x8ull; \ 853 offset; }) 854 855 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLUCPKTSX(a) ({ \ 856 u64 offset; \ 857 \ 858 offset = 0x1b440ull; \ 859 if (mcs->hw->mcs_blks > 1) \ 860 offset = 0xf078ull; \ 861 offset += (a) * 0x8ull; \ 862 offset; }) 863 864 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLBCPKTSX(a) ({ \ 865 u64 offset; \ 866 \ 867 offset = 0x1ac40ull; \ 868 if (mcs->hw->mcs_blks > 1) \ 869 offset = 0xfc78ull; \ 870 offset += (a) * 0x8ull; \ 871 offset; }) 872 873 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLMCPKTSX(a) ({ \ 874 u64 offset; \ 875 \ 876 offset = 0x1a440ull; \ 877 if (mcs->hw->mcs_blks > 1) \ 878 offset = 0xfa78ull; \ 879 offset += (a) * 0x8ull; \ 880 offset; }) 881 882 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLOCTETSX(a) ({ \ 883 u64 offset; \ 884 \ 885 offset = 0x18c40ull; \ 886 if (mcs->hw->mcs_blks > 1) \ 887 offset = 0xf678ull; \ 888 offset += (a) * 0x8ull; \ 889 offset; }) 890 891 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLUCPKTSX(a) ({ \ 892 u64 offset; \ 893 \ 894 offset = 0x19c40ull; \ 895 if (mcs->hw->mcs_blks > 1) \ 896 offset = 0xf878ull; \ 897 offset += (a) * 0x8ull; \ 898 offset; }) 899 900 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYENCRYPTEDX(a) ({ \ 901 u64 offset; \ 902 \ 903 offset = 0x17c40ull; \ 904 if (mcs->hw->mcs_blks > 1) \ 905 offset = 0x10878ull; \ 906 offset += (a) * 0x8ull; \ 907 offset; }) 908 909 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYPROTECTEDX(a) ({ \ 910 u64 offset; \ 911 \ 912 offset = 0x17440ull; \ 913 if (mcs->hw->mcs_blks > 1) \ 914 offset = 0x10678ull; \ 915 offset += (a) * 0x8ull; \ 916 offset; }) 917 918 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSCTRLPORTDISABLEDX(a) ({ \ 919 u64 offset; \ 920 \ 921 offset = 0x1e440ull; \ 922 if (mcs->hw->mcs_blks > 1) \ 923 offset = 0xfe78ull; \ 924 offset += (a) * 0x8ull; \ 925 offset; }) 926 927 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMHITX(a) ({ \ 928 u64 offset; \ 929 \ 930 offset = 0x23240ull; \ 931 if (mcs->hw->mcs_blks > 1) \ 932 offset = 0x10ed8ull; \ 933 offset += (a) * 0x8ull; \ 934 offset; }) 935 936 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMMISSX(a) ({ \ 937 u64 offset; \ 938 \ 939 offset = 0x22c40ull; \ 940 if (mcs->hw->mcs_blks > 1) \ 941 offset = 0x10e98ull; \ 942 offset += (a) * 0x8ull; \ 943 offset; }) 944 945 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSPARSEERRX(a) ({ \ 946 u64 offset; \ 947 \ 948 offset = 0x22e40ull; \ 949 if (mcs->hw->mcs_blks > 1) \ 950 offset = 0x10e78ull; \ 951 offset += (a) * 0x8ull; \ 952 offset; }) 953 954 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCENCRYPTEDX(a) ({ \ 955 u64 offset; \ 956 \ 957 offset = 0x20440ull; \ 958 if (mcs->hw->mcs_blks > 1) \ 959 offset = 0x10c78ull; \ 960 offset += (a) * 0x8ull; \ 961 offset; }) 962 963 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCPROTECTEDX(a) ({ \ 964 u64 offset; \ 965 \ 966 offset = 0x1fc40ull; \ 967 if (mcs->hw->mcs_blks > 1) \ 968 offset = 0x10a78ull; \ 969 offset += (a) * 0x8ull; \ 970 offset; }) 971 972 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECTAGINSERTIONERRX(a) ({ \ 973 u64 offset; \ 974 \ 975 offset = 0x23040ull; \ 976 if (mcs->hw->mcs_blks > 1) \ 977 offset = 0x110d8ull; \ 978 offset += (a) * 0x8ull; \ 979 offset; }) 980 981 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYNOACTIVESAX(a) ({ \ 982 u64 offset; \ 983 \ 984 offset = 0x1dc40ull; \ 985 if (mcs->hw->mcs_blks > 1) \ 986 offset = 0x10278ull; \ 987 offset += (a) * 0x8ull; \ 988 offset; }) 989 990 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYTOOLONGX(a) ({ \ 991 u64 offset; \ 992 \ 993 offset = 0x1d440ull; \ 994 if (mcs->hw->mcs_blks > 1) \ 995 offset = 0x10478ull; \ 996 offset += (a) * 0x8ull; \ 997 offset; }) 998 999 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYUNTAGGEDX(a) ({ \ 1000 u64 offset; \ 1001 \ 1002 offset = 0x1cc40ull; \ 1003 if (mcs->hw->mcs_blks > 1) \ 1004 offset = 0x10078ull; \ 1005 offset += (a) * 0x8ull; \ 1006 offset; }) 1007 1008 #define MCSX_CSE_TX_SLAVE_CTRL ({ \ 1009 u64 offset; \ 1010 \ 1011 offset = 0x54a0ull; \ 1012 if (mcs->hw->mcs_blks > 1) \ 1013 offset = 0xa00ull; \ 1014 offset; }) 1015 1016 #define MCSX_CSE_TX_SLAVE_STATS_CLEAR ({ \ 1017 u64 offset; \ 1018 \ 1019 offset = 0x54b8ull; \ 1020 if (mcs->hw->mcs_blks > 1) \ 1021 offset = 0xa18ull; \ 1022 offset; }) 1023 1024 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCENCRYPTEDX(a) (0x1f440ull + (a) * 0x8ull) 1025 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCPROTECTEDX(a) (0x1ec40ull + (a) * 0x8ull) 1026 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSEARLYPREEMPTERRX(a) (0x10eb8ull + (a) * 0x8ull) 1027 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAENCRYPTEDX(a) (0x21c40ull + (a) * 0x8ull) 1028 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAPROTECTEDX(a) (0x20c40ull + (a) * 0x8ull) 1029 1030 #define MCSX_IP_INT ({ \ 1031 u64 offset; \ 1032 \ 1033 offset = 0x80028ull; \ 1034 if (mcs->hw->mcs_blks > 1) \ 1035 offset = 0x60028ull; \ 1036 offset; }) 1037 1038 #define MCSX_IP_INT_ENA_W1S ({ \ 1039 u64 offset; \ 1040 \ 1041 offset = 0x80040ull; \ 1042 if (mcs->hw->mcs_blks > 1) \ 1043 offset = 0x60040ull; \ 1044 offset; }) 1045 1046 #define MCSX_IP_INT_ENA_W1C ({ \ 1047 u64 offset; \ 1048 \ 1049 offset = 0x80038ull; \ 1050 if (mcs->hw->mcs_blks > 1) \ 1051 offset = 0x60038ull; \ 1052 offset; }) 1053 1054 #define MCSX_TOP_SLAVE_INT_SUM ({ \ 1055 u64 offset; \ 1056 \ 1057 offset = 0xc20ull; \ 1058 if (mcs->hw->mcs_blks > 1) \ 1059 offset = 0xab8ull; \ 1060 offset; }) 1061 1062 #define MCSX_TOP_SLAVE_INT_SUM_ENB ({ \ 1063 u64 offset; \ 1064 \ 1065 offset = 0xc28ull; \ 1066 if (mcs->hw->mcs_blks > 1) \ 1067 offset = 0xac0ull; \ 1068 offset; }) 1069 1070 #define MCSX_CPM_RX_SLAVE_RX_INT ({ \ 1071 u64 offset; \ 1072 \ 1073 offset = 0x23c00ull; \ 1074 if (mcs->hw->mcs_blks > 1) \ 1075 offset = 0x0ad8ull; \ 1076 offset; }) 1077 1078 #define MCSX_CPM_RX_SLAVE_RX_INT_ENB ({ \ 1079 u64 offset; \ 1080 \ 1081 offset = 0x23c08ull; \ 1082 if (mcs->hw->mcs_blks > 1) \ 1083 offset = 0xae0ull; \ 1084 offset; }) 1085 1086 #define MCSX_CPM_TX_SLAVE_TX_INT ({ \ 1087 u64 offset; \ 1088 \ 1089 offset = 0x3d490ull; \ 1090 if (mcs->hw->mcs_blks > 1) \ 1091 offset = 0x54a0ull; \ 1092 offset; }) 1093 1094 #define MCSX_CPM_TX_SLAVE_TX_INT_ENB ({ \ 1095 u64 offset; \ 1096 \ 1097 offset = 0x3d498ull; \ 1098 if (mcs->hw->mcs_blks > 1) \ 1099 offset = 0x54a8ull; \ 1100 offset; }) 1101 1102 #endif 1103