1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell MCS driver
3  *
4  * Copyright (C) 2022 Marvell.
5  */
6 
7 #ifndef MCS_REG_H
8 #define MCS_REG_H
9 
10 #include <linux/bits.h>
11 
12 /* Registers */
13 #define MCSX_IP_MODE					0x900c8ull
14 #define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({	\
15 	u64 offset;					\
16 							\
17 	offset = 0x408ull;				\
18 	if (mcs->hw->mcs_blks > 1)			\
19 		offset = 0xa28ull;			\
20 	offset += (a) * 0x8ull;				\
21 	offset; })
22 
23 
24 #define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({		\
25 	u64 offset;					\
26 							\
27 	offset = 0x808ull;				\
28 	if (mcs->hw->mcs_blks > 1)			\
29 		offset = 0xa68ull;			\
30 	offset += (a) * 0x8ull;				\
31 	offset; })
32 
33 #define MCSX_MIL_GLOBAL	({				\
34 	u64 offset;					\
35 							\
36 	offset = 0x80000ull;				\
37 	if (mcs->hw->mcs_blks > 1)			\
38 		offset = 0x60000ull;			\
39 	offset; })
40 
41 #define MCSX_MIL_RX_LMACX_CFG(a) ({			\
42 	u64 offset;					\
43 							\
44 	offset = 0x900a8ull;				\
45 	if (mcs->hw->mcs_blks > 1)			\
46 		offset = 0x700a8ull;			\
47 	offset += (a) * 0x800ull;			\
48 	offset; })
49 
50 #define MCSX_HIL_GLOBAL ({				\
51 	u64 offset;					\
52 							\
53 	offset = 0xc0000ull;				\
54 	if (mcs->hw->mcs_blks > 1)			\
55 		offset = 0xa0000ull;			\
56 	offset; })
57 
58 #define MCSX_LINK_LMACX_CFG(a) ({			\
59 	u64 offset;					\
60 							\
61 	offset = 0x90000ull;				\
62 	if (mcs->hw->mcs_blks > 1)			\
63 		offset = 0x70000ull;			\
64 	offset += (a) * 0x800ull;			\
65 	offset; })
66 
67 #define MCSX_MIL_RX_GBL_STATUS ({			\
68 	u64 offset;					\
69 							\
70 	offset = 0x800c8ull;				\
71 	if (mcs->hw->mcs_blks > 1)			\
72 		offset = 0x600c8ull;			\
73 	offset; })
74 
75 #define MCSX_MIL_IP_GBL_STATUS ({			\
76 	u64 offset;					\
77 							\
78 	offset = 0x800d0ull;				\
79 	if (mcs->hw->mcs_blks > 1)			\
80 		offset = 0x600d0ull;			\
81 	offset; })
82 
83 /* PAB */
84 #define MCSX_PAB_RX_SLAVE_PORT_CFGX(a) ({	\
85 	u64 offset;				\
86 						\
87 	offset = 0x1718ull;			\
88 	if (mcs->hw->mcs_blks > 1)		\
89 		offset = 0x280ull;		\
90 	offset += (a) * 0x40ull;		\
91 	offset; })
92 
93 #define MCSX_PAB_TX_SLAVE_PORT_CFGX(a)			(0x2930ull + (a) * 0x40ull)
94 
95 /* PEX registers */
96 #define MCSX_PEX_RX_SLAVE_VLAN_CFGX(a)          (0x3b58ull + (a) * 0x8ull)
97 #define MCSX_PEX_TX_SLAVE_VLAN_CFGX(a)          (0x46f8ull + (a) * 0x8ull)
98 #define MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(a)	(0x788ull + (a) * 0x8ull)
99 #define MCSX_PEX_TX_SLAVE_PORT_CONFIG(a)		(0x4738ull + (a) * 0x8ull)
100 #define MCSX_PEX_RX_SLAVE_PORT_CFGX(a)		(0x3b98ull + (a) * 0x8ull)
101 #define MCSX_PEX_RX_SLAVE_RULE_ETYPE_CFGX(a) ({	\
102 	u64 offset;					\
103 							\
104 	offset = 0x3fc0ull;				\
105 	if (mcs->hw->mcs_blks > 1)			\
106 		offset = 0x558ull;			\
107 	offset += (a) * 0x8ull;				\
108 	offset; })
109 
110 #define MCSX_PEX_RX_SLAVE_RULE_DAX(a) ({	\
111 	u64 offset;					\
112 							\
113 	offset = 0x4000ull;				\
114 	if (mcs->hw->mcs_blks > 1)			\
115 		offset = 0x598ull;			\
116 	offset += (a) * 0x8ull;				\
117 	offset; })
118 
119 #define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MINX(a) ({	\
120 	u64 offset;					\
121 							\
122 	offset = 0x4040ull;				\
123 	if (mcs->hw->mcs_blks > 1)			\
124 		offset = 0x5d8ull;			\
125 	offset += (a) * 0x8ull;				\
126 	offset; })
127 
128 #define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MAXX(a) ({	\
129 	u64 offset;					\
130 							\
131 	offset = 0x4048ull;				\
132 	if (mcs->hw->mcs_blks > 1)			\
133 		offset = 0x5e0ull;			\
134 	offset += (a) * 0x8ull;				\
135 	offset; })
136 
137 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_MINX(a) ({	\
138 	u64 offset;					\
139 							\
140 	offset = 0x4080ull;				\
141 	if (mcs->hw->mcs_blks > 1)			\
142 		offset = 0x648ull;			\
143 	offset += (a) * 0x8ull;				\
144 	offset; })
145 
146 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_MAXX(a) ({	\
147 	u64 offset;					\
148 							\
149 	offset = 0x4088ull;				\
150 	if (mcs->hw->mcs_blks > 1)			\
151 		offset = 0x650ull;			\
152 	offset += (a) * 0x8ull;				\
153 	offset; })
154 
155 #define MCSX_PEX_RX_SLAVE_RULE_COMBO_ETX(a) ({	\
156 	u64 offset;					\
157 							\
158 	offset = 0x4090ull;				\
159 	if (mcs->hw->mcs_blks > 1)			\
160 		offset = 0x658ull;			\
161 	offset += (a) * 0x8ull;				\
162 	offset; })
163 
164 #define MCSX_PEX_RX_SLAVE_RULE_MAC ({	\
165 	u64 offset;					\
166 							\
167 	offset = 0x40e0ull;				\
168 	if (mcs->hw->mcs_blks > 1)			\
169 		offset = 0x6d8ull;			\
170 	offset; })
171 
172 #define MCSX_PEX_RX_SLAVE_RULE_ENABLE ({	\
173 	u64 offset;					\
174 							\
175 	offset = 0x40e8ull;				\
176 	if (mcs->hw->mcs_blks > 1)			\
177 		offset = 0x6e0ull;			\
178 	offset; })
179 
180 #define MCSX_PEX_TX_SLAVE_RULE_ETYPE_CFGX(a) ({	\
181 	u64 offset;					\
182 							\
183 	offset = 0x4b60ull;				\
184 	if (mcs->hw->mcs_blks > 1)			\
185 		offset = 0x7d8ull;			\
186 	offset += (a) * 0x8ull;				\
187 	offset; })
188 
189 #define MCSX_PEX_TX_SLAVE_RULE_DAX(a) ({	\
190 	u64 offset;					\
191 							\
192 	offset = 0x4ba0ull;				\
193 	if (mcs->hw->mcs_blks > 1)			\
194 		offset = 0x818ull;			\
195 	offset += (a) * 0x8ull;				\
196 	offset; })
197 
198 #define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MINX(a) ({	\
199 	u64 offset;					\
200 							\
201 	offset = 0x4be0ull;				\
202 	if (mcs->hw->mcs_blks > 1)			\
203 		offset = 0x858ull;			\
204 	offset += (a) * 0x8ull;				\
205 	offset; })
206 
207 #define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MAXX(a) ({	\
208 	u64 offset;					\
209 							\
210 	offset = 0x4be8ull;				\
211 	if (mcs->hw->mcs_blks > 1)			\
212 		offset = 0x860ull;			\
213 	offset += (a) * 0x8ull;				\
214 	offset; })
215 
216 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_MINX(a) ({	\
217 	u64 offset;					\
218 							\
219 	offset = 0x4c20ull;				\
220 	if (mcs->hw->mcs_blks > 1)			\
221 		offset = 0x8c8ull;			\
222 	offset += (a) * 0x8ull;				\
223 	offset; })
224 
225 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_MAXX(a) ({	\
226 	u64 offset;					\
227 							\
228 	offset = 0x4c28ull;				\
229 	if (mcs->hw->mcs_blks > 1)			\
230 		offset = 0x8d0ull;			\
231 	offset += (a) * 0x8ull;				\
232 	offset; })
233 
234 #define MCSX_PEX_TX_SLAVE_RULE_COMBO_ETX(a) ({	\
235 	u64 offset;					\
236 							\
237 	offset = 0x4c30ull;				\
238 	if (mcs->hw->mcs_blks > 1)			\
239 		offset = 0x8d8ull;			\
240 	offset += (a) * 0x8ull;				\
241 	offset; })
242 
243 #define MCSX_PEX_TX_SLAVE_RULE_MAC ({	\
244 	u64 offset;					\
245 							\
246 	offset = 0x4c80ull;				\
247 	if (mcs->hw->mcs_blks > 1)			\
248 		offset = 0x958ull;			\
249 	offset; })
250 
251 #define MCSX_PEX_TX_SLAVE_RULE_ENABLE ({	\
252 	u64 offset;					\
253 							\
254 	offset = 0x4c88ull;				\
255 	if (mcs->hw->mcs_blks > 1)			\
256 		offset = 0x960ull;			\
257 	offset; })
258 
259 #define MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION ({		\
260 	u64 offset;					\
261 							\
262 	offset = 0x3b50ull;				\
263 	if (mcs->hw->mcs_blks > 1)			\
264 		offset = 0x4c0ull;			\
265 	offset; })
266 
267 /* CNF10K-B */
268 #define MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(a)        (0x4c8ull + (a) * 0x8ull)
269 #define MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(a)        (0x748ull + (a) * 0x8ull)
270 #define MCSX_PEX_RX_SLAVE_ETYPE_ENABLE          0x6e8ull
271 #define MCSX_PEX_TX_SLAVE_ETYPE_ENABLE          0x968ull
272 
273 /* BEE */
274 #define MCSX_BBE_RX_SLAVE_PADDING_CTL			0xe08ull
275 #define MCSX_BBE_TX_SLAVE_PADDING_CTL			0x12f8ull
276 #define MCSX_BBE_RX_SLAVE_CAL_ENTRY			0x180ull
277 #define MCSX_BBE_RX_SLAVE_CAL_LEN			0x188ull
278 #define MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(a)		(0x290ull + (a) * 0x40ull)
279 #define MCSX_BBE_RX_SLAVE_DFIFO_OVERFLOW_0		0xe20
280 #define MCSX_BBE_TX_SLAVE_DFIFO_OVERFLOW_0		0x1298
281 #define MCSX_BBE_RX_SLAVE_PLFIFO_OVERFLOW_0		0xe40
282 #define MCSX_BBE_TX_SLAVE_PLFIFO_OVERFLOW_0		0x12b8
283 #define MCSX_BBE_RX_SLAVE_BBE_INT ({	\
284 	u64 offset;			\
285 					\
286 	offset = 0xe00ull;		\
287 	if (mcs->hw->mcs_blks > 1)	\
288 		offset = 0x160ull;	\
289 	offset; })
290 
291 #define MCSX_BBE_RX_SLAVE_BBE_INT_ENB ({	\
292 	u64 offset;			\
293 					\
294 	offset = 0xe08ull;		\
295 	if (mcs->hw->mcs_blks > 1)	\
296 		offset = 0x168ull;	\
297 	offset; })
298 
299 #define MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW ({	\
300 	u64 offset;			\
301 					\
302 	offset = 0xe08ull;		\
303 	if (mcs->hw->mcs_blks > 1)	\
304 		offset = 0x178ull;	\
305 	offset; })
306 
307 #define MCSX_BBE_TX_SLAVE_BBE_INT ({	\
308 	u64 offset;			\
309 					\
310 	offset = 0x1278ull;		\
311 	if (mcs->hw->mcs_blks > 1)	\
312 		offset = 0x1e0ull;	\
313 	offset; })
314 
315 #define MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW ({	\
316 	u64 offset;			\
317 					\
318 	offset = 0x1278ull;		\
319 	if (mcs->hw->mcs_blks > 1)	\
320 		offset = 0x1f8ull;	\
321 	offset; })
322 
323 #define MCSX_BBE_TX_SLAVE_BBE_INT_ENB ({	\
324 	u64 offset;			\
325 					\
326 	offset = 0x1280ull;		\
327 	if (mcs->hw->mcs_blks > 1)	\
328 		offset = 0x1e8ull;	\
329 	offset; })
330 
331 #define MCSX_PAB_RX_SLAVE_PAB_INT ({	\
332 	u64 offset;			\
333 					\
334 	offset = 0x16f0ull;		\
335 	if (mcs->hw->mcs_blks > 1)	\
336 		offset = 0x260ull;	\
337 	offset; })
338 
339 #define MCSX_PAB_RX_SLAVE_PAB_INT_ENB ({	\
340 	u64 offset;			\
341 					\
342 	offset = 0x16f8ull;		\
343 	if (mcs->hw->mcs_blks > 1)	\
344 		offset = 0x268ull;	\
345 	offset; })
346 
347 #define MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW ({	\
348 	u64 offset;			\
349 					\
350 	offset = 0x16f8ull;		\
351 	if (mcs->hw->mcs_blks > 1)	\
352 		offset = 0x278ull;	\
353 	offset; })
354 
355 #define MCSX_PAB_TX_SLAVE_PAB_INT ({	\
356 	u64 offset;			\
357 					\
358 	offset = 0x2908ull;		\
359 	if (mcs->hw->mcs_blks > 1)	\
360 		offset = 0x380ull;	\
361 	offset; })
362 
363 #define MCSX_PAB_TX_SLAVE_PAB_INT_ENB ({	\
364 	u64 offset;			\
365 					\
366 	offset = 0x2910ull;		\
367 	if (mcs->hw->mcs_blks > 1)	\
368 		offset = 0x388ull;	\
369 	offset; })
370 
371 #define MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW ({	\
372 	u64 offset;			\
373 					\
374 	offset = 0x16f8ull;		\
375 	if (mcs->hw->mcs_blks > 1)	\
376 		offset = 0x398ull;	\
377 	offset; })
378 
379 /* CPM registers */
380 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({	\
381 	u64 offset;					\
382 							\
383 	offset = 0x30740ull;				\
384 	if (mcs->hw->mcs_blks > 1)			\
385 		offset = 0x3bf8ull;			\
386 	offset += (a) * 0x8ull + (b) * 0x20ull;		\
387 	offset; })
388 
389 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({	\
390 	u64 offset;					\
391 							\
392 	offset = 0x34740ull;				\
393 	if (mcs->hw->mcs_blks > 1)			\
394 		offset = 0x43f8ull;			\
395 	offset += (a) * 0x8ull + (b) * 0x20ull;		\
396 	offset; })
397 
398 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_0 ({		\
399 	u64 offset;					\
400 							\
401 	offset = 0x30700ull;				\
402 	if (mcs->hw->mcs_blks > 1)			\
403 		offset = 0x3bd8ull;			\
404 	offset; })
405 
406 #define MCSX_CPM_RX_SLAVE_SC_CAMX(a, b)	({		\
407 	u64 offset;					\
408 							\
409 	offset = 0x38780ull;				\
410 	if (mcs->hw->mcs_blks > 1)			\
411 		offset = 0x4c08ull;			\
412 	offset +=  (a) * 0x8ull + (b) * 0x10ull;	\
413 	offset; })
414 
415 #define MCSX_CPM_RX_SLAVE_SC_CAM_ENA(a)	({		\
416 	u64 offset;					\
417 							\
418 	offset = 0x38740ull + (a) * 0x8ull;		\
419 	if (mcs->hw->mcs_blks > 1)			\
420 		offset = 0x4bf8ull;			\
421 	offset; })
422 
423 #define MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(a) ({		\
424 	u64 offset;					\
425 							\
426 	offset = 0x23ee0ull;				\
427 	if (mcs->hw->mcs_blks > 1)			\
428 		offset = 0xbd0ull;			\
429 	offset += (a) * 0x8ull;				\
430 	offset; })
431 
432 #define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_0X(a) ({	\
433 	u64 offset;					\
434 							\
435 	offset = (0x246e0ull + (a) * 0x10ull);		\
436 	if (mcs->hw->mcs_blks > 1)			\
437 		offset = (0xdd0ull + (a) * 0x8ull);	\
438 	offset; })
439 
440 #define MCSX_CPM_RX_SLAVE_SA_KEY_LOCKOUTX(a) ({		\
441 	u64 offset;					\
442 							\
443 	offset = 0x23E90ull;				\
444 	if (mcs->hw->mcs_blks > 1)			\
445 		offset = 0xbb0ull;			\
446 	offset += (a) * 0x8ull;				\
447 	offset; })
448 
449 #define MCSX_CPM_RX_SLAVE_SA_MAP_MEMX(a) ({		\
450 	u64 offset;					\
451 							\
452 	offset = 0x256e0ull;				\
453 	if (mcs->hw->mcs_blks > 1)			\
454 		offset = 0xfd0ull;			\
455 	offset += (a) * 0x8ull;				\
456 	offset; })
457 
458 #define MCSX_CPM_RX_SLAVE_SA_PLCY_MEMX(a, b) ({		\
459 	u64 offset;					\
460 							\
461 	offset = 0x27700ull;				\
462 	if (mcs->hw->mcs_blks > 1)			\
463 		offset = 0x17d8ull;			\
464 	offset +=  (a) * 0x8ull + (b) * 0x40ull;	\
465 	offset; })
466 
467 #define MCSX_CPM_RX_SLAVE_SA_PN_TABLE_MEMX(a) ({	\
468 	u64 offset;					\
469 							\
470 	offset = 0x2f700ull;				\
471 	if (mcs->hw->mcs_blks > 1)			\
472 		offset = 0x37d8;			\
473 	offset += (a) * 0x8ull;				\
474 	offset; })
475 
476 #define MCSX_CPM_RX_SLAVE_XPN_THRESHOLD	({		\
477 	u64 offset;					\
478 							\
479 	offset = 0x23e40ull;				\
480 	if (mcs->hw->mcs_blks > 1)			\
481 		offset = 0xb90ull;			\
482 	offset; })
483 
484 #define MCSX_CPM_RX_SLAVE_PN_THRESHOLD	({		\
485 	u64 offset;					\
486 							\
487 	offset = 0x23e48ull;				\
488 	if (mcs->hw->mcs_blks > 1)			\
489 		offset = 0xb98ull;			\
490 	offset; })
491 
492 #define MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(a)	({	\
493 	u64 offset;					\
494 							\
495 	offset = 0x23e50ull;				\
496 	if (mcs->hw->mcs_blks > 1)			\
497 		offset = 0xba0ull;			\
498 	offset += (a) * 0x8ull;				\
499 	offset; })
500 
501 #define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_1		0x30708ull
502 #define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(a)		(0x246e8ull + (a) * 0x10ull)
503 
504 /* TX registers */
505 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({	\
506 	u64 offset;					\
507 							\
508 	offset = 0x51d50ull;				\
509 	if (mcs->hw->mcs_blks > 1)			\
510 		offset = 0xa7c0ull;			\
511 	offset += (a) * 0x8ull + (b) * 0x20ull;		\
512 	offset; })
513 
514 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({	\
515 	u64 offset;					\
516 							\
517 	offset = 0x55d50ull;				\
518 	if (mcs->hw->mcs_blks > 1)			\
519 		offset = 0xafc0ull;			\
520 	offset += (a) * 0x8ull + (b) * 0x20ull;		\
521 	offset; })
522 
523 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_0 ({		\
524 	u64 offset;					\
525 							\
526 	offset = 0x51d10ull;				\
527 	if (mcs->hw->mcs_blks > 1)			\
528 		offset = 0xa7a0ull;			\
529 	offset; })
530 
531 #define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(a) ({		\
532 	u64 offset;					\
533 							\
534 	offset = 0x3e508ull + (a) * 0x8ull;		\
535 	if (mcs->hw->mcs_blks > 1)			\
536 		offset = 0x5550ull + (a) * 0x10ull;	\
537 	offset; })
538 
539 #define MCSX_CPM_TX_SLAVE_SECY_PLCY_MEMX(a) ({	\
540 	u64 offset;					\
541 							\
542 	offset = 0x3ed08ull;				\
543 	if (mcs->hw->mcs_blks > 1)			\
544 		offset = 0x5950ull;			\
545 	offset += (a) * 0x8ull;				\
546 	offset; })
547 
548 #define MCSX_CPM_TX_SLAVE_SA_KEY_LOCKOUTX(a) ({		\
549 	u64 offset;					\
550 							\
551 	offset = 0x3e4c0ull;				\
552 	if (mcs->hw->mcs_blks > 1)			\
553 		offset = 0x5538ull;			\
554 	offset += (a) * 0x8ull;				\
555 	offset; })
556 
557 #define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(a) ({		\
558 	u64 offset;					\
559 							\
560 	offset = 0x3fd10ull + (a) * 0x10ull;		\
561 	if (mcs->hw->mcs_blks > 1)			\
562 		offset = 0x6150ull + (a) * 0x8ull;	\
563 	offset; })
564 
565 #define MCSX_CPM_TX_SLAVE_SA_PLCY_MEMX(a, b) ({		\
566 	u64 offset;					\
567 							\
568 	offset = 0x40d10ull;				\
569 	if (mcs->hw->mcs_blks > 1)			\
570 		offset = 0x63a0ull;			\
571 	offset += (a) * 0x8ull + (b) * 0x80ull;		\
572 	offset; })
573 
574 #define MCSX_CPM_TX_SLAVE_SA_PN_TABLE_MEMX(a) ({	\
575 	u64 offset;					\
576 							\
577 	offset = 0x50d10ull;				\
578 	if (mcs->hw->mcs_blks > 1)			\
579 		offset = 0xa3a0ull;			\
580 	offset += (a) * 0x8ull;				\
581 	offset; })
582 
583 #define MCSX_CPM_TX_SLAVE_XPN_THRESHOLD ({		\
584 	u64 offset;					\
585 							\
586 	offset = 0x3e4b0ull;				\
587 	if (mcs->hw->mcs_blks > 1)			\
588 		offset = 0x5528ull;			\
589 	offset; })
590 
591 #define MCSX_CPM_TX_SLAVE_PN_THRESHOLD ({		\
592 	u64 offset;					\
593 							\
594 	offset = 0x3e4b8ull;				\
595 	if (mcs->hw->mcs_blks > 1)			\
596 		offset = 0x5530ull;			\
597 	offset; })
598 
599 #define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_1X(a)		(0x3fd18ull + (a) * 0x10ull)
600 #define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(a)		(0x5558ull + (a) * 0x10ull)
601 #define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_1		0x51d18ull
602 #define MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(a)		(0x5b50 + (a) * 0x8ull)
603 #define MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(a)		(0x5d50 + (a) * 0x8ull)
604 #define MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(a)		(0x5f50 + (a) * 0x8ull)
605 #define MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0		0x5500ull
606 
607 /* CSE */
608 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLBCPKTSX(a) ({	\
609 	u64 offset;					\
610 							\
611 	offset = 0x9e80ull;				\
612 	if (mcs->hw->mcs_blks > 1)			\
613 		offset = 0xc218ull;			\
614 	offset += (a) * 0x8ull;				\
615 	offset; })
616 
617 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLMCPKTSX(a) ({	\
618 	u64 offset;					\
619 							\
620 	offset = 0x9680ull;				\
621 	if (mcs->hw->mcs_blks > 1)			\
622 		offset = 0xc018ull;			\
623 	offset += (a) * 0x8ull;				\
624 	offset; })
625 
626 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLOCTETSX(a) ({	\
627 	u64 offset;					\
628 							\
629 	offset = 0x6e80ull;				\
630 	if (mcs->hw->mcs_blks > 1)			\
631 		offset = 0xbc18ull;			\
632 	offset +=  (a) * 0x8ull;			\
633 	offset; })
634 
635 #define MCSX_CSE_RX_MEM_SLAVE_IFINCTLUCPKTSX(a) ({	\
636 	u64 offset;					\
637 							\
638 	offset = 0x8e80ull;				\
639 	if (mcs->hw->mcs_blks > 1)			\
640 		offset = 0xbe18ull;			\
641 	offset +=  (a) * 0x8ull;			\
642 	offset; })
643 
644 #define	MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLBCPKTSX(a) ({	\
645 	u64 offset;					\
646 							\
647 	offset = 0x8680ull;				\
648 	if (mcs->hw->mcs_blks > 1)			\
649 		offset = 0xca18ull;			\
650 	offset +=  (a) * 0x8ull;			\
651 	offset; })
652 
653 #define	MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLMCPKTSX(a) ({	\
654 	u64 offset;					\
655 							\
656 	offset = 0x7e80ull;				\
657 	if (mcs->hw->mcs_blks > 1)			\
658 		offset = 0xc818ull;			\
659 	offset +=  (a) * 0x8ull;			\
660 	offset; })
661 
662 #define	MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLOCTETSX(a) ({	\
663 	u64 offset;					\
664 							\
665 	offset = 0x6680ull;				\
666 	if (mcs->hw->mcs_blks > 1)			\
667 		offset = 0xc418ull;			\
668 	offset +=  (a) * 0x8ull;			\
669 	offset; })
670 
671 #define	MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLUCPKTSX(a) ({	\
672 	u64 offset;					\
673 							\
674 	offset = 0x7680ull;				\
675 	if (mcs->hw->mcs_blks > 1)			\
676 		offset = 0xc618ull;			\
677 	offset +=  (a) * 0x8ull;			\
678 	offset; })
679 
680 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYDECRYPTEDX(a) ({ \
681 	u64 offset;					\
682 							\
683 	offset = 0x5e80ull;				\
684 	if (mcs->hw->mcs_blks > 1)			\
685 		offset = 0xdc18ull;			\
686 	offset += (a) * 0x8ull;				\
687 	offset; })
688 
689 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYVALIDATEX(a)({ \
690 	u64 offset;					\
691 							\
692 	offset = 0x5680ull;				\
693 	if (mcs->hw->mcs_blks > 1)			\
694 		offset = 0xda18ull;			\
695 	offset += (a) * 0x8ull;				\
696 	offset; })
697 
698 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSCTRLPORTDISABLEDX(a) ({ \
699 	u64 offset;					\
700 							\
701 	offset = 0xd680ull;				\
702 	if (mcs->hw->mcs_blks > 1)			\
703 		offset = 0xce18ull;			\
704 	offset += (a) * 0x8ull;				\
705 	offset; })
706 
707 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMHITX(a) ({ \
708 	u64 offset;					\
709 							\
710 	offset = 0x16a80ull;				\
711 	if (mcs->hw->mcs_blks > 1)			\
712 		offset = 0xec78ull;			\
713 	offset += (a) * 0x8ull;				\
714 	offset; })
715 
716 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMMISSX(a) ({ \
717 	u64 offset;					\
718 							\
719 	offset = 0x16680ull;				\
720 	if (mcs->hw->mcs_blks > 1)			\
721 		offset = 0xec38ull;			\
722 	offset += (a) * 0x8ull;				\
723 	offset; })
724 
725 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSPARSEERRX(a) ({	\
726 	u64 offset;					\
727 							\
728 	offset = 0x16880ull;				\
729 	if (mcs->hw->mcs_blks > 1)			\
730 		offset = 0xec18ull;			\
731 	offset += (a) * 0x8ull;				\
732 	offset; })
733 
734 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCCAMHITX(a) ({	\
735 	u64 offset;					\
736 							\
737 	offset = 0xfe80ull;				\
738 	if (mcs->hw->mcs_blks > 1)			\
739 		offset = 0xde18ull;			\
740 	offset += (a) * 0x8ull;				\
741 	offset; })
742 
743 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCINVALIDX(a) ({	\
744 	u64 offset;					\
745 							\
746 	offset = 0x10680ull;				\
747 	if (mcs->hw->mcs_blks > 1)			\
748 		offset = 0xe418ull;			\
749 	offset += (a) * 0x8ull;				\
750 	offset; })
751 
752 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(a) ({	\
753 	u64 offset;					\
754 							\
755 	offset = 0x10e80ull;				\
756 	if (mcs->hw->mcs_blks > 1)			\
757 		offset = 0xe218ull;			\
758 	offset += (a) * 0x8ull;				\
759 	offset; })
760 
761 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYBADTAGX(a) ({	\
762 	u64 offset;					\
763 							\
764 	offset = 0xae80ull;				\
765 	if (mcs->hw->mcs_blks > 1)			\
766 		offset = 0xd418ull;			\
767 	offset += (a) * 0x8ull;				\
768 	offset; })
769 
770 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAX(a) ({	\
771 	u64 offset;					\
772 							\
773 	offset = 0xc680ull;				\
774 	if (mcs->hw->mcs_blks > 1)			\
775 		offset = 0xd618ull;			\
776 	offset += (a) * 0x8ull;				\
777 	offset; })
778 
779 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAERRORX(a) ({ \
780 	u64 offset;					\
781 							\
782 	offset = 0xce80ull;				\
783 	if (mcs->hw->mcs_blks > 1)			\
784 		offset = 0xd818ull;			\
785 	offset += (a) * 0x8ull;				\
786 	offset; })
787 
788 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(a) ({ \
789 	u64 offset;					\
790 							\
791 	offset = 0xbe80ull;				\
792 	if (mcs->hw->mcs_blks > 1)			\
793 		offset = 0xcc18ull;			\
794 	offset += (a) * 0x8ull;				\
795 	offset; })
796 
797 #define MCSX_CSE_RX_SLAVE_CTRL	({			\
798 	u64 offset;					\
799 							\
800 	offset = 0x52a0ull;				\
801 	if (mcs->hw->mcs_blks > 1)			\
802 		offset = 0x9c0ull;			\
803 	offset; })
804 
805 #define MCSX_CSE_RX_SLAVE_STATS_CLEAR	({		\
806 	u64 offset;					\
807 							\
808 	offset = 0x52b8ull;				\
809 	if (mcs->hw->mcs_blks > 1)			\
810 		offset = 0x9d8ull;			\
811 	offset; })
812 
813 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(a) ({	\
814 	u64 offset;					\
815 							\
816 	offset = 0xee80ull;				\
817 	if (mcs->hw->mcs_blks > 1)			\
818 		offset = 0xe818ull;			\
819 	offset += (a) * 0x8ull;				\
820 	offset; })
821 
822 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) ({	\
823 	u64 offset;					\
824 							\
825 	offset = 0xa680ull;				\
826 	if (mcs->hw->mcs_blks > 1)			\
827 		offset = 0xd018ull;			\
828 	offset += (a) * 0x8ull;				\
829 	offset; })
830 
831 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a)	({	\
832 	u64 offset;						\
833 								\
834 	offset = 0xf680ull;					\
835 	if (mcs->hw->mcs_blks > 1)				\
836 		offset = 0xe018ull;				\
837 	offset += (a) * 0x8ull;					\
838 	offset; })
839 
840 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a)	(0xe680ull + (a) * 0x8ull)
841 #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a)	(0xde80ull + (a) * 0x8ull)
842 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a)	(0xd218 + (a) * 0x8ull)
843 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a)		(0xb680ull + (a) * 0x8ull)
844 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a)	(0x12680ull + (a) * 0x8ull)
845 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a) * 0x8ull)
846 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a)	(0x13680ull + (a) * 0x8ull)
847 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAOKX(a)		(0x11680ull + (a) * 0x8ull)
848 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAUNUSEDSAX(a)	(0x14680ull + (a) * 0x8ull)
849 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSEARLYPREEMPTERRX(a) (0xec58ull + (a) * 0x8ull)
850 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCOKX(a)		(0xea18ull + (a) * 0x8ull)
851 #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCDELAYEDX(a)	(0xe618ull + (a) * 0x8ull)
852 
853 /* CSE TX */
854 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCOMMONOCTETSX(a)	(0x18440ull + (a) * 0x8ull)
855 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLBCPKTSX(a) ({	\
856 	u64 offset;					\
857 							\
858 	offset = 0x1c440ull;				\
859 	if (mcs->hw->mcs_blks > 1)			\
860 		offset = 0xf478ull;			\
861 	offset += (a) * 0x8ull;				\
862 	offset; })
863 
864 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLMCPKTSX(a) ({	\
865 	u64 offset;					\
866 							\
867 	offset = 0x1bc40ull;				\
868 	if (mcs->hw->mcs_blks > 1)			\
869 		offset = 0xf278ull;			\
870 	offset += (a) * 0x8ull;				\
871 	offset; })
872 
873 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLOCTETSX(a) ({	\
874 	u64 offset;					\
875 							\
876 	offset = 0x19440ull;				\
877 	if (mcs->hw->mcs_blks > 1)			\
878 		offset = 0xee78ull;			\
879 	offset += (a) * 0x8ull;				\
880 	offset; })
881 
882 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLUCPKTSX(a) ({	\
883 	u64 offset;					\
884 							\
885 	offset = 0x1b440ull;				\
886 	if (mcs->hw->mcs_blks > 1)			\
887 		offset = 0xf078ull;			\
888 	offset += (a) * 0x8ull;				\
889 	offset; })
890 
891 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLBCPKTSX(a) ({	\
892 	u64 offset;					\
893 							\
894 	offset = 0x1ac40ull;				\
895 	if (mcs->hw->mcs_blks > 1)			\
896 		offset = 0xfc78ull;			\
897 	offset += (a) * 0x8ull;				\
898 	offset; })
899 
900 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLMCPKTSX(a) ({	\
901 	u64 offset;					\
902 							\
903 	offset = 0x1a440ull;				\
904 	if (mcs->hw->mcs_blks > 1)			\
905 		offset = 0xfa78ull;			\
906 	offset += (a) * 0x8ull;				\
907 	offset; })
908 
909 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLOCTETSX(a) ({	\
910 	u64 offset;					\
911 							\
912 	offset = 0x18c40ull;				\
913 	if (mcs->hw->mcs_blks > 1)			\
914 		offset = 0xf678ull;			\
915 	offset += (a) * 0x8ull;				\
916 	offset; })
917 
918 #define MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLUCPKTSX(a) ({	\
919 	u64 offset;					\
920 							\
921 	offset = 0x19c40ull;				\
922 	if (mcs->hw->mcs_blks > 1)			\
923 		offset = 0xf878ull;			\
924 	offset += (a) * 0x8ull;				\
925 	offset; })
926 
927 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYENCRYPTEDX(a) ({	\
928 	u64 offset;					\
929 							\
930 	offset = 0x17c40ull;				\
931 	if (mcs->hw->mcs_blks > 1)			\
932 		offset = 0x10878ull;			\
933 	offset += (a) * 0x8ull;				\
934 	offset; })
935 
936 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYPROTECTEDX(a) ({	\
937 	u64 offset;					\
938 							\
939 	offset = 0x17440ull;				\
940 	if (mcs->hw->mcs_blks > 1)			\
941 		offset = 0x10678ull;			\
942 	offset += (a) * 0x8ull;				\
943 	offset; })
944 
945 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSCTRLPORTDISABLEDX(a) ({	\
946 	u64 offset;					\
947 							\
948 	offset = 0x1e440ull;				\
949 	if (mcs->hw->mcs_blks > 1)			\
950 		offset = 0xfe78ull;			\
951 	offset += (a) * 0x8ull;				\
952 	offset; })
953 
954 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMHITX(a) ({	\
955 	u64 offset;					\
956 							\
957 	offset = 0x23240ull;				\
958 	if (mcs->hw->mcs_blks > 1)			\
959 		offset = 0x10ed8ull;			\
960 	offset += (a) * 0x8ull;				\
961 	offset; })
962 
963 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMMISSX(a) ({	\
964 	u64 offset;					\
965 							\
966 	offset = 0x22c40ull;				\
967 	if (mcs->hw->mcs_blks > 1)			\
968 		offset = 0x10e98ull;			\
969 	offset += (a) * 0x8ull;				\
970 	offset; })
971 
972 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSPARSEERRX(a) ({	\
973 	u64 offset;					\
974 							\
975 	offset = 0x22e40ull;				\
976 	if (mcs->hw->mcs_blks > 1)			\
977 		offset = 0x10e78ull;			\
978 	offset += (a) * 0x8ull;				\
979 	offset; })
980 
981 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCENCRYPTEDX(a) ({	\
982 	u64 offset;					\
983 							\
984 	offset = 0x20440ull;				\
985 	if (mcs->hw->mcs_blks > 1)			\
986 		offset = 0x10c78ull;			\
987 	offset += (a) * 0x8ull;				\
988 	offset; })
989 
990 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCPROTECTEDX(a) ({	\
991 	u64 offset;					\
992 							\
993 	offset = 0x1fc40ull;				\
994 	if (mcs->hw->mcs_blks > 1)			\
995 		offset = 0x10a78ull;			\
996 	offset += (a) * 0x8ull;				\
997 	offset; })
998 
999 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECTAGINSERTIONERRX(a) ({	\
1000 	u64 offset;					\
1001 							\
1002 	offset = 0x23040ull;				\
1003 	if (mcs->hw->mcs_blks > 1)			\
1004 		offset = 0x110d8ull;			\
1005 	offset += (a) * 0x8ull;				\
1006 	offset; })
1007 
1008 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYNOACTIVESAX(a) ({	\
1009 	u64 offset;					\
1010 							\
1011 	offset = 0x1dc40ull;				\
1012 	if (mcs->hw->mcs_blks > 1)			\
1013 		offset = 0x10278ull;			\
1014 	offset += (a) * 0x8ull;				\
1015 	offset; })
1016 
1017 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYTOOLONGX(a) ({	\
1018 	u64 offset;					\
1019 							\
1020 	offset = 0x1d440ull;				\
1021 	if (mcs->hw->mcs_blks > 1)			\
1022 		offset = 0x10478ull;			\
1023 	offset += (a) * 0x8ull;				\
1024 	offset; })
1025 
1026 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYUNTAGGEDX(a) ({	\
1027 	u64 offset;					\
1028 							\
1029 	offset = 0x1cc40ull;				\
1030 	if (mcs->hw->mcs_blks > 1)			\
1031 		offset = 0x10078ull;			\
1032 	offset += (a) * 0x8ull;				\
1033 	offset; })
1034 
1035 #define MCSX_CSE_TX_SLAVE_CTRL	({	\
1036 	u64 offset;					\
1037 							\
1038 	offset = 0x54a0ull;				\
1039 	if (mcs->hw->mcs_blks > 1)			\
1040 		offset = 0xa00ull;			\
1041 	offset; })
1042 
1043 #define MCSX_CSE_TX_SLAVE_STATS_CLEAR ({		\
1044 	u64 offset;					\
1045 							\
1046 	offset = 0x54b8ull;				\
1047 	if (mcs->hw->mcs_blks > 1)			\
1048 		offset = 0xa18ull;			\
1049 	offset; })
1050 
1051 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCENCRYPTEDX(a)	(0x1f440ull + (a) * 0x8ull)
1052 #define MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCPROTECTEDX(a)	(0x1ec40ull + (a) * 0x8ull)
1053 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSEARLYPREEMPTERRX(a) (0x10eb8ull + (a) * 0x8ull)
1054 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAENCRYPTEDX(a)	(0x21c40ull + (a) * 0x8ull)
1055 #define MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAPROTECTEDX(a)	(0x20c40ull + (a) * 0x8ull)
1056 
1057 #define MCSX_IP_INT ({			\
1058 	u64 offset;			\
1059 					\
1060 	offset = 0x80028ull;		\
1061 	if (mcs->hw->mcs_blks > 1)	\
1062 		offset = 0x60028ull;	\
1063 	offset; })
1064 
1065 #define MCSX_IP_INT_ENA_W1S ({		\
1066 	u64 offset;			\
1067 					\
1068 	offset = 0x80040ull;		\
1069 	if (mcs->hw->mcs_blks > 1)	\
1070 		offset = 0x60040ull;	\
1071 	offset; })
1072 
1073 #define MCSX_IP_INT_ENA_W1C ({		\
1074 	u64 offset;			\
1075 					\
1076 	offset = 0x80038ull;		\
1077 	if (mcs->hw->mcs_blks > 1)	\
1078 		offset = 0x60038ull;	\
1079 	offset; })
1080 
1081 #define MCSX_TOP_SLAVE_INT_SUM ({	\
1082 	u64 offset;			\
1083 					\
1084 	offset = 0xc20ull;		\
1085 	if (mcs->hw->mcs_blks > 1)	\
1086 		offset = 0xab8ull;	\
1087 	offset; })
1088 
1089 #define MCSX_TOP_SLAVE_INT_SUM_ENB ({	\
1090 	u64 offset;			\
1091 					\
1092 	offset = 0xc28ull;		\
1093 	if (mcs->hw->mcs_blks > 1)	\
1094 		offset = 0xac0ull;	\
1095 	offset; })
1096 
1097 #define MCSX_CPM_RX_SLAVE_RX_INT ({	\
1098 	u64 offset;			\
1099 					\
1100 	offset = 0x23c00ull;		\
1101 	if (mcs->hw->mcs_blks > 1)	\
1102 		offset = 0x0ad8ull;	\
1103 	offset; })
1104 
1105 #define MCSX_CPM_RX_SLAVE_RX_INT_ENB ({	\
1106 	u64 offset;			\
1107 					\
1108 	offset = 0x23c08ull;		\
1109 	if (mcs->hw->mcs_blks > 1)	\
1110 		offset = 0xae0ull;	\
1111 	offset; })
1112 
1113 #define MCSX_CPM_TX_SLAVE_TX_INT ({	\
1114 	u64 offset;			\
1115 					\
1116 	offset = 0x3d490ull;		\
1117 	if (mcs->hw->mcs_blks > 1)	\
1118 		offset = 0x54a0ull;	\
1119 	offset; })
1120 
1121 #define MCSX_CPM_TX_SLAVE_TX_INT_ENB ({	\
1122 	u64 offset;			\
1123 					\
1124 	offset = 0x3d498ull;		\
1125 	if (mcs->hw->mcs_blks > 1)	\
1126 		offset = 0x54a8ull;	\
1127 	offset; })
1128 
1129 #endif
1130