1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/module.h>
9 #include <linux/pci.h>
10 
11 #include "rvu_struct.h"
12 #include "common.h"
13 #include "mbox.h"
14 #include "rvu.h"
15 
16 struct reg_range {
17 	u64  start;
18 	u64  end;
19 };
20 
21 struct hw_reg_map {
22 	u8	regblk;
23 	u8	num_ranges;
24 	u64	mask;
25 #define	 MAX_REG_RANGES	8
26 	struct reg_range range[MAX_REG_RANGES];
27 };
28 
29 static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
30 	{NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 	{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 			      {0x1200, 0x12E0} } },
33 	{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 			      {0x1610, 0x1618}, {0x1700, 0x17B0} } },
35 	{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
36 	{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
37 };
38 
39 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg)
40 {
41 	int idx;
42 	struct hw_reg_map *map;
43 
44 	/* Only 64bit offsets */
45 	if (reg & 0x07)
46 		return false;
47 
48 	if (regmap == TXSCHQ_HWREGMAP) {
49 		if (regblk >= NIX_TXSCH_LVL_CNT)
50 			return false;
51 		map = &txsch_reg_map[regblk];
52 	} else {
53 		return false;
54 	}
55 
56 	/* Should never happen */
57 	if (map->regblk != regblk)
58 		return false;
59 
60 	reg &= map->mask;
61 
62 	for (idx = 0; idx < map->num_ranges; idx++) {
63 		if (reg >= map->range[idx].start &&
64 		    reg < map->range[idx].end)
65 			return true;
66 	}
67 	return false;
68 }
69