1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/pci.h> 15 #include <linux/iommu.h> 16 17 #include <mbox.h> 18 #include "otx2_reg.h" 19 #include "otx2_txrx.h" 20 21 /* PCI device IDs */ 22 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 23 24 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 25 26 /* PCI BAR nos */ 27 #define PCI_CFG_REG_BAR_NUM 2 28 #define PCI_MBOX_BAR_NUM 4 29 30 #define NAME_SIZE 32 31 32 enum arua_mapped_qtypes { 33 AURA_NIX_RQ, 34 AURA_NIX_SQ, 35 }; 36 37 /* NIX LF interrupts range*/ 38 #define NIX_LF_QINT_VEC_START 0x00 39 #define NIX_LF_CINT_VEC_START 0x40 40 #define NIX_LF_GINT_VEC 0x80 41 #define NIX_LF_ERR_VEC 0x81 42 #define NIX_LF_POISON_VEC 0x82 43 44 /* RSS configuration */ 45 struct otx2_rss_info { 46 u8 enable; 47 u32 flowkey_cfg; 48 u16 rss_size; 49 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 50 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 51 u8 key[RSS_HASH_KEY_SIZE]; 52 }; 53 54 /* NIX (or NPC) RX errors */ 55 enum otx2_errlvl { 56 NPC_ERRLVL_RE, 57 NPC_ERRLVL_LID_LA, 58 NPC_ERRLVL_LID_LB, 59 NPC_ERRLVL_LID_LC, 60 NPC_ERRLVL_LID_LD, 61 NPC_ERRLVL_LID_LE, 62 NPC_ERRLVL_LID_LF, 63 NPC_ERRLVL_LID_LG, 64 NPC_ERRLVL_LID_LH, 65 NPC_ERRLVL_NIX = 0x0F, 66 }; 67 68 enum otx2_errcodes_re { 69 /* NPC_ERRLVL_RE errcodes */ 70 ERRCODE_FCS = 0x7, 71 ERRCODE_FCS_RCV = 0x8, 72 ERRCODE_UNDERSIZE = 0x10, 73 ERRCODE_OVERSIZE = 0x11, 74 ERRCODE_OL2_LEN_MISMATCH = 0x12, 75 /* NPC_ERRLVL_NIX errcodes */ 76 ERRCODE_OL3_LEN = 0x10, 77 ERRCODE_OL4_LEN = 0x11, 78 ERRCODE_OL4_CSUM = 0x12, 79 ERRCODE_IL3_LEN = 0x20, 80 ERRCODE_IL4_LEN = 0x21, 81 ERRCODE_IL4_CSUM = 0x22, 82 }; 83 84 /* NIX TX stats */ 85 enum nix_stat_lf_tx { 86 TX_UCAST = 0x0, 87 TX_BCAST = 0x1, 88 TX_MCAST = 0x2, 89 TX_DROP = 0x3, 90 TX_OCTS = 0x4, 91 TX_STATS_ENUM_LAST, 92 }; 93 94 /* NIX RX stats */ 95 enum nix_stat_lf_rx { 96 RX_OCTS = 0x0, 97 RX_UCAST = 0x1, 98 RX_BCAST = 0x2, 99 RX_MCAST = 0x3, 100 RX_DROP = 0x4, 101 RX_DROP_OCTS = 0x5, 102 RX_FCS = 0x6, 103 RX_ERR = 0x7, 104 RX_DRP_BCAST = 0x8, 105 RX_DRP_MCAST = 0x9, 106 RX_DRP_L3BCAST = 0xa, 107 RX_DRP_L3MCAST = 0xb, 108 RX_STATS_ENUM_LAST, 109 }; 110 111 struct otx2_dev_stats { 112 u64 rx_bytes; 113 u64 rx_frames; 114 u64 rx_ucast_frames; 115 u64 rx_bcast_frames; 116 u64 rx_mcast_frames; 117 u64 rx_drops; 118 119 u64 tx_bytes; 120 u64 tx_frames; 121 u64 tx_ucast_frames; 122 u64 tx_bcast_frames; 123 u64 tx_mcast_frames; 124 u64 tx_drops; 125 }; 126 127 /* Driver counted stats */ 128 struct otx2_drv_stats { 129 atomic_t rx_fcs_errs; 130 atomic_t rx_oversize_errs; 131 atomic_t rx_undersize_errs; 132 atomic_t rx_csum_errs; 133 atomic_t rx_len_errs; 134 atomic_t rx_other_errs; 135 }; 136 137 struct mbox { 138 struct otx2_mbox mbox; 139 struct work_struct mbox_wrk; 140 struct otx2_mbox mbox_up; 141 struct work_struct mbox_up_wrk; 142 struct otx2_nic *pfvf; 143 void *bbuf_base; /* Bounce buffer for mbox memory */ 144 struct mutex lock; /* serialize mailbox access */ 145 int num_msgs; /* mbox number of messages */ 146 int up_num_msgs; /* mbox_up number of messages */ 147 }; 148 149 struct otx2_hw { 150 struct pci_dev *pdev; 151 struct otx2_rss_info rss_info; 152 u16 rx_queues; 153 u16 tx_queues; 154 u16 max_queues; 155 u16 pool_cnt; 156 u16 rqpool_cnt; 157 u16 sqpool_cnt; 158 159 /* NPA */ 160 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 161 u32 stack_pg_bytes; /* Size of stack page */ 162 u16 sqb_size; 163 164 /* NIX */ 165 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 166 167 /* HW settings, coalescing etc */ 168 u16 rx_chan_base; 169 u16 tx_chan_base; 170 u16 cq_qcount_wait; 171 u16 cq_ecount_wait; 172 u16 rq_skid; 173 u8 cq_time_wait; 174 175 /* For TSO segmentation */ 176 u8 lso_tsov4_idx; 177 u8 lso_tsov6_idx; 178 u8 hw_tso; 179 180 /* MSI-X */ 181 u8 cint_cnt; /* CQ interrupt count */ 182 u16 npa_msixoff; /* Offset of NPA vectors */ 183 u16 nix_msixoff; /* Offset of NIX vectors */ 184 char *irq_name; 185 cpumask_var_t *affinity_mask; 186 187 /* Stats */ 188 struct otx2_dev_stats dev_stats; 189 struct otx2_drv_stats drv_stats; 190 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 191 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 192 }; 193 194 struct refill_work { 195 struct delayed_work pool_refill_work; 196 struct otx2_nic *pf; 197 }; 198 199 struct otx2_nic { 200 void __iomem *reg_base; 201 struct net_device *netdev; 202 void *iommu_domain; 203 u16 max_frs; 204 u16 rbsize; /* Receive buffer size */ 205 206 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 207 u64 flags; 208 209 struct otx2_qset qset; 210 struct otx2_hw hw; 211 struct pci_dev *pdev; 212 struct device *dev; 213 214 /* Mbox */ 215 struct mbox mbox; 216 struct workqueue_struct *mbox_wq; 217 218 u16 pcifunc; /* RVU PF_FUNC */ 219 struct cgx_link_user_info linfo; 220 221 u64 reset_count; 222 struct work_struct reset_task; 223 struct refill_work *refill_wrk; 224 225 /* Ethtool stuff */ 226 u32 msg_enable; 227 228 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 229 int nix_blkaddr; 230 }; 231 232 static inline bool is_96xx_A0(struct pci_dev *pdev) 233 { 234 return (pdev->revision == 0x00) && 235 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 236 } 237 238 static inline bool is_96xx_B0(struct pci_dev *pdev) 239 { 240 return (pdev->revision == 0x01) && 241 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 242 } 243 244 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 245 { 246 struct otx2_hw *hw = &pfvf->hw; 247 248 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 249 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 250 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 251 252 hw->hw_tso = true; 253 254 if (is_96xx_A0(pfvf->pdev)) { 255 hw->hw_tso = false; 256 257 /* Time based irq coalescing is not supported */ 258 pfvf->hw.cq_qcount_wait = 0x0; 259 260 /* Due to HW issue previous silicons required minimum 261 * 600 unused CQE to avoid CQ overflow. 262 */ 263 pfvf->hw.rq_skid = 600; 264 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 265 } 266 } 267 268 /* Register read/write APIs */ 269 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 270 { 271 u64 blkaddr; 272 273 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 274 case BLKTYPE_NIX: 275 blkaddr = nic->nix_blkaddr; 276 break; 277 case BLKTYPE_NPA: 278 blkaddr = BLKADDR_NPA; 279 break; 280 default: 281 blkaddr = BLKADDR_RVUM; 282 break; 283 }; 284 285 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 286 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 287 288 return nic->reg_base + offset; 289 } 290 291 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 292 { 293 void __iomem *addr = otx2_get_regaddr(nic, offset); 294 295 writeq(val, addr); 296 } 297 298 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 299 { 300 void __iomem *addr = otx2_get_regaddr(nic, offset); 301 302 return readq(addr); 303 } 304 305 /* Mbox bounce buffer APIs */ 306 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 307 { 308 struct otx2_mbox *otx2_mbox; 309 struct otx2_mbox_dev *mdev; 310 311 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 312 if (!mbox->bbuf_base) 313 return -ENOMEM; 314 315 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 316 * prepare all mbox messages in bounce buffer instead of directly 317 * in hw mbox memory. 318 */ 319 otx2_mbox = &mbox->mbox; 320 mdev = &otx2_mbox->dev[0]; 321 mdev->mbase = mbox->bbuf_base; 322 323 otx2_mbox = &mbox->mbox_up; 324 mdev = &otx2_mbox->dev[0]; 325 mdev->mbase = mbox->bbuf_base; 326 return 0; 327 } 328 329 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 330 { 331 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 332 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 333 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 334 struct mbox_hdr *hdr; 335 u64 msg_size; 336 337 if (mdev->mbase == hw_mbase) 338 return; 339 340 hdr = hw_mbase + mbox->rx_start; 341 msg_size = hdr->msg_size; 342 343 if (msg_size > mbox->rx_size - msgs_offset) 344 msg_size = mbox->rx_size - msgs_offset; 345 346 /* Copy mbox messages from mbox memory to bounce buffer */ 347 memcpy(mdev->mbase + mbox->rx_start, 348 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 349 } 350 351 static inline void otx2_mbox_lock_init(struct mbox *mbox) 352 { 353 mutex_init(&mbox->lock); 354 } 355 356 static inline void otx2_mbox_lock(struct mbox *mbox) 357 { 358 mutex_lock(&mbox->lock); 359 } 360 361 static inline void otx2_mbox_unlock(struct mbox *mbox) 362 { 363 mutex_unlock(&mbox->lock); 364 } 365 366 /* With the absence of API for 128-bit IO memory access for arm64, 367 * implement required operations at place. 368 */ 369 #if defined(CONFIG_ARM64) 370 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 371 { 372 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 373 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 374 } 375 376 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 377 { 378 u64 result; 379 380 __asm__ volatile(".cpu generic+lse\n" 381 "ldadd %x[i], %x[r], [%[b]]" 382 : [r]"=r"(result), "+m"(*ptr) 383 : [i]"r"(incr), [b]"r"(ptr) 384 : "memory"); 385 return result; 386 } 387 388 static inline u64 otx2_lmt_flush(uint64_t addr) 389 { 390 u64 result = 0; 391 392 __asm__ volatile(".cpu generic+lse\n" 393 "ldeor xzr,%x[rf],[%[rs]]" 394 : [rf]"=r"(result) 395 : [rs]"r"(addr)); 396 return result; 397 } 398 399 #else 400 #define otx2_write128(lo, hi, addr) 401 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 402 #define otx2_lmt_flush(addr) ({ 0; }) 403 #endif 404 405 /* Alloc pointer from pool/aura */ 406 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 407 { 408 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 409 NPA_LF_AURA_OP_ALLOCX(0)); 410 u64 incr = (u64)aura | BIT_ULL(63); 411 412 return otx2_atomic64_add(incr, ptr); 413 } 414 415 /* Free pointer to a pool/aura */ 416 static inline void otx2_aura_freeptr(struct otx2_nic *pfvf, 417 int aura, s64 buf) 418 { 419 otx2_write128((u64)buf, (u64)aura | BIT_ULL(63), 420 otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0)); 421 } 422 423 /* Update page ref count */ 424 static inline void otx2_get_page(struct otx2_pool *pool) 425 { 426 if (!pool->page) 427 return; 428 429 if (pool->pageref) 430 page_ref_add(pool->page, pool->pageref); 431 pool->pageref = 0; 432 pool->page = NULL; 433 } 434 435 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 436 { 437 if (type == AURA_NIX_SQ) 438 return pfvf->hw.rqpool_cnt + idx; 439 440 /* AURA_NIX_RQ */ 441 return idx; 442 } 443 444 /* Mbox APIs */ 445 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 446 { 447 int err; 448 449 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 450 return 0; 451 otx2_mbox_msg_send(&mbox->mbox, 0); 452 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 453 if (err) 454 return err; 455 456 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 457 } 458 459 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 460 { 461 int err; 462 463 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 464 return 0; 465 otx2_mbox_msg_send(&mbox->mbox_up, devid); 466 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 467 if (err) 468 return err; 469 470 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 471 } 472 473 /* Use this API to send mbox msgs in atomic context 474 * where sleeping is not allowed 475 */ 476 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 477 { 478 int err; 479 480 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 481 return 0; 482 otx2_mbox_msg_send(&mbox->mbox, 0); 483 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 484 if (err) 485 return err; 486 487 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 488 } 489 490 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 491 static struct _req_type __maybe_unused \ 492 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 493 { \ 494 struct _req_type *req; \ 495 \ 496 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 497 &mbox->mbox, 0, sizeof(struct _req_type), \ 498 sizeof(struct _rsp_type)); \ 499 if (!req) \ 500 return NULL; \ 501 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 502 req->hdr.id = _id; \ 503 return req; \ 504 } 505 506 MBOX_MESSAGES 507 #undef M 508 509 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 510 int \ 511 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 512 struct _req_type *req, \ 513 struct _rsp_type *rsp); \ 514 515 MBOX_UP_CGX_MESSAGES 516 #undef M 517 518 /* Time to wait before watchdog kicks off */ 519 #define OTX2_TX_TIMEOUT (100 * HZ) 520 521 #define RVU_PFVF_PF_SHIFT 10 522 #define RVU_PFVF_PF_MASK 0x3F 523 #define RVU_PFVF_FUNC_SHIFT 0 524 #define RVU_PFVF_FUNC_MASK 0x3FF 525 526 static inline int rvu_get_pf(u16 pcifunc) 527 { 528 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 529 } 530 531 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 532 struct page *page, 533 size_t offset, size_t size, 534 enum dma_data_direction dir) 535 { 536 dma_addr_t iova; 537 538 iova = dma_map_page_attrs(pfvf->dev, page, 539 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 540 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 541 return (dma_addr_t)NULL; 542 return iova; 543 } 544 545 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 546 dma_addr_t addr, size_t size, 547 enum dma_data_direction dir) 548 { 549 dma_unmap_page_attrs(pfvf->dev, addr, size, 550 dir, DMA_ATTR_SKIP_CPU_SYNC); 551 } 552 553 /* MSI-X APIs */ 554 void otx2_free_cints(struct otx2_nic *pfvf, int n); 555 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 556 int otx2_set_mac_address(struct net_device *netdev, void *p); 557 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 558 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 559 void otx2_get_mac_from_af(struct net_device *netdev); 560 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 561 562 /* RVU block related APIs */ 563 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 564 int otx2_detach_resources(struct mbox *mbox); 565 int otx2_config_npa(struct otx2_nic *pfvf); 566 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 567 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 568 void otx2_aura_pool_free(struct otx2_nic *pfvf); 569 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 570 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 571 int otx2_config_nix(struct otx2_nic *pfvf); 572 int otx2_config_nix_queues(struct otx2_nic *pfvf); 573 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 574 int otx2_txsch_alloc(struct otx2_nic *pfvf); 575 int otx2_txschq_stop(struct otx2_nic *pfvf); 576 void otx2_sqb_flush(struct otx2_nic *pfvf); 577 dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 578 gfp_t gfp); 579 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 580 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 581 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 582 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 583 584 /* RSS configuration APIs*/ 585 int otx2_rss_init(struct otx2_nic *pfvf); 586 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 587 void otx2_set_rss_key(struct otx2_nic *pfvf); 588 int otx2_set_rss_table(struct otx2_nic *pfvf); 589 590 /* Mbox handlers */ 591 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 592 struct msix_offset_rsp *rsp); 593 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 594 struct npa_lf_alloc_rsp *rsp); 595 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 596 struct nix_lf_alloc_rsp *rsp); 597 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 598 struct nix_txsch_alloc_rsp *rsp); 599 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 600 struct cgx_stats_rsp *rsp); 601 602 /* Device stats APIs */ 603 void otx2_get_dev_stats(struct otx2_nic *pfvf); 604 void otx2_get_stats64(struct net_device *netdev, 605 struct rtnl_link_stats64 *stats); 606 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 607 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 608 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 609 void otx2_set_ethtool_ops(struct net_device *netdev); 610 611 int otx2_open(struct net_device *netdev); 612 int otx2_stop(struct net_device *netdev); 613 int otx2_set_real_num_queues(struct net_device *netdev, 614 int tx_queues, int rx_queues); 615 #endif /* OTX2_COMMON_H */ 616