1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/etherdevice.h> 12 #include <net/ip.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 #include "otx2_txrx.h" 19 20 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 21 22 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 23 { 24 struct nix_cqe_hdr_s *cqe_hdr; 25 26 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 27 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 28 return NULL; 29 30 cq->cq_head++; 31 cq->cq_head &= (cq->cqe_cnt - 1); 32 33 return cqe_hdr; 34 } 35 36 static unsigned int frag_num(unsigned int i) 37 { 38 #ifdef __BIG_ENDIAN 39 return (i & ~3) + 3 - (i & 3); 40 #else 41 return i; 42 #endif 43 } 44 45 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 46 struct sk_buff *skb, int seg, int *len) 47 { 48 const skb_frag_t *frag; 49 struct page *page; 50 int offset; 51 52 /* First segment is always skb->data */ 53 if (!seg) { 54 page = virt_to_page(skb->data); 55 offset = offset_in_page(skb->data); 56 *len = skb_headlen(skb); 57 } else { 58 frag = &skb_shinfo(skb)->frags[seg - 1]; 59 page = skb_frag_page(frag); 60 offset = skb_frag_off(frag); 61 *len = skb_frag_size(frag); 62 } 63 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 64 } 65 66 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 67 { 68 int seg; 69 70 for (seg = 0; seg < sg->num_segs; seg++) { 71 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 72 sg->size[seg], DMA_TO_DEVICE); 73 } 74 sg->num_segs = 0; 75 } 76 77 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 78 struct otx2_cq_queue *cq, 79 struct otx2_snd_queue *sq, 80 struct nix_cqe_tx_s *cqe, 81 int budget, int *tx_pkts, int *tx_bytes) 82 { 83 struct nix_send_comp_s *snd_comp = &cqe->comp; 84 struct sk_buff *skb = NULL; 85 struct sg_list *sg; 86 87 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 88 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 89 pfvf->netdev->name, cq->cint_idx, 90 snd_comp->status); 91 92 sg = &sq->sg[snd_comp->sqe_id]; 93 skb = (struct sk_buff *)sg->skb; 94 if (unlikely(!skb)) 95 return; 96 97 *tx_bytes += skb->len; 98 (*tx_pkts)++; 99 otx2_dma_unmap_skb_frags(pfvf, sg); 100 napi_consume_skb(skb, budget); 101 sg->skb = (u64)NULL; 102 } 103 104 static void otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 105 u64 iova, int len) 106 { 107 struct page *page; 108 void *va; 109 110 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 111 page = virt_to_page(va); 112 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 113 va - page_address(page), len, pfvf->rbsize); 114 115 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM, 116 pfvf->rbsize, DMA_FROM_DEVICE); 117 } 118 119 static void otx2_set_rxhash(struct otx2_nic *pfvf, 120 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 121 { 122 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 123 struct otx2_rss_info *rss; 124 u32 hash = 0; 125 126 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 127 return; 128 129 rss = &pfvf->hw.rss_info; 130 if (rss->flowkey_cfg) { 131 if (rss->flowkey_cfg & 132 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 133 hash_type = PKT_HASH_TYPE_L4; 134 else 135 hash_type = PKT_HASH_TYPE_L3; 136 hash = cqe->hdr.flow_tag; 137 } 138 skb_set_hash(skb, hash, hash_type); 139 } 140 141 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 142 struct nix_cqe_rx_s *cqe, int qidx) 143 { 144 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 145 struct nix_rx_parse_s *parse = &cqe->parse; 146 147 if (netif_msg_rx_err(pfvf)) 148 netdev_err(pfvf->netdev, 149 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 150 qidx, parse->errlev, parse->errcode); 151 152 if (parse->errlev == NPC_ERRLVL_RE) { 153 switch (parse->errcode) { 154 case ERRCODE_FCS: 155 case ERRCODE_FCS_RCV: 156 atomic_inc(&stats->rx_fcs_errs); 157 break; 158 case ERRCODE_UNDERSIZE: 159 atomic_inc(&stats->rx_undersize_errs); 160 break; 161 case ERRCODE_OVERSIZE: 162 atomic_inc(&stats->rx_oversize_errs); 163 break; 164 case ERRCODE_OL2_LEN_MISMATCH: 165 atomic_inc(&stats->rx_len_errs); 166 break; 167 default: 168 atomic_inc(&stats->rx_other_errs); 169 break; 170 } 171 } else if (parse->errlev == NPC_ERRLVL_NIX) { 172 switch (parse->errcode) { 173 case ERRCODE_OL3_LEN: 174 case ERRCODE_OL4_LEN: 175 case ERRCODE_IL3_LEN: 176 case ERRCODE_IL4_LEN: 177 atomic_inc(&stats->rx_len_errs); 178 break; 179 case ERRCODE_OL4_CSUM: 180 case ERRCODE_IL4_CSUM: 181 atomic_inc(&stats->rx_csum_errs); 182 break; 183 default: 184 atomic_inc(&stats->rx_other_errs); 185 break; 186 } 187 } else { 188 atomic_inc(&stats->rx_other_errs); 189 /* For now ignore all the NPC parser errors and 190 * pass the packets to stack. 191 */ 192 return false; 193 } 194 195 /* If RXALL is enabled pass on packets to stack. */ 196 if (cqe->sg.segs && (pfvf->netdev->features & NETIF_F_RXALL)) 197 return false; 198 199 /* Free buffer back to pool */ 200 if (cqe->sg.segs) 201 otx2_aura_freeptr(pfvf, qidx, cqe->sg.seg_addr & ~0x07ULL); 202 return true; 203 } 204 205 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 206 struct napi_struct *napi, 207 struct otx2_cq_queue *cq, 208 struct nix_cqe_rx_s *cqe) 209 { 210 struct nix_rx_parse_s *parse = &cqe->parse; 211 struct sk_buff *skb = NULL; 212 213 if (unlikely(parse->errlev || parse->errcode)) { 214 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 215 return; 216 } 217 218 skb = napi_get_frags(napi); 219 if (unlikely(!skb)) 220 return; 221 222 otx2_skb_add_frag(pfvf, skb, cqe->sg.seg_addr, cqe->sg.seg_size); 223 cq->pool_ptrs++; 224 225 otx2_set_rxhash(pfvf, cqe, skb); 226 227 skb_record_rx_queue(skb, cq->cq_idx); 228 if (pfvf->netdev->features & NETIF_F_RXCSUM) 229 skb->ip_summed = CHECKSUM_UNNECESSARY; 230 231 napi_gro_frags(napi); 232 } 233 234 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 235 struct napi_struct *napi, 236 struct otx2_cq_queue *cq, int budget) 237 { 238 struct nix_cqe_rx_s *cqe; 239 int processed_cqe = 0; 240 s64 bufptr; 241 242 while (likely(processed_cqe < budget)) { 243 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 244 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 245 !cqe->sg.seg_addr) { 246 if (!processed_cqe) 247 return 0; 248 break; 249 } 250 cq->cq_head++; 251 cq->cq_head &= (cq->cqe_cnt - 1); 252 253 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 254 255 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 256 cqe->sg.seg_addr = 0x00; 257 processed_cqe++; 258 } 259 260 /* Free CQEs to HW */ 261 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 262 ((u64)cq->cq_idx << 32) | processed_cqe); 263 264 if (unlikely(!cq->pool_ptrs)) 265 return 0; 266 267 /* Refill pool with new buffers */ 268 while (cq->pool_ptrs) { 269 bufptr = otx2_alloc_rbuf(pfvf, cq->rbpool, GFP_ATOMIC); 270 if (unlikely(bufptr <= 0)) { 271 struct refill_work *work; 272 struct delayed_work *dwork; 273 274 work = &pfvf->refill_wrk[cq->cq_idx]; 275 dwork = &work->pool_refill_work; 276 /* Schedule a task if no other task is running */ 277 if (!cq->refill_task_sched) { 278 cq->refill_task_sched = true; 279 schedule_delayed_work(dwork, 280 msecs_to_jiffies(100)); 281 } 282 break; 283 } 284 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 285 cq->pool_ptrs--; 286 } 287 288 return processed_cqe; 289 } 290 291 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 292 struct otx2_cq_queue *cq, int budget) 293 { 294 int tx_pkts = 0, tx_bytes = 0; 295 struct nix_cqe_tx_s *cqe; 296 int processed_cqe = 0; 297 298 while (likely(processed_cqe < budget)) { 299 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 300 if (unlikely(!cqe)) { 301 if (!processed_cqe) 302 return 0; 303 break; 304 } 305 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[cq->cint_idx], 306 cqe, budget, &tx_pkts, &tx_bytes); 307 308 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 309 processed_cqe++; 310 } 311 312 /* Free CQEs to HW */ 313 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 314 ((u64)cq->cq_idx << 32) | processed_cqe); 315 316 if (likely(tx_pkts)) { 317 struct netdev_queue *txq; 318 319 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx); 320 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 321 /* Check if queue was stopped earlier due to ring full */ 322 smp_mb(); 323 if (netif_tx_queue_stopped(txq) && 324 netif_carrier_ok(pfvf->netdev)) 325 netif_tx_wake_queue(txq); 326 } 327 return 0; 328 } 329 330 int otx2_napi_handler(struct napi_struct *napi, int budget) 331 { 332 struct otx2_cq_poll *cq_poll; 333 int workdone = 0, cq_idx, i; 334 struct otx2_cq_queue *cq; 335 struct otx2_qset *qset; 336 struct otx2_nic *pfvf; 337 338 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 339 pfvf = (struct otx2_nic *)cq_poll->dev; 340 qset = &pfvf->qset; 341 342 for (i = CQS_PER_CINT - 1; i >= 0; i--) { 343 cq_idx = cq_poll->cq_ids[i]; 344 if (unlikely(cq_idx == CINT_INVALID_CQ)) 345 continue; 346 cq = &qset->cq[cq_idx]; 347 if (cq->cq_type == CQ_RX) { 348 /* If the RQ refill WQ task is running, skip napi 349 * scheduler for this queue. 350 */ 351 if (cq->refill_task_sched) 352 continue; 353 workdone += otx2_rx_napi_handler(pfvf, napi, 354 cq, budget); 355 } else { 356 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 357 } 358 } 359 360 /* Clear the IRQ */ 361 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 362 363 if (workdone < budget && napi_complete_done(napi, workdone)) { 364 /* If interface is going down, don't re-enable IRQ */ 365 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 366 return workdone; 367 368 /* Re-enable interrupts */ 369 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 370 BIT_ULL(0)); 371 } 372 return workdone; 373 } 374 375 static void otx2_sqe_flush(struct otx2_snd_queue *sq, int size) 376 { 377 u64 status; 378 379 /* Packet data stores should finish before SQE is flushed to HW */ 380 dma_wmb(); 381 382 do { 383 memcpy(sq->lmt_addr, sq->sqe_base, size); 384 status = otx2_lmt_flush(sq->io_addr); 385 } while (status == 0); 386 387 sq->head++; 388 sq->head &= (sq->sqe_cnt - 1); 389 } 390 391 #define MAX_SEGS_PER_SG 3 392 /* Add SQE scatter/gather subdescriptor structure */ 393 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 394 struct sk_buff *skb, int num_segs, int *offset) 395 { 396 struct nix_sqe_sg_s *sg = NULL; 397 u64 dma_addr, *iova = NULL; 398 u16 *sg_lens = NULL; 399 int seg, len; 400 401 sq->sg[sq->head].num_segs = 0; 402 403 for (seg = 0; seg < num_segs; seg++) { 404 if ((seg % MAX_SEGS_PER_SG) == 0) { 405 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 406 sg->ld_type = NIX_SEND_LDTYPE_LDD; 407 sg->subdc = NIX_SUBDC_SG; 408 sg->segs = 0; 409 sg_lens = (void *)sg; 410 iova = (void *)sg + sizeof(*sg); 411 /* Next subdc always starts at a 16byte boundary. 412 * So if sg->segs is whether 2 or 3, offset += 16bytes. 413 */ 414 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 415 *offset += sizeof(*sg) + (3 * sizeof(u64)); 416 else 417 *offset += sizeof(*sg) + sizeof(u64); 418 } 419 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 420 if (dma_mapping_error(pfvf->dev, dma_addr)) 421 return false; 422 423 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 424 sg->segs++; 425 *iova++ = dma_addr; 426 427 /* Save DMA mapping info for later unmapping */ 428 sq->sg[sq->head].dma_addr[seg] = dma_addr; 429 sq->sg[sq->head].size[seg] = len; 430 sq->sg[sq->head].num_segs++; 431 } 432 433 sq->sg[sq->head].skb = (u64)skb; 434 return true; 435 } 436 437 /* Add SQE extended header subdescriptor */ 438 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 439 struct sk_buff *skb, int *offset) 440 { 441 struct nix_sqe_ext_s *ext; 442 443 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 444 ext->subdc = NIX_SUBDC_EXT; 445 if (skb_shinfo(skb)->gso_size) { 446 ext->lso = 1; 447 ext->lso_sb = skb_transport_offset(skb) + tcp_hdrlen(skb); 448 ext->lso_mps = skb_shinfo(skb)->gso_size; 449 450 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 451 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 452 ext->lso_format = pfvf->hw.lso_tsov4_idx; 453 454 /* HW adds payload size to 'ip_hdr->tot_len' while 455 * sending TSO segment, hence set payload length 456 * in IP header of the packet to just header length. 457 */ 458 ip_hdr(skb)->tot_len = 459 htons(ext->lso_sb - skb_network_offset(skb)); 460 } else { 461 ext->lso_format = pfvf->hw.lso_tsov6_idx; 462 ipv6_hdr(skb)->payload_len = 463 htons(ext->lso_sb - skb_network_offset(skb)); 464 } 465 } 466 *offset += sizeof(*ext); 467 } 468 469 /* Add SQE header subdescriptor structure */ 470 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 471 struct nix_sqe_hdr_s *sqe_hdr, 472 struct sk_buff *skb, u16 qidx) 473 { 474 int proto = 0; 475 476 /* Check if SQE was framed before, if yes then no need to 477 * set these constants again and again. 478 */ 479 if (!sqe_hdr->total) { 480 /* Don't free Tx buffers to Aura */ 481 sqe_hdr->df = 1; 482 sqe_hdr->aura = sq->aura_id; 483 /* Post a CQE Tx after pkt transmission */ 484 sqe_hdr->pnc = 1; 485 sqe_hdr->sq = qidx; 486 } 487 sqe_hdr->total = skb->len; 488 /* Set SQE identifier which will be used later for freeing SKB */ 489 sqe_hdr->sqe_id = sq->head; 490 491 /* Offload TCP/UDP checksum to HW */ 492 if (skb->ip_summed == CHECKSUM_PARTIAL) { 493 sqe_hdr->ol3ptr = skb_network_offset(skb); 494 sqe_hdr->ol4ptr = skb_transport_offset(skb); 495 /* get vlan protocol Ethertype */ 496 if (eth_type_vlan(skb->protocol)) 497 skb->protocol = vlan_get_protocol(skb); 498 499 if (skb->protocol == htons(ETH_P_IP)) { 500 proto = ip_hdr(skb)->protocol; 501 /* In case of TSO, HW needs this to be explicitly set. 502 * So set this always, instead of adding a check. 503 */ 504 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 505 } else if (skb->protocol == htons(ETH_P_IPV6)) { 506 proto = ipv6_hdr(skb)->nexthdr; 507 } 508 509 if (proto == IPPROTO_TCP) 510 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 511 else if (proto == IPPROTO_UDP) 512 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 513 } 514 } 515 516 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 517 struct otx2_snd_queue *sq, 518 struct sk_buff *skb, int sqe, int hdr_len) 519 { 520 int num_segs = skb_shinfo(skb)->nr_frags + 1; 521 struct sg_list *sg = &sq->sg[sqe]; 522 u64 dma_addr; 523 int seg, len; 524 525 sg->num_segs = 0; 526 527 /* Get payload length at skb->data */ 528 len = skb_headlen(skb) - hdr_len; 529 530 for (seg = 0; seg < num_segs; seg++) { 531 /* Skip skb->data, if there is no payload */ 532 if (!seg && !len) 533 continue; 534 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 535 if (dma_mapping_error(pfvf->dev, dma_addr)) 536 goto unmap; 537 538 /* Save DMA mapping info for later unmapping */ 539 sg->dma_addr[sg->num_segs] = dma_addr; 540 sg->size[sg->num_segs] = len; 541 sg->num_segs++; 542 } 543 return 0; 544 unmap: 545 otx2_dma_unmap_skb_frags(pfvf, sg); 546 return -EINVAL; 547 } 548 549 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 550 struct sk_buff *skb, int seg, 551 u64 seg_addr, int hdr_len, int sqe) 552 { 553 struct sg_list *sg = &sq->sg[sqe]; 554 const skb_frag_t *frag; 555 int offset; 556 557 if (seg < 0) 558 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 559 560 frag = &skb_shinfo(skb)->frags[seg]; 561 offset = seg_addr - (u64)skb_frag_address(frag); 562 if (skb_headlen(skb) - hdr_len) 563 seg++; 564 return sg->dma_addr[seg] + offset; 565 } 566 567 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 568 struct sg_list *list, int *offset) 569 { 570 struct nix_sqe_sg_s *sg = NULL; 571 u16 *sg_lens = NULL; 572 u64 *iova = NULL; 573 int seg; 574 575 /* Add SG descriptors with buffer addresses */ 576 for (seg = 0; seg < list->num_segs; seg++) { 577 if ((seg % MAX_SEGS_PER_SG) == 0) { 578 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 579 sg->ld_type = NIX_SEND_LDTYPE_LDD; 580 sg->subdc = NIX_SUBDC_SG; 581 sg->segs = 0; 582 sg_lens = (void *)sg; 583 iova = (void *)sg + sizeof(*sg); 584 /* Next subdc always starts at a 16byte boundary. 585 * So if sg->segs is whether 2 or 3, offset += 16bytes. 586 */ 587 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 588 *offset += sizeof(*sg) + (3 * sizeof(u64)); 589 else 590 *offset += sizeof(*sg) + sizeof(u64); 591 } 592 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 593 *iova++ = list->dma_addr[seg]; 594 sg->segs++; 595 } 596 } 597 598 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 599 struct sk_buff *skb, u16 qidx) 600 { 601 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 602 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 603 int tcp_data, seg_len, pkt_len, offset; 604 struct nix_sqe_hdr_s *sqe_hdr; 605 int first_sqe = sq->head; 606 struct sg_list list; 607 struct tso_t tso; 608 609 /* Map SKB's fragments to DMA. 610 * It's done here to avoid mapping for every TSO segment's packet. 611 */ 612 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 613 dev_kfree_skb_any(skb); 614 return; 615 } 616 617 netdev_tx_sent_queue(txq, skb->len); 618 619 tso_start(skb, &tso); 620 tcp_data = skb->len - hdr_len; 621 while (tcp_data > 0) { 622 char *hdr; 623 624 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 625 tcp_data -= seg_len; 626 627 /* Set SQE's SEND_HDR */ 628 memset(sq->sqe_base, 0, sq->sqe_size); 629 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 630 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 631 offset = sizeof(*sqe_hdr); 632 633 /* Add TSO segment's pkt header */ 634 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 635 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 636 list.dma_addr[0] = 637 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 638 list.size[0] = hdr_len; 639 list.num_segs = 1; 640 641 /* Add TSO segment's payload data fragments */ 642 pkt_len = hdr_len; 643 while (seg_len > 0) { 644 int size; 645 646 size = min_t(int, tso.size, seg_len); 647 648 list.size[list.num_segs] = size; 649 list.dma_addr[list.num_segs] = 650 otx2_tso_frag_dma_addr(sq, skb, 651 tso.next_frag_idx - 1, 652 (u64)tso.data, hdr_len, 653 first_sqe); 654 list.num_segs++; 655 pkt_len += size; 656 seg_len -= size; 657 tso_build_data(skb, &tso, size); 658 } 659 sqe_hdr->total = pkt_len; 660 otx2_sqe_tso_add_sg(sq, &list, &offset); 661 662 /* DMA mappings and skb needs to be freed only after last 663 * TSO segment is transmitted out. So set 'PNC' only for 664 * last segment. Also point last segment's sqe_id to first 665 * segment's SQE index where skb address and DMA mappings 666 * are saved. 667 */ 668 if (!tcp_data) { 669 sqe_hdr->pnc = 1; 670 sqe_hdr->sqe_id = first_sqe; 671 sq->sg[first_sqe].skb = (u64)skb; 672 } else { 673 sqe_hdr->pnc = 0; 674 } 675 676 sqe_hdr->sizem1 = (offset / 16) - 1; 677 678 /* Flush SQE to HW */ 679 otx2_sqe_flush(sq, offset); 680 } 681 } 682 683 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 684 struct sk_buff *skb) 685 { 686 int payload_len, last_seg_size; 687 688 if (!pfvf->hw.hw_tso) 689 return false; 690 691 /* HW has an issue due to which when the payload of the last LSO 692 * segment is shorter than 16 bytes, some header fields may not 693 * be correctly modified, hence don't offload such TSO segments. 694 */ 695 if (!is_96xx_B0(pfvf->pdev)) 696 return true; 697 698 payload_len = skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb)); 699 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 700 if (last_seg_size && last_seg_size < 16) 701 return false; 702 703 return true; 704 } 705 706 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 707 { 708 if (!skb_shinfo(skb)->gso_size) 709 return 1; 710 711 /* HW TSO */ 712 if (is_hw_tso_supported(pfvf, skb)) 713 return 1; 714 715 /* SW TSO */ 716 return skb_shinfo(skb)->gso_segs; 717 } 718 719 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 720 struct sk_buff *skb, u16 qidx) 721 { 722 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 723 struct otx2_nic *pfvf = netdev_priv(netdev); 724 int offset, num_segs, free_sqe; 725 struct nix_sqe_hdr_s *sqe_hdr; 726 727 /* Check if there is room for new SQE. 728 * 'Num of SQBs freed to SQ's pool - SQ's Aura count' 729 * will give free SQE count. 730 */ 731 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 732 733 if (free_sqe < sq->sqe_thresh || 734 free_sqe < otx2_get_sqe_count(pfvf, skb)) 735 return false; 736 737 num_segs = skb_shinfo(skb)->nr_frags + 1; 738 739 /* If SKB doesn't fit in a single SQE, linearize it. 740 * TODO: Consider adding JUMP descriptor instead. 741 */ 742 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 743 if (__skb_linearize(skb)) { 744 dev_kfree_skb_any(skb); 745 return true; 746 } 747 num_segs = skb_shinfo(skb)->nr_frags + 1; 748 } 749 750 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 751 otx2_sq_append_tso(pfvf, sq, skb, qidx); 752 return true; 753 } 754 755 /* Set SQE's SEND_HDR. 756 * Do not clear the first 64bit as it contains constant info. 757 */ 758 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 759 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 760 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 761 offset = sizeof(*sqe_hdr); 762 763 /* Add extended header if needed */ 764 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 765 766 /* Add SG subdesc with data frags */ 767 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 768 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 769 return false; 770 } 771 772 sqe_hdr->sizem1 = (offset / 16) - 1; 773 774 netdev_tx_sent_queue(txq, skb->len); 775 776 /* Flush SQE to HW */ 777 otx2_sqe_flush(sq, offset); 778 779 return true; 780 } 781 782 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 783 { 784 struct nix_cqe_rx_s *cqe; 785 int processed_cqe = 0; 786 u64 iova, pa; 787 788 while ((cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq))) { 789 if (!cqe->sg.subdc) 790 continue; 791 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 792 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 793 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); 794 put_page(virt_to_page(phys_to_virt(pa))); 795 processed_cqe++; 796 } 797 798 /* Free CQEs to HW */ 799 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 800 ((u64)cq->cq_idx << 32) | processed_cqe); 801 } 802 803 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 804 { 805 struct sk_buff *skb = NULL; 806 struct otx2_snd_queue *sq; 807 struct nix_cqe_tx_s *cqe; 808 int processed_cqe = 0; 809 struct sg_list *sg; 810 811 sq = &pfvf->qset.sq[cq->cint_idx]; 812 813 while ((cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq))) { 814 sg = &sq->sg[cqe->comp.sqe_id]; 815 skb = (struct sk_buff *)sg->skb; 816 if (skb) { 817 otx2_dma_unmap_skb_frags(pfvf, sg); 818 dev_kfree_skb_any(skb); 819 sg->skb = (u64)NULL; 820 } 821 processed_cqe++; 822 } 823 824 /* Free CQEs to HW */ 825 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 826 ((u64)cq->cq_idx << 32) | processed_cqe); 827 } 828 829 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 830 { 831 struct msg_req *msg; 832 int err; 833 834 otx2_mbox_lock(&pfvf->mbox); 835 if (enable) 836 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 837 else 838 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 839 840 if (!msg) { 841 otx2_mbox_unlock(&pfvf->mbox); 842 return -ENOMEM; 843 } 844 845 err = otx2_sync_mbox_msg(&pfvf->mbox); 846 otx2_mbox_unlock(&pfvf->mbox); 847 return err; 848 } 849