1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/refcount.h> 13 14 #define MTK_QDMA_PAGE_SIZE 2048 15 #define MTK_MAX_RX_LENGTH 1536 16 #define MTK_TX_DMA_BUF_LEN 0x3fff 17 #define MTK_DMA_SIZE 256 18 #define MTK_NAPI_WEIGHT 64 19 #define MTK_MAC_COUNT 2 20 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 21 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 22 #define MTK_DMA_DUMMY_DESC 0xffffffff 23 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 24 NETIF_MSG_PROBE | \ 25 NETIF_MSG_LINK | \ 26 NETIF_MSG_TIMER | \ 27 NETIF_MSG_IFDOWN | \ 28 NETIF_MSG_IFUP | \ 29 NETIF_MSG_RX_ERR | \ 30 NETIF_MSG_TX_ERR) 31 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 32 NETIF_F_RXCSUM | \ 33 NETIF_F_HW_VLAN_CTAG_TX | \ 34 NETIF_F_HW_VLAN_CTAG_RX | \ 35 NETIF_F_SG | NETIF_F_TSO | \ 36 NETIF_F_TSO6 | \ 37 NETIF_F_IPV6_CSUM) 38 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 39 40 #define MTK_MAX_RX_RING_NUM 4 41 #define MTK_HW_LRO_DMA_SIZE 8 42 43 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 44 #define MTK_MAX_LRO_IP_CNT 2 45 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 46 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 47 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 48 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 49 #define MTK_HW_LRO_MAX_AGG_CNT 64 50 #define MTK_HW_LRO_BW_THRE 3000 51 #define MTK_HW_LRO_REPLACE_DELTA 1000 52 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 53 54 /* Frame Engine Global Reset Register */ 55 #define MTK_RST_GL 0x04 56 #define RST_GL_PSE BIT(0) 57 58 /* Frame Engine Interrupt Status Register */ 59 #define MTK_INT_STATUS2 0x08 60 #define MTK_GDM1_AF BIT(28) 61 #define MTK_GDM2_AF BIT(29) 62 63 /* PDMA HW LRO Alter Flow Timer Register */ 64 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 65 66 /* Frame Engine Interrupt Grouping Register */ 67 #define MTK_FE_INT_GRP 0x20 68 69 /* CDMP Ingress Control Register */ 70 #define MTK_CDMQ_IG_CTRL 0x1400 71 #define MTK_CDMQ_STAG_EN BIT(0) 72 73 /* CDMP Exgress Control Register */ 74 #define MTK_CDMP_EG_CTRL 0x404 75 76 /* GDM Exgress Control Register */ 77 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 78 #define MTK_GDMA_ICS_EN BIT(22) 79 #define MTK_GDMA_TCS_EN BIT(21) 80 #define MTK_GDMA_UCS_EN BIT(20) 81 82 /* Unicast Filter MAC Address Register - Low */ 83 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 84 85 /* Unicast Filter MAC Address Register - High */ 86 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 87 88 /* PDMA RX Base Pointer Register */ 89 #define MTK_PRX_BASE_PTR0 0x900 90 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 91 92 /* PDMA RX Maximum Count Register */ 93 #define MTK_PRX_MAX_CNT0 0x904 94 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 95 96 /* PDMA RX CPU Pointer Register */ 97 #define MTK_PRX_CRX_IDX0 0x908 98 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 99 100 /* PDMA HW LRO Control Registers */ 101 #define MTK_PDMA_LRO_CTRL_DW0 0x980 102 #define MTK_LRO_EN BIT(0) 103 #define MTK_L3_CKS_UPD_EN BIT(7) 104 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 105 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 106 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 107 108 #define MTK_PDMA_LRO_CTRL_DW1 0x984 109 #define MTK_PDMA_LRO_CTRL_DW2 0x988 110 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 111 #define MTK_ADMA_MODE BIT(15) 112 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 113 114 /* PDMA Global Configuration Register */ 115 #define MTK_PDMA_GLO_CFG 0xa04 116 #define MTK_MULTI_EN BIT(10) 117 118 /* PDMA Reset Index Register */ 119 #define MTK_PDMA_RST_IDX 0xa08 120 #define MTK_PST_DRX_IDX0 BIT(16) 121 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 122 123 /* PDMA Delay Interrupt Register */ 124 #define MTK_PDMA_DELAY_INT 0xa0c 125 #define MTK_PDMA_DELAY_RX_EN BIT(15) 126 #define MTK_PDMA_DELAY_RX_PINT 4 127 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 128 #define MTK_PDMA_DELAY_RX_PTIME 4 129 #define MTK_PDMA_DELAY_RX_DELAY \ 130 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 131 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 132 133 /* PDMA Interrupt Status Register */ 134 #define MTK_PDMA_INT_STATUS 0xa20 135 136 /* PDMA Interrupt Mask Register */ 137 #define MTK_PDMA_INT_MASK 0xa28 138 139 /* PDMA HW LRO Alter Flow Delta Register */ 140 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 141 142 /* PDMA Interrupt grouping registers */ 143 #define MTK_PDMA_INT_GRP1 0xa50 144 #define MTK_PDMA_INT_GRP2 0xa54 145 146 /* PDMA HW LRO IP Setting Registers */ 147 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 148 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 149 #define MTK_RING_MYIP_VLD BIT(9) 150 151 /* PDMA HW LRO Ring Control Registers */ 152 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 153 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 154 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 155 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 156 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 157 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 158 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 159 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 160 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 161 #define MTK_RING_VLD BIT(8) 162 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 163 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 164 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 165 166 /* QDMA TX Queue Configuration Registers */ 167 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 168 #define QDMA_RES_THRES 4 169 170 /* QDMA TX Queue Scheduler Registers */ 171 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 172 173 /* QDMA RX Base Pointer Register */ 174 #define MTK_QRX_BASE_PTR0 0x1900 175 176 /* QDMA RX Maximum Count Register */ 177 #define MTK_QRX_MAX_CNT0 0x1904 178 179 /* QDMA RX CPU Pointer Register */ 180 #define MTK_QRX_CRX_IDX0 0x1908 181 182 /* QDMA RX DMA Pointer Register */ 183 #define MTK_QRX_DRX_IDX0 0x190C 184 185 /* QDMA Global Configuration Register */ 186 #define MTK_QDMA_GLO_CFG 0x1A04 187 #define MTK_RX_2B_OFFSET BIT(31) 188 #define MTK_RX_BT_32DWORDS (3 << 11) 189 #define MTK_NDP_CO_PRO BIT(10) 190 #define MTK_TX_WB_DDONE BIT(6) 191 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 192 #define MTK_RX_DMA_BUSY BIT(3) 193 #define MTK_TX_DMA_BUSY BIT(1) 194 #define MTK_RX_DMA_EN BIT(2) 195 #define MTK_TX_DMA_EN BIT(0) 196 #define MTK_DMA_BUSY_TIMEOUT HZ 197 198 /* QDMA Reset Index Register */ 199 #define MTK_QDMA_RST_IDX 0x1A08 200 201 /* QDMA Delay Interrupt Register */ 202 #define MTK_QDMA_DELAY_INT 0x1A0C 203 204 /* QDMA Flow Control Register */ 205 #define MTK_QDMA_FC_THRES 0x1A10 206 #define FC_THRES_DROP_MODE BIT(20) 207 #define FC_THRES_DROP_EN (7 << 16) 208 #define FC_THRES_MIN 0x4444 209 210 /* QDMA Interrupt Status Register */ 211 #define MTK_QMTK_INT_STATUS 0x1A18 212 #define MTK_RX_DONE_DLY BIT(30) 213 #define MTK_RX_DONE_INT3 BIT(19) 214 #define MTK_RX_DONE_INT2 BIT(18) 215 #define MTK_RX_DONE_INT1 BIT(17) 216 #define MTK_RX_DONE_INT0 BIT(16) 217 #define MTK_TX_DONE_INT3 BIT(3) 218 #define MTK_TX_DONE_INT2 BIT(2) 219 #define MTK_TX_DONE_INT1 BIT(1) 220 #define MTK_TX_DONE_INT0 BIT(0) 221 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 222 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 223 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 224 225 /* QDMA Interrupt grouping registers */ 226 #define MTK_QDMA_INT_GRP1 0x1a20 227 #define MTK_QDMA_INT_GRP2 0x1a24 228 #define MTK_RLS_DONE_INT BIT(0) 229 230 /* QDMA Interrupt Status Register */ 231 #define MTK_QDMA_INT_MASK 0x1A1C 232 233 /* QDMA Interrupt Mask Register */ 234 #define MTK_QDMA_HRED2 0x1A44 235 236 /* QDMA TX Forward CPU Pointer Register */ 237 #define MTK_QTX_CTX_PTR 0x1B00 238 239 /* QDMA TX Forward DMA Pointer Register */ 240 #define MTK_QTX_DTX_PTR 0x1B04 241 242 /* QDMA TX Release CPU Pointer Register */ 243 #define MTK_QTX_CRX_PTR 0x1B10 244 245 /* QDMA TX Release DMA Pointer Register */ 246 #define MTK_QTX_DRX_PTR 0x1B14 247 248 /* QDMA FQ Head Pointer Register */ 249 #define MTK_QDMA_FQ_HEAD 0x1B20 250 251 /* QDMA FQ Head Pointer Register */ 252 #define MTK_QDMA_FQ_TAIL 0x1B24 253 254 /* QDMA FQ Free Page Counter Register */ 255 #define MTK_QDMA_FQ_CNT 0x1B28 256 257 /* QDMA FQ Free Page Buffer Length Register */ 258 #define MTK_QDMA_FQ_BLEN 0x1B2C 259 260 /* GMA1 Received Good Byte Count Register */ 261 #define MTK_GDM1_TX_GBCNT 0x2400 262 #define MTK_STAT_OFFSET 0x40 263 264 /* QDMA descriptor txd4 */ 265 #define TX_DMA_CHKSUM (0x7 << 29) 266 #define TX_DMA_TSO BIT(28) 267 #define TX_DMA_FPORT_SHIFT 25 268 #define TX_DMA_FPORT_MASK 0x7 269 #define TX_DMA_INS_VLAN BIT(16) 270 271 /* QDMA descriptor txd3 */ 272 #define TX_DMA_OWNER_CPU BIT(31) 273 #define TX_DMA_LS0 BIT(30) 274 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 275 #define TX_DMA_SWC BIT(14) 276 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 277 278 /* QDMA descriptor rxd2 */ 279 #define RX_DMA_DONE BIT(31) 280 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 281 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 282 283 /* QDMA descriptor rxd3 */ 284 #define RX_DMA_VID(_x) ((_x) & 0xfff) 285 286 /* QDMA descriptor rxd4 */ 287 #define RX_DMA_L4_VALID BIT(24) 288 #define RX_DMA_FPORT_SHIFT 19 289 #define RX_DMA_FPORT_MASK 0x7 290 291 /* PHY Indirect Access Control registers */ 292 #define MTK_PHY_IAC 0x10004 293 #define PHY_IAC_ACCESS BIT(31) 294 #define PHY_IAC_READ BIT(19) 295 #define PHY_IAC_WRITE BIT(18) 296 #define PHY_IAC_START BIT(16) 297 #define PHY_IAC_ADDR_SHIFT 20 298 #define PHY_IAC_REG_SHIFT 25 299 #define PHY_IAC_TIMEOUT HZ 300 301 #define MTK_MAC_MISC 0x1000c 302 #define MTK_MUX_TO_ESW BIT(0) 303 304 /* Mac control registers */ 305 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 306 #define MAC_MCR_MAX_RX_1536 BIT(24) 307 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 308 #define MAC_MCR_FORCE_MODE BIT(15) 309 #define MAC_MCR_TX_EN BIT(14) 310 #define MAC_MCR_RX_EN BIT(13) 311 #define MAC_MCR_BACKOFF_EN BIT(9) 312 #define MAC_MCR_BACKPR_EN BIT(8) 313 #define MAC_MCR_FORCE_RX_FC BIT(5) 314 #define MAC_MCR_FORCE_TX_FC BIT(4) 315 #define MAC_MCR_SPEED_1000 BIT(3) 316 #define MAC_MCR_SPEED_100 BIT(2) 317 #define MAC_MCR_FORCE_DPX BIT(1) 318 #define MAC_MCR_FORCE_LINK BIT(0) 319 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 320 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 321 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 322 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 323 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 324 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 325 326 /* TRGMII RXC control register */ 327 #define TRGMII_RCK_CTRL 0x10300 328 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 329 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 330 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 331 #define RXC_DQSISEL BIT(30) 332 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 333 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 334 335 /* TRGMII RXC control register */ 336 #define TRGMII_TCK_CTRL 0x10340 337 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 338 #define TXC_INV BIT(30) 339 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 340 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 341 342 /* TRGMII Interface mode register */ 343 #define INTF_MODE 0x10390 344 #define TRGMII_INTF_DIS BIT(0) 345 #define TRGMII_MODE BIT(1) 346 #define TRGMII_CENTRAL_ALIGNED BIT(2) 347 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 348 #define INTF_MODE_RGMII_10_100 0 349 350 /* GPIO port control registers for GMAC 2*/ 351 #define GPIO_OD33_CTRL8 0x4c0 352 #define GPIO_BIAS_CTRL 0xed0 353 #define GPIO_DRV_SEL10 0xf00 354 355 /* ethernet subsystem chip id register */ 356 #define ETHSYS_CHIPID0_3 0x0 357 #define ETHSYS_CHIPID4_7 0x4 358 #define MT7623_ETH 7623 359 #define MT7622_ETH 7622 360 #define MT7621_ETH 7621 361 362 /* ethernet subsystem config register */ 363 #define ETHSYS_SYSCFG0 0x14 364 #define SYSCFG0_GE_MASK 0x3 365 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 366 #define SYSCFG0_SGMII_MASK (3 << 8) 367 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8)) 368 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8)) 369 370 /* ethernet subsystem clock register */ 371 #define ETHSYS_CLKCFG0 0x2c 372 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 373 374 /* ethernet reset control register */ 375 #define ETHSYS_RSTCTRL 0x34 376 #define RSTCTRL_FE BIT(6) 377 #define RSTCTRL_PPE BIT(31) 378 379 /* SGMII subsystem config registers */ 380 /* Register to auto-negotiation restart */ 381 #define SGMSYS_PCS_CONTROL_1 0x0 382 #define SGMII_AN_RESTART BIT(9) 383 384 /* Register to programmable link timer, the unit in 2 * 8ns */ 385 #define SGMSYS_PCS_LINK_TIMER 0x18 386 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 387 388 /* Register to control remote fault */ 389 #define SGMSYS_SGMII_MODE 0x20 390 #define SGMII_REMOTE_FAULT_DIS BIT(8) 391 392 /* Register to power up QPHY */ 393 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 394 #define SGMII_PHYA_PWD BIT(4) 395 396 struct mtk_rx_dma { 397 unsigned int rxd1; 398 unsigned int rxd2; 399 unsigned int rxd3; 400 unsigned int rxd4; 401 } __packed __aligned(4); 402 403 struct mtk_tx_dma { 404 unsigned int txd1; 405 unsigned int txd2; 406 unsigned int txd3; 407 unsigned int txd4; 408 } __packed __aligned(4); 409 410 struct mtk_eth; 411 struct mtk_mac; 412 413 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 414 * @stats_lock: make sure that stats operations are atomic 415 * @reg_offset: the status register offset of the SoC 416 * @syncp: the refcount 417 * 418 * All of the supported SoCs have hardware counters for traffic statistics. 419 * Whenever the status IRQ triggers we can read the latest stats from these 420 * counters and store them in this struct. 421 */ 422 struct mtk_hw_stats { 423 u64 tx_bytes; 424 u64 tx_packets; 425 u64 tx_skip; 426 u64 tx_collisions; 427 u64 rx_bytes; 428 u64 rx_packets; 429 u64 rx_overflow; 430 u64 rx_fcs_errors; 431 u64 rx_short_errors; 432 u64 rx_long_errors; 433 u64 rx_checksum_errors; 434 u64 rx_flow_control_packets; 435 436 spinlock_t stats_lock; 437 u32 reg_offset; 438 struct u64_stats_sync syncp; 439 }; 440 441 enum mtk_tx_flags { 442 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 443 * track how memory was allocated so that it can be freed properly. 444 */ 445 MTK_TX_FLAGS_SINGLE0 = 0x01, 446 MTK_TX_FLAGS_PAGE0 = 0x02, 447 448 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 449 * SKB out instead of looking up through hardware TX descriptor. 450 */ 451 MTK_TX_FLAGS_FPORT0 = 0x04, 452 MTK_TX_FLAGS_FPORT1 = 0x08, 453 }; 454 455 /* This enum allows us to identify how the clock is defined on the array of the 456 * clock in the order 457 */ 458 enum mtk_clks_map { 459 MTK_CLK_ETHIF, 460 MTK_CLK_ESW, 461 MTK_CLK_GP0, 462 MTK_CLK_GP1, 463 MTK_CLK_GP2, 464 MTK_CLK_TRGPLL, 465 MTK_CLK_SGMII_TX_250M, 466 MTK_CLK_SGMII_RX_250M, 467 MTK_CLK_SGMII_CDR_REF, 468 MTK_CLK_SGMII_CDR_FB, 469 MTK_CLK_SGMII_CK, 470 MTK_CLK_ETH2PLL, 471 MTK_CLK_MAX 472 }; 473 474 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 475 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 476 BIT(MTK_CLK_TRGPLL)) 477 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 478 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 479 BIT(MTK_CLK_GP2) | \ 480 BIT(MTK_CLK_SGMII_TX_250M) | \ 481 BIT(MTK_CLK_SGMII_RX_250M) | \ 482 BIT(MTK_CLK_SGMII_CDR_REF) | \ 483 BIT(MTK_CLK_SGMII_CDR_FB) | \ 484 BIT(MTK_CLK_SGMII_CK) | \ 485 BIT(MTK_CLK_ETH2PLL)) 486 #define MT7621_CLKS_BITMAP (0) 487 488 enum mtk_dev_state { 489 MTK_HW_INIT, 490 MTK_RESETTING 491 }; 492 493 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 494 * by the TX descriptor s 495 * @skb: The SKB pointer of the packet being sent 496 * @dma_addr0: The base addr of the first segment 497 * @dma_len0: The length of the first segment 498 * @dma_addr1: The base addr of the second segment 499 * @dma_len1: The length of the second segment 500 */ 501 struct mtk_tx_buf { 502 struct sk_buff *skb; 503 u32 flags; 504 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 505 DEFINE_DMA_UNMAP_LEN(dma_len0); 506 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 507 DEFINE_DMA_UNMAP_LEN(dma_len1); 508 }; 509 510 /* struct mtk_tx_ring - This struct holds info describing a TX ring 511 * @dma: The descriptor ring 512 * @buf: The memory pointed at by the ring 513 * @phys: The physical addr of tx_buf 514 * @next_free: Pointer to the next free descriptor 515 * @last_free: Pointer to the last free descriptor 516 * @thresh: The threshold of minimum amount of free descriptors 517 * @free_count: QDMA uses a linked list. Track how many free descriptors 518 * are present 519 */ 520 struct mtk_tx_ring { 521 struct mtk_tx_dma *dma; 522 struct mtk_tx_buf *buf; 523 dma_addr_t phys; 524 struct mtk_tx_dma *next_free; 525 struct mtk_tx_dma *last_free; 526 u16 thresh; 527 atomic_t free_count; 528 }; 529 530 /* PDMA rx ring mode */ 531 enum mtk_rx_flags { 532 MTK_RX_FLAGS_NORMAL = 0, 533 MTK_RX_FLAGS_HWLRO, 534 MTK_RX_FLAGS_QDMA, 535 }; 536 537 /* struct mtk_rx_ring - This struct holds info describing a RX ring 538 * @dma: The descriptor ring 539 * @data: The memory pointed at by the ring 540 * @phys: The physical addr of rx_buf 541 * @frag_size: How big can each fragment be 542 * @buf_size: The size of each packet buffer 543 * @calc_idx: The current head of ring 544 */ 545 struct mtk_rx_ring { 546 struct mtk_rx_dma *dma; 547 u8 **data; 548 dma_addr_t phys; 549 u16 frag_size; 550 u16 buf_size; 551 u16 dma_size; 552 bool calc_idx_update; 553 u16 calc_idx; 554 u32 crx_idx_reg; 555 }; 556 557 #define MTK_TRGMII BIT(0) 558 #define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII) 559 #define MTK_ESW BIT(4) 560 #define MTK_GMAC1_ESW (BIT(5) | MTK_ESW) 561 #define MTK_SGMII BIT(8) 562 #define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII) 563 #define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII) 564 #define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \ 565 MTK_GMAC2_SGMII) 566 #define MTK_HWLRO BIT(12) 567 #define MTK_SHARED_INT BIT(13) 568 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 569 570 /* struct mtk_eth_data - This is the structure holding all differences 571 * among various plaforms 572 * @caps Flags shown the extra capability for the SoC 573 * @required_clks Flags shown the bitmap for required clocks on 574 * the target SoC 575 * @required_pctl A bool value to show whether the SoC requires 576 * the extra setup for those pins used by GMAC. 577 */ 578 struct mtk_soc_data { 579 u32 caps; 580 u32 required_clks; 581 bool required_pctl; 582 }; 583 584 /* currently no SoC has more than 2 macs */ 585 #define MTK_MAX_DEVS 2 586 587 /* struct mtk_eth - This is the main datasructure for holding the state 588 * of the driver 589 * @dev: The device pointer 590 * @base: The mapped register i/o base 591 * @page_lock: Make sure that register operations are atomic 592 * @tx_irq__lock: Make sure that IRQ register operations are atomic 593 * @rx_irq__lock: Make sure that IRQ register operations are atomic 594 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 595 * dummy for NAPI to work 596 * @netdev: The netdev instances 597 * @mac: Each netdev is linked to a physical MAC 598 * @irq: The IRQ that we are using 599 * @msg_enable: Ethtool msg level 600 * @ethsys: The register map pointing at the range used to setup 601 * MII modes 602 * @sgmiisys: The register map pointing at the range used to setup 603 * SGMII modes 604 * @pctl: The register map pointing at the range used to setup 605 * GMAC port drive/slew values 606 * @dma_refcnt: track how many netdevs are using the DMA engine 607 * @tx_ring: Pointer to the memory holding info about the TX ring 608 * @rx_ring: Pointer to the memory holding info about the RX ring 609 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 610 * @tx_napi: The TX NAPI struct 611 * @rx_napi: The RX NAPI struct 612 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 613 * @phy_scratch_ring: physical address of scratch_ring 614 * @scratch_head: The scratch memory that scratch_ring points to. 615 * @clks: clock array for all clocks required 616 * @mii_bus: If there is a bus we need to create an instance for it 617 * @pending_work: The workqueue used to reset the dma ring 618 * @state: Initialization and runtime state of the device 619 * @soc: Holding specific data among vaious SoCs 620 */ 621 622 struct mtk_eth { 623 struct device *dev; 624 void __iomem *base; 625 spinlock_t page_lock; 626 spinlock_t tx_irq_lock; 627 spinlock_t rx_irq_lock; 628 struct net_device dummy_dev; 629 struct net_device *netdev[MTK_MAX_DEVS]; 630 struct mtk_mac *mac[MTK_MAX_DEVS]; 631 int irq[3]; 632 u32 msg_enable; 633 unsigned long sysclk; 634 struct regmap *ethsys; 635 struct regmap *sgmiisys; 636 struct regmap *pctl; 637 bool hwlro; 638 refcount_t dma_refcnt; 639 struct mtk_tx_ring tx_ring; 640 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 641 struct mtk_rx_ring rx_ring_qdma; 642 struct napi_struct tx_napi; 643 struct napi_struct rx_napi; 644 struct mtk_tx_dma *scratch_ring; 645 dma_addr_t phy_scratch_ring; 646 void *scratch_head; 647 struct clk *clks[MTK_CLK_MAX]; 648 649 struct mii_bus *mii_bus; 650 struct work_struct pending_work; 651 unsigned long state; 652 653 const struct mtk_soc_data *soc; 654 }; 655 656 /* struct mtk_mac - the structure that holds the info about the MACs of the 657 * SoC 658 * @id: The number of the MAC 659 * @ge_mode: Interface mode kept for setup restoring 660 * @of_node: Our devicetree node 661 * @hw: Backpointer to our main datastruture 662 * @hw_stats: Packet statistics counter 663 * @trgmii Indicate if the MAC uses TRGMII connected to internal 664 switch 665 */ 666 struct mtk_mac { 667 int id; 668 int ge_mode; 669 struct device_node *of_node; 670 struct mtk_eth *hw; 671 struct mtk_hw_stats *hw_stats; 672 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 673 int hwlro_ip_cnt; 674 bool trgmii; 675 }; 676 677 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 678 extern const struct of_device_id of_mtk_match[]; 679 680 /* read the hardware status register */ 681 void mtk_stats_update_mac(struct mtk_mac *mac); 682 683 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 684 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 685 686 #endif /* MTK_ETH_H */ 687