1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "en/params.h" 5 #include "en/txrx.h" 6 #include "en/port.h" 7 #include "en_accel/en_accel.h" 8 #include "en_accel/ipsec.h" 9 #include <net/xdp_sock_drv.h> 10 11 static u8 mlx5e_mpwrq_min_page_shift(struct mlx5_core_dev *mdev) 12 { 13 u8 min_page_shift = MLX5_CAP_GEN_2(mdev, log_min_mkey_entity_size); 14 15 return min_page_shift ? : 12; 16 } 17 18 u8 mlx5e_mpwrq_page_shift(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *xsk) 19 { 20 u8 req_page_shift = xsk ? order_base_2(xsk->chunk_size) : PAGE_SHIFT; 21 u8 min_page_shift = mlx5e_mpwrq_min_page_shift(mdev); 22 23 /* Regular RQ uses order-0 pages, the NIC must be able to map them. */ 24 if (WARN_ON_ONCE(!xsk && req_page_shift < min_page_shift)) 25 min_page_shift = req_page_shift; 26 27 return max(req_page_shift, min_page_shift); 28 } 29 30 enum mlx5e_mpwrq_umr_mode 31 mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *xsk) 32 { 33 /* Different memory management schemes use different mechanisms to map 34 * user-mode memory. The stricter guarantees we have, the faster 35 * mechanisms we use: 36 * 1. MTT - direct mapping in page granularity. 37 * 2. KSM - indirect mapping to another MKey to arbitrary addresses, but 38 * all mappings have the same size. 39 * 3. KLM - indirect mapping to another MKey to arbitrary addresses, and 40 * mappings can have different sizes. 41 */ 42 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 43 bool unaligned = xsk ? xsk->unaligned : false; 44 bool oversized = false; 45 46 if (xsk) { 47 oversized = xsk->chunk_size < (1 << page_shift); 48 WARN_ON_ONCE(xsk->chunk_size > (1 << page_shift)); 49 } 50 51 /* XSK frame size doesn't match the UMR page size, either because the 52 * frame size is not a power of two, or it's smaller than the minimal 53 * page size supported by the firmware. 54 * It's possible to receive packets bigger than MTU in certain setups. 55 * To avoid writing over the XSK frame boundary, the top region of each 56 * stride is mapped to a garbage page, resulting in two mappings of 57 * different sizes per frame. 58 */ 59 if (oversized) { 60 /* An optimization for frame sizes equal to 3 * power_of_two. 61 * 3 KSMs point to the frame, and one KSM points to the garbage 62 * page, which works faster than KLM. 63 */ 64 if (xsk->chunk_size % 3 == 0 && is_power_of_2(xsk->chunk_size / 3)) 65 return MLX5E_MPWRQ_UMR_MODE_TRIPLE; 66 67 return MLX5E_MPWRQ_UMR_MODE_OVERSIZED; 68 } 69 70 /* XSK frames can start at arbitrary unaligned locations, but they all 71 * have the same size which is a power of two. It allows to optimize to 72 * one KSM per frame. 73 */ 74 if (unaligned) 75 return MLX5E_MPWRQ_UMR_MODE_UNALIGNED; 76 77 /* XSK: frames are naturally aligned, MTT can be used. 78 * Non-XSK: Allocations happen in units of CPU pages, therefore, the 79 * mappings are naturally aligned. 80 */ 81 return MLX5E_MPWRQ_UMR_MODE_ALIGNED; 82 } 83 84 u8 mlx5e_mpwrq_umr_entry_size(enum mlx5e_mpwrq_umr_mode mode) 85 { 86 switch (mode) { 87 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 88 return sizeof(struct mlx5_mtt); 89 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 90 return sizeof(struct mlx5_ksm); 91 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 92 return sizeof(struct mlx5_klm) * 2; 93 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 94 return sizeof(struct mlx5_ksm) * 4; 95 } 96 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", mode); 97 return 0; 98 } 99 100 u8 mlx5e_mpwrq_log_wqe_sz(struct mlx5_core_dev *mdev, u8 page_shift, 101 enum mlx5e_mpwrq_umr_mode umr_mode) 102 { 103 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); 104 u8 max_pages_per_wqe, max_log_mpwqe_size; 105 u16 max_wqe_size; 106 107 /* Keep in sync with MLX5_MPWRQ_MAX_PAGES_PER_WQE. */ 108 max_wqe_size = mlx5e_get_max_sq_aligned_wqebbs(mdev) * MLX5_SEND_WQE_BB; 109 max_pages_per_wqe = ALIGN_DOWN(max_wqe_size - sizeof(struct mlx5e_umr_wqe), 110 MLX5_UMR_FLEX_ALIGNMENT) / umr_entry_size; 111 max_log_mpwqe_size = ilog2(max_pages_per_wqe) + page_shift; 112 113 WARN_ON_ONCE(max_log_mpwqe_size < MLX5E_ORDER2_MAX_PACKET_MTU); 114 115 return min_t(u8, max_log_mpwqe_size, MLX5_MPWRQ_MAX_LOG_WQE_SZ); 116 } 117 118 u8 mlx5e_mpwrq_pages_per_wqe(struct mlx5_core_dev *mdev, u8 page_shift, 119 enum mlx5e_mpwrq_umr_mode umr_mode) 120 { 121 u8 log_wqe_sz = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); 122 u8 pages_per_wqe; 123 124 pages_per_wqe = log_wqe_sz > page_shift ? (1 << (log_wqe_sz - page_shift)) : 1; 125 126 /* Two MTTs are needed to form an octword. The number of MTTs is encoded 127 * in octwords in a UMR WQE, so we need at least two to avoid mapping 128 * garbage addresses. 129 */ 130 if (WARN_ON_ONCE(pages_per_wqe < 2 && umr_mode == MLX5E_MPWRQ_UMR_MODE_ALIGNED)) 131 pages_per_wqe = 2; 132 133 /* Sanity check for further calculations to succeed. */ 134 BUILD_BUG_ON(MLX5_MPWRQ_MAX_PAGES_PER_WQE > 64); 135 if (WARN_ON_ONCE(pages_per_wqe > MLX5_MPWRQ_MAX_PAGES_PER_WQE)) 136 return MLX5_MPWRQ_MAX_PAGES_PER_WQE; 137 138 return pages_per_wqe; 139 } 140 141 u16 mlx5e_mpwrq_umr_wqe_sz(struct mlx5_core_dev *mdev, u8 page_shift, 142 enum mlx5e_mpwrq_umr_mode umr_mode) 143 { 144 u8 pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, page_shift, umr_mode); 145 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); 146 u16 umr_wqe_sz; 147 148 umr_wqe_sz = sizeof(struct mlx5e_umr_wqe) + 149 ALIGN(pages_per_wqe * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT); 150 151 WARN_ON_ONCE(DIV_ROUND_UP(umr_wqe_sz, MLX5_SEND_WQE_DS) > MLX5_WQE_CTRL_DS_MASK); 152 153 return umr_wqe_sz; 154 } 155 156 u8 mlx5e_mpwrq_umr_wqebbs(struct mlx5_core_dev *mdev, u8 page_shift, 157 enum mlx5e_mpwrq_umr_mode umr_mode) 158 { 159 return DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(mdev, page_shift, umr_mode), 160 MLX5_SEND_WQE_BB); 161 } 162 163 u8 mlx5e_mpwrq_mtts_per_wqe(struct mlx5_core_dev *mdev, u8 page_shift, 164 enum mlx5e_mpwrq_umr_mode umr_mode) 165 { 166 u8 pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, page_shift, umr_mode); 167 168 /* Add another page as a buffer between WQEs. This page will absorb 169 * write overflow by the hardware, when receiving packets larger than 170 * MTU. These oversize packets are dropped by the driver at a later 171 * stage. 172 */ 173 return ALIGN(pages_per_wqe + 1, 174 MLX5_SEND_WQE_BB / mlx5e_mpwrq_umr_entry_size(umr_mode)); 175 } 176 177 u32 mlx5e_mpwrq_max_num_entries(struct mlx5_core_dev *mdev, 178 enum mlx5e_mpwrq_umr_mode umr_mode) 179 { 180 /* Same limits apply to KSMs and KLMs. */ 181 u32 klm_limit = min(MLX5E_MAX_RQ_NUM_KSMS, 182 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size)); 183 184 switch (umr_mode) { 185 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 186 return MLX5E_MAX_RQ_NUM_MTTS; 187 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 188 return klm_limit; 189 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 190 /* Each entry is two KLMs. */ 191 return klm_limit / 2; 192 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 193 /* Each entry is four KSMs. */ 194 return klm_limit / 4; 195 } 196 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode); 197 return 0; 198 } 199 200 static u8 mlx5e_mpwrq_max_log_rq_size(struct mlx5_core_dev *mdev, u8 page_shift, 201 enum mlx5e_mpwrq_umr_mode umr_mode) 202 { 203 u8 mtts_per_wqe = mlx5e_mpwrq_mtts_per_wqe(mdev, page_shift, umr_mode); 204 u32 max_entries = mlx5e_mpwrq_max_num_entries(mdev, umr_mode); 205 206 return ilog2(max_entries / mtts_per_wqe); 207 } 208 209 u8 mlx5e_mpwrq_max_log_rq_pkts(struct mlx5_core_dev *mdev, u8 page_shift, 210 enum mlx5e_mpwrq_umr_mode umr_mode) 211 { 212 return mlx5e_mpwrq_max_log_rq_size(mdev, page_shift, umr_mode) + 213 mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode) - 214 MLX5E_ORDER2_MAX_PACKET_MTU; 215 } 216 217 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, 218 struct mlx5e_xsk_param *xsk) 219 { 220 u16 headroom; 221 222 if (xsk) 223 return xsk->headroom; 224 225 headroom = NET_IP_ALIGN; 226 if (params->xdp_prog) 227 headroom += XDP_PACKET_HEADROOM; 228 else 229 headroom += MLX5_RX_HEADROOM; 230 231 return headroom; 232 } 233 234 static u32 mlx5e_rx_get_linear_sz_xsk(struct mlx5e_params *params, 235 struct mlx5e_xsk_param *xsk) 236 { 237 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 238 239 return xsk->headroom + hw_mtu; 240 } 241 242 static u32 mlx5e_rx_get_linear_sz_skb(struct mlx5e_params *params, bool xsk) 243 { 244 /* SKBs built on XDP_PASS on XSK RQs don't have headroom. */ 245 u16 headroom = xsk ? 0 : mlx5e_get_linear_rq_headroom(params, NULL); 246 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 247 248 return MLX5_SKB_FRAG_SZ(headroom + hw_mtu); 249 } 250 251 static u32 mlx5e_rx_get_linear_stride_sz(struct mlx5_core_dev *mdev, 252 struct mlx5e_params *params, 253 struct mlx5e_xsk_param *xsk, 254 bool mpwqe) 255 { 256 /* XSK frames are mapped as individual pages, because frames may come in 257 * an arbitrary order from random locations in the UMEM. 258 */ 259 if (xsk) 260 return mpwqe ? 1 << mlx5e_mpwrq_page_shift(mdev, xsk) : PAGE_SIZE; 261 262 /* XDP in mlx5e doesn't support multiple packets per page. */ 263 if (params->xdp_prog) 264 return PAGE_SIZE; 265 266 return roundup_pow_of_two(mlx5e_rx_get_linear_sz_skb(params, false)); 267 } 268 269 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5_core_dev *mdev, 270 struct mlx5e_params *params, 271 struct mlx5e_xsk_param *xsk) 272 { 273 u32 linear_stride_sz = mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true); 274 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 275 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 276 277 return mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode) - 278 order_base_2(linear_stride_sz); 279 } 280 281 bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, 282 struct mlx5e_params *params, 283 struct mlx5e_xsk_param *xsk) 284 { 285 if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) 286 return false; 287 288 /* Both XSK and non-XSK cases allocate an SKB on XDP_PASS. Packet data 289 * must fit into a CPU page. 290 */ 291 if (mlx5e_rx_get_linear_sz_skb(params, xsk) > PAGE_SIZE) 292 return false; 293 294 /* XSK frames must be big enough to hold the packet data. */ 295 if (xsk && mlx5e_rx_get_linear_sz_xsk(params, xsk) > xsk->chunk_size) 296 return false; 297 298 return true; 299 } 300 301 static bool mlx5e_verify_rx_mpwqe_strides(struct mlx5_core_dev *mdev, 302 u8 log_stride_sz, u8 log_num_strides, 303 u8 page_shift, 304 enum mlx5e_mpwrq_umr_mode umr_mode) 305 { 306 if (log_stride_sz + log_num_strides != 307 mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode)) 308 return false; 309 310 if (log_stride_sz < MLX5_MPWQE_LOG_STRIDE_SZ_BASE || 311 log_stride_sz > MLX5_MPWQE_LOG_STRIDE_SZ_MAX) 312 return false; 313 314 if (log_num_strides > MLX5_MPWQE_LOG_NUM_STRIDES_MAX) 315 return false; 316 317 if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) 318 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE; 319 320 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_BASE; 321 } 322 323 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, 324 struct mlx5e_params *params, 325 struct mlx5e_xsk_param *xsk) 326 { 327 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 328 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 329 u8 log_num_strides; 330 u8 log_stride_sz; 331 u8 log_wqe_sz; 332 333 if (!mlx5e_rx_is_linear_skb(mdev, params, xsk)) 334 return false; 335 336 log_stride_sz = order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true)); 337 log_wqe_sz = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); 338 339 if (log_wqe_sz < log_stride_sz) 340 return false; 341 342 log_num_strides = log_wqe_sz - log_stride_sz; 343 344 return mlx5e_verify_rx_mpwqe_strides(mdev, log_stride_sz, 345 log_num_strides, page_shift, 346 umr_mode); 347 } 348 349 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, 350 struct mlx5e_params *params, 351 struct mlx5e_xsk_param *xsk) 352 { 353 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 354 u8 log_pkts_per_wqe, page_shift, max_log_rq_size; 355 356 log_pkts_per_wqe = mlx5e_mpwqe_log_pkts_per_wqe(mdev, params, xsk); 357 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 358 max_log_rq_size = mlx5e_mpwrq_max_log_rq_size(mdev, page_shift, umr_mode); 359 360 /* Numbers are unsigned, don't subtract to avoid underflow. */ 361 if (params->log_rq_mtu_frames < 362 log_pkts_per_wqe + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) 363 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; 364 365 /* Ethtool's rx_max_pending is calculated for regular RQ, that uses 366 * pages of PAGE_SIZE. Max length of an XSK RQ might differ if it uses a 367 * frame size not equal to PAGE_SIZE. 368 * A stricter condition is checked in mlx5e_mpwrq_validate_xsk, WARN on 369 * unexpected failure. 370 */ 371 if (WARN_ON_ONCE(params->log_rq_mtu_frames > log_pkts_per_wqe + max_log_rq_size)) 372 return max_log_rq_size; 373 374 return params->log_rq_mtu_frames - log_pkts_per_wqe; 375 } 376 377 u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, 378 struct mlx5e_params *params) 379 { 380 return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE)); 381 } 382 383 u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, 384 struct mlx5e_params *params) 385 { 386 return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE); 387 } 388 389 u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, 390 struct mlx5e_params *params) 391 { 392 u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * 393 PAGE_SIZE; 394 395 return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); 396 } 397 398 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, 399 struct mlx5e_params *params, 400 struct mlx5e_xsk_param *xsk) 401 { 402 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) 403 return order_base_2(mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, true)); 404 405 return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); 406 } 407 408 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, 409 struct mlx5e_params *params, 410 struct mlx5e_xsk_param *xsk) 411 { 412 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 413 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 414 u8 log_wqe_size, log_stride_size; 415 416 log_wqe_size = mlx5e_mpwrq_log_wqe_sz(mdev, page_shift, umr_mode); 417 log_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 418 WARN(log_wqe_size < log_stride_size, 419 "Log WQE size %u < log stride size %u (page shift %u, umr mode %d, xsk on? %d)\n", 420 log_wqe_size, log_stride_size, page_shift, umr_mode, !!xsk); 421 return log_wqe_size - log_stride_size; 422 } 423 424 u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz) 425 { 426 #define UMR_WQE_BULK (2) 427 return min_t(unsigned int, UMR_WQE_BULK, wq_sz / 2 - 1); 428 } 429 430 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, 431 struct mlx5e_params *params, 432 struct mlx5e_xsk_param *xsk) 433 { 434 u16 linear_headroom = mlx5e_get_linear_rq_headroom(params, xsk); 435 436 if (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) 437 return linear_headroom; 438 439 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) 440 return linear_headroom; 441 442 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 443 return linear_headroom; 444 445 return 0; 446 } 447 448 u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 449 { 450 bool is_mpwqe = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 451 u16 stop_room; 452 453 stop_room = mlx5e_ktls_get_stop_room(mdev, params); 454 stop_room += mlx5e_stop_room_for_max_wqe(mdev); 455 if (is_mpwqe) 456 /* A MPWQE can take up to the maximum cacheline-aligned WQE + 457 * all the normal stop room can be taken if a new packet breaks 458 * the active MPWQE session and allocates its WQEs right away. 459 */ 460 stop_room += mlx5e_stop_room_for_mpwqe(mdev); 461 462 return stop_room; 463 } 464 465 int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 466 { 467 size_t sq_size = 1 << params->log_sq_size; 468 u16 stop_room; 469 470 stop_room = mlx5e_calc_sq_stop_room(mdev, params); 471 if (stop_room >= sq_size) { 472 mlx5_core_err(mdev, "Stop room %u is bigger than the SQ size %zu\n", 473 stop_room, sq_size); 474 return -EINVAL; 475 } 476 477 return 0; 478 } 479 480 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) 481 { 482 struct dim_cq_moder moder = {}; 483 484 moder.cq_period_mode = cq_period_mode; 485 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 486 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 487 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 488 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; 489 490 return moder; 491 } 492 493 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) 494 { 495 struct dim_cq_moder moder = {}; 496 497 moder.cq_period_mode = cq_period_mode; 498 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 499 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 500 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 501 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; 502 503 return moder; 504 } 505 506 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) 507 { 508 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? 509 DIM_CQ_PERIOD_MODE_START_FROM_CQE : 510 DIM_CQ_PERIOD_MODE_START_FROM_EQE; 511 } 512 513 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 514 { 515 if (params->tx_dim_enabled) { 516 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 517 518 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); 519 } else { 520 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); 521 } 522 } 523 524 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 525 { 526 if (params->rx_dim_enabled) { 527 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 528 529 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); 530 } else { 531 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); 532 } 533 } 534 535 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 536 { 537 mlx5e_reset_tx_moderation(params, cq_period_mode); 538 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 539 params->tx_cq_moderation.cq_period_mode == 540 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 541 } 542 543 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 544 { 545 mlx5e_reset_rx_moderation(params, cq_period_mode); 546 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 547 params->rx_cq_moderation.cq_period_mode == 548 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 549 } 550 551 bool slow_pci_heuristic(struct mlx5_core_dev *mdev) 552 { 553 u32 link_speed = 0; 554 u32 pci_bw = 0; 555 556 mlx5e_port_max_linkspeed(mdev, &link_speed); 557 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); 558 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", 559 link_speed, pci_bw); 560 561 #define MLX5E_SLOW_PCI_RATIO (2) 562 563 return link_speed && pci_bw && 564 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; 565 } 566 567 int mlx5e_mpwrq_validate_regular(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 568 { 569 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, NULL); 570 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, NULL); 571 572 if (!mlx5e_check_fragmented_striding_rq_cap(mdev, page_shift, umr_mode)) 573 return -EOPNOTSUPP; 574 575 if (params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 576 return -EINVAL; 577 578 return 0; 579 } 580 581 int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_params *params, 582 struct mlx5e_xsk_param *xsk) 583 { 584 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 585 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 586 u16 max_mtu_pkts; 587 588 if (!mlx5e_check_fragmented_striding_rq_cap(mdev, page_shift, umr_mode)) { 589 mlx5_core_err(mdev, "Striding RQ for XSK can't be activated with page_shift %u and umr_mode %d\n", 590 page_shift, umr_mode); 591 return -EOPNOTSUPP; 592 } 593 594 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) { 595 mlx5_core_err(mdev, "Striding RQ linear mode for XSK can't be activated with current params\n"); 596 return -EINVAL; 597 } 598 599 /* Current RQ length is too big for the given frame size, the 600 * needed number of WQEs exceeds the maximum. 601 */ 602 max_mtu_pkts = min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE, 603 mlx5e_mpwrq_max_log_rq_pkts(mdev, page_shift, xsk->unaligned)); 604 if (params->log_rq_mtu_frames > max_mtu_pkts) { 605 mlx5_core_err(mdev, "Current RQ length %d is too big for XSK with given frame size %u\n", 606 1 << params->log_rq_mtu_frames, xsk->chunk_size); 607 return -EINVAL; 608 } 609 610 return 0; 611 } 612 613 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, 614 struct mlx5e_params *params) 615 { 616 params->log_rq_mtu_frames = is_kdump_kernel() ? 617 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 618 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 619 } 620 621 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 622 { 623 params->rq_wq_type = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? 624 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : 625 MLX5_WQ_TYPE_CYCLIC; 626 } 627 628 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, 629 struct mlx5e_params *params) 630 { 631 /* Prefer Striding RQ, unless any of the following holds: 632 * - Striding RQ configuration is not possible/supported. 633 * - CQE compression is ON, and stride_index mini_cqe layout is not supported. 634 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear. 635 * 636 * No XSK params: checking the availability of striding RQ in general. 637 */ 638 if ((!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) || 639 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) && 640 !mlx5e_mpwrq_validate_regular(mdev, params) && 641 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) || 642 !mlx5e_rx_is_linear_skb(mdev, params, NULL))) 643 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true); 644 mlx5e_set_rq_type(mdev, params); 645 mlx5e_init_rq_type_params(mdev, params); 646 } 647 648 /* Build queue parameters */ 649 650 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c) 651 { 652 *ccp = (struct mlx5e_create_cq_param) { 653 .napi = &c->napi, 654 .ch_stats = c->stats, 655 .node = cpu_to_node(c->cpu), 656 .ix = c->ix, 657 }; 658 } 659 660 static int mlx5e_max_nonlinear_mtu(int first_frag_size, int frag_size, bool xdp) 661 { 662 if (xdp) 663 /* XDP requires all fragments to be of the same size. */ 664 return first_frag_size + (MLX5E_MAX_RX_FRAGS - 1) * frag_size; 665 666 /* Optimization for small packets: the last fragment is bigger than the others. */ 667 return first_frag_size + (MLX5E_MAX_RX_FRAGS - 2) * frag_size + PAGE_SIZE; 668 } 669 670 #define DEFAULT_FRAG_SIZE (2048) 671 672 static int mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, 673 struct mlx5e_params *params, 674 struct mlx5e_xsk_param *xsk, 675 struct mlx5e_rq_frags_info *info) 676 { 677 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); 678 int frag_size_max = DEFAULT_FRAG_SIZE; 679 int first_frag_size_max; 680 u32 buf_size = 0; 681 u16 headroom; 682 int max_mtu; 683 int i; 684 685 if (mlx5e_rx_is_linear_skb(mdev, params, xsk)) { 686 int frag_stride; 687 688 frag_stride = mlx5e_rx_get_linear_stride_sz(mdev, params, xsk, false); 689 690 info->arr[0].frag_size = byte_count; 691 info->arr[0].frag_stride = frag_stride; 692 info->num_frags = 1; 693 694 /* N WQEs share the same page, N = PAGE_SIZE / frag_stride. The 695 * first WQE in the page is responsible for allocation of this 696 * page, this WQE's index is k*N. If WQEs [k*N+1; k*N+N-1] are 697 * still not completed, the allocation must stop before k*N. 698 */ 699 info->wqe_index_mask = (PAGE_SIZE / frag_stride) - 1; 700 701 goto out; 702 } 703 704 headroom = mlx5e_get_linear_rq_headroom(params, xsk); 705 first_frag_size_max = SKB_WITH_OVERHEAD(frag_size_max - headroom); 706 707 max_mtu = mlx5e_max_nonlinear_mtu(first_frag_size_max, frag_size_max, 708 params->xdp_prog); 709 if (byte_count > max_mtu || params->xdp_prog) { 710 frag_size_max = PAGE_SIZE; 711 first_frag_size_max = SKB_WITH_OVERHEAD(frag_size_max - headroom); 712 713 max_mtu = mlx5e_max_nonlinear_mtu(first_frag_size_max, frag_size_max, 714 params->xdp_prog); 715 if (byte_count > max_mtu) { 716 mlx5_core_err(mdev, "MTU %u is too big for non-linear legacy RQ (max %d)\n", 717 params->sw_mtu, max_mtu); 718 return -EINVAL; 719 } 720 } 721 722 i = 0; 723 while (buf_size < byte_count) { 724 int frag_size = byte_count - buf_size; 725 726 if (i == 0) 727 frag_size = min(frag_size, first_frag_size_max); 728 else if (i < MLX5E_MAX_RX_FRAGS - 1) 729 frag_size = min(frag_size, frag_size_max); 730 731 info->arr[i].frag_size = frag_size; 732 buf_size += frag_size; 733 734 if (params->xdp_prog) { 735 /* XDP multi buffer expects fragments of the same size. */ 736 info->arr[i].frag_stride = frag_size_max; 737 } else { 738 if (i == 0) { 739 /* Ensure that headroom and tailroom are included. */ 740 frag_size += headroom; 741 frag_size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 742 } 743 info->arr[i].frag_stride = roundup_pow_of_two(frag_size); 744 } 745 746 i++; 747 } 748 info->num_frags = i; 749 750 /* The last fragment of WQE with index 2*N may share the page with the 751 * first fragment of WQE with index 2*N+1 in certain cases. If WQE 2*N+1 752 * is not completed yet, WQE 2*N must not be allocated, as it's 753 * responsible for allocating a new page. 754 */ 755 if (frag_size_max == PAGE_SIZE) { 756 /* No WQE can start in the middle of a page. */ 757 info->wqe_index_mask = 0; 758 } else { 759 /* PAGE_SIZEs starting from 8192 don't use 2K-sized fragments, 760 * because there would be more than MLX5E_MAX_RX_FRAGS of them. 761 */ 762 WARN_ON(PAGE_SIZE != 2 * DEFAULT_FRAG_SIZE); 763 764 /* Odd number of fragments allows to pack the last fragment of 765 * the previous WQE and the first fragment of the next WQE into 766 * the same page. 767 * As long as DEFAULT_FRAG_SIZE is 2048, and MLX5E_MAX_RX_FRAGS 768 * is 4, the last fragment can be bigger than the rest only if 769 * it's the fourth one, so WQEs consisting of 3 fragments will 770 * always share a page. 771 * When a page is shared, WQE bulk size is 2, otherwise just 1. 772 */ 773 info->wqe_index_mask = info->num_frags % 2; 774 } 775 776 out: 777 /* Bulking optimization to skip allocation until at least 8 WQEs can be 778 * allocated in a row. At the same time, never start allocation when 779 * the page is still used by older WQEs. 780 */ 781 info->wqe_bulk = max_t(u8, info->wqe_index_mask + 1, 8); 782 783 info->log_num_frags = order_base_2(info->num_frags); 784 785 return 0; 786 } 787 788 static u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs) 789 { 790 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs; 791 792 switch (wq_type) { 793 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 794 sz += sizeof(struct mlx5e_rx_wqe_ll); 795 break; 796 default: /* MLX5_WQ_TYPE_CYCLIC */ 797 sz += sizeof(struct mlx5e_rx_wqe_cyc); 798 } 799 800 return order_base_2(sz); 801 } 802 803 static void mlx5e_build_common_cq_param(struct mlx5_core_dev *mdev, 804 struct mlx5e_cq_param *param) 805 { 806 void *cqc = param->cqc; 807 808 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 809 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) 810 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); 811 } 812 813 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, 814 struct mlx5e_params *params, 815 struct mlx5e_xsk_param *xsk) 816 { 817 int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 818 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 819 int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 820 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 821 int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); 822 int wqe_size = BIT(log_stride_sz) * num_strides; 823 824 /* +1 is for the case that the pkt_per_rsrv dont consume the reservation 825 * so we get a filler cqe for the rest of the reservation. 826 */ 827 return order_base_2((wqe_size / rsrv_size) * wq_size * (pkt_per_rsrv + 1)); 828 } 829 830 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, 831 struct mlx5e_params *params, 832 struct mlx5e_xsk_param *xsk, 833 struct mlx5e_cq_param *param) 834 { 835 bool hw_stridx = false; 836 void *cqc = param->cqc; 837 u8 log_cq_size; 838 839 switch (params->rq_wq_type) { 840 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 841 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); 842 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 843 log_cq_size = mlx5e_shampo_get_log_cq_size(mdev, params, xsk); 844 else 845 log_cq_size = mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk) + 846 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 847 break; 848 default: /* MLX5_WQ_TYPE_CYCLIC */ 849 log_cq_size = params->log_rq_mtu_frames; 850 } 851 852 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); 853 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 854 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ? 855 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM); 856 MLX5_SET(cqc, cqc, cqe_compression_layout, 857 MLX5_CAP_GEN(mdev, enhanced_cqe_compression) ? 858 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED : 859 MLX5_CQE_COMPRESS_LAYOUT_BASIC); 860 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 861 } 862 863 mlx5e_build_common_cq_param(mdev, param); 864 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; 865 } 866 867 static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 868 { 869 bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO; 870 bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) && 871 MLX5_CAP_GEN(mdev, relaxed_ordering_write); 872 873 return ro && lro_en ? 874 MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; 875 } 876 877 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, 878 struct mlx5e_params *params, 879 struct mlx5e_xsk_param *xsk, 880 u16 q_counter, 881 struct mlx5e_rq_param *param) 882 { 883 void *rqc = param->rqc; 884 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 885 int ndsegs = 1; 886 int err; 887 888 switch (params->rq_wq_type) { 889 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: { 890 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 891 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 892 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 893 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 894 895 if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, 896 log_wqe_num_of_strides, 897 page_shift, umr_mode)) { 898 mlx5_core_err(mdev, 899 "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u, umr_mode %d\n", 900 log_wqe_stride_size, log_wqe_num_of_strides, 901 umr_mode); 902 return -EINVAL; 903 } 904 905 MLX5_SET(wq, wq, log_wqe_num_of_strides, 906 log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE); 907 MLX5_SET(wq, wq, log_wqe_stride_size, 908 log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); 909 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); 910 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 911 MLX5_SET(wq, wq, shampo_enable, true); 912 MLX5_SET(wq, wq, log_reservation_size, 913 mlx5e_shampo_get_log_rsrv_size(mdev, params)); 914 MLX5_SET(wq, wq, 915 log_max_num_of_packets_per_reservation, 916 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 917 MLX5_SET(wq, wq, log_headers_entry_size, 918 mlx5e_shampo_get_log_hd_entry_size(mdev, params)); 919 MLX5_SET(rqc, rqc, reservation_timeout, 920 params->packet_merge.timeout); 921 MLX5_SET(rqc, rqc, shampo_match_criteria_type, 922 params->packet_merge.shampo.match_criteria_type); 923 MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, 924 params->packet_merge.shampo.alignment_granularity); 925 } 926 break; 927 } 928 default: /* MLX5_WQ_TYPE_CYCLIC */ 929 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); 930 err = mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info); 931 if (err) 932 return err; 933 ndsegs = param->frags_info.num_frags; 934 } 935 936 MLX5_SET(wq, wq, wq_type, params->rq_wq_type); 937 MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params)); 938 MLX5_SET(wq, wq, log_wq_stride, 939 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs)); 940 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 941 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 942 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); 943 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); 944 945 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 946 mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp); 947 948 return 0; 949 } 950 951 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, 952 u16 q_counter, 953 struct mlx5e_rq_param *param) 954 { 955 void *rqc = param->rqc; 956 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 957 958 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 959 MLX5_SET(wq, wq, log_wq_stride, 960 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); 961 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 962 963 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 964 } 965 966 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev, 967 struct mlx5e_params *params, 968 struct mlx5e_cq_param *param) 969 { 970 void *cqc = param->cqc; 971 972 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); 973 974 mlx5e_build_common_cq_param(mdev, param); 975 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; 976 } 977 978 void mlx5e_build_sq_param_common(struct mlx5_core_dev *mdev, 979 struct mlx5e_sq_param *param) 980 { 981 void *sqc = param->sqc; 982 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 983 984 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 985 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 986 987 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 988 } 989 990 void mlx5e_build_sq_param(struct mlx5_core_dev *mdev, 991 struct mlx5e_params *params, 992 struct mlx5e_sq_param *param) 993 { 994 void *sqc = param->sqc; 995 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 996 bool allow_swp; 997 998 allow_swp = 999 mlx5_geneve_tx_allowed(mdev) || !!mlx5_ipsec_device_caps(mdev); 1000 mlx5e_build_sq_param_common(mdev, param); 1001 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 1002 MLX5_SET(sqc, sqc, allow_swp, allow_swp); 1003 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 1004 param->stop_room = mlx5e_calc_sq_stop_room(mdev, params); 1005 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 1006 } 1007 1008 static void mlx5e_build_ico_cq_param(struct mlx5_core_dev *mdev, 1009 u8 log_wq_size, 1010 struct mlx5e_cq_param *param) 1011 { 1012 void *cqc = param->cqc; 1013 1014 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); 1015 1016 mlx5e_build_common_cq_param(mdev, param); 1017 1018 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1019 } 1020 1021 /* This function calculates the maximum number of headers entries that are needed 1022 * per WQE, the formula is based on the size of the reservations and the 1023 * restriction we have about max packets for reservation that is equal to max 1024 * headers per reservation. 1025 */ 1026 u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, 1027 struct mlx5e_params *params, 1028 struct mlx5e_rq_param *rq_param) 1029 { 1030 int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 1031 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); 1032 int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 1033 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); 1034 int wqe_size = BIT(log_stride_sz) * num_strides; 1035 u32 hd_per_wqe; 1036 1037 /* Assumption: hd_per_wqe % 8 == 0. */ 1038 hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv; 1039 mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n", 1040 __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); 1041 return hd_per_wqe; 1042 } 1043 1044 /* This function calculates the maximum number of headers entries that are needed 1045 * for the WQ, this value is uesed to allocate the header buffer in HW, thus 1046 * must be a pow of 2. 1047 */ 1048 u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, 1049 struct mlx5e_params *params, 1050 struct mlx5e_rq_param *rq_param) 1051 { 1052 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 1053 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 1054 u32 hd_per_wqe, hd_per_wq; 1055 1056 hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 1057 hd_per_wq = roundup_pow_of_two(hd_per_wqe * wq_size); 1058 return hd_per_wq; 1059 } 1060 1061 static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev, 1062 struct mlx5e_params *params, 1063 struct mlx5e_rq_param *rq_param) 1064 { 1065 int max_num_of_umr_per_wqe, max_hd_per_wqe, max_klm_per_umr, rest; 1066 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 1067 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 1068 u32 wqebbs; 1069 1070 max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev); 1071 max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 1072 max_num_of_umr_per_wqe = max_hd_per_wqe / max_klm_per_umr; 1073 rest = max_hd_per_wqe % max_klm_per_umr; 1074 wqebbs = MLX5E_KLM_UMR_WQEBBS(max_klm_per_umr) * max_num_of_umr_per_wqe; 1075 if (rest) 1076 wqebbs += MLX5E_KLM_UMR_WQEBBS(rest); 1077 wqebbs *= wq_size; 1078 return wqebbs; 1079 } 1080 1081 static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_core_dev *mdev, 1082 struct mlx5e_params *params, 1083 struct mlx5e_xsk_param *xsk) 1084 { 1085 enum mlx5e_mpwrq_umr_mode umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 1086 u8 page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 1087 u8 umr_wqebbs; 1088 1089 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); 1090 1091 return umr_wqebbs * (1 << mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); 1092 } 1093 1094 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, 1095 struct mlx5e_params *params, 1096 struct mlx5e_rq_param *rqp) 1097 { 1098 u32 wqebbs, total_pages, useful_space; 1099 1100 /* MLX5_WQ_TYPE_CYCLIC */ 1101 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 1102 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 1103 1104 /* UMR WQEs for the regular RQ. */ 1105 wqebbs = mlx5e_mpwrq_total_umr_wqebbs(mdev, params, NULL); 1106 1107 /* If XDP program is attached, XSK may be turned on at any time without 1108 * restarting the channel. ICOSQ must be big enough to fit UMR WQEs of 1109 * both regular RQ and XSK RQ. 1110 * 1111 * XSK uses different values of page_shift, and the total number of UMR 1112 * WQEBBs depends on it. This dependency is complex and not monotonic, 1113 * especially taking into consideration that some of the parameters come 1114 * from capabilities. Hence, we have to try all valid values of XSK 1115 * frame size (and page_shift) to find the maximum. 1116 */ 1117 if (params->xdp_prog) { 1118 u32 max_xsk_wqebbs = 0; 1119 u8 frame_shift; 1120 1121 for (frame_shift = XDP_UMEM_MIN_CHUNK_SHIFT; 1122 frame_shift <= PAGE_SHIFT; frame_shift++) { 1123 /* The headroom doesn't affect the calculation. */ 1124 struct mlx5e_xsk_param xsk = { 1125 .chunk_size = 1 << frame_shift, 1126 .unaligned = false, 1127 }; 1128 1129 /* XSK aligned mode. */ 1130 max_xsk_wqebbs = max(max_xsk_wqebbs, 1131 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); 1132 1133 /* XSK unaligned mode, frame size is a power of two. */ 1134 xsk.unaligned = true; 1135 max_xsk_wqebbs = max(max_xsk_wqebbs, 1136 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); 1137 1138 /* XSK unaligned mode, frame size is not equal to stride size. */ 1139 xsk.chunk_size -= 1; 1140 max_xsk_wqebbs = max(max_xsk_wqebbs, 1141 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); 1142 1143 /* XSK unaligned mode, frame size is a triple power of two. */ 1144 xsk.chunk_size = (1 << frame_shift) / 4 * 3; 1145 max_xsk_wqebbs = max(max_xsk_wqebbs, 1146 mlx5e_mpwrq_total_umr_wqebbs(mdev, params, &xsk)); 1147 } 1148 1149 wqebbs += max_xsk_wqebbs; 1150 } 1151 1152 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 1153 wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp); 1154 1155 /* UMR WQEs don't cross the page boundary, they are padded with NOPs. 1156 * This padding is always smaller than the max WQE size. That gives us 1157 * at least (PAGE_SIZE - (max WQE size - MLX5_SEND_WQE_BB)) useful bytes 1158 * per page. The number of pages is estimated as the total size of WQEs 1159 * divided by the useful space in page, rounding up. If some WQEs don't 1160 * fully fit into the useful space, they can occupy part of the padding, 1161 * which proves this estimation to be correct (reserve enough space). 1162 */ 1163 useful_space = PAGE_SIZE - mlx5e_get_max_sq_wqebbs(mdev) + MLX5_SEND_WQE_BB; 1164 total_pages = DIV_ROUND_UP(wqebbs * MLX5_SEND_WQE_BB, useful_space); 1165 wqebbs = total_pages * (PAGE_SIZE / MLX5_SEND_WQE_BB); 1166 1167 return max_t(u8, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE, order_base_2(wqebbs)); 1168 } 1169 1170 static u8 mlx5e_build_async_icosq_log_wq_sz(struct mlx5_core_dev *mdev) 1171 { 1172 if (mlx5e_is_ktls_rx(mdev)) 1173 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 1174 1175 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 1176 } 1177 1178 static void mlx5e_build_icosq_param(struct mlx5_core_dev *mdev, 1179 u8 log_wq_size, 1180 struct mlx5e_sq_param *param) 1181 { 1182 void *sqc = param->sqc; 1183 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1184 1185 mlx5e_build_sq_param_common(mdev, param); 1186 1187 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 1188 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 1189 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 1190 } 1191 1192 static void mlx5e_build_async_icosq_param(struct mlx5_core_dev *mdev, 1193 u8 log_wq_size, 1194 struct mlx5e_sq_param *param) 1195 { 1196 void *sqc = param->sqc; 1197 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1198 1199 mlx5e_build_sq_param_common(mdev, param); 1200 param->stop_room = mlx5e_stop_room_for_wqe(mdev, 1); /* for XSK NOP */ 1201 param->is_tls = mlx5e_is_ktls_rx(mdev); 1202 if (param->is_tls) 1203 param->stop_room += mlx5e_stop_room_for_wqe(mdev, 1); /* for TLS RX resync NOP */ 1204 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 1205 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 1206 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 1207 } 1208 1209 void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev, 1210 struct mlx5e_params *params, 1211 struct mlx5e_xsk_param *xsk, 1212 struct mlx5e_sq_param *param) 1213 { 1214 void *sqc = param->sqc; 1215 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1216 1217 mlx5e_build_sq_param_common(mdev, param); 1218 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 1219 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE); 1220 param->is_xdp_mb = !mlx5e_rx_is_linear_skb(mdev, params, xsk); 1221 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 1222 } 1223 1224 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, 1225 struct mlx5e_params *params, 1226 u16 q_counter, 1227 struct mlx5e_channel_param *cparam) 1228 { 1229 u8 icosq_log_wq_sz, async_icosq_log_wq_sz; 1230 int err; 1231 1232 err = mlx5e_build_rq_param(mdev, params, NULL, q_counter, &cparam->rq); 1233 if (err) 1234 return err; 1235 1236 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(mdev, params, &cparam->rq); 1237 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(mdev); 1238 1239 mlx5e_build_sq_param(mdev, params, &cparam->txq_sq); 1240 mlx5e_build_xdpsq_param(mdev, params, NULL, &cparam->xdp_sq); 1241 mlx5e_build_icosq_param(mdev, icosq_log_wq_sz, &cparam->icosq); 1242 mlx5e_build_async_icosq_param(mdev, async_icosq_log_wq_sz, &cparam->async_icosq); 1243 1244 return 0; 1245 } 1246