1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <net/tc_act/tc_gact.h> 34 #include <linux/mlx5/fs.h> 35 #include <net/vxlan.h> 36 #include <net/geneve.h> 37 #include <linux/bpf.h> 38 #include <linux/if_bridge.h> 39 #include <linux/filter.h> 40 #include <net/page_pool.h> 41 #include <net/xdp_sock_drv.h> 42 #include "eswitch.h" 43 #include "en.h" 44 #include "en/txrx.h" 45 #include "en_tc.h" 46 #include "en_rep.h" 47 #include "en_accel/ipsec.h" 48 #include "en_accel/macsec.h" 49 #include "en_accel/en_accel.h" 50 #include "en_accel/ktls.h" 51 #include "lib/vxlan.h" 52 #include "lib/clock.h" 53 #include "en/port.h" 54 #include "en/xdp.h" 55 #include "lib/eq.h" 56 #include "en/monitor_stats.h" 57 #include "en/health.h" 58 #include "en/params.h" 59 #include "en/xsk/pool.h" 60 #include "en/xsk/setup.h" 61 #include "en/xsk/rx.h" 62 #include "en/xsk/tx.h" 63 #include "en/hv_vhca_stats.h" 64 #include "en/devlink.h" 65 #include "lib/mlx5.h" 66 #include "en/ptp.h" 67 #include "en/htb.h" 68 #include "qos.h" 69 #include "en/trap.h" 70 71 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 72 enum mlx5e_mpwrq_umr_mode umr_mode) 73 { 74 u16 umr_wqebbs, max_wqebbs; 75 bool striding_rq_umr; 76 77 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) && 78 MLX5_CAP_ETH(mdev, reg_umr_sq); 79 if (!striding_rq_umr) 80 return false; 81 82 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); 83 max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 84 /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is 85 * calculated from mlx5e_get_max_sq_aligned_wqebbs. 86 */ 87 if (WARN_ON(umr_wqebbs > max_wqebbs)) 88 return false; 89 90 return true; 91 } 92 93 void mlx5e_update_carrier(struct mlx5e_priv *priv) 94 { 95 struct mlx5_core_dev *mdev = priv->mdev; 96 u8 port_state; 97 bool up; 98 99 port_state = mlx5_query_vport_state(mdev, 100 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, 101 0); 102 103 up = port_state == VPORT_STATE_UP; 104 if (up == netif_carrier_ok(priv->netdev)) 105 netif_carrier_event(priv->netdev); 106 if (up) { 107 netdev_info(priv->netdev, "Link up\n"); 108 netif_carrier_on(priv->netdev); 109 } else { 110 netdev_info(priv->netdev, "Link down\n"); 111 netif_carrier_off(priv->netdev); 112 } 113 } 114 115 static void mlx5e_update_carrier_work(struct work_struct *work) 116 { 117 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 118 update_carrier_work); 119 120 mutex_lock(&priv->state_lock); 121 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 122 if (priv->profile->update_carrier) 123 priv->profile->update_carrier(priv); 124 mutex_unlock(&priv->state_lock); 125 } 126 127 static void mlx5e_update_stats_work(struct work_struct *work) 128 { 129 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 130 update_stats_work); 131 132 mutex_lock(&priv->state_lock); 133 priv->profile->update_stats(priv); 134 mutex_unlock(&priv->state_lock); 135 } 136 137 void mlx5e_queue_update_stats(struct mlx5e_priv *priv) 138 { 139 if (!priv->profile->update_stats) 140 return; 141 142 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state))) 143 return; 144 145 queue_work(priv->wq, &priv->update_stats_work); 146 } 147 148 static int async_event(struct notifier_block *nb, unsigned long event, void *data) 149 { 150 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb); 151 struct mlx5_eqe *eqe = data; 152 153 if (event != MLX5_EVENT_TYPE_PORT_CHANGE) 154 return NOTIFY_DONE; 155 156 switch (eqe->sub_type) { 157 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 158 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 159 queue_work(priv->wq, &priv->update_carrier_work); 160 break; 161 default: 162 return NOTIFY_DONE; 163 } 164 165 return NOTIFY_OK; 166 } 167 168 static void mlx5e_enable_async_events(struct mlx5e_priv *priv) 169 { 170 priv->events_nb.notifier_call = async_event; 171 mlx5_notifier_register(priv->mdev, &priv->events_nb); 172 } 173 174 static void mlx5e_disable_async_events(struct mlx5e_priv *priv) 175 { 176 mlx5_notifier_unregister(priv->mdev, &priv->events_nb); 177 } 178 179 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data) 180 { 181 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb); 182 int err; 183 184 switch (event) { 185 case MLX5_DRIVER_EVENT_TYPE_TRAP: 186 err = mlx5e_handle_trap_event(priv, data); 187 break; 188 default: 189 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event); 190 err = -EINVAL; 191 } 192 return err; 193 } 194 195 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv) 196 { 197 priv->blocking_events_nb.notifier_call = blocking_event; 198 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb); 199 } 200 201 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) 202 { 203 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); 204 } 205 206 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode) 207 { 208 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); 209 u32 sz; 210 211 sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT); 212 213 return sz / MLX5_OCTWORD; 214 } 215 216 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, 217 struct mlx5e_icosq *sq, 218 struct mlx5e_umr_wqe *wqe) 219 { 220 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 221 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; 222 u16 octowords; 223 u8 ds_cnt; 224 225 ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift, 226 rq->mpwqe.umr_mode), 227 MLX5_SEND_WQE_DS); 228 229 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | 230 ds_cnt); 231 cseg->umr_mkey = rq->mpwqe.umr_mkey_be; 232 233 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 234 octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode); 235 ucseg->xlt_octowords = cpu_to_be16(octowords); 236 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 237 } 238 239 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) 240 { 241 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo), 242 GFP_KERNEL, node); 243 if (!rq->mpwqe.shampo) 244 return -ENOMEM; 245 return 0; 246 } 247 248 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) 249 { 250 kvfree(rq->mpwqe.shampo); 251 } 252 253 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) 254 { 255 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 256 257 shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, 258 node); 259 if (!shampo->bitmap) 260 return -ENOMEM; 261 262 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq, 263 sizeof(*shampo->info)), 264 GFP_KERNEL, node); 265 if (!shampo->info) { 266 kvfree(shampo->bitmap); 267 return -ENOMEM; 268 } 269 return 0; 270 } 271 272 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) 273 { 274 kvfree(rq->mpwqe.shampo->bitmap); 275 kvfree(rq->mpwqe.shampo->info); 276 } 277 278 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) 279 { 280 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 281 size_t alloc_size; 282 283 alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info, alloc_units, 284 rq->mpwqe.pages_per_wqe)); 285 286 rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node); 287 if (!rq->mpwqe.info) 288 return -ENOMEM; 289 290 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe); 291 292 return 0; 293 } 294 295 296 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode) 297 { 298 switch (umr_mode) { 299 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 300 return MLX5_MKC_ACCESS_MODE_MTT; 301 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 302 return MLX5_MKC_ACCESS_MODE_KSM; 303 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 304 return MLX5_MKC_ACCESS_MODE_KLMS; 305 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 306 return MLX5_MKC_ACCESS_MODE_KSM; 307 } 308 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode); 309 return 0; 310 } 311 312 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, 313 u32 npages, u8 page_shift, u32 *umr_mkey, 314 dma_addr_t filler_addr, 315 enum mlx5e_mpwrq_umr_mode umr_mode, 316 u32 xsk_chunk_size) 317 { 318 struct mlx5_mtt *mtt; 319 struct mlx5_ksm *ksm; 320 struct mlx5_klm *klm; 321 u32 octwords; 322 int inlen; 323 void *mkc; 324 u32 *in; 325 int err; 326 int i; 327 328 if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED || 329 umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) && 330 !MLX5_CAP_GEN(mdev, fixed_buffer_size)) { 331 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n"); 332 return -EINVAL; 333 } 334 335 octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode); 336 337 inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in), 338 MLX5_OCTWORD, octwords); 339 if (inlen < 0) 340 return inlen; 341 342 in = kvzalloc(inlen, GFP_KERNEL); 343 if (!in) 344 return -ENOMEM; 345 346 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 347 348 MLX5_SET(mkc, mkc, free, 1); 349 MLX5_SET(mkc, mkc, umr_en, 1); 350 MLX5_SET(mkc, mkc, lw, 1); 351 MLX5_SET(mkc, mkc, lr, 1); 352 MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode)); 353 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 354 MLX5_SET(mkc, mkc, qpn, 0xffffff); 355 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); 356 MLX5_SET64(mkc, mkc, len, npages << page_shift); 357 MLX5_SET(mkc, mkc, translations_octword_size, octwords); 358 if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) 359 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2); 360 else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED) 361 MLX5_SET(mkc, mkc, log_page_size, page_shift); 362 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords); 363 364 /* Initialize the mkey with all MTTs pointing to a default 365 * page (filler_addr). When the channels are activated, UMR 366 * WQEs will redirect the RX WQEs to the actual memory from 367 * the RQ's pool, while the gaps (wqe_overflow) remain mapped 368 * to the default page. 369 */ 370 switch (umr_mode) { 371 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 372 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 373 for (i = 0; i < npages; i++) { 374 klm[i << 1] = (struct mlx5_klm) { 375 .va = cpu_to_be64(filler_addr), 376 .bcount = cpu_to_be32(xsk_chunk_size), 377 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 378 }; 379 klm[(i << 1) + 1] = (struct mlx5_klm) { 380 .va = cpu_to_be64(filler_addr), 381 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size), 382 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 383 }; 384 } 385 break; 386 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 387 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 388 for (i = 0; i < npages; i++) 389 ksm[i] = (struct mlx5_ksm) { 390 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 391 .va = cpu_to_be64(filler_addr), 392 }; 393 break; 394 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 395 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 396 for (i = 0; i < npages; i++) 397 mtt[i] = (struct mlx5_mtt) { 398 .ptag = cpu_to_be64(filler_addr), 399 }; 400 break; 401 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 402 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 403 for (i = 0; i < npages * 4; i++) { 404 ksm[i] = (struct mlx5_ksm) { 405 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 406 .va = cpu_to_be64(filler_addr), 407 }; 408 } 409 break; 410 } 411 412 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 413 414 kvfree(in); 415 return err; 416 } 417 418 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev, 419 u64 nentries, 420 u32 *umr_mkey) 421 { 422 int inlen; 423 void *mkc; 424 u32 *in; 425 int err; 426 427 inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 428 429 in = kvzalloc(inlen, GFP_KERNEL); 430 if (!in) 431 return -ENOMEM; 432 433 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 434 435 MLX5_SET(mkc, mkc, free, 1); 436 MLX5_SET(mkc, mkc, umr_en, 1); 437 MLX5_SET(mkc, mkc, lw, 1); 438 MLX5_SET(mkc, mkc, lr, 1); 439 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); 440 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 441 MLX5_SET(mkc, mkc, qpn, 0xffffff); 442 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); 443 MLX5_SET(mkc, mkc, translations_octword_size, nentries); 444 MLX5_SET(mkc, mkc, length64, 1); 445 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 446 447 kvfree(in); 448 return err; 449 } 450 451 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) 452 { 453 u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0; 454 u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 455 u32 num_entries, max_num_entries; 456 u32 umr_mkey; 457 int err; 458 459 max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode); 460 461 /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */ 462 if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe, 463 &num_entries) || 464 num_entries > max_num_entries)) 465 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n", 466 __func__, wq_size, rq->mpwqe.mtts_per_wqe, 467 max_num_entries); 468 469 err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift, 470 &umr_mkey, rq->wqe_overflow.addr, 471 rq->mpwqe.umr_mode, xsk_chunk_size); 472 rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey); 473 return err; 474 } 475 476 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, 477 struct mlx5e_rq *rq) 478 { 479 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); 480 481 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) { 482 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n", 483 max_klm_size, rq->mpwqe.shampo->hd_per_wq); 484 return -EINVAL; 485 } 486 return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, 487 &rq->mpwqe.shampo->mkey); 488 } 489 490 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) 491 { 492 struct mlx5e_wqe_frag_info next_frag = {}; 493 struct mlx5e_wqe_frag_info *prev = NULL; 494 int i; 495 496 if (rq->xsk_pool) { 497 /* Assumptions used by XSK batched allocator. */ 498 WARN_ON(rq->wqe.info.num_frags != 1); 499 WARN_ON(rq->wqe.info.log_num_frags != 0); 500 WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE); 501 } 502 503 next_frag.au = &rq->wqe.alloc_units[0]; 504 505 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { 506 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 507 struct mlx5e_wqe_frag_info *frag = 508 &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; 509 int f; 510 511 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { 512 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { 513 next_frag.au++; 514 next_frag.offset = 0; 515 if (prev) 516 prev->last_in_page = true; 517 } 518 *frag = next_frag; 519 520 /* prepare next */ 521 next_frag.offset += frag_info[f].frag_stride; 522 prev = frag; 523 } 524 } 525 526 if (prev) 527 prev->last_in_page = true; 528 } 529 530 static int mlx5e_init_au_list(struct mlx5e_rq *rq, int wq_sz, int node) 531 { 532 int len = wq_sz << rq->wqe.info.log_num_frags; 533 534 rq->wqe.alloc_units = kvzalloc_node(array_size(len, sizeof(*rq->wqe.alloc_units)), 535 GFP_KERNEL, node); 536 if (!rq->wqe.alloc_units) 537 return -ENOMEM; 538 539 mlx5e_init_frags_partition(rq); 540 541 return 0; 542 } 543 544 static void mlx5e_free_au_list(struct mlx5e_rq *rq) 545 { 546 kvfree(rq->wqe.alloc_units); 547 } 548 549 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work) 550 { 551 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work); 552 553 mlx5e_reporter_rq_cqe_err(rq); 554 } 555 556 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 557 { 558 rq->wqe_overflow.page = alloc_page(GFP_KERNEL); 559 if (!rq->wqe_overflow.page) 560 return -ENOMEM; 561 562 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, 563 PAGE_SIZE, rq->buff.map_dir); 564 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { 565 __free_page(rq->wqe_overflow.page); 566 return -ENOMEM; 567 } 568 return 0; 569 } 570 571 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 572 { 573 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, 574 rq->buff.map_dir); 575 __free_page(rq->wqe_overflow.page); 576 } 577 578 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 579 struct mlx5e_rq *rq) 580 { 581 struct mlx5_core_dev *mdev = c->mdev; 582 int err; 583 584 rq->wq_type = params->rq_wq_type; 585 rq->pdev = c->pdev; 586 rq->netdev = c->netdev; 587 rq->priv = c->priv; 588 rq->tstamp = c->tstamp; 589 rq->clock = &mdev->clock; 590 rq->icosq = &c->icosq; 591 rq->ix = c->ix; 592 rq->channel = c; 593 rq->mdev = mdev; 594 rq->hw_mtu = 595 MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en; 596 rq->xdpsq = &c->rq_xdpsq; 597 rq->stats = &c->priv->channel_stats[c->ix]->rq; 598 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev); 599 err = mlx5e_rq_set_handlers(rq, params, NULL); 600 if (err) 601 return err; 602 603 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id); 604 } 605 606 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, 607 struct mlx5e_params *params, 608 struct mlx5e_rq_param *rqp, 609 struct mlx5e_rq *rq, 610 u32 *pool_size, 611 int node) 612 { 613 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq); 614 int wq_size; 615 int err; 616 617 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 618 return 0; 619 err = mlx5e_rq_shampo_hd_alloc(rq, node); 620 if (err) 621 goto out; 622 rq->mpwqe.shampo->hd_per_wq = 623 mlx5e_shampo_hd_per_wq(mdev, params, rqp); 624 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq); 625 if (err) 626 goto err_shampo_hd; 627 err = mlx5e_rq_shampo_hd_info_alloc(rq, node); 628 if (err) 629 goto err_shampo_info; 630 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node); 631 if (!rq->hw_gro_data) { 632 err = -ENOMEM; 633 goto err_hw_gro_data; 634 } 635 rq->mpwqe.shampo->key = 636 cpu_to_be32(rq->mpwqe.shampo->mkey); 637 rq->mpwqe.shampo->hd_per_wqe = 638 mlx5e_shampo_hd_per_wqe(mdev, params, rqp); 639 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 640 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) / 641 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; 642 return 0; 643 644 err_hw_gro_data: 645 mlx5e_rq_shampo_hd_info_free(rq); 646 err_shampo_info: 647 mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); 648 err_shampo_hd: 649 mlx5e_rq_shampo_hd_free(rq); 650 out: 651 return err; 652 } 653 654 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) 655 { 656 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 657 return; 658 659 kvfree(rq->hw_gro_data); 660 mlx5e_rq_shampo_hd_info_free(rq); 661 mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); 662 mlx5e_rq_shampo_hd_free(rq); 663 } 664 665 static int mlx5e_alloc_rq(struct mlx5e_params *params, 666 struct mlx5e_xsk_param *xsk, 667 struct mlx5e_rq_param *rqp, 668 int node, struct mlx5e_rq *rq) 669 { 670 struct page_pool_params pp_params = { 0 }; 671 struct mlx5_core_dev *mdev = rq->mdev; 672 void *rqc = rqp->rqc; 673 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 674 u32 pool_size; 675 int wq_sz; 676 int err; 677 int i; 678 679 rqp->wq.db_numa_node = node; 680 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); 681 682 if (params->xdp_prog) 683 bpf_prog_inc(params->xdp_prog); 684 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); 685 686 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 687 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk); 688 pool_size = 1 << params->log_rq_mtu_frames; 689 690 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey); 691 692 switch (rq->wq_type) { 693 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 694 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, 695 &rq->wq_ctrl); 696 if (err) 697 goto err_rq_xdp_prog; 698 699 err = mlx5e_alloc_mpwqe_rq_drop_page(rq); 700 if (err) 701 goto err_rq_wq_destroy; 702 703 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; 704 705 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 706 707 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 708 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 709 rq->mpwqe.pages_per_wqe = 710 mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, 711 rq->mpwqe.umr_mode); 712 rq->mpwqe.umr_wqebbs = 713 mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, 714 rq->mpwqe.umr_mode); 715 rq->mpwqe.mtts_per_wqe = 716 mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift, 717 rq->mpwqe.umr_mode); 718 719 pool_size = rq->mpwqe.pages_per_wqe << 720 mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); 721 722 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 723 rq->mpwqe.num_strides = 724 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 725 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz); 726 727 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz); 728 729 err = mlx5e_create_rq_umr_mkey(mdev, rq); 730 if (err) 731 goto err_rq_drop_page; 732 733 err = mlx5e_rq_alloc_mpwqe_info(rq, node); 734 if (err) 735 goto err_rq_mkey; 736 737 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node); 738 if (err) 739 goto err_free_mpwqe_info; 740 741 break; 742 default: /* MLX5_WQ_TYPE_CYCLIC */ 743 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, 744 &rq->wq_ctrl); 745 if (err) 746 goto err_rq_xdp_prog; 747 748 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; 749 750 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); 751 752 rq->wqe.info = rqp->frags_info; 753 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride; 754 755 rq->wqe.frags = 756 kvzalloc_node(array_size(sizeof(*rq->wqe.frags), 757 (wq_sz << rq->wqe.info.log_num_frags)), 758 GFP_KERNEL, node); 759 if (!rq->wqe.frags) { 760 err = -ENOMEM; 761 goto err_rq_wq_destroy; 762 } 763 764 err = mlx5e_init_au_list(rq, wq_sz, node); 765 if (err) 766 goto err_rq_frags; 767 } 768 769 if (xsk) { 770 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 771 MEM_TYPE_XSK_BUFF_POOL, NULL); 772 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq); 773 } else { 774 /* Create a page_pool and register it with rxq */ 775 pp_params.order = 0; 776 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ 777 pp_params.pool_size = pool_size; 778 pp_params.nid = node; 779 pp_params.dev = rq->pdev; 780 pp_params.dma_dir = rq->buff.map_dir; 781 782 /* page_pool can be used even when there is no rq->xdp_prog, 783 * given page_pool does not handle DMA mapping there is no 784 * required state to clear. And page_pool gracefully handle 785 * elevated refcnt. 786 */ 787 rq->page_pool = page_pool_create(&pp_params); 788 if (IS_ERR(rq->page_pool)) { 789 err = PTR_ERR(rq->page_pool); 790 rq->page_pool = NULL; 791 goto err_free_by_rq_type; 792 } 793 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) 794 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 795 MEM_TYPE_PAGE_POOL, rq->page_pool); 796 } 797 if (err) 798 goto err_destroy_page_pool; 799 800 for (i = 0; i < wq_sz; i++) { 801 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 802 struct mlx5e_rx_wqe_ll *wqe = 803 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); 804 u32 byte_count = 805 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; 806 u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) << 807 rq->mpwqe.page_shift; 808 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ? 809 0 : rq->buff.headroom; 810 811 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom); 812 wqe->data[0].byte_count = cpu_to_be32(byte_count); 813 wqe->data[0].lkey = rq->mpwqe.umr_mkey_be; 814 } else { 815 struct mlx5e_rx_wqe_cyc *wqe = 816 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); 817 int f; 818 819 for (f = 0; f < rq->wqe.info.num_frags; f++) { 820 u32 frag_size = rq->wqe.info.arr[f].frag_size | 821 MLX5_HW_START_PADDING; 822 823 wqe->data[f].byte_count = cpu_to_be32(frag_size); 824 wqe->data[f].lkey = rq->mkey_be; 825 } 826 /* check if num_frags is not a pow of two */ 827 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { 828 wqe->data[f].byte_count = 0; 829 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 830 wqe->data[f].addr = 0; 831 } 832 } 833 } 834 835 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); 836 837 switch (params->rx_cq_moderation.cq_period_mode) { 838 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 839 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 840 break; 841 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 842 default: 843 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 844 } 845 846 rq->page_cache.head = 0; 847 rq->page_cache.tail = 0; 848 849 return 0; 850 851 err_destroy_page_pool: 852 page_pool_destroy(rq->page_pool); 853 err_free_by_rq_type: 854 switch (rq->wq_type) { 855 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 856 mlx5e_rq_free_shampo(rq); 857 err_free_mpwqe_info: 858 kvfree(rq->mpwqe.info); 859 err_rq_mkey: 860 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); 861 err_rq_drop_page: 862 mlx5e_free_mpwqe_rq_drop_page(rq); 863 break; 864 default: /* MLX5_WQ_TYPE_CYCLIC */ 865 mlx5e_free_au_list(rq); 866 err_rq_frags: 867 kvfree(rq->wqe.frags); 868 } 869 err_rq_wq_destroy: 870 mlx5_wq_destroy(&rq->wq_ctrl); 871 err_rq_xdp_prog: 872 if (params->xdp_prog) 873 bpf_prog_put(params->xdp_prog); 874 875 return err; 876 } 877 878 static void mlx5e_free_rq(struct mlx5e_rq *rq) 879 { 880 struct bpf_prog *old_prog; 881 int i; 882 883 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) { 884 old_prog = rcu_dereference_protected(rq->xdp_prog, 885 lockdep_is_held(&rq->priv->state_lock)); 886 if (old_prog) 887 bpf_prog_put(old_prog); 888 } 889 890 switch (rq->wq_type) { 891 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 892 kvfree(rq->mpwqe.info); 893 mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); 894 mlx5e_free_mpwqe_rq_drop_page(rq); 895 mlx5e_rq_free_shampo(rq); 896 break; 897 default: /* MLX5_WQ_TYPE_CYCLIC */ 898 kvfree(rq->wqe.frags); 899 mlx5e_free_au_list(rq); 900 } 901 902 for (i = rq->page_cache.head; i != rq->page_cache.tail; 903 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { 904 /* With AF_XDP, page_cache is not used, so this loop is not 905 * entered, and it's safe to call mlx5e_page_release_dynamic 906 * directly. 907 */ 908 mlx5e_page_release_dynamic(rq, rq->page_cache.page_cache[i], false); 909 } 910 911 xdp_rxq_info_unreg(&rq->xdp_rxq); 912 page_pool_destroy(rq->page_pool); 913 mlx5_wq_destroy(&rq->wq_ctrl); 914 } 915 916 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 917 { 918 struct mlx5_core_dev *mdev = rq->mdev; 919 u8 ts_format; 920 void *in; 921 void *rqc; 922 void *wq; 923 int inlen; 924 int err; 925 926 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 927 sizeof(u64) * rq->wq_ctrl.buf.npages; 928 in = kvzalloc(inlen, GFP_KERNEL); 929 if (!in) 930 return -ENOMEM; 931 932 ts_format = mlx5_is_real_time_rq(mdev) ? 933 MLX5_TIMESTAMP_FORMAT_REAL_TIME : 934 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 935 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 936 wq = MLX5_ADDR_OF(rqc, rqc, wq); 937 938 memcpy(rqc, param->rqc, sizeof(param->rqc)); 939 940 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); 941 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 942 MLX5_SET(rqc, rqc, ts_format, ts_format); 943 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 944 MLX5_ADAPTER_PAGE_SHIFT); 945 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 946 947 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { 948 MLX5_SET(wq, wq, log_headers_buffer_entry_num, 949 order_base_2(rq->mpwqe.shampo->hd_per_wq)); 950 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey); 951 } 952 953 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, 954 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 955 956 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 957 958 kvfree(in); 959 960 return err; 961 } 962 963 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state) 964 { 965 struct mlx5_core_dev *mdev = rq->mdev; 966 967 void *in; 968 void *rqc; 969 int inlen; 970 int err; 971 972 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 973 in = kvzalloc(inlen, GFP_KERNEL); 974 if (!in) 975 return -ENOMEM; 976 977 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY) 978 mlx5e_rqwq_reset(rq); 979 980 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 981 982 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 983 MLX5_SET(rqc, rqc, state, next_state); 984 985 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 986 987 kvfree(in); 988 989 return err; 990 } 991 992 static int mlx5e_rq_to_ready(struct mlx5e_rq *rq, int curr_state) 993 { 994 struct net_device *dev = rq->netdev; 995 int err; 996 997 err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST); 998 if (err) { 999 netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn); 1000 return err; 1001 } 1002 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1003 if (err) { 1004 netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn); 1005 return err; 1006 } 1007 1008 return 0; 1009 } 1010 1011 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state) 1012 { 1013 mlx5e_free_rx_descs(rq); 1014 1015 return mlx5e_rq_to_ready(rq, curr_state); 1016 } 1017 1018 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) 1019 { 1020 struct mlx5_core_dev *mdev = rq->mdev; 1021 void *in; 1022 void *rqc; 1023 int inlen; 1024 int err; 1025 1026 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1027 in = kvzalloc(inlen, GFP_KERNEL); 1028 if (!in) 1029 return -ENOMEM; 1030 1031 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1032 1033 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 1034 MLX5_SET64(modify_rq_in, in, modify_bitmask, 1035 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 1036 MLX5_SET(rqc, rqc, vsd, vsd); 1037 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 1038 1039 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 1040 1041 kvfree(in); 1042 1043 return err; 1044 } 1045 1046 void mlx5e_destroy_rq(struct mlx5e_rq *rq) 1047 { 1048 mlx5_core_destroy_rq(rq->mdev, rq->rqn); 1049 } 1050 1051 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) 1052 { 1053 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); 1054 1055 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); 1056 1057 do { 1058 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) 1059 return 0; 1060 1061 msleep(20); 1062 } while (time_before(jiffies, exp_time)); 1063 1064 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", 1065 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); 1066 1067 mlx5e_reporter_rx_timeout(rq); 1068 return -ETIMEDOUT; 1069 } 1070 1071 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq) 1072 { 1073 struct mlx5_wq_ll *wq; 1074 u16 head; 1075 int i; 1076 1077 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 1078 return; 1079 1080 wq = &rq->mpwqe.wq; 1081 head = wq->head; 1082 1083 /* Outstanding UMR WQEs (in progress) start at wq->head */ 1084 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) { 1085 rq->dealloc_wqe(rq, head); 1086 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 1087 } 1088 1089 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { 1090 u16 len; 1091 1092 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) & 1093 (rq->mpwqe.shampo->hd_per_wq - 1); 1094 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false); 1095 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci; 1096 } 1097 1098 rq->mpwqe.actual_wq_head = wq->head; 1099 rq->mpwqe.umr_in_progress = 0; 1100 rq->mpwqe.umr_completed = 0; 1101 } 1102 1103 void mlx5e_free_rx_descs(struct mlx5e_rq *rq) 1104 { 1105 __be16 wqe_ix_be; 1106 u16 wqe_ix; 1107 1108 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 1109 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 1110 1111 mlx5e_free_rx_in_progress_descs(rq); 1112 1113 while (!mlx5_wq_ll_is_empty(wq)) { 1114 struct mlx5e_rx_wqe_ll *wqe; 1115 1116 wqe_ix_be = *wq->tail_next; 1117 wqe_ix = be16_to_cpu(wqe_ix_be); 1118 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); 1119 rq->dealloc_wqe(rq, wqe_ix); 1120 mlx5_wq_ll_pop(wq, wqe_ix_be, 1121 &wqe->next.next_wqe_index); 1122 } 1123 1124 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 1125 mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq, 1126 0, true); 1127 } else { 1128 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1129 1130 while (!mlx5_wq_cyc_is_empty(wq)) { 1131 wqe_ix = mlx5_wq_cyc_get_tail(wq); 1132 rq->dealloc_wqe(rq, wqe_ix); 1133 mlx5_wq_cyc_pop(wq); 1134 } 1135 } 1136 1137 } 1138 1139 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1140 struct mlx5e_xsk_param *xsk, int node, 1141 struct mlx5e_rq *rq) 1142 { 1143 struct mlx5_core_dev *mdev = rq->mdev; 1144 int err; 1145 1146 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 1147 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state); 1148 1149 err = mlx5e_alloc_rq(params, xsk, param, node, rq); 1150 if (err) 1151 return err; 1152 1153 err = mlx5e_create_rq(rq, param); 1154 if (err) 1155 goto err_free_rq; 1156 1157 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1158 if (err) 1159 goto err_destroy_rq; 1160 1161 if (MLX5_CAP_ETH(mdev, cqe_checksum_full)) 1162 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state); 1163 1164 if (params->rx_dim_enabled) 1165 __set_bit(MLX5E_RQ_STATE_AM, &rq->state); 1166 1167 /* We disable csum_complete when XDP is enabled since 1168 * XDP programs might manipulate packets which will render 1169 * skb->checksum incorrect. 1170 */ 1171 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog) 1172 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state); 1173 1174 /* For CQE compression on striding RQ, use stride index provided by 1175 * HW if capability is supported. 1176 */ 1177 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) && 1178 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) 1179 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state); 1180 1181 /* For enhanced CQE compression packet processing. decompress 1182 * session according to the enhanced layout. 1183 */ 1184 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) && 1185 MLX5_CAP_GEN(mdev, enhanced_cqe_compression)) 1186 __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state); 1187 1188 return 0; 1189 1190 err_destroy_rq: 1191 mlx5e_destroy_rq(rq); 1192 err_free_rq: 1193 mlx5e_free_rq(rq); 1194 1195 return err; 1196 } 1197 1198 void mlx5e_activate_rq(struct mlx5e_rq *rq) 1199 { 1200 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 1201 } 1202 1203 void mlx5e_deactivate_rq(struct mlx5e_rq *rq) 1204 { 1205 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 1206 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */ 1207 } 1208 1209 void mlx5e_close_rq(struct mlx5e_rq *rq) 1210 { 1211 cancel_work_sync(&rq->dim.work); 1212 cancel_work_sync(&rq->recover_work); 1213 mlx5e_destroy_rq(rq); 1214 mlx5e_free_rx_descs(rq); 1215 mlx5e_free_rq(rq); 1216 } 1217 1218 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) 1219 { 1220 kvfree(sq->db.xdpi_fifo.xi); 1221 kvfree(sq->db.wqe_info); 1222 } 1223 1224 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa) 1225 { 1226 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo; 1227 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1228 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1229 size_t size; 1230 1231 size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq); 1232 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa); 1233 if (!xdpi_fifo->xi) 1234 return -ENOMEM; 1235 1236 xdpi_fifo->pc = &sq->xdpi_fifo_pc; 1237 xdpi_fifo->cc = &sq->xdpi_fifo_cc; 1238 xdpi_fifo->mask = dsegs_per_wq - 1; 1239 1240 return 0; 1241 } 1242 1243 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) 1244 { 1245 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1246 size_t size; 1247 int err; 1248 1249 size = array_size(sizeof(*sq->db.wqe_info), wq_sz); 1250 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1251 if (!sq->db.wqe_info) 1252 return -ENOMEM; 1253 1254 err = mlx5e_alloc_xdpsq_fifo(sq, numa); 1255 if (err) { 1256 mlx5e_free_xdpsq_db(sq); 1257 return err; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 1264 struct mlx5e_params *params, 1265 struct xsk_buff_pool *xsk_pool, 1266 struct mlx5e_sq_param *param, 1267 struct mlx5e_xdpsq *sq, 1268 bool is_redirect) 1269 { 1270 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1271 struct mlx5_core_dev *mdev = c->mdev; 1272 struct mlx5_wq_cyc *wq = &sq->wq; 1273 int err; 1274 1275 sq->pdev = c->pdev; 1276 sq->mkey_be = c->mkey_be; 1277 sq->channel = c; 1278 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1279 sq->min_inline_mode = params->tx_min_inline_mode; 1280 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN; 1281 sq->xsk_pool = xsk_pool; 1282 1283 sq->stats = sq->xsk_pool ? 1284 &c->priv->channel_stats[c->ix]->xsksq : 1285 is_redirect ? 1286 &c->priv->channel_stats[c->ix]->xdpsq : 1287 &c->priv->channel_stats[c->ix]->rq_xdpsq; 1288 sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) : 1289 mlx5e_stop_room_for_max_wqe(mdev); 1290 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 1291 1292 param->wq.db_numa_node = cpu_to_node(c->cpu); 1293 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1294 if (err) 1295 return err; 1296 wq->db = &wq->db[MLX5_SND_DBR]; 1297 1298 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); 1299 if (err) 1300 goto err_sq_wq_destroy; 1301 1302 return 0; 1303 1304 err_sq_wq_destroy: 1305 mlx5_wq_destroy(&sq->wq_ctrl); 1306 1307 return err; 1308 } 1309 1310 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) 1311 { 1312 mlx5e_free_xdpsq_db(sq); 1313 mlx5_wq_destroy(&sq->wq_ctrl); 1314 } 1315 1316 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) 1317 { 1318 kvfree(sq->db.wqe_info); 1319 } 1320 1321 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) 1322 { 1323 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1324 size_t size; 1325 1326 size = array_size(wq_sz, sizeof(*sq->db.wqe_info)); 1327 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1328 if (!sq->db.wqe_info) 1329 return -ENOMEM; 1330 1331 return 0; 1332 } 1333 1334 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work) 1335 { 1336 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1337 recover_work); 1338 1339 mlx5e_reporter_icosq_cqe_err(sq); 1340 } 1341 1342 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work) 1343 { 1344 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1345 recover_work); 1346 1347 /* Not implemented yet. */ 1348 1349 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n"); 1350 } 1351 1352 static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 1353 struct mlx5e_sq_param *param, 1354 struct mlx5e_icosq *sq, 1355 work_func_t recover_work_func) 1356 { 1357 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1358 struct mlx5_core_dev *mdev = c->mdev; 1359 struct mlx5_wq_cyc *wq = &sq->wq; 1360 int err; 1361 1362 sq->channel = c; 1363 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1364 sq->reserved_room = param->stop_room; 1365 1366 param->wq.db_numa_node = cpu_to_node(c->cpu); 1367 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1368 if (err) 1369 return err; 1370 wq->db = &wq->db[MLX5_SND_DBR]; 1371 1372 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); 1373 if (err) 1374 goto err_sq_wq_destroy; 1375 1376 INIT_WORK(&sq->recover_work, recover_work_func); 1377 1378 return 0; 1379 1380 err_sq_wq_destroy: 1381 mlx5_wq_destroy(&sq->wq_ctrl); 1382 1383 return err; 1384 } 1385 1386 static void mlx5e_free_icosq(struct mlx5e_icosq *sq) 1387 { 1388 mlx5e_free_icosq_db(sq); 1389 mlx5_wq_destroy(&sq->wq_ctrl); 1390 } 1391 1392 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) 1393 { 1394 kvfree(sq->db.wqe_info); 1395 kvfree(sq->db.skb_fifo.fifo); 1396 kvfree(sq->db.dma_fifo); 1397 } 1398 1399 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) 1400 { 1401 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1402 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1403 1404 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, 1405 sizeof(*sq->db.dma_fifo)), 1406 GFP_KERNEL, numa); 1407 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz, 1408 sizeof(*sq->db.skb_fifo.fifo)), 1409 GFP_KERNEL, numa); 1410 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, 1411 sizeof(*sq->db.wqe_info)), 1412 GFP_KERNEL, numa); 1413 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) { 1414 mlx5e_free_txqsq_db(sq); 1415 return -ENOMEM; 1416 } 1417 1418 sq->dma_fifo_mask = df_sz - 1; 1419 1420 sq->db.skb_fifo.pc = &sq->skb_fifo_pc; 1421 sq->db.skb_fifo.cc = &sq->skb_fifo_cc; 1422 sq->db.skb_fifo.mask = df_sz - 1; 1423 1424 return 0; 1425 } 1426 1427 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 1428 int txq_ix, 1429 struct mlx5e_params *params, 1430 struct mlx5e_sq_param *param, 1431 struct mlx5e_txqsq *sq, 1432 int tc) 1433 { 1434 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1435 struct mlx5_core_dev *mdev = c->mdev; 1436 struct mlx5_wq_cyc *wq = &sq->wq; 1437 int err; 1438 1439 sq->pdev = c->pdev; 1440 sq->clock = &mdev->clock; 1441 sq->mkey_be = c->mkey_be; 1442 sq->netdev = c->netdev; 1443 sq->mdev = c->mdev; 1444 sq->priv = c->priv; 1445 sq->ch_ix = c->ix; 1446 sq->txq_ix = txq_ix; 1447 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1448 sq->min_inline_mode = params->tx_min_inline_mode; 1449 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1450 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 1451 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); 1452 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) 1453 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); 1454 if (mlx5_ipsec_device_caps(c->priv->mdev)) 1455 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); 1456 if (param->is_mpw) 1457 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); 1458 sq->stop_room = param->stop_room; 1459 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev); 1460 1461 param->wq.db_numa_node = cpu_to_node(c->cpu); 1462 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1463 if (err) 1464 return err; 1465 wq->db = &wq->db[MLX5_SND_DBR]; 1466 1467 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); 1468 if (err) 1469 goto err_sq_wq_destroy; 1470 1471 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); 1472 sq->dim.mode = params->tx_cq_moderation.cq_period_mode; 1473 1474 return 0; 1475 1476 err_sq_wq_destroy: 1477 mlx5_wq_destroy(&sq->wq_ctrl); 1478 1479 return err; 1480 } 1481 1482 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) 1483 { 1484 mlx5e_free_txqsq_db(sq); 1485 mlx5_wq_destroy(&sq->wq_ctrl); 1486 } 1487 1488 static int mlx5e_create_sq(struct mlx5_core_dev *mdev, 1489 struct mlx5e_sq_param *param, 1490 struct mlx5e_create_sq_param *csp, 1491 u32 *sqn) 1492 { 1493 u8 ts_format; 1494 void *in; 1495 void *sqc; 1496 void *wq; 1497 int inlen; 1498 int err; 1499 1500 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1501 sizeof(u64) * csp->wq_ctrl->buf.npages; 1502 in = kvzalloc(inlen, GFP_KERNEL); 1503 if (!in) 1504 return -ENOMEM; 1505 1506 ts_format = mlx5_is_real_time_sq(mdev) ? 1507 MLX5_TIMESTAMP_FORMAT_REAL_TIME : 1508 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1509 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1510 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1511 1512 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1513 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); 1514 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); 1515 MLX5_SET(sqc, sqc, cqn, csp->cqn); 1516 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn); 1517 MLX5_SET(sqc, sqc, ts_format, ts_format); 1518 1519 1520 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 1521 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); 1522 1523 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1524 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1525 1526 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1527 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index); 1528 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - 1529 MLX5_ADAPTER_PAGE_SHIFT); 1530 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); 1531 1532 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, 1533 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 1534 1535 err = mlx5_core_create_sq(mdev, in, inlen, sqn); 1536 1537 kvfree(in); 1538 1539 return err; 1540 } 1541 1542 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1543 struct mlx5e_modify_sq_param *p) 1544 { 1545 u64 bitmask = 0; 1546 void *in; 1547 void *sqc; 1548 int inlen; 1549 int err; 1550 1551 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1552 in = kvzalloc(inlen, GFP_KERNEL); 1553 if (!in) 1554 return -ENOMEM; 1555 1556 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1557 1558 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); 1559 MLX5_SET(sqc, sqc, state, p->next_state); 1560 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { 1561 bitmask |= 1; 1562 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); 1563 } 1564 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) { 1565 bitmask |= 1 << 2; 1566 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id); 1567 } 1568 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask); 1569 1570 err = mlx5_core_modify_sq(mdev, sqn, in); 1571 1572 kvfree(in); 1573 1574 return err; 1575 } 1576 1577 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) 1578 { 1579 mlx5_core_destroy_sq(mdev, sqn); 1580 } 1581 1582 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1583 struct mlx5e_sq_param *param, 1584 struct mlx5e_create_sq_param *csp, 1585 u16 qos_queue_group_id, 1586 u32 *sqn) 1587 { 1588 struct mlx5e_modify_sq_param msp = {0}; 1589 int err; 1590 1591 err = mlx5e_create_sq(mdev, param, csp, sqn); 1592 if (err) 1593 return err; 1594 1595 msp.curr_state = MLX5_SQC_STATE_RST; 1596 msp.next_state = MLX5_SQC_STATE_RDY; 1597 if (qos_queue_group_id) { 1598 msp.qos_update = true; 1599 msp.qos_queue_group_id = qos_queue_group_id; 1600 } 1601 err = mlx5e_modify_sq(mdev, *sqn, &msp); 1602 if (err) 1603 mlx5e_destroy_sq(mdev, *sqn); 1604 1605 return err; 1606 } 1607 1608 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1609 struct mlx5e_txqsq *sq, u32 rate); 1610 1611 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1612 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1613 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1614 struct mlx5e_sq_stats *sq_stats) 1615 { 1616 struct mlx5e_create_sq_param csp = {}; 1617 u32 tx_rate; 1618 int err; 1619 1620 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); 1621 if (err) 1622 return err; 1623 1624 sq->stats = sq_stats; 1625 1626 csp.tisn = tisn; 1627 csp.tis_lst_sz = 1; 1628 csp.cqn = sq->cq.mcq.cqn; 1629 csp.wq_ctrl = &sq->wq_ctrl; 1630 csp.min_inline_mode = sq->min_inline_mode; 1631 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn); 1632 if (err) 1633 goto err_free_txqsq; 1634 1635 tx_rate = c->priv->tx_rates[sq->txq_ix]; 1636 if (tx_rate) 1637 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); 1638 1639 if (params->tx_dim_enabled) 1640 sq->state |= BIT(MLX5E_SQ_STATE_AM); 1641 1642 return 0; 1643 1644 err_free_txqsq: 1645 mlx5e_free_txqsq(sq); 1646 1647 return err; 1648 } 1649 1650 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) 1651 { 1652 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix); 1653 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1654 netdev_tx_reset_queue(sq->txq); 1655 netif_tx_start_queue(sq->txq); 1656 } 1657 1658 void mlx5e_tx_disable_queue(struct netdev_queue *txq) 1659 { 1660 __netif_tx_lock_bh(txq); 1661 netif_tx_stop_queue(txq); 1662 __netif_tx_unlock_bh(txq); 1663 } 1664 1665 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) 1666 { 1667 struct mlx5_wq_cyc *wq = &sq->wq; 1668 1669 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1670 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */ 1671 1672 mlx5e_tx_disable_queue(sq->txq); 1673 1674 /* last doorbell out, godspeed .. */ 1675 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { 1676 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 1677 struct mlx5e_tx_wqe *nop; 1678 1679 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) { 1680 .num_wqebbs = 1, 1681 }; 1682 1683 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); 1684 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); 1685 } 1686 } 1687 1688 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) 1689 { 1690 struct mlx5_core_dev *mdev = sq->mdev; 1691 struct mlx5_rate_limit rl = {0}; 1692 1693 cancel_work_sync(&sq->dim.work); 1694 cancel_work_sync(&sq->recover_work); 1695 mlx5e_destroy_sq(mdev, sq->sqn); 1696 if (sq->rate_limit) { 1697 rl.rate = sq->rate_limit; 1698 mlx5_rl_remove_rate(mdev, &rl); 1699 } 1700 mlx5e_free_txqsq_descs(sq); 1701 mlx5e_free_txqsq(sq); 1702 } 1703 1704 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work) 1705 { 1706 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq, 1707 recover_work); 1708 1709 mlx5e_reporter_tx_err_cqe(sq); 1710 } 1711 1712 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, 1713 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq, 1714 work_func_t recover_work_func) 1715 { 1716 struct mlx5e_create_sq_param csp = {}; 1717 int err; 1718 1719 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func); 1720 if (err) 1721 return err; 1722 1723 csp.cqn = sq->cq.mcq.cqn; 1724 csp.wq_ctrl = &sq->wq_ctrl; 1725 csp.min_inline_mode = params->tx_min_inline_mode; 1726 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1727 if (err) 1728 goto err_free_icosq; 1729 1730 if (param->is_tls) { 1731 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list(); 1732 if (IS_ERR(sq->ktls_resync)) { 1733 err = PTR_ERR(sq->ktls_resync); 1734 goto err_destroy_icosq; 1735 } 1736 } 1737 return 0; 1738 1739 err_destroy_icosq: 1740 mlx5e_destroy_sq(c->mdev, sq->sqn); 1741 err_free_icosq: 1742 mlx5e_free_icosq(sq); 1743 1744 return err; 1745 } 1746 1747 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq) 1748 { 1749 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1750 } 1751 1752 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) 1753 { 1754 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1755 synchronize_net(); /* Sync with NAPI. */ 1756 } 1757 1758 static void mlx5e_close_icosq(struct mlx5e_icosq *sq) 1759 { 1760 struct mlx5e_channel *c = sq->channel; 1761 1762 if (sq->ktls_resync) 1763 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync); 1764 mlx5e_destroy_sq(c->mdev, sq->sqn); 1765 mlx5e_free_icosq_descs(sq); 1766 mlx5e_free_icosq(sq); 1767 } 1768 1769 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1770 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1771 struct mlx5e_xdpsq *sq, bool is_redirect) 1772 { 1773 struct mlx5e_create_sq_param csp = {}; 1774 int err; 1775 1776 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect); 1777 if (err) 1778 return err; 1779 1780 csp.tis_lst_sz = 1; 1781 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */ 1782 csp.cqn = sq->cq.mcq.cqn; 1783 csp.wq_ctrl = &sq->wq_ctrl; 1784 csp.min_inline_mode = sq->min_inline_mode; 1785 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1786 1787 /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet 1788 * supported by upstream, and there is no defined trigger to allow 1789 * transmitting redirected multi-buffer frames. 1790 */ 1791 if (param->is_xdp_mb && !is_redirect) 1792 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state); 1793 1794 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1795 if (err) 1796 goto err_free_xdpsq; 1797 1798 mlx5e_set_xmit_fp(sq, param->is_mpw); 1799 1800 if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) { 1801 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1; 1802 unsigned int inline_hdr_sz = 0; 1803 int i; 1804 1805 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 1806 inline_hdr_sz = MLX5E_XDP_MIN_INLINE; 1807 ds_cnt++; 1808 } 1809 1810 /* Pre initialize fixed WQE fields */ 1811 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { 1812 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); 1813 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 1814 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 1815 struct mlx5_wqe_data_seg *dseg; 1816 1817 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) { 1818 .num_wqebbs = 1, 1819 .num_pkts = 1, 1820 }; 1821 1822 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 1823 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); 1824 1825 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); 1826 dseg->lkey = sq->mkey_be; 1827 } 1828 } 1829 1830 return 0; 1831 1832 err_free_xdpsq: 1833 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1834 mlx5e_free_xdpsq(sq); 1835 1836 return err; 1837 } 1838 1839 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) 1840 { 1841 struct mlx5e_channel *c = sq->channel; 1842 1843 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1844 synchronize_net(); /* Sync with NAPI. */ 1845 1846 mlx5e_destroy_sq(c->mdev, sq->sqn); 1847 mlx5e_free_xdpsq_descs(sq); 1848 mlx5e_free_xdpsq(sq); 1849 } 1850 1851 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv, 1852 struct mlx5e_cq_param *param, 1853 struct mlx5e_cq *cq) 1854 { 1855 struct mlx5_core_dev *mdev = priv->mdev; 1856 struct mlx5_core_cq *mcq = &cq->mcq; 1857 int err; 1858 u32 i; 1859 1860 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1861 &cq->wq_ctrl); 1862 if (err) 1863 return err; 1864 1865 mcq->cqe_sz = 64; 1866 mcq->set_ci_db = cq->wq_ctrl.db.db; 1867 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1868 *mcq->set_ci_db = 0; 1869 *mcq->arm_db = 0; 1870 mcq->vector = param->eq_ix; 1871 mcq->comp = mlx5e_completion_event; 1872 mcq->event = mlx5e_cq_error_event; 1873 1874 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1875 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1876 1877 cqe->op_own = 0xf1; 1878 cqe->validity_iteration_count = 0xff; 1879 } 1880 1881 cq->mdev = mdev; 1882 cq->netdev = priv->netdev; 1883 cq->priv = priv; 1884 1885 return 0; 1886 } 1887 1888 static int mlx5e_alloc_cq(struct mlx5e_priv *priv, 1889 struct mlx5e_cq_param *param, 1890 struct mlx5e_create_cq_param *ccp, 1891 struct mlx5e_cq *cq) 1892 { 1893 int err; 1894 1895 param->wq.buf_numa_node = ccp->node; 1896 param->wq.db_numa_node = ccp->node; 1897 param->eq_ix = ccp->ix; 1898 1899 err = mlx5e_alloc_cq_common(priv, param, cq); 1900 1901 cq->napi = ccp->napi; 1902 cq->ch_stats = ccp->ch_stats; 1903 1904 return err; 1905 } 1906 1907 static void mlx5e_free_cq(struct mlx5e_cq *cq) 1908 { 1909 mlx5_wq_destroy(&cq->wq_ctrl); 1910 } 1911 1912 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) 1913 { 1914 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 1915 struct mlx5_core_dev *mdev = cq->mdev; 1916 struct mlx5_core_cq *mcq = &cq->mcq; 1917 1918 void *in; 1919 void *cqc; 1920 int inlen; 1921 int eqn; 1922 int err; 1923 1924 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn); 1925 if (err) 1926 return err; 1927 1928 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1929 sizeof(u64) * cq->wq_ctrl.buf.npages; 1930 in = kvzalloc(inlen, GFP_KERNEL); 1931 if (!in) 1932 return -ENOMEM; 1933 1934 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1935 1936 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1937 1938 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, 1939 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); 1940 1941 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); 1942 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); 1943 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 1944 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1945 MLX5_ADAPTER_PAGE_SHIFT); 1946 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1947 1948 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out)); 1949 1950 kvfree(in); 1951 1952 if (err) 1953 return err; 1954 1955 mlx5e_cq_arm(cq); 1956 1957 return 0; 1958 } 1959 1960 static void mlx5e_destroy_cq(struct mlx5e_cq *cq) 1961 { 1962 mlx5_core_destroy_cq(cq->mdev, &cq->mcq); 1963 } 1964 1965 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1966 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1967 struct mlx5e_cq *cq) 1968 { 1969 struct mlx5_core_dev *mdev = priv->mdev; 1970 int err; 1971 1972 err = mlx5e_alloc_cq(priv, param, ccp, cq); 1973 if (err) 1974 return err; 1975 1976 err = mlx5e_create_cq(cq, param); 1977 if (err) 1978 goto err_free_cq; 1979 1980 if (MLX5_CAP_GEN(mdev, cq_moderation)) 1981 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); 1982 return 0; 1983 1984 err_free_cq: 1985 mlx5e_free_cq(cq); 1986 1987 return err; 1988 } 1989 1990 void mlx5e_close_cq(struct mlx5e_cq *cq) 1991 { 1992 mlx5e_destroy_cq(cq); 1993 mlx5e_free_cq(cq); 1994 } 1995 1996 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1997 struct mlx5e_params *params, 1998 struct mlx5e_create_cq_param *ccp, 1999 struct mlx5e_channel_param *cparam) 2000 { 2001 int err; 2002 int tc; 2003 2004 for (tc = 0; tc < c->num_tc; tc++) { 2005 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp, 2006 ccp, &c->sq[tc].cq); 2007 if (err) 2008 goto err_close_tx_cqs; 2009 } 2010 2011 return 0; 2012 2013 err_close_tx_cqs: 2014 for (tc--; tc >= 0; tc--) 2015 mlx5e_close_cq(&c->sq[tc].cq); 2016 2017 return err; 2018 } 2019 2020 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2021 { 2022 int tc; 2023 2024 for (tc = 0; tc < c->num_tc; tc++) 2025 mlx5e_close_cq(&c->sq[tc].cq); 2026 } 2027 2028 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq) 2029 { 2030 int tc; 2031 2032 for (tc = 0; tc < TC_MAX_QUEUE; tc++) 2033 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count) 2034 return tc; 2035 2036 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq); 2037 return -ENOENT; 2038 } 2039 2040 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix, 2041 u32 *hw_id) 2042 { 2043 int tc; 2044 2045 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) { 2046 *hw_id = 0; 2047 return 0; 2048 } 2049 2050 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix); 2051 if (tc < 0) 2052 return tc; 2053 2054 if (tc >= params->mqprio.num_tc) { 2055 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u", 2056 tc, params->mqprio.num_tc); 2057 return -EINVAL; 2058 } 2059 2060 *hw_id = params->mqprio.channel.hw_id[tc]; 2061 return 0; 2062 } 2063 2064 static int mlx5e_open_sqs(struct mlx5e_channel *c, 2065 struct mlx5e_params *params, 2066 struct mlx5e_channel_param *cparam) 2067 { 2068 int err, tc; 2069 2070 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) { 2071 int txq_ix = c->ix + tc * params->num_channels; 2072 u32 qos_queue_group_id; 2073 2074 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id); 2075 if (err) 2076 goto err_close_sqs; 2077 2078 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix, 2079 params, &cparam->txq_sq, &c->sq[tc], tc, 2080 qos_queue_group_id, 2081 &c->priv->channel_stats[c->ix]->sq[tc]); 2082 if (err) 2083 goto err_close_sqs; 2084 } 2085 2086 return 0; 2087 2088 err_close_sqs: 2089 for (tc--; tc >= 0; tc--) 2090 mlx5e_close_txqsq(&c->sq[tc]); 2091 2092 return err; 2093 } 2094 2095 static void mlx5e_close_sqs(struct mlx5e_channel *c) 2096 { 2097 int tc; 2098 2099 for (tc = 0; tc < c->num_tc; tc++) 2100 mlx5e_close_txqsq(&c->sq[tc]); 2101 } 2102 2103 static int mlx5e_set_sq_maxrate(struct net_device *dev, 2104 struct mlx5e_txqsq *sq, u32 rate) 2105 { 2106 struct mlx5e_priv *priv = netdev_priv(dev); 2107 struct mlx5_core_dev *mdev = priv->mdev; 2108 struct mlx5e_modify_sq_param msp = {0}; 2109 struct mlx5_rate_limit rl = {0}; 2110 u16 rl_index = 0; 2111 int err; 2112 2113 if (rate == sq->rate_limit) 2114 /* nothing to do */ 2115 return 0; 2116 2117 if (sq->rate_limit) { 2118 rl.rate = sq->rate_limit; 2119 /* remove current rl index to free space to next ones */ 2120 mlx5_rl_remove_rate(mdev, &rl); 2121 } 2122 2123 sq->rate_limit = 0; 2124 2125 if (rate) { 2126 rl.rate = rate; 2127 err = mlx5_rl_add_rate(mdev, &rl_index, &rl); 2128 if (err) { 2129 netdev_err(dev, "Failed configuring rate %u: %d\n", 2130 rate, err); 2131 return err; 2132 } 2133 } 2134 2135 msp.curr_state = MLX5_SQC_STATE_RDY; 2136 msp.next_state = MLX5_SQC_STATE_RDY; 2137 msp.rl_index = rl_index; 2138 msp.rl_update = true; 2139 err = mlx5e_modify_sq(mdev, sq->sqn, &msp); 2140 if (err) { 2141 netdev_err(dev, "Failed configuring rate %u: %d\n", 2142 rate, err); 2143 /* remove the rate from the table */ 2144 if (rate) 2145 mlx5_rl_remove_rate(mdev, &rl); 2146 return err; 2147 } 2148 2149 sq->rate_limit = rate; 2150 return 0; 2151 } 2152 2153 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 2154 { 2155 struct mlx5e_priv *priv = netdev_priv(dev); 2156 struct mlx5_core_dev *mdev = priv->mdev; 2157 struct mlx5e_txqsq *sq = priv->txq2sq[index]; 2158 int err = 0; 2159 2160 if (!mlx5_rl_is_supported(mdev)) { 2161 netdev_err(dev, "Rate limiting is not supported on this device\n"); 2162 return -EINVAL; 2163 } 2164 2165 /* rate is given in Mb/sec, HW config is in Kb/sec */ 2166 rate = rate << 10; 2167 2168 /* Check whether rate in valid range, 0 is always valid */ 2169 if (rate && !mlx5_rl_is_in_range(mdev, rate)) { 2170 netdev_err(dev, "TX rate %u, is not in range\n", rate); 2171 return -ERANGE; 2172 } 2173 2174 mutex_lock(&priv->state_lock); 2175 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 2176 err = mlx5e_set_sq_maxrate(dev, sq, rate); 2177 if (!err) 2178 priv->tx_rates[index] = rate; 2179 mutex_unlock(&priv->state_lock); 2180 2181 return err; 2182 } 2183 2184 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 2185 struct mlx5e_rq_param *rq_params) 2186 { 2187 int err; 2188 2189 err = mlx5e_init_rxq_rq(c, params, &c->rq); 2190 if (err) 2191 return err; 2192 2193 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq); 2194 } 2195 2196 static int mlx5e_open_queues(struct mlx5e_channel *c, 2197 struct mlx5e_params *params, 2198 struct mlx5e_channel_param *cparam) 2199 { 2200 struct dim_cq_moder icocq_moder = {0, 0}; 2201 struct mlx5e_create_cq_param ccp; 2202 int err; 2203 2204 mlx5e_build_create_cq_param(&ccp, c); 2205 2206 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp, 2207 &c->async_icosq.cq); 2208 if (err) 2209 return err; 2210 2211 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp, 2212 &c->icosq.cq); 2213 if (err) 2214 goto err_close_async_icosq_cq; 2215 2216 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam); 2217 if (err) 2218 goto err_close_icosq_cq; 2219 2220 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, 2221 &c->xdpsq.cq); 2222 if (err) 2223 goto err_close_tx_cqs; 2224 2225 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, 2226 &c->rq.cq); 2227 if (err) 2228 goto err_close_xdp_tx_cqs; 2229 2230 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, 2231 &ccp, &c->rq_xdpsq.cq) : 0; 2232 if (err) 2233 goto err_close_rx_cq; 2234 2235 spin_lock_init(&c->async_icosq_lock); 2236 2237 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, 2238 mlx5e_async_icosq_err_cqe_work); 2239 if (err) 2240 goto err_close_xdpsq_cq; 2241 2242 mutex_init(&c->icosq_recovery_lock); 2243 2244 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq, 2245 mlx5e_icosq_err_cqe_work); 2246 if (err) 2247 goto err_close_async_icosq; 2248 2249 err = mlx5e_open_sqs(c, params, cparam); 2250 if (err) 2251 goto err_close_icosq; 2252 2253 err = mlx5e_open_rxq_rq(c, params, &cparam->rq); 2254 if (err) 2255 goto err_close_sqs; 2256 2257 if (c->xdp) { 2258 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, 2259 &c->rq_xdpsq, false); 2260 if (err) 2261 goto err_close_rq; 2262 } 2263 2264 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); 2265 if (err) 2266 goto err_close_xdp_sq; 2267 2268 return 0; 2269 2270 err_close_xdp_sq: 2271 if (c->xdp) 2272 mlx5e_close_xdpsq(&c->rq_xdpsq); 2273 2274 err_close_rq: 2275 mlx5e_close_rq(&c->rq); 2276 2277 err_close_sqs: 2278 mlx5e_close_sqs(c); 2279 2280 err_close_icosq: 2281 mlx5e_close_icosq(&c->icosq); 2282 2283 err_close_async_icosq: 2284 mlx5e_close_icosq(&c->async_icosq); 2285 2286 err_close_xdpsq_cq: 2287 if (c->xdp) 2288 mlx5e_close_cq(&c->rq_xdpsq.cq); 2289 2290 err_close_rx_cq: 2291 mlx5e_close_cq(&c->rq.cq); 2292 2293 err_close_xdp_tx_cqs: 2294 mlx5e_close_cq(&c->xdpsq.cq); 2295 2296 err_close_tx_cqs: 2297 mlx5e_close_tx_cqs(c); 2298 2299 err_close_icosq_cq: 2300 mlx5e_close_cq(&c->icosq.cq); 2301 2302 err_close_async_icosq_cq: 2303 mlx5e_close_cq(&c->async_icosq.cq); 2304 2305 return err; 2306 } 2307 2308 static void mlx5e_close_queues(struct mlx5e_channel *c) 2309 { 2310 mlx5e_close_xdpsq(&c->xdpsq); 2311 if (c->xdp) 2312 mlx5e_close_xdpsq(&c->rq_xdpsq); 2313 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */ 2314 cancel_work_sync(&c->icosq.recover_work); 2315 mlx5e_close_rq(&c->rq); 2316 mlx5e_close_sqs(c); 2317 mlx5e_close_icosq(&c->icosq); 2318 mutex_destroy(&c->icosq_recovery_lock); 2319 mlx5e_close_icosq(&c->async_icosq); 2320 if (c->xdp) 2321 mlx5e_close_cq(&c->rq_xdpsq.cq); 2322 mlx5e_close_cq(&c->rq.cq); 2323 mlx5e_close_cq(&c->xdpsq.cq); 2324 mlx5e_close_tx_cqs(c); 2325 mlx5e_close_cq(&c->icosq.cq); 2326 mlx5e_close_cq(&c->async_icosq.cq); 2327 } 2328 2329 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) 2330 { 2331 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id); 2332 2333 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev); 2334 } 2335 2336 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu) 2337 { 2338 if (ix > priv->stats_nch) { 2339 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix, 2340 priv->stats_nch); 2341 return -EINVAL; 2342 } 2343 2344 if (priv->channel_stats[ix]) 2345 return 0; 2346 2347 /* Asymmetric dynamic memory allocation. 2348 * Freed in mlx5e_priv_arrays_free, not on channel closure. 2349 */ 2350 mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix); 2351 priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats), 2352 GFP_KERNEL, cpu_to_node(cpu)); 2353 if (!priv->channel_stats[ix]) 2354 return -ENOMEM; 2355 priv->stats_nch++; 2356 2357 return 0; 2358 } 2359 2360 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) 2361 { 2362 spin_lock_bh(&c->async_icosq_lock); 2363 mlx5e_trigger_irq(&c->async_icosq); 2364 spin_unlock_bh(&c->async_icosq_lock); 2365 } 2366 2367 void mlx5e_trigger_napi_sched(struct napi_struct *napi) 2368 { 2369 local_bh_disable(); 2370 napi_schedule(napi); 2371 local_bh_enable(); 2372 } 2373 2374 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 2375 struct mlx5e_params *params, 2376 struct mlx5e_channel_param *cparam, 2377 struct xsk_buff_pool *xsk_pool, 2378 struct mlx5e_channel **cp) 2379 { 2380 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix)); 2381 struct net_device *netdev = priv->netdev; 2382 struct mlx5e_xsk_param xsk; 2383 struct mlx5e_channel *c; 2384 unsigned int irq; 2385 int err; 2386 2387 err = mlx5_vector2irqn(priv->mdev, ix, &irq); 2388 if (err) 2389 return err; 2390 2391 err = mlx5e_channel_stats_alloc(priv, ix, cpu); 2392 if (err) 2393 return err; 2394 2395 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); 2396 if (!c) 2397 return -ENOMEM; 2398 2399 c->priv = priv; 2400 c->mdev = priv->mdev; 2401 c->tstamp = &priv->tstamp; 2402 c->ix = ix; 2403 c->cpu = cpu; 2404 c->pdev = mlx5_core_dma_dev(priv->mdev); 2405 c->netdev = priv->netdev; 2406 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey); 2407 c->num_tc = mlx5e_get_dcb_num_tc(params); 2408 c->xdp = !!params->xdp_prog; 2409 c->stats = &priv->channel_stats[ix]->ch; 2410 c->aff_mask = irq_get_effective_affinity_mask(irq); 2411 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix); 2412 2413 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll); 2414 2415 err = mlx5e_open_queues(c, params, cparam); 2416 if (unlikely(err)) 2417 goto err_napi_del; 2418 2419 if (xsk_pool) { 2420 mlx5e_build_xsk_param(xsk_pool, &xsk); 2421 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c); 2422 if (unlikely(err)) 2423 goto err_close_queues; 2424 } 2425 2426 *cp = c; 2427 2428 return 0; 2429 2430 err_close_queues: 2431 mlx5e_close_queues(c); 2432 2433 err_napi_del: 2434 netif_napi_del(&c->napi); 2435 2436 kvfree(c); 2437 2438 return err; 2439 } 2440 2441 static void mlx5e_activate_channel(struct mlx5e_channel *c) 2442 { 2443 int tc; 2444 2445 napi_enable(&c->napi); 2446 2447 for (tc = 0; tc < c->num_tc; tc++) 2448 mlx5e_activate_txqsq(&c->sq[tc]); 2449 mlx5e_activate_icosq(&c->icosq); 2450 mlx5e_activate_icosq(&c->async_icosq); 2451 2452 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2453 mlx5e_activate_xsk(c); 2454 else 2455 mlx5e_activate_rq(&c->rq); 2456 2457 mlx5e_trigger_napi_icosq(c); 2458 } 2459 2460 static void mlx5e_deactivate_channel(struct mlx5e_channel *c) 2461 { 2462 int tc; 2463 2464 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2465 mlx5e_deactivate_xsk(c); 2466 else 2467 mlx5e_deactivate_rq(&c->rq); 2468 2469 mlx5e_deactivate_icosq(&c->async_icosq); 2470 mlx5e_deactivate_icosq(&c->icosq); 2471 for (tc = 0; tc < c->num_tc; tc++) 2472 mlx5e_deactivate_txqsq(&c->sq[tc]); 2473 mlx5e_qos_deactivate_queues(c); 2474 2475 napi_disable(&c->napi); 2476 } 2477 2478 static void mlx5e_close_channel(struct mlx5e_channel *c) 2479 { 2480 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2481 mlx5e_close_xsk(c); 2482 mlx5e_close_queues(c); 2483 mlx5e_qos_close_queues(c); 2484 netif_napi_del(&c->napi); 2485 2486 kvfree(c); 2487 } 2488 2489 int mlx5e_open_channels(struct mlx5e_priv *priv, 2490 struct mlx5e_channels *chs) 2491 { 2492 struct mlx5e_channel_param *cparam; 2493 int err = -ENOMEM; 2494 int i; 2495 2496 chs->num = chs->params.num_channels; 2497 2498 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); 2499 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); 2500 if (!chs->c || !cparam) 2501 goto err_free; 2502 2503 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam); 2504 if (err) 2505 goto err_free; 2506 2507 for (i = 0; i < chs->num; i++) { 2508 struct xsk_buff_pool *xsk_pool = NULL; 2509 2510 if (chs->params.xdp_prog) 2511 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i); 2512 2513 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]); 2514 if (err) 2515 goto err_close_channels; 2516 } 2517 2518 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) { 2519 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp); 2520 if (err) 2521 goto err_close_channels; 2522 } 2523 2524 if (priv->htb) { 2525 err = mlx5e_qos_open_queues(priv, chs); 2526 if (err) 2527 goto err_close_ptp; 2528 } 2529 2530 mlx5e_health_channels_update(priv); 2531 kvfree(cparam); 2532 return 0; 2533 2534 err_close_ptp: 2535 if (chs->ptp) 2536 mlx5e_ptp_close(chs->ptp); 2537 2538 err_close_channels: 2539 for (i--; i >= 0; i--) 2540 mlx5e_close_channel(chs->c[i]); 2541 2542 err_free: 2543 kfree(chs->c); 2544 kvfree(cparam); 2545 chs->num = 0; 2546 return err; 2547 } 2548 2549 static void mlx5e_activate_channels(struct mlx5e_channels *chs) 2550 { 2551 int i; 2552 2553 for (i = 0; i < chs->num; i++) 2554 mlx5e_activate_channel(chs->c[i]); 2555 2556 if (chs->ptp) 2557 mlx5e_ptp_activate_channel(chs->ptp); 2558 } 2559 2560 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) 2561 { 2562 int err = 0; 2563 int i; 2564 2565 for (i = 0; i < chs->num; i++) { 2566 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT; 2567 struct mlx5e_channel *c = chs->c[i]; 2568 2569 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2570 continue; 2571 2572 err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout); 2573 2574 /* Don't wait on the XSK RQ, because the newer xdpsock sample 2575 * doesn't provide any Fill Ring entries at the setup stage. 2576 */ 2577 } 2578 2579 return err ? -ETIMEDOUT : 0; 2580 } 2581 2582 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) 2583 { 2584 int i; 2585 2586 if (chs->ptp) 2587 mlx5e_ptp_deactivate_channel(chs->ptp); 2588 2589 for (i = 0; i < chs->num; i++) 2590 mlx5e_deactivate_channel(chs->c[i]); 2591 } 2592 2593 void mlx5e_close_channels(struct mlx5e_channels *chs) 2594 { 2595 int i; 2596 2597 if (chs->ptp) { 2598 mlx5e_ptp_close(chs->ptp); 2599 chs->ptp = NULL; 2600 } 2601 for (i = 0; i < chs->num; i++) 2602 mlx5e_close_channel(chs->c[i]); 2603 2604 kfree(chs->c); 2605 chs->num = 0; 2606 } 2607 2608 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv) 2609 { 2610 struct mlx5e_rx_res *res = priv->rx_res; 2611 2612 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge); 2613 } 2614 2615 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge); 2616 2617 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, 2618 struct mlx5e_params *params, u16 mtu) 2619 { 2620 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); 2621 int err; 2622 2623 err = mlx5_set_port_mtu(mdev, hw_mtu, 1); 2624 if (err) 2625 return err; 2626 2627 /* Update vport context MTU */ 2628 mlx5_modify_nic_vport_mtu(mdev, hw_mtu); 2629 return 0; 2630 } 2631 2632 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, 2633 struct mlx5e_params *params, u16 *mtu) 2634 { 2635 u16 hw_mtu = 0; 2636 int err; 2637 2638 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); 2639 if (err || !hw_mtu) /* fallback to port oper mtu */ 2640 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); 2641 2642 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); 2643 } 2644 2645 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) 2646 { 2647 struct mlx5e_params *params = &priv->channels.params; 2648 struct net_device *netdev = priv->netdev; 2649 struct mlx5_core_dev *mdev = priv->mdev; 2650 u16 mtu; 2651 int err; 2652 2653 err = mlx5e_set_mtu(mdev, params, params->sw_mtu); 2654 if (err) 2655 return err; 2656 2657 mlx5e_query_mtu(mdev, params, &mtu); 2658 if (mtu != params->sw_mtu) 2659 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", 2660 __func__, mtu, params->sw_mtu); 2661 2662 params->sw_mtu = mtu; 2663 return 0; 2664 } 2665 2666 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu); 2667 2668 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv) 2669 { 2670 struct mlx5e_params *params = &priv->channels.params; 2671 struct net_device *netdev = priv->netdev; 2672 struct mlx5_core_dev *mdev = priv->mdev; 2673 u16 max_mtu; 2674 2675 /* MTU range: 68 - hw-specific max */ 2676 netdev->min_mtu = ETH_MIN_MTU; 2677 2678 mlx5_query_port_max_mtu(mdev, &max_mtu, 1); 2679 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu), 2680 ETH_MAX_MTU); 2681 } 2682 2683 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc, 2684 struct netdev_tc_txq *tc_to_txq) 2685 { 2686 int tc, err; 2687 2688 netdev_reset_tc(netdev); 2689 2690 if (ntc == 1) 2691 return 0; 2692 2693 err = netdev_set_num_tc(netdev, ntc); 2694 if (err) { 2695 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc); 2696 return err; 2697 } 2698 2699 for (tc = 0; tc < ntc; tc++) { 2700 u16 count, offset; 2701 2702 count = tc_to_txq[tc].count; 2703 offset = tc_to_txq[tc].offset; 2704 netdev_set_tc_queue(netdev, tc, count, offset); 2705 } 2706 2707 return 0; 2708 } 2709 2710 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) 2711 { 2712 int nch, ntc, num_txqs, err; 2713 int qos_queues = 0; 2714 2715 if (priv->htb) 2716 qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb); 2717 2718 nch = priv->channels.params.num_channels; 2719 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params); 2720 num_txqs = nch * ntc + qos_queues; 2721 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) 2722 num_txqs += ntc; 2723 2724 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs); 2725 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs); 2726 if (err) 2727 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err); 2728 2729 return err; 2730 } 2731 2732 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) 2733 { 2734 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq; 2735 struct net_device *netdev = priv->netdev; 2736 int old_num_txqs, old_ntc; 2737 int nch, ntc; 2738 int err; 2739 int i; 2740 2741 old_num_txqs = netdev->real_num_tx_queues; 2742 old_ntc = netdev->num_tc ? : 1; 2743 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++) 2744 old_tc_to_txq[i] = netdev->tc_to_txq[i]; 2745 2746 nch = priv->channels.params.num_channels; 2747 ntc = priv->channels.params.mqprio.num_tc; 2748 tc_to_txq = priv->channels.params.mqprio.tc_to_txq; 2749 2750 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq); 2751 if (err) 2752 goto err_out; 2753 err = mlx5e_update_tx_netdev_queues(priv); 2754 if (err) 2755 goto err_tcs; 2756 err = netif_set_real_num_rx_queues(netdev, nch); 2757 if (err) { 2758 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); 2759 goto err_txqs; 2760 } 2761 2762 return 0; 2763 2764 err_txqs: 2765 /* netif_set_real_num_rx_queues could fail only when nch increased. Only 2766 * one of nch and ntc is changed in this function. That means, the call 2767 * to netif_set_real_num_tx_queues below should not fail, because it 2768 * decreases the number of TX queues. 2769 */ 2770 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); 2771 2772 err_tcs: 2773 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc, 2774 old_tc_to_txq)); 2775 err_out: 2776 return err; 2777 } 2778 2779 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues); 2780 2781 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, 2782 struct mlx5e_params *params) 2783 { 2784 struct mlx5_core_dev *mdev = priv->mdev; 2785 int num_comp_vectors, ix, irq; 2786 2787 num_comp_vectors = mlx5_comp_vectors_count(mdev); 2788 2789 for (ix = 0; ix < params->num_channels; ix++) { 2790 cpumask_clear(priv->scratchpad.cpumask); 2791 2792 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { 2793 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq)); 2794 2795 cpumask_set_cpu(cpu, priv->scratchpad.cpumask); 2796 } 2797 2798 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); 2799 } 2800 } 2801 2802 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv) 2803 { 2804 u16 count = priv->channels.params.num_channels; 2805 int err; 2806 2807 err = mlx5e_update_netdev_queues(priv); 2808 if (err) 2809 return err; 2810 2811 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); 2812 2813 /* This function may be called on attach, before priv->rx_res is created. */ 2814 if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res) 2815 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count); 2816 2817 return 0; 2818 } 2819 2820 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed); 2821 2822 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv) 2823 { 2824 int i, ch, tc, num_tc; 2825 2826 ch = priv->channels.num; 2827 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params); 2828 2829 for (i = 0; i < ch; i++) { 2830 for (tc = 0; tc < num_tc; tc++) { 2831 struct mlx5e_channel *c = priv->channels.c[i]; 2832 struct mlx5e_txqsq *sq = &c->sq[tc]; 2833 2834 priv->txq2sq[sq->txq_ix] = sq; 2835 } 2836 } 2837 2838 if (!priv->channels.ptp) 2839 goto out; 2840 2841 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state)) 2842 goto out; 2843 2844 for (tc = 0; tc < num_tc; tc++) { 2845 struct mlx5e_ptp *c = priv->channels.ptp; 2846 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq; 2847 2848 priv->txq2sq[sq->txq_ix] = sq; 2849 } 2850 2851 out: 2852 /* Make the change to txq2sq visible before the queue is started. 2853 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE, 2854 * which pairs with this barrier. 2855 */ 2856 smp_wmb(); 2857 } 2858 2859 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) 2860 { 2861 mlx5e_build_txq_maps(priv); 2862 mlx5e_activate_channels(&priv->channels); 2863 if (priv->htb) 2864 mlx5e_qos_activate_queues(priv); 2865 mlx5e_xdp_tx_enable(priv); 2866 2867 /* dev_watchdog() wants all TX queues to be started when the carrier is 2868 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1. 2869 * Make it happy to avoid TX timeout false alarms. 2870 */ 2871 netif_tx_start_all_queues(priv->netdev); 2872 2873 if (mlx5e_is_vport_rep(priv)) 2874 mlx5e_rep_activate_channels(priv); 2875 2876 mlx5e_wait_channels_min_rx_wqes(&priv->channels); 2877 2878 if (priv->rx_res) 2879 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels); 2880 } 2881 2882 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) 2883 { 2884 if (priv->rx_res) 2885 mlx5e_rx_res_channels_deactivate(priv->rx_res); 2886 2887 if (mlx5e_is_vport_rep(priv)) 2888 mlx5e_rep_deactivate_channels(priv); 2889 2890 /* The results of ndo_select_queue are unreliable, while netdev config 2891 * is being changed (real_num_tx_queues, num_tc). Stop all queues to 2892 * prevent ndo_start_xmit from being called, so that it can assume that 2893 * the selected queue is always valid. 2894 */ 2895 netif_tx_disable(priv->netdev); 2896 2897 mlx5e_xdp_tx_disable(priv); 2898 mlx5e_deactivate_channels(&priv->channels); 2899 } 2900 2901 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv, 2902 struct mlx5e_params *new_params, 2903 mlx5e_fp_preactivate preactivate, 2904 void *context) 2905 { 2906 struct mlx5e_params old_params; 2907 2908 old_params = priv->channels.params; 2909 priv->channels.params = *new_params; 2910 2911 if (preactivate) { 2912 int err; 2913 2914 err = preactivate(priv, context); 2915 if (err) { 2916 priv->channels.params = old_params; 2917 return err; 2918 } 2919 } 2920 2921 return 0; 2922 } 2923 2924 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, 2925 struct mlx5e_channels *new_chs, 2926 mlx5e_fp_preactivate preactivate, 2927 void *context) 2928 { 2929 struct net_device *netdev = priv->netdev; 2930 struct mlx5e_channels old_chs; 2931 int carrier_ok; 2932 int err = 0; 2933 2934 carrier_ok = netif_carrier_ok(netdev); 2935 netif_carrier_off(netdev); 2936 2937 mlx5e_deactivate_priv_channels(priv); 2938 2939 old_chs = priv->channels; 2940 priv->channels = *new_chs; 2941 2942 /* New channels are ready to roll, call the preactivate hook if needed 2943 * to modify HW settings or update kernel parameters. 2944 */ 2945 if (preactivate) { 2946 err = preactivate(priv, context); 2947 if (err) { 2948 priv->channels = old_chs; 2949 goto out; 2950 } 2951 } 2952 2953 mlx5e_close_channels(&old_chs); 2954 priv->profile->update_rx(priv); 2955 2956 mlx5e_selq_apply(&priv->selq); 2957 out: 2958 mlx5e_activate_priv_channels(priv); 2959 2960 /* return carrier back if needed */ 2961 if (carrier_ok) 2962 netif_carrier_on(netdev); 2963 2964 return err; 2965 } 2966 2967 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 2968 struct mlx5e_params *params, 2969 mlx5e_fp_preactivate preactivate, 2970 void *context, bool reset) 2971 { 2972 struct mlx5e_channels new_chs = {}; 2973 int err; 2974 2975 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state); 2976 if (!reset) 2977 return mlx5e_switch_priv_params(priv, params, preactivate, context); 2978 2979 new_chs.params = *params; 2980 2981 mlx5e_selq_prepare_params(&priv->selq, &new_chs.params); 2982 2983 err = mlx5e_open_channels(priv, &new_chs); 2984 if (err) 2985 goto err_cancel_selq; 2986 2987 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context); 2988 if (err) 2989 goto err_close; 2990 2991 return 0; 2992 2993 err_close: 2994 mlx5e_close_channels(&new_chs); 2995 2996 err_cancel_selq: 2997 mlx5e_selq_cancel(&priv->selq); 2998 return err; 2999 } 3000 3001 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv) 3002 { 3003 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true); 3004 } 3005 3006 void mlx5e_timestamp_init(struct mlx5e_priv *priv) 3007 { 3008 priv->tstamp.tx_type = HWTSTAMP_TX_OFF; 3009 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; 3010 } 3011 3012 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, 3013 enum mlx5_port_status state) 3014 { 3015 struct mlx5_eswitch *esw = mdev->priv.eswitch; 3016 int vport_admin_state; 3017 3018 mlx5_set_port_admin_status(mdev, state); 3019 3020 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS || 3021 !MLX5_CAP_GEN(mdev, uplink_follow)) 3022 return; 3023 3024 if (state == MLX5_PORT_UP) 3025 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO; 3026 else 3027 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN; 3028 3029 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state); 3030 } 3031 3032 int mlx5e_open_locked(struct net_device *netdev) 3033 { 3034 struct mlx5e_priv *priv = netdev_priv(netdev); 3035 int err; 3036 3037 mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params); 3038 3039 set_bit(MLX5E_STATE_OPENED, &priv->state); 3040 3041 err = mlx5e_open_channels(priv, &priv->channels); 3042 if (err) 3043 goto err_clear_state_opened_flag; 3044 3045 err = priv->profile->update_rx(priv); 3046 if (err) 3047 goto err_close_channels; 3048 3049 mlx5e_selq_apply(&priv->selq); 3050 mlx5e_activate_priv_channels(priv); 3051 mlx5e_apply_traps(priv, true); 3052 if (priv->profile->update_carrier) 3053 priv->profile->update_carrier(priv); 3054 3055 mlx5e_queue_update_stats(priv); 3056 return 0; 3057 3058 err_close_channels: 3059 mlx5e_close_channels(&priv->channels); 3060 err_clear_state_opened_flag: 3061 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3062 mlx5e_selq_cancel(&priv->selq); 3063 return err; 3064 } 3065 3066 int mlx5e_open(struct net_device *netdev) 3067 { 3068 struct mlx5e_priv *priv = netdev_priv(netdev); 3069 int err; 3070 3071 mutex_lock(&priv->state_lock); 3072 err = mlx5e_open_locked(netdev); 3073 if (!err) 3074 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP); 3075 mutex_unlock(&priv->state_lock); 3076 3077 return err; 3078 } 3079 3080 int mlx5e_close_locked(struct net_device *netdev) 3081 { 3082 struct mlx5e_priv *priv = netdev_priv(netdev); 3083 3084 /* May already be CLOSED in case a previous configuration operation 3085 * (e.g RX/TX queue size change) that involves close&open failed. 3086 */ 3087 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3088 return 0; 3089 3090 mlx5e_apply_traps(priv, false); 3091 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3092 3093 netif_carrier_off(priv->netdev); 3094 mlx5e_deactivate_priv_channels(priv); 3095 mlx5e_close_channels(&priv->channels); 3096 3097 return 0; 3098 } 3099 3100 int mlx5e_close(struct net_device *netdev) 3101 { 3102 struct mlx5e_priv *priv = netdev_priv(netdev); 3103 int err; 3104 3105 if (!netif_device_present(netdev)) 3106 return -ENODEV; 3107 3108 mutex_lock(&priv->state_lock); 3109 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN); 3110 err = mlx5e_close_locked(netdev); 3111 mutex_unlock(&priv->state_lock); 3112 3113 return err; 3114 } 3115 3116 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) 3117 { 3118 mlx5_wq_destroy(&rq->wq_ctrl); 3119 } 3120 3121 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, 3122 struct mlx5e_rq *rq, 3123 struct mlx5e_rq_param *param) 3124 { 3125 void *rqc = param->rqc; 3126 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 3127 int err; 3128 3129 param->wq.db_numa_node = param->wq.buf_numa_node; 3130 3131 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, 3132 &rq->wq_ctrl); 3133 if (err) 3134 return err; 3135 3136 /* Mark as unused given "Drop-RQ" packets never reach XDP */ 3137 xdp_rxq_info_unused(&rq->xdp_rxq); 3138 3139 rq->mdev = mdev; 3140 3141 return 0; 3142 } 3143 3144 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv, 3145 struct mlx5e_cq *cq, 3146 struct mlx5e_cq_param *param) 3147 { 3148 struct mlx5_core_dev *mdev = priv->mdev; 3149 3150 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3151 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3152 3153 return mlx5e_alloc_cq_common(priv, param, cq); 3154 } 3155 3156 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 3157 struct mlx5e_rq *drop_rq) 3158 { 3159 struct mlx5_core_dev *mdev = priv->mdev; 3160 struct mlx5e_cq_param cq_param = {}; 3161 struct mlx5e_rq_param rq_param = {}; 3162 struct mlx5e_cq *cq = &drop_rq->cq; 3163 int err; 3164 3165 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param); 3166 3167 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param); 3168 if (err) 3169 return err; 3170 3171 err = mlx5e_create_cq(cq, &cq_param); 3172 if (err) 3173 goto err_free_cq; 3174 3175 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); 3176 if (err) 3177 goto err_destroy_cq; 3178 3179 err = mlx5e_create_rq(drop_rq, &rq_param); 3180 if (err) 3181 goto err_free_rq; 3182 3183 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3184 if (err) 3185 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); 3186 3187 return 0; 3188 3189 err_free_rq: 3190 mlx5e_free_drop_rq(drop_rq); 3191 3192 err_destroy_cq: 3193 mlx5e_destroy_cq(cq); 3194 3195 err_free_cq: 3196 mlx5e_free_cq(cq); 3197 3198 return err; 3199 } 3200 3201 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 3202 { 3203 mlx5e_destroy_rq(drop_rq); 3204 mlx5e_free_drop_rq(drop_rq); 3205 mlx5e_destroy_cq(&drop_rq->cq); 3206 mlx5e_free_cq(&drop_rq->cq); 3207 } 3208 3209 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) 3210 { 3211 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3212 3213 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); 3214 3215 if (MLX5_GET(tisc, tisc, tls_en)) 3216 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); 3217 3218 if (mlx5_lag_is_lacp_owner(mdev)) 3219 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 3220 3221 return mlx5_core_create_tis(mdev, in, tisn); 3222 } 3223 3224 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) 3225 { 3226 mlx5_core_destroy_tis(mdev, tisn); 3227 } 3228 3229 void mlx5e_destroy_tises(struct mlx5e_priv *priv) 3230 { 3231 int tc, i; 3232 3233 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) 3234 for (tc = 0; tc < priv->profile->max_tc; tc++) 3235 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3236 } 3237 3238 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev) 3239 { 3240 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; 3241 } 3242 3243 int mlx5e_create_tises(struct mlx5e_priv *priv) 3244 { 3245 int tc, i; 3246 int err; 3247 3248 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { 3249 for (tc = 0; tc < priv->profile->max_tc; tc++) { 3250 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 3251 void *tisc; 3252 3253 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3254 3255 MLX5_SET(tisc, tisc, prio, tc << 1); 3256 3257 if (mlx5e_lag_should_assign_affinity(priv->mdev)) 3258 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1); 3259 3260 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]); 3261 if (err) 3262 goto err_close_tises; 3263 } 3264 } 3265 3266 return 0; 3267 3268 err_close_tises: 3269 for (; i >= 0; i--) { 3270 for (tc--; tc >= 0; tc--) 3271 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3272 tc = priv->profile->max_tc; 3273 } 3274 3275 return err; 3276 } 3277 3278 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) 3279 { 3280 if (priv->mqprio_rl) { 3281 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3282 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3283 priv->mqprio_rl = NULL; 3284 } 3285 mlx5e_accel_cleanup_tx(priv); 3286 mlx5e_destroy_tises(priv); 3287 } 3288 3289 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) 3290 { 3291 int err; 3292 int i; 3293 3294 for (i = 0; i < chs->num; i++) { 3295 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); 3296 if (err) 3297 return err; 3298 } 3299 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state)) 3300 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd); 3301 3302 return 0; 3303 } 3304 3305 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq, 3306 int ntc, int nch) 3307 { 3308 int tc; 3309 3310 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE); 3311 3312 /* Map netdev TCs to offset 0. 3313 * We have our own UP to TXQ mapping for DCB mode of QoS 3314 */ 3315 for (tc = 0; tc < ntc; tc++) { 3316 tc_to_txq[tc] = (struct netdev_tc_txq) { 3317 .count = nch, 3318 .offset = 0, 3319 }; 3320 } 3321 } 3322 3323 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq, 3324 struct tc_mqprio_qopt *qopt) 3325 { 3326 int tc; 3327 3328 for (tc = 0; tc < TC_MAX_QUEUE; tc++) { 3329 tc_to_txq[tc] = (struct netdev_tc_txq) { 3330 .count = qopt->count[tc], 3331 .offset = qopt->offset[tc], 3332 }; 3333 } 3334 } 3335 3336 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc) 3337 { 3338 params->mqprio.mode = TC_MQPRIO_MODE_DCB; 3339 params->mqprio.num_tc = num_tc; 3340 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc, 3341 params->num_channels); 3342 } 3343 3344 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params, 3345 struct mlx5e_mqprio_rl *rl) 3346 { 3347 int tc; 3348 3349 for (tc = 0; tc < TC_MAX_QUEUE; tc++) { 3350 u32 hw_id = 0; 3351 3352 if (rl) 3353 mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id); 3354 params->mqprio.channel.hw_id[tc] = hw_id; 3355 } 3356 } 3357 3358 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params, 3359 struct tc_mqprio_qopt_offload *mqprio, 3360 struct mlx5e_mqprio_rl *rl) 3361 { 3362 int tc; 3363 3364 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL; 3365 params->mqprio.num_tc = mqprio->qopt.num_tc; 3366 3367 for (tc = 0; tc < TC_MAX_QUEUE; tc++) 3368 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc]; 3369 3370 mlx5e_mqprio_rl_update_params(params, rl); 3371 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt); 3372 } 3373 3374 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params) 3375 { 3376 mlx5e_params_mqprio_dcb_set(params, 1); 3377 } 3378 3379 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv, 3380 struct tc_mqprio_qopt *mqprio) 3381 { 3382 struct mlx5e_params new_params; 3383 u8 tc = mqprio->num_tc; 3384 int err; 3385 3386 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 3387 3388 if (tc && tc != MLX5E_MAX_NUM_TC) 3389 return -EINVAL; 3390 3391 new_params = priv->channels.params; 3392 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1); 3393 3394 err = mlx5e_safe_switch_params(priv, &new_params, 3395 mlx5e_num_channels_changed_ctx, NULL, true); 3396 3397 if (!err && priv->mqprio_rl) { 3398 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3399 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3400 priv->mqprio_rl = NULL; 3401 } 3402 3403 priv->max_opened_tc = max_t(u8, priv->max_opened_tc, 3404 mlx5e_get_dcb_num_tc(&priv->channels.params)); 3405 return err; 3406 } 3407 3408 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv, 3409 struct tc_mqprio_qopt_offload *mqprio) 3410 { 3411 struct net_device *netdev = priv->netdev; 3412 struct mlx5e_ptp *ptp_channel; 3413 int agg_count = 0; 3414 int i; 3415 3416 ptp_channel = priv->channels.ptp; 3417 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) { 3418 netdev_err(netdev, 3419 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n"); 3420 return -EINVAL; 3421 } 3422 3423 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 || 3424 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC) 3425 return -EINVAL; 3426 3427 for (i = 0; i < mqprio->qopt.num_tc; i++) { 3428 if (!mqprio->qopt.count[i]) { 3429 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i); 3430 return -EINVAL; 3431 } 3432 if (mqprio->min_rate[i]) { 3433 netdev_err(netdev, "Min tx rate is not supported\n"); 3434 return -EINVAL; 3435 } 3436 3437 if (mqprio->max_rate[i]) { 3438 int err; 3439 3440 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]); 3441 if (err) 3442 return err; 3443 } 3444 3445 if (mqprio->qopt.offset[i] != agg_count) { 3446 netdev_err(netdev, "Discontinuous queues config is not supported\n"); 3447 return -EINVAL; 3448 } 3449 agg_count += mqprio->qopt.count[i]; 3450 } 3451 3452 if (priv->channels.params.num_channels != agg_count) { 3453 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n", 3454 agg_count, priv->channels.params.num_channels); 3455 return -EINVAL; 3456 } 3457 3458 return 0; 3459 } 3460 3461 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[]) 3462 { 3463 int tc; 3464 3465 for (tc = 0; tc < num_tc; tc++) 3466 if (max_rate[tc]) 3467 return true; 3468 return false; 3469 } 3470 3471 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev, 3472 u8 num_tc, u64 max_rate[]) 3473 { 3474 struct mlx5e_mqprio_rl *rl; 3475 int err; 3476 3477 if (!mlx5e_mqprio_rate_limit(num_tc, max_rate)) 3478 return NULL; 3479 3480 rl = mlx5e_mqprio_rl_alloc(); 3481 if (!rl) 3482 return ERR_PTR(-ENOMEM); 3483 3484 err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate); 3485 if (err) { 3486 mlx5e_mqprio_rl_free(rl); 3487 return ERR_PTR(err); 3488 } 3489 3490 return rl; 3491 } 3492 3493 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv, 3494 struct tc_mqprio_qopt_offload *mqprio) 3495 { 3496 mlx5e_fp_preactivate preactivate; 3497 struct mlx5e_params new_params; 3498 struct mlx5e_mqprio_rl *rl; 3499 bool nch_changed; 3500 int err; 3501 3502 err = mlx5e_mqprio_channel_validate(priv, mqprio); 3503 if (err) 3504 return err; 3505 3506 rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate); 3507 if (IS_ERR(rl)) 3508 return PTR_ERR(rl); 3509 3510 new_params = priv->channels.params; 3511 mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl); 3512 3513 nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1; 3514 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx : 3515 mlx5e_update_netdev_queues_ctx; 3516 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true); 3517 if (err) { 3518 if (rl) { 3519 mlx5e_mqprio_rl_cleanup(rl); 3520 mlx5e_mqprio_rl_free(rl); 3521 } 3522 return err; 3523 } 3524 3525 if (priv->mqprio_rl) { 3526 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3527 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3528 } 3529 priv->mqprio_rl = rl; 3530 3531 return 0; 3532 } 3533 3534 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, 3535 struct tc_mqprio_qopt_offload *mqprio) 3536 { 3537 /* MQPRIO is another toplevel qdisc that can't be attached 3538 * simultaneously with the offloaded HTB. 3539 */ 3540 if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq))) 3541 return -EINVAL; 3542 3543 switch (mqprio->mode) { 3544 case TC_MQPRIO_MODE_DCB: 3545 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt); 3546 case TC_MQPRIO_MODE_CHANNEL: 3547 return mlx5e_setup_tc_mqprio_channel(priv, mqprio); 3548 default: 3549 return -EOPNOTSUPP; 3550 } 3551 } 3552 3553 static LIST_HEAD(mlx5e_block_cb_list); 3554 3555 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, 3556 void *type_data) 3557 { 3558 struct mlx5e_priv *priv = netdev_priv(dev); 3559 bool tc_unbind = false; 3560 int err; 3561 3562 if (type == TC_SETUP_BLOCK && 3563 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND) 3564 tc_unbind = true; 3565 3566 if (!netif_device_present(dev) && !tc_unbind) 3567 return -ENODEV; 3568 3569 switch (type) { 3570 case TC_SETUP_BLOCK: { 3571 struct flow_block_offload *f = type_data; 3572 3573 f->unlocked_driver_cb = true; 3574 return flow_block_cb_setup_simple(type_data, 3575 &mlx5e_block_cb_list, 3576 mlx5e_setup_tc_block_cb, 3577 priv, priv, true); 3578 } 3579 case TC_SETUP_QDISC_MQPRIO: 3580 mutex_lock(&priv->state_lock); 3581 err = mlx5e_setup_tc_mqprio(priv, type_data); 3582 mutex_unlock(&priv->state_lock); 3583 return err; 3584 case TC_SETUP_QDISC_HTB: 3585 mutex_lock(&priv->state_lock); 3586 err = mlx5e_htb_setup_tc(priv, type_data); 3587 mutex_unlock(&priv->state_lock); 3588 return err; 3589 default: 3590 return -EOPNOTSUPP; 3591 } 3592 } 3593 3594 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s) 3595 { 3596 int i; 3597 3598 for (i = 0; i < priv->stats_nch; i++) { 3599 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i]; 3600 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; 3601 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 3602 int j; 3603 3604 s->rx_packets += rq_stats->packets + xskrq_stats->packets; 3605 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes; 3606 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets; 3607 3608 for (j = 0; j < priv->max_opened_tc; j++) { 3609 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 3610 3611 s->tx_packets += sq_stats->packets; 3612 s->tx_bytes += sq_stats->bytes; 3613 s->tx_dropped += sq_stats->dropped; 3614 } 3615 } 3616 if (priv->tx_ptp_opened) { 3617 for (i = 0; i < priv->max_opened_tc; i++) { 3618 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i]; 3619 3620 s->tx_packets += sq_stats->packets; 3621 s->tx_bytes += sq_stats->bytes; 3622 s->tx_dropped += sq_stats->dropped; 3623 } 3624 } 3625 if (priv->rx_ptp_opened) { 3626 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq; 3627 3628 s->rx_packets += rq_stats->packets; 3629 s->rx_bytes += rq_stats->bytes; 3630 s->multicast += rq_stats->mcast_packets; 3631 } 3632 } 3633 3634 void 3635 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 3636 { 3637 struct mlx5e_priv *priv = netdev_priv(dev); 3638 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 3639 3640 if (!netif_device_present(dev)) 3641 return; 3642 3643 /* In switchdev mode, monitor counters doesn't monitor 3644 * rx/tx stats of 802_3. The update stats mechanism 3645 * should keep the 802_3 layout counters updated 3646 */ 3647 if (!mlx5e_monitor_counter_supported(priv) || 3648 mlx5e_is_uplink_rep(priv)) { 3649 /* update HW stats in background for next time */ 3650 mlx5e_queue_update_stats(priv); 3651 } 3652 3653 if (mlx5e_is_uplink_rep(priv)) { 3654 struct mlx5e_vport_stats *vstats = &priv->stats.vport; 3655 3656 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); 3657 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); 3658 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); 3659 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); 3660 3661 /* vport multicast also counts packets that are dropped due to steering 3662 * or rx out of buffer 3663 */ 3664 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); 3665 } else { 3666 mlx5e_fold_sw_stats64(priv, stats); 3667 } 3668 3669 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; 3670 3671 stats->rx_length_errors = 3672 PPORT_802_3_GET(pstats, a_in_range_length_errors) + 3673 PPORT_802_3_GET(pstats, a_out_of_range_length_field) + 3674 PPORT_802_3_GET(pstats, a_frame_too_long_errors) + 3675 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small); 3676 stats->rx_crc_errors = 3677 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); 3678 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); 3679 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); 3680 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 3681 stats->rx_frame_errors; 3682 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; 3683 } 3684 3685 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv) 3686 { 3687 if (mlx5e_is_uplink_rep(priv)) 3688 return; /* no rx mode for uplink rep */ 3689 3690 queue_work(priv->wq, &priv->set_rx_mode_work); 3691 } 3692 3693 static void mlx5e_set_rx_mode(struct net_device *dev) 3694 { 3695 struct mlx5e_priv *priv = netdev_priv(dev); 3696 3697 mlx5e_nic_set_rx_mode(priv); 3698 } 3699 3700 static int mlx5e_set_mac(struct net_device *netdev, void *addr) 3701 { 3702 struct mlx5e_priv *priv = netdev_priv(netdev); 3703 struct sockaddr *saddr = addr; 3704 3705 if (!is_valid_ether_addr(saddr->sa_data)) 3706 return -EADDRNOTAVAIL; 3707 3708 netif_addr_lock_bh(netdev); 3709 eth_hw_addr_set(netdev, saddr->sa_data); 3710 netif_addr_unlock_bh(netdev); 3711 3712 mlx5e_nic_set_rx_mode(priv); 3713 3714 return 0; 3715 } 3716 3717 #define MLX5E_SET_FEATURE(features, feature, enable) \ 3718 do { \ 3719 if (enable) \ 3720 *features |= feature; \ 3721 else \ 3722 *features &= ~feature; \ 3723 } while (0) 3724 3725 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); 3726 3727 static int set_feature_lro(struct net_device *netdev, bool enable) 3728 { 3729 struct mlx5e_priv *priv = netdev_priv(netdev); 3730 struct mlx5_core_dev *mdev = priv->mdev; 3731 struct mlx5e_params *cur_params; 3732 struct mlx5e_params new_params; 3733 bool reset = true; 3734 int err = 0; 3735 3736 mutex_lock(&priv->state_lock); 3737 3738 cur_params = &priv->channels.params; 3739 new_params = *cur_params; 3740 3741 if (enable) 3742 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO; 3743 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO) 3744 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; 3745 else 3746 goto out; 3747 3748 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO && 3749 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) { 3750 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 3751 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) == 3752 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL)) 3753 reset = false; 3754 } 3755 } 3756 3757 err = mlx5e_safe_switch_params(priv, &new_params, 3758 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset); 3759 out: 3760 mutex_unlock(&priv->state_lock); 3761 return err; 3762 } 3763 3764 static int set_feature_hw_gro(struct net_device *netdev, bool enable) 3765 { 3766 struct mlx5e_priv *priv = netdev_priv(netdev); 3767 struct mlx5e_params new_params; 3768 bool reset = true; 3769 int err = 0; 3770 3771 mutex_lock(&priv->state_lock); 3772 new_params = priv->channels.params; 3773 3774 if (enable) { 3775 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO; 3776 new_params.packet_merge.shampo.match_criteria_type = 3777 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED; 3778 new_params.packet_merge.shampo.alignment_granularity = 3779 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE; 3780 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 3781 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; 3782 } else { 3783 goto out; 3784 } 3785 3786 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 3787 out: 3788 mutex_unlock(&priv->state_lock); 3789 return err; 3790 } 3791 3792 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) 3793 { 3794 struct mlx5e_priv *priv = netdev_priv(netdev); 3795 3796 if (enable) 3797 mlx5e_enable_cvlan_filter(priv->fs, 3798 !!(priv->netdev->flags & IFF_PROMISC)); 3799 else 3800 mlx5e_disable_cvlan_filter(priv->fs, 3801 !!(priv->netdev->flags & IFF_PROMISC)); 3802 3803 return 0; 3804 } 3805 3806 static int set_feature_hw_tc(struct net_device *netdev, bool enable) 3807 { 3808 struct mlx5e_priv *priv = netdev_priv(netdev); 3809 int err = 0; 3810 3811 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 3812 int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) : 3813 MLX5_TC_FLAG(NIC_OFFLOAD); 3814 if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) { 3815 netdev_err(netdev, 3816 "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 3817 return -EINVAL; 3818 } 3819 #endif 3820 3821 mutex_lock(&priv->state_lock); 3822 if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) { 3823 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n"); 3824 err = -EINVAL; 3825 } 3826 mutex_unlock(&priv->state_lock); 3827 3828 return err; 3829 } 3830 3831 static int set_feature_rx_all(struct net_device *netdev, bool enable) 3832 { 3833 struct mlx5e_priv *priv = netdev_priv(netdev); 3834 struct mlx5_core_dev *mdev = priv->mdev; 3835 3836 return mlx5_set_port_fcs(mdev, !enable); 3837 } 3838 3839 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable) 3840 { 3841 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {}; 3842 bool supported, curr_state; 3843 int err; 3844 3845 if (!MLX5_CAP_GEN(mdev, ports_check)) 3846 return 0; 3847 3848 err = mlx5_query_ports_check(mdev, in, sizeof(in)); 3849 if (err) 3850 return err; 3851 3852 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap); 3853 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc); 3854 3855 if (!supported || enable == curr_state) 3856 return 0; 3857 3858 MLX5_SET(pcmr_reg, in, local_port, 1); 3859 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable); 3860 3861 return mlx5_set_ports_check(mdev, in, sizeof(in)); 3862 } 3863 3864 static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx) 3865 { 3866 struct mlx5_core_dev *mdev = priv->mdev; 3867 bool enable = *(bool *)ctx; 3868 3869 return mlx5e_set_rx_port_ts(mdev, enable); 3870 } 3871 3872 static int set_feature_rx_fcs(struct net_device *netdev, bool enable) 3873 { 3874 struct mlx5e_priv *priv = netdev_priv(netdev); 3875 struct mlx5e_channels *chs = &priv->channels; 3876 struct mlx5e_params new_params; 3877 int err; 3878 3879 mutex_lock(&priv->state_lock); 3880 3881 new_params = chs->params; 3882 new_params.scatter_fcs_en = enable; 3883 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap, 3884 &new_params.scatter_fcs_en, true); 3885 mutex_unlock(&priv->state_lock); 3886 return err; 3887 } 3888 3889 static int set_feature_rx_vlan(struct net_device *netdev, bool enable) 3890 { 3891 struct mlx5e_priv *priv = netdev_priv(netdev); 3892 int err = 0; 3893 3894 mutex_lock(&priv->state_lock); 3895 3896 mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable); 3897 priv->channels.params.vlan_strip_disable = !enable; 3898 3899 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3900 goto unlock; 3901 3902 err = mlx5e_modify_channels_vsd(&priv->channels, !enable); 3903 if (err) { 3904 mlx5e_fs_set_vlan_strip_disable(priv->fs, enable); 3905 priv->channels.params.vlan_strip_disable = enable; 3906 } 3907 unlock: 3908 mutex_unlock(&priv->state_lock); 3909 3910 return err; 3911 } 3912 3913 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3914 { 3915 struct mlx5e_priv *priv = netdev_priv(dev); 3916 struct mlx5e_flow_steering *fs = priv->fs; 3917 3918 if (mlx5e_is_uplink_rep(priv)) 3919 return 0; /* no vlan table for uplink rep */ 3920 3921 return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid); 3922 } 3923 3924 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3925 { 3926 struct mlx5e_priv *priv = netdev_priv(dev); 3927 struct mlx5e_flow_steering *fs = priv->fs; 3928 3929 if (mlx5e_is_uplink_rep(priv)) 3930 return 0; /* no vlan table for uplink rep */ 3931 3932 return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid); 3933 } 3934 3935 #ifdef CONFIG_MLX5_EN_ARFS 3936 static int set_feature_arfs(struct net_device *netdev, bool enable) 3937 { 3938 struct mlx5e_priv *priv = netdev_priv(netdev); 3939 int err; 3940 3941 if (enable) 3942 err = mlx5e_arfs_enable(priv->fs); 3943 else 3944 err = mlx5e_arfs_disable(priv->fs); 3945 3946 return err; 3947 } 3948 #endif 3949 3950 static int mlx5e_handle_feature(struct net_device *netdev, 3951 netdev_features_t *features, 3952 netdev_features_t feature, 3953 mlx5e_feature_handler feature_handler) 3954 { 3955 netdev_features_t changes = *features ^ netdev->features; 3956 bool enable = !!(*features & feature); 3957 int err; 3958 3959 if (!(changes & feature)) 3960 return 0; 3961 3962 err = feature_handler(netdev, enable); 3963 if (err) { 3964 MLX5E_SET_FEATURE(features, feature, !enable); 3965 netdev_err(netdev, "%s feature %pNF failed, err %d\n", 3966 enable ? "Enable" : "Disable", &feature, err); 3967 return err; 3968 } 3969 3970 return 0; 3971 } 3972 3973 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features) 3974 { 3975 netdev_features_t oper_features = features; 3976 int err = 0; 3977 3978 #define MLX5E_HANDLE_FEATURE(feature, handler) \ 3979 mlx5e_handle_feature(netdev, &oper_features, feature, handler) 3980 3981 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); 3982 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro); 3983 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, 3984 set_feature_cvlan_filter); 3985 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc); 3986 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); 3987 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); 3988 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); 3989 #ifdef CONFIG_MLX5_EN_ARFS 3990 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); 3991 #endif 3992 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx); 3993 3994 if (err) { 3995 netdev->features = oper_features; 3996 return -EINVAL; 3997 } 3998 3999 return 0; 4000 } 4001 4002 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev, 4003 netdev_features_t features) 4004 { 4005 features &= ~NETIF_F_HW_TLS_RX; 4006 if (netdev->features & NETIF_F_HW_TLS_RX) 4007 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n"); 4008 4009 features &= ~NETIF_F_HW_TLS_TX; 4010 if (netdev->features & NETIF_F_HW_TLS_TX) 4011 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n"); 4012 4013 features &= ~NETIF_F_NTUPLE; 4014 if (netdev->features & NETIF_F_NTUPLE) 4015 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n"); 4016 4017 features &= ~NETIF_F_GRO_HW; 4018 if (netdev->features & NETIF_F_GRO_HW) 4019 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n"); 4020 4021 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4022 if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 4023 netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n"); 4024 4025 return features; 4026 } 4027 4028 static netdev_features_t mlx5e_fix_features(struct net_device *netdev, 4029 netdev_features_t features) 4030 { 4031 struct mlx5e_priv *priv = netdev_priv(netdev); 4032 struct mlx5e_vlan_table *vlan; 4033 struct mlx5e_params *params; 4034 4035 if (!netif_device_present(netdev)) 4036 return features; 4037 4038 vlan = mlx5e_fs_get_vlan(priv->fs); 4039 mutex_lock(&priv->state_lock); 4040 params = &priv->channels.params; 4041 if (!vlan || 4042 !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) { 4043 /* HW strips the outer C-tag header, this is a problem 4044 * for S-tag traffic. 4045 */ 4046 features &= ~NETIF_F_HW_VLAN_CTAG_RX; 4047 if (!params->vlan_strip_disable) 4048 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); 4049 } 4050 4051 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 4052 if (features & NETIF_F_LRO) { 4053 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); 4054 features &= ~NETIF_F_LRO; 4055 } 4056 if (features & NETIF_F_GRO_HW) { 4057 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n"); 4058 features &= ~NETIF_F_GRO_HW; 4059 } 4060 } 4061 4062 if (params->xdp_prog) { 4063 if (features & NETIF_F_LRO) { 4064 netdev_warn(netdev, "LRO is incompatible with XDP\n"); 4065 features &= ~NETIF_F_LRO; 4066 } 4067 if (features & NETIF_F_GRO_HW) { 4068 netdev_warn(netdev, "HW GRO is incompatible with XDP\n"); 4069 features &= ~NETIF_F_GRO_HW; 4070 } 4071 } 4072 4073 if (priv->xsk.refcnt) { 4074 if (features & NETIF_F_LRO) { 4075 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n", 4076 priv->xsk.refcnt); 4077 features &= ~NETIF_F_LRO; 4078 } 4079 if (features & NETIF_F_GRO_HW) { 4080 netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n", 4081 priv->xsk.refcnt); 4082 features &= ~NETIF_F_GRO_HW; 4083 } 4084 } 4085 4086 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 4087 features &= ~NETIF_F_RXHASH; 4088 if (netdev->features & NETIF_F_RXHASH) 4089 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n"); 4090 4091 if (features & NETIF_F_GRO_HW) { 4092 netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n"); 4093 features &= ~NETIF_F_GRO_HW; 4094 } 4095 } 4096 4097 if (mlx5e_is_uplink_rep(priv)) 4098 features = mlx5e_fix_uplink_rep_features(netdev, features); 4099 4100 mutex_unlock(&priv->state_lock); 4101 4102 return features; 4103 } 4104 4105 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev, 4106 struct mlx5e_channels *chs, 4107 struct mlx5e_params *new_params, 4108 struct mlx5_core_dev *mdev) 4109 { 4110 u16 ix; 4111 4112 for (ix = 0; ix < chs->params.num_channels; ix++) { 4113 struct xsk_buff_pool *xsk_pool = 4114 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); 4115 struct mlx5e_xsk_param xsk; 4116 4117 if (!xsk_pool) 4118 continue; 4119 4120 mlx5e_build_xsk_param(xsk_pool, &xsk); 4121 4122 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) { 4123 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk); 4124 int max_mtu_frame, max_mtu_page, max_mtu; 4125 4126 /* Two criteria must be met: 4127 * 1. HW MTU + all headrooms <= XSK frame size. 4128 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE. 4129 */ 4130 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr); 4131 max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0)); 4132 max_mtu = min(max_mtu_frame, max_mtu_page); 4133 4134 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n", 4135 new_params->sw_mtu, ix, max_mtu); 4136 return false; 4137 } 4138 } 4139 4140 return true; 4141 } 4142 4143 static bool mlx5e_params_validate_xdp(struct net_device *netdev, 4144 struct mlx5_core_dev *mdev, 4145 struct mlx5e_params *params) 4146 { 4147 bool is_linear; 4148 4149 /* No XSK params: AF_XDP can't be enabled yet at the point of setting 4150 * the XDP program. 4151 */ 4152 is_linear = mlx5e_rx_is_linear_skb(mdev, params, NULL); 4153 4154 if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) { 4155 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n", 4156 params->sw_mtu, 4157 mlx5e_xdp_max_mtu(params, NULL)); 4158 return false; 4159 } 4160 if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) { 4161 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n", 4162 params->sw_mtu, 4163 mlx5e_xdp_max_mtu(params, NULL)); 4164 return false; 4165 } 4166 4167 return true; 4168 } 4169 4170 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 4171 mlx5e_fp_preactivate preactivate) 4172 { 4173 struct mlx5e_priv *priv = netdev_priv(netdev); 4174 struct mlx5e_params new_params; 4175 struct mlx5e_params *params; 4176 bool reset = true; 4177 int err = 0; 4178 4179 mutex_lock(&priv->state_lock); 4180 4181 params = &priv->channels.params; 4182 4183 new_params = *params; 4184 new_params.sw_mtu = new_mtu; 4185 err = mlx5e_validate_params(priv->mdev, &new_params); 4186 if (err) 4187 goto out; 4188 4189 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev, 4190 &new_params)) { 4191 err = -EINVAL; 4192 goto out; 4193 } 4194 4195 if (priv->xsk.refcnt && 4196 !mlx5e_xsk_validate_mtu(netdev, &priv->channels, 4197 &new_params, priv->mdev)) { 4198 err = -EINVAL; 4199 goto out; 4200 } 4201 4202 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO) 4203 reset = false; 4204 4205 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && 4206 params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) { 4207 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL); 4208 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, 4209 &new_params, NULL); 4210 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL); 4211 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL); 4212 4213 /* Always reset in linear mode - hw_mtu is used in data path. 4214 * Check that the mode was non-linear and didn't change. 4215 * If XSK is active, XSK RQs are linear. 4216 * Reset if the RQ size changed, even if it's non-linear. 4217 */ 4218 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt && 4219 sz_old == sz_new) 4220 reset = false; 4221 } 4222 4223 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset); 4224 4225 out: 4226 netdev->mtu = params->sw_mtu; 4227 mutex_unlock(&priv->state_lock); 4228 return err; 4229 } 4230 4231 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) 4232 { 4233 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx); 4234 } 4235 4236 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) 4237 { 4238 bool set = *(bool *)ctx; 4239 4240 return mlx5e_ptp_rx_manage_fs(priv, set); 4241 } 4242 4243 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter) 4244 { 4245 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; 4246 int err; 4247 4248 if (!rx_filter) 4249 /* Reset CQE compression to Admin default */ 4250 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false); 4251 4252 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS)) 4253 return 0; 4254 4255 /* Disable CQE compression */ 4256 netdev_warn(priv->netdev, "Disabling RX cqe compression\n"); 4257 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true); 4258 if (err) 4259 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); 4260 4261 return err; 4262 } 4263 4264 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx) 4265 { 4266 struct mlx5e_params new_params; 4267 4268 if (ptp_rx == priv->channels.params.ptp_rx) 4269 return 0; 4270 4271 new_params = priv->channels.params; 4272 new_params.ptp_rx = ptp_rx; 4273 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 4274 &new_params.ptp_rx, true); 4275 } 4276 4277 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 4278 { 4279 struct hwtstamp_config config; 4280 bool rx_cqe_compress_def; 4281 bool ptp_rx; 4282 int err; 4283 4284 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 4285 (mlx5_clock_get_ptp_index(priv->mdev) == -1)) 4286 return -EOPNOTSUPP; 4287 4288 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 4289 return -EFAULT; 4290 4291 /* TX HW timestamp */ 4292 switch (config.tx_type) { 4293 case HWTSTAMP_TX_OFF: 4294 case HWTSTAMP_TX_ON: 4295 break; 4296 default: 4297 return -ERANGE; 4298 } 4299 4300 mutex_lock(&priv->state_lock); 4301 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; 4302 4303 /* RX HW timestamp */ 4304 switch (config.rx_filter) { 4305 case HWTSTAMP_FILTER_NONE: 4306 ptp_rx = false; 4307 break; 4308 case HWTSTAMP_FILTER_ALL: 4309 case HWTSTAMP_FILTER_SOME: 4310 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4311 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4312 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4313 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4314 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4315 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4316 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4317 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4318 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4319 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4320 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4321 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4322 case HWTSTAMP_FILTER_NTP_ALL: 4323 config.rx_filter = HWTSTAMP_FILTER_ALL; 4324 /* ptp_rx is set if both HW TS is set and CQE 4325 * compression is set 4326 */ 4327 ptp_rx = rx_cqe_compress_def; 4328 break; 4329 default: 4330 err = -ERANGE; 4331 goto err_unlock; 4332 } 4333 4334 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX)) 4335 err = mlx5e_hwstamp_config_no_ptp_rx(priv, 4336 config.rx_filter != HWTSTAMP_FILTER_NONE); 4337 else 4338 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx); 4339 if (err) 4340 goto err_unlock; 4341 4342 memcpy(&priv->tstamp, &config, sizeof(config)); 4343 mutex_unlock(&priv->state_lock); 4344 4345 /* might need to fix some features */ 4346 netdev_update_features(priv->netdev); 4347 4348 return copy_to_user(ifr->ifr_data, &config, 4349 sizeof(config)) ? -EFAULT : 0; 4350 err_unlock: 4351 mutex_unlock(&priv->state_lock); 4352 return err; 4353 } 4354 4355 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) 4356 { 4357 struct hwtstamp_config *cfg = &priv->tstamp; 4358 4359 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) 4360 return -EOPNOTSUPP; 4361 4362 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; 4363 } 4364 4365 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4366 { 4367 struct mlx5e_priv *priv = netdev_priv(dev); 4368 4369 switch (cmd) { 4370 case SIOCSHWTSTAMP: 4371 return mlx5e_hwstamp_set(priv, ifr); 4372 case SIOCGHWTSTAMP: 4373 return mlx5e_hwstamp_get(priv, ifr); 4374 default: 4375 return -EOPNOTSUPP; 4376 } 4377 } 4378 4379 #ifdef CONFIG_MLX5_ESWITCH 4380 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 4381 { 4382 struct mlx5e_priv *priv = netdev_priv(dev); 4383 struct mlx5_core_dev *mdev = priv->mdev; 4384 4385 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); 4386 } 4387 4388 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, 4389 __be16 vlan_proto) 4390 { 4391 struct mlx5e_priv *priv = netdev_priv(dev); 4392 struct mlx5_core_dev *mdev = priv->mdev; 4393 4394 if (vlan_proto != htons(ETH_P_8021Q)) 4395 return -EPROTONOSUPPORT; 4396 4397 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, 4398 vlan, qos); 4399 } 4400 4401 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) 4402 { 4403 struct mlx5e_priv *priv = netdev_priv(dev); 4404 struct mlx5_core_dev *mdev = priv->mdev; 4405 4406 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); 4407 } 4408 4409 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) 4410 { 4411 struct mlx5e_priv *priv = netdev_priv(dev); 4412 struct mlx5_core_dev *mdev = priv->mdev; 4413 4414 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); 4415 } 4416 4417 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 4418 int max_tx_rate) 4419 { 4420 struct mlx5e_priv *priv = netdev_priv(dev); 4421 struct mlx5_core_dev *mdev = priv->mdev; 4422 4423 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, 4424 max_tx_rate, min_tx_rate); 4425 } 4426 4427 static int mlx5_vport_link2ifla(u8 esw_link) 4428 { 4429 switch (esw_link) { 4430 case MLX5_VPORT_ADMIN_STATE_DOWN: 4431 return IFLA_VF_LINK_STATE_DISABLE; 4432 case MLX5_VPORT_ADMIN_STATE_UP: 4433 return IFLA_VF_LINK_STATE_ENABLE; 4434 } 4435 return IFLA_VF_LINK_STATE_AUTO; 4436 } 4437 4438 static int mlx5_ifla_link2vport(u8 ifla_link) 4439 { 4440 switch (ifla_link) { 4441 case IFLA_VF_LINK_STATE_DISABLE: 4442 return MLX5_VPORT_ADMIN_STATE_DOWN; 4443 case IFLA_VF_LINK_STATE_ENABLE: 4444 return MLX5_VPORT_ADMIN_STATE_UP; 4445 } 4446 return MLX5_VPORT_ADMIN_STATE_AUTO; 4447 } 4448 4449 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, 4450 int link_state) 4451 { 4452 struct mlx5e_priv *priv = netdev_priv(dev); 4453 struct mlx5_core_dev *mdev = priv->mdev; 4454 4455 if (mlx5e_is_uplink_rep(priv)) 4456 return -EOPNOTSUPP; 4457 4458 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, 4459 mlx5_ifla_link2vport(link_state)); 4460 } 4461 4462 int mlx5e_get_vf_config(struct net_device *dev, 4463 int vf, struct ifla_vf_info *ivi) 4464 { 4465 struct mlx5e_priv *priv = netdev_priv(dev); 4466 struct mlx5_core_dev *mdev = priv->mdev; 4467 int err; 4468 4469 if (!netif_device_present(dev)) 4470 return -EOPNOTSUPP; 4471 4472 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); 4473 if (err) 4474 return err; 4475 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); 4476 return 0; 4477 } 4478 4479 int mlx5e_get_vf_stats(struct net_device *dev, 4480 int vf, struct ifla_vf_stats *vf_stats) 4481 { 4482 struct mlx5e_priv *priv = netdev_priv(dev); 4483 struct mlx5_core_dev *mdev = priv->mdev; 4484 4485 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, 4486 vf_stats); 4487 } 4488 4489 static bool 4490 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id) 4491 { 4492 struct mlx5e_priv *priv = netdev_priv(dev); 4493 4494 if (!netif_device_present(dev)) 4495 return false; 4496 4497 if (!mlx5e_is_uplink_rep(priv)) 4498 return false; 4499 4500 return mlx5e_rep_has_offload_stats(dev, attr_id); 4501 } 4502 4503 static int 4504 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, 4505 void *sp) 4506 { 4507 struct mlx5e_priv *priv = netdev_priv(dev); 4508 4509 if (!mlx5e_is_uplink_rep(priv)) 4510 return -EOPNOTSUPP; 4511 4512 return mlx5e_rep_get_offload_stats(attr_id, dev, sp); 4513 } 4514 #endif 4515 4516 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type) 4517 { 4518 switch (proto_type) { 4519 case IPPROTO_GRE: 4520 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); 4521 case IPPROTO_IPIP: 4522 case IPPROTO_IPV6: 4523 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || 4524 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); 4525 default: 4526 return false; 4527 } 4528 } 4529 4530 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev, 4531 struct sk_buff *skb) 4532 { 4533 switch (skb->inner_protocol) { 4534 case htons(ETH_P_IP): 4535 case htons(ETH_P_IPV6): 4536 case htons(ETH_P_TEB): 4537 return true; 4538 case htons(ETH_P_MPLS_UC): 4539 case htons(ETH_P_MPLS_MC): 4540 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); 4541 } 4542 return false; 4543 } 4544 4545 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 4546 struct sk_buff *skb, 4547 netdev_features_t features) 4548 { 4549 unsigned int offset = 0; 4550 struct udphdr *udph; 4551 u8 proto; 4552 u16 port; 4553 4554 switch (vlan_get_protocol(skb)) { 4555 case htons(ETH_P_IP): 4556 proto = ip_hdr(skb)->protocol; 4557 break; 4558 case htons(ETH_P_IPV6): 4559 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); 4560 break; 4561 default: 4562 goto out; 4563 } 4564 4565 switch (proto) { 4566 case IPPROTO_GRE: 4567 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb)) 4568 return features; 4569 break; 4570 case IPPROTO_IPIP: 4571 case IPPROTO_IPV6: 4572 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP)) 4573 return features; 4574 break; 4575 case IPPROTO_UDP: 4576 udph = udp_hdr(skb); 4577 port = be16_to_cpu(udph->dest); 4578 4579 /* Verify if UDP port is being offloaded by HW */ 4580 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) 4581 return features; 4582 4583 #if IS_ENABLED(CONFIG_GENEVE) 4584 /* Support Geneve offload for default UDP port */ 4585 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev)) 4586 return features; 4587 #endif 4588 break; 4589 #ifdef CONFIG_MLX5_EN_IPSEC 4590 case IPPROTO_ESP: 4591 return mlx5e_ipsec_feature_check(skb, features); 4592 #endif 4593 } 4594 4595 out: 4596 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ 4597 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 4598 } 4599 4600 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 4601 struct net_device *netdev, 4602 netdev_features_t features) 4603 { 4604 struct mlx5e_priv *priv = netdev_priv(netdev); 4605 4606 features = vlan_features_check(skb, features); 4607 features = vxlan_features_check(skb, features); 4608 4609 /* Validate if the tunneled packet is being offloaded by HW */ 4610 if (skb->encapsulation && 4611 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) 4612 return mlx5e_tunnel_features_check(priv, skb, features); 4613 4614 return features; 4615 } 4616 4617 static void mlx5e_tx_timeout_work(struct work_struct *work) 4618 { 4619 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 4620 tx_timeout_work); 4621 struct net_device *netdev = priv->netdev; 4622 int i; 4623 4624 rtnl_lock(); 4625 mutex_lock(&priv->state_lock); 4626 4627 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 4628 goto unlock; 4629 4630 for (i = 0; i < netdev->real_num_tx_queues; i++) { 4631 struct netdev_queue *dev_queue = 4632 netdev_get_tx_queue(netdev, i); 4633 struct mlx5e_txqsq *sq = priv->txq2sq[i]; 4634 4635 if (!netif_xmit_stopped(dev_queue)) 4636 continue; 4637 4638 if (mlx5e_reporter_tx_timeout(sq)) 4639 /* break if tried to reopened channels */ 4640 break; 4641 } 4642 4643 unlock: 4644 mutex_unlock(&priv->state_lock); 4645 rtnl_unlock(); 4646 } 4647 4648 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue) 4649 { 4650 struct mlx5e_priv *priv = netdev_priv(dev); 4651 4652 netdev_err(dev, "TX timeout detected\n"); 4653 queue_work(priv->wq, &priv->tx_timeout_work); 4654 } 4655 4656 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog) 4657 { 4658 struct net_device *netdev = priv->netdev; 4659 struct mlx5e_params new_params; 4660 4661 if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) { 4662 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n"); 4663 return -EINVAL; 4664 } 4665 4666 new_params = priv->channels.params; 4667 new_params.xdp_prog = prog; 4668 4669 if (!mlx5e_params_validate_xdp(netdev, priv->mdev, &new_params)) 4670 return -EINVAL; 4671 4672 return 0; 4673 } 4674 4675 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog) 4676 { 4677 struct bpf_prog *old_prog; 4678 4679 old_prog = rcu_replace_pointer(rq->xdp_prog, prog, 4680 lockdep_is_held(&rq->priv->state_lock)); 4681 if (old_prog) 4682 bpf_prog_put(old_prog); 4683 } 4684 4685 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) 4686 { 4687 struct mlx5e_priv *priv = netdev_priv(netdev); 4688 struct mlx5e_params new_params; 4689 struct bpf_prog *old_prog; 4690 int err = 0; 4691 bool reset; 4692 int i; 4693 4694 mutex_lock(&priv->state_lock); 4695 4696 if (prog) { 4697 err = mlx5e_xdp_allowed(priv, prog); 4698 if (err) 4699 goto unlock; 4700 } 4701 4702 /* no need for full reset when exchanging programs */ 4703 reset = (!priv->channels.params.xdp_prog || !prog); 4704 4705 new_params = priv->channels.params; 4706 new_params.xdp_prog = prog; 4707 4708 /* XDP affects striding RQ parameters. Block XDP if striding RQ won't be 4709 * supported with the new parameters: if PAGE_SIZE is bigger than 4710 * MLX5_MPWQE_LOG_STRIDE_SZ_MAX, striding RQ can't be used, even though 4711 * the MTU is small enough for the linear mode, because XDP uses strides 4712 * of PAGE_SIZE on regular RQs. 4713 */ 4714 if (reset && MLX5E_GET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 4715 /* Checking for regular RQs here; XSK RQs were checked on XSK bind. */ 4716 err = mlx5e_mpwrq_validate_regular(priv->mdev, &new_params); 4717 if (err) 4718 goto unlock; 4719 } 4720 4721 old_prog = priv->channels.params.xdp_prog; 4722 4723 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 4724 if (err) 4725 goto unlock; 4726 4727 if (old_prog) 4728 bpf_prog_put(old_prog); 4729 4730 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) 4731 goto unlock; 4732 4733 /* exchanging programs w/o reset, we update ref counts on behalf 4734 * of the channels RQs here. 4735 */ 4736 bpf_prog_add(prog, priv->channels.num); 4737 for (i = 0; i < priv->channels.num; i++) { 4738 struct mlx5e_channel *c = priv->channels.c[i]; 4739 4740 mlx5e_rq_replace_xdp_prog(&c->rq, prog); 4741 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) { 4742 bpf_prog_inc(prog); 4743 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog); 4744 } 4745 } 4746 4747 unlock: 4748 mutex_unlock(&priv->state_lock); 4749 4750 /* Need to fix some features. */ 4751 if (!err) 4752 netdev_update_features(netdev); 4753 4754 return err; 4755 } 4756 4757 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4758 { 4759 switch (xdp->command) { 4760 case XDP_SETUP_PROG: 4761 return mlx5e_xdp_set(dev, xdp->prog); 4762 case XDP_SETUP_XSK_POOL: 4763 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool, 4764 xdp->xsk.queue_id); 4765 default: 4766 return -EINVAL; 4767 } 4768 } 4769 4770 #ifdef CONFIG_MLX5_ESWITCH 4771 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 4772 struct net_device *dev, u32 filter_mask, 4773 int nlflags) 4774 { 4775 struct mlx5e_priv *priv = netdev_priv(dev); 4776 struct mlx5_core_dev *mdev = priv->mdev; 4777 u8 mode, setting; 4778 int err; 4779 4780 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); 4781 if (err) 4782 return err; 4783 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; 4784 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 4785 mode, 4786 0, 0, nlflags, filter_mask, NULL); 4787 } 4788 4789 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 4790 u16 flags, struct netlink_ext_ack *extack) 4791 { 4792 struct mlx5e_priv *priv = netdev_priv(dev); 4793 struct mlx5_core_dev *mdev = priv->mdev; 4794 struct nlattr *attr, *br_spec; 4795 u16 mode = BRIDGE_MODE_UNDEF; 4796 u8 setting; 4797 int rem; 4798 4799 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 4800 if (!br_spec) 4801 return -EINVAL; 4802 4803 nla_for_each_nested(attr, br_spec, rem) { 4804 if (nla_type(attr) != IFLA_BRIDGE_MODE) 4805 continue; 4806 4807 if (nla_len(attr) < sizeof(mode)) 4808 return -EINVAL; 4809 4810 mode = nla_get_u16(attr); 4811 if (mode > BRIDGE_MODE_VEPA) 4812 return -EINVAL; 4813 4814 break; 4815 } 4816 4817 if (mode == BRIDGE_MODE_UNDEF) 4818 return -EINVAL; 4819 4820 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; 4821 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting); 4822 } 4823 #endif 4824 4825 const struct net_device_ops mlx5e_netdev_ops = { 4826 .ndo_open = mlx5e_open, 4827 .ndo_stop = mlx5e_close, 4828 .ndo_start_xmit = mlx5e_xmit, 4829 .ndo_setup_tc = mlx5e_setup_tc, 4830 .ndo_select_queue = mlx5e_select_queue, 4831 .ndo_get_stats64 = mlx5e_get_stats, 4832 .ndo_set_rx_mode = mlx5e_set_rx_mode, 4833 .ndo_set_mac_address = mlx5e_set_mac, 4834 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, 4835 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, 4836 .ndo_set_features = mlx5e_set_features, 4837 .ndo_fix_features = mlx5e_fix_features, 4838 .ndo_change_mtu = mlx5e_change_nic_mtu, 4839 .ndo_eth_ioctl = mlx5e_ioctl, 4840 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, 4841 .ndo_features_check = mlx5e_features_check, 4842 .ndo_tx_timeout = mlx5e_tx_timeout, 4843 .ndo_bpf = mlx5e_xdp, 4844 .ndo_xdp_xmit = mlx5e_xdp_xmit, 4845 .ndo_xsk_wakeup = mlx5e_xsk_wakeup, 4846 #ifdef CONFIG_MLX5_EN_ARFS 4847 .ndo_rx_flow_steer = mlx5e_rx_flow_steer, 4848 #endif 4849 #ifdef CONFIG_MLX5_ESWITCH 4850 .ndo_bridge_setlink = mlx5e_bridge_setlink, 4851 .ndo_bridge_getlink = mlx5e_bridge_getlink, 4852 4853 /* SRIOV E-Switch NDOs */ 4854 .ndo_set_vf_mac = mlx5e_set_vf_mac, 4855 .ndo_set_vf_vlan = mlx5e_set_vf_vlan, 4856 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, 4857 .ndo_set_vf_trust = mlx5e_set_vf_trust, 4858 .ndo_set_vf_rate = mlx5e_set_vf_rate, 4859 .ndo_get_vf_config = mlx5e_get_vf_config, 4860 .ndo_set_vf_link_state = mlx5e_set_vf_link_state, 4861 .ndo_get_vf_stats = mlx5e_get_vf_stats, 4862 .ndo_has_offload_stats = mlx5e_has_offload_stats, 4863 .ndo_get_offload_stats = mlx5e_get_offload_stats, 4864 #endif 4865 }; 4866 4867 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) 4868 { 4869 int i; 4870 4871 /* The supported periods are organized in ascending order */ 4872 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) 4873 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) 4874 break; 4875 4876 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); 4877 } 4878 4879 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) 4880 { 4881 struct mlx5e_params *params = &priv->channels.params; 4882 struct mlx5_core_dev *mdev = priv->mdev; 4883 u8 rx_cq_period_mode; 4884 4885 params->sw_mtu = mtu; 4886 params->hard_mtu = MLX5E_ETH_HARD_MTU; 4887 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2, 4888 priv->max_nch); 4889 mlx5e_params_mqprio_reset(params); 4890 4891 /* SQ */ 4892 params->log_sq_size = is_kdump_kernel() ? 4893 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : 4894 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 4895 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); 4896 4897 /* XDP SQ */ 4898 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); 4899 4900 /* set CQE compression */ 4901 params->rx_cqe_compress_def = false; 4902 if (MLX5_CAP_GEN(mdev, cqe_compression) && 4903 MLX5_CAP_GEN(mdev, vport_group_manager)) 4904 params->rx_cqe_compress_def = slow_pci_heuristic(mdev); 4905 4906 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); 4907 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); 4908 4909 /* RQ */ 4910 mlx5e_build_rq_params(mdev, params); 4911 4912 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); 4913 4914 /* CQ moderation params */ 4915 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 4916 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 4917 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 4918 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4919 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4920 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); 4921 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 4922 4923 /* TX inline */ 4924 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); 4925 4926 params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev); 4927 4928 /* AF_XDP */ 4929 params->xsk = xsk; 4930 4931 /* Do not update netdev->features directly in here 4932 * on mlx5e_attach_netdev() we will call mlx5e_update_features() 4933 * To update netdev->features please modify mlx5e_fix_features() 4934 */ 4935 } 4936 4937 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) 4938 { 4939 struct mlx5e_priv *priv = netdev_priv(netdev); 4940 u8 addr[ETH_ALEN]; 4941 4942 mlx5_query_mac_address(priv->mdev, addr); 4943 if (is_zero_ether_addr(addr) && 4944 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { 4945 eth_hw_addr_random(netdev); 4946 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); 4947 return; 4948 } 4949 4950 eth_hw_addr_set(netdev, addr); 4951 } 4952 4953 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table, 4954 unsigned int entry, struct udp_tunnel_info *ti) 4955 { 4956 struct mlx5e_priv *priv = netdev_priv(netdev); 4957 4958 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port)); 4959 } 4960 4961 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table, 4962 unsigned int entry, struct udp_tunnel_info *ti) 4963 { 4964 struct mlx5e_priv *priv = netdev_priv(netdev); 4965 4966 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port)); 4967 } 4968 4969 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv) 4970 { 4971 if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) 4972 return; 4973 4974 priv->nic_info.set_port = mlx5e_vxlan_set_port; 4975 priv->nic_info.unset_port = mlx5e_vxlan_unset_port; 4976 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 4977 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN; 4978 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN; 4979 /* Don't count the space hard-coded to the IANA port */ 4980 priv->nic_info.tables[0].n_entries = 4981 mlx5_vxlan_max_udp_ports(priv->mdev) - 1; 4982 4983 priv->netdev->udp_tunnel_nic_info = &priv->nic_info; 4984 } 4985 4986 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev) 4987 { 4988 int tt; 4989 4990 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) { 4991 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt))) 4992 return true; 4993 } 4994 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)); 4995 } 4996 4997 static void mlx5e_build_nic_netdev(struct net_device *netdev) 4998 { 4999 struct mlx5e_priv *priv = netdev_priv(netdev); 5000 struct mlx5_core_dev *mdev = priv->mdev; 5001 bool fcs_supported; 5002 bool fcs_enabled; 5003 5004 SET_NETDEV_DEV(netdev, mdev->device); 5005 5006 netdev->netdev_ops = &mlx5e_netdev_ops; 5007 5008 mlx5e_dcbnl_build_netdev(netdev); 5009 5010 netdev->watchdog_timeo = 15 * HZ; 5011 5012 netdev->ethtool_ops = &mlx5e_ethtool_ops; 5013 5014 netdev->vlan_features |= NETIF_F_SG; 5015 netdev->vlan_features |= NETIF_F_HW_CSUM; 5016 netdev->vlan_features |= NETIF_F_GRO; 5017 netdev->vlan_features |= NETIF_F_TSO; 5018 netdev->vlan_features |= NETIF_F_TSO6; 5019 netdev->vlan_features |= NETIF_F_RXCSUM; 5020 netdev->vlan_features |= NETIF_F_RXHASH; 5021 netdev->vlan_features |= NETIF_F_GSO_PARTIAL; 5022 5023 netdev->mpls_features |= NETIF_F_SG; 5024 netdev->mpls_features |= NETIF_F_HW_CSUM; 5025 netdev->mpls_features |= NETIF_F_TSO; 5026 netdev->mpls_features |= NETIF_F_TSO6; 5027 5028 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; 5029 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; 5030 5031 /* Tunneled LRO is not supported in the driver, and the same RQs are 5032 * shared between inner and outer TIRs, so the driver can't disable LRO 5033 * for inner TIRs while having it enabled for outer TIRs. Due to this, 5034 * block LRO altogether if the firmware declares tunneled LRO support. 5035 */ 5036 if (!!MLX5_CAP_ETH(mdev, lro_cap) && 5037 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) && 5038 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) && 5039 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT, 5040 MLX5E_MPWRQ_UMR_MODE_ALIGNED)) 5041 netdev->vlan_features |= NETIF_F_LRO; 5042 5043 netdev->hw_features = netdev->vlan_features; 5044 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 5045 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 5046 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 5047 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; 5048 5049 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) { 5050 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 5051 netdev->hw_enc_features |= NETIF_F_TSO; 5052 netdev->hw_enc_features |= NETIF_F_TSO6; 5053 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; 5054 } 5055 5056 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) { 5057 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 5058 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5059 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | 5060 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5061 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; 5062 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL | 5063 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5064 } 5065 5066 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) { 5067 netdev->hw_features |= NETIF_F_GSO_GRE | 5068 NETIF_F_GSO_GRE_CSUM; 5069 netdev->hw_enc_features |= NETIF_F_GSO_GRE | 5070 NETIF_F_GSO_GRE_CSUM; 5071 netdev->gso_partial_features |= NETIF_F_GSO_GRE | 5072 NETIF_F_GSO_GRE_CSUM; 5073 } 5074 5075 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) { 5076 netdev->hw_features |= NETIF_F_GSO_IPXIP4 | 5077 NETIF_F_GSO_IPXIP6; 5078 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 | 5079 NETIF_F_GSO_IPXIP6; 5080 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 | 5081 NETIF_F_GSO_IPXIP6; 5082 } 5083 5084 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; 5085 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 5086 netdev->features |= NETIF_F_GSO_UDP_L4; 5087 5088 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); 5089 5090 if (fcs_supported) 5091 netdev->hw_features |= NETIF_F_RXALL; 5092 5093 if (MLX5_CAP_ETH(mdev, scatter_fcs)) 5094 netdev->hw_features |= NETIF_F_RXFCS; 5095 5096 if (mlx5_qos_is_supported(mdev)) 5097 netdev->hw_features |= NETIF_F_HW_TC; 5098 5099 netdev->features = netdev->hw_features; 5100 5101 /* Defaults */ 5102 if (fcs_enabled) 5103 netdev->features &= ~NETIF_F_RXALL; 5104 netdev->features &= ~NETIF_F_LRO; 5105 netdev->features &= ~NETIF_F_GRO_HW; 5106 netdev->features &= ~NETIF_F_RXFCS; 5107 5108 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) 5109 if (FT_CAP(flow_modify_en) && 5110 FT_CAP(modify_root) && 5111 FT_CAP(identified_miss_table_mode) && 5112 FT_CAP(flow_table_modify)) { 5113 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 5114 netdev->hw_features |= NETIF_F_HW_TC; 5115 #endif 5116 #ifdef CONFIG_MLX5_EN_ARFS 5117 netdev->hw_features |= NETIF_F_NTUPLE; 5118 #endif 5119 } 5120 5121 netdev->features |= NETIF_F_HIGHDMA; 5122 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 5123 5124 netdev->priv_flags |= IFF_UNICAST_FLT; 5125 5126 netif_set_tso_max_size(netdev, GSO_MAX_SIZE); 5127 mlx5e_set_netdev_dev_addr(netdev); 5128 mlx5e_macsec_build_netdev(priv); 5129 mlx5e_ipsec_build_netdev(priv); 5130 mlx5e_ktls_build_netdev(priv); 5131 } 5132 5133 void mlx5e_create_q_counters(struct mlx5e_priv *priv) 5134 { 5135 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 5136 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 5137 struct mlx5_core_dev *mdev = priv->mdev; 5138 int err; 5139 5140 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 5141 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5142 if (!err) 5143 priv->q_counter = 5144 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5145 5146 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5147 if (!err) 5148 priv->drop_rq_q_counter = 5149 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5150 } 5151 5152 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) 5153 { 5154 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 5155 5156 MLX5_SET(dealloc_q_counter_in, in, opcode, 5157 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 5158 if (priv->q_counter) { 5159 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5160 priv->q_counter); 5161 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5162 } 5163 5164 if (priv->drop_rq_q_counter) { 5165 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5166 priv->drop_rq_q_counter); 5167 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5168 } 5169 } 5170 5171 static int mlx5e_nic_init(struct mlx5_core_dev *mdev, 5172 struct net_device *netdev) 5173 { 5174 struct mlx5e_priv *priv = netdev_priv(netdev); 5175 struct mlx5e_flow_steering *fs; 5176 int err; 5177 5178 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu); 5179 mlx5e_vxlan_set_netdev_info(priv); 5180 5181 mlx5e_timestamp_init(priv); 5182 5183 fs = mlx5e_fs_init(priv->profile, mdev, 5184 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5185 if (!fs) { 5186 err = -ENOMEM; 5187 mlx5_core_err(mdev, "FS initialization failed, %d\n", err); 5188 return err; 5189 } 5190 priv->fs = fs; 5191 5192 err = mlx5e_ktls_init(priv); 5193 if (err) 5194 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); 5195 5196 mlx5e_health_create_reporters(priv); 5197 return 0; 5198 } 5199 5200 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) 5201 { 5202 mlx5e_health_destroy_reporters(priv); 5203 mlx5e_ktls_cleanup(priv); 5204 mlx5e_fs_cleanup(priv->fs); 5205 } 5206 5207 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) 5208 { 5209 struct mlx5_core_dev *mdev = priv->mdev; 5210 enum mlx5e_rx_res_features features; 5211 int err; 5212 5213 priv->rx_res = mlx5e_rx_res_alloc(); 5214 if (!priv->rx_res) 5215 return -ENOMEM; 5216 5217 mlx5e_create_q_counters(priv); 5218 5219 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 5220 if (err) { 5221 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 5222 goto err_destroy_q_counters; 5223 } 5224 5225 features = MLX5E_RX_RES_FEATURE_PTP; 5226 if (priv->channels.params.tunneled_offload_en) 5227 features |= MLX5E_RX_RES_FEATURE_INNER_FT; 5228 err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features, 5229 priv->max_nch, priv->drop_rq.rqn, 5230 &priv->channels.params.packet_merge, 5231 priv->channels.params.num_channels); 5232 if (err) 5233 goto err_close_drop_rq; 5234 5235 err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile, 5236 priv->netdev); 5237 if (err) { 5238 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); 5239 goto err_destroy_rx_res; 5240 } 5241 5242 err = mlx5e_tc_nic_init(priv); 5243 if (err) 5244 goto err_destroy_flow_steering; 5245 5246 err = mlx5e_accel_init_rx(priv); 5247 if (err) 5248 goto err_tc_nic_cleanup; 5249 5250 #ifdef CONFIG_MLX5_EN_ARFS 5251 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev); 5252 #endif 5253 5254 return 0; 5255 5256 err_tc_nic_cleanup: 5257 mlx5e_tc_nic_cleanup(priv); 5258 err_destroy_flow_steering: 5259 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), 5260 priv->profile); 5261 err_destroy_rx_res: 5262 mlx5e_rx_res_destroy(priv->rx_res); 5263 err_close_drop_rq: 5264 mlx5e_close_drop_rq(&priv->drop_rq); 5265 err_destroy_q_counters: 5266 mlx5e_destroy_q_counters(priv); 5267 mlx5e_rx_res_free(priv->rx_res); 5268 priv->rx_res = NULL; 5269 return err; 5270 } 5271 5272 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) 5273 { 5274 mlx5e_accel_cleanup_rx(priv); 5275 mlx5e_tc_nic_cleanup(priv); 5276 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), 5277 priv->profile); 5278 mlx5e_rx_res_destroy(priv->rx_res); 5279 mlx5e_close_drop_rq(&priv->drop_rq); 5280 mlx5e_destroy_q_counters(priv); 5281 mlx5e_rx_res_free(priv->rx_res); 5282 priv->rx_res = NULL; 5283 } 5284 5285 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv) 5286 { 5287 struct mlx5e_params *params; 5288 struct mlx5e_mqprio_rl *rl; 5289 5290 params = &priv->channels.params; 5291 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) 5292 return; 5293 5294 rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc, 5295 params->mqprio.channel.max_rate); 5296 if (IS_ERR(rl)) 5297 rl = NULL; 5298 priv->mqprio_rl = rl; 5299 mlx5e_mqprio_rl_update_params(params, rl); 5300 } 5301 5302 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) 5303 { 5304 int err; 5305 5306 err = mlx5e_create_tises(priv); 5307 if (err) { 5308 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); 5309 return err; 5310 } 5311 5312 err = mlx5e_accel_init_tx(priv); 5313 if (err) 5314 goto err_destroy_tises; 5315 5316 mlx5e_set_mqprio_rl(priv); 5317 mlx5e_dcbnl_initialize(priv); 5318 return 0; 5319 5320 err_destroy_tises: 5321 mlx5e_destroy_tises(priv); 5322 return err; 5323 } 5324 5325 static void mlx5e_nic_enable(struct mlx5e_priv *priv) 5326 { 5327 struct net_device *netdev = priv->netdev; 5328 struct mlx5_core_dev *mdev = priv->mdev; 5329 int err; 5330 5331 mlx5e_fs_init_l2_addr(priv->fs, netdev); 5332 mlx5e_ipsec_init(priv); 5333 5334 err = mlx5e_macsec_init(priv); 5335 if (err) 5336 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err); 5337 5338 /* Marking the link as currently not needed by the Driver */ 5339 if (!netif_running(netdev)) 5340 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN); 5341 5342 mlx5e_set_netdev_mtu_boundaries(priv); 5343 mlx5e_set_dev_port_mtu(priv); 5344 5345 mlx5_lag_add_netdev(mdev, netdev); 5346 5347 mlx5e_enable_async_events(priv); 5348 mlx5e_enable_blocking_events(priv); 5349 if (mlx5e_monitor_counter_supported(priv)) 5350 mlx5e_monitor_counter_init(priv); 5351 5352 mlx5e_hv_vhca_stats_create(priv); 5353 if (netdev->reg_state != NETREG_REGISTERED) 5354 return; 5355 mlx5e_dcbnl_init_app(priv); 5356 5357 mlx5e_nic_set_rx_mode(priv); 5358 5359 rtnl_lock(); 5360 if (netif_running(netdev)) 5361 mlx5e_open(netdev); 5362 udp_tunnel_nic_reset_ntf(priv->netdev); 5363 netif_device_attach(netdev); 5364 rtnl_unlock(); 5365 } 5366 5367 static void mlx5e_nic_disable(struct mlx5e_priv *priv) 5368 { 5369 struct mlx5_core_dev *mdev = priv->mdev; 5370 5371 if (priv->netdev->reg_state == NETREG_REGISTERED) 5372 mlx5e_dcbnl_delete_app(priv); 5373 5374 rtnl_lock(); 5375 if (netif_running(priv->netdev)) 5376 mlx5e_close(priv->netdev); 5377 netif_device_detach(priv->netdev); 5378 rtnl_unlock(); 5379 5380 mlx5e_nic_set_rx_mode(priv); 5381 5382 mlx5e_hv_vhca_stats_destroy(priv); 5383 if (mlx5e_monitor_counter_supported(priv)) 5384 mlx5e_monitor_counter_cleanup(priv); 5385 5386 mlx5e_disable_blocking_events(priv); 5387 if (priv->en_trap) { 5388 mlx5e_deactivate_trap(priv); 5389 mlx5e_close_trap(priv->en_trap); 5390 priv->en_trap = NULL; 5391 } 5392 mlx5e_disable_async_events(priv); 5393 mlx5_lag_remove_netdev(mdev, priv->netdev); 5394 mlx5_vxlan_reset_to_default(mdev->vxlan); 5395 mlx5e_macsec_cleanup(priv); 5396 mlx5e_ipsec_cleanup(priv); 5397 } 5398 5399 int mlx5e_update_nic_rx(struct mlx5e_priv *priv) 5400 { 5401 return mlx5e_refresh_tirs(priv, false, false); 5402 } 5403 5404 static const struct mlx5e_profile mlx5e_nic_profile = { 5405 .init = mlx5e_nic_init, 5406 .cleanup = mlx5e_nic_cleanup, 5407 .init_rx = mlx5e_init_nic_rx, 5408 .cleanup_rx = mlx5e_cleanup_nic_rx, 5409 .init_tx = mlx5e_init_nic_tx, 5410 .cleanup_tx = mlx5e_cleanup_nic_tx, 5411 .enable = mlx5e_nic_enable, 5412 .disable = mlx5e_nic_disable, 5413 .update_rx = mlx5e_update_nic_rx, 5414 .update_stats = mlx5e_stats_update_ndo_stats, 5415 .update_carrier = mlx5e_update_carrier, 5416 .rx_handlers = &mlx5e_rx_handlers_nic, 5417 .max_tc = MLX5E_MAX_NUM_TC, 5418 .stats_grps = mlx5e_nic_stats_grps, 5419 .stats_grps_num = mlx5e_nic_stats_grps_num, 5420 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) | 5421 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) | 5422 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) | 5423 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) | 5424 BIT(MLX5E_PROFILE_FEATURE_FS_TC), 5425 }; 5426 5427 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev, 5428 const struct mlx5e_profile *profile) 5429 { 5430 int nch; 5431 5432 nch = mlx5e_get_max_num_channels(mdev); 5433 5434 if (profile->max_nch_limit) 5435 nch = min_t(int, nch, profile->max_nch_limit(mdev)); 5436 return nch; 5437 } 5438 5439 static unsigned int 5440 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev, 5441 const struct mlx5e_profile *profile) 5442 5443 { 5444 unsigned int max_nch, tmp; 5445 5446 /* core resources */ 5447 max_nch = mlx5e_profile_max_num_channels(mdev, profile); 5448 5449 /* netdev rx queues */ 5450 max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues); 5451 5452 /* netdev tx queues */ 5453 tmp = netdev->num_tx_queues; 5454 if (mlx5_qos_is_supported(mdev)) 5455 tmp -= mlx5e_qos_max_leaf_nodes(mdev); 5456 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 5457 tmp -= profile->max_tc; 5458 tmp = tmp / profile->max_tc; 5459 max_nch = min_t(unsigned int, max_nch, tmp); 5460 5461 return max_nch; 5462 } 5463 5464 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev) 5465 { 5466 /* Indirect TIRS: 2 sets of TTCs (inner + outer steering) 5467 * and 1 set of direct TIRS 5468 */ 5469 return 2 * MLX5E_NUM_INDIR_TIRS 5470 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile); 5471 } 5472 5473 void mlx5e_set_rx_mode_work(struct work_struct *work) 5474 { 5475 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 5476 set_rx_mode_work); 5477 5478 return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev); 5479 } 5480 5481 /* mlx5e generic netdev management API (move to en_common.c) */ 5482 int mlx5e_priv_init(struct mlx5e_priv *priv, 5483 const struct mlx5e_profile *profile, 5484 struct net_device *netdev, 5485 struct mlx5_core_dev *mdev) 5486 { 5487 int nch, num_txqs, node; 5488 int err; 5489 5490 num_txqs = netdev->num_tx_queues; 5491 nch = mlx5e_calc_max_nch(mdev, netdev, profile); 5492 node = dev_to_node(mlx5_core_dma_dev(mdev)); 5493 5494 /* priv init */ 5495 priv->mdev = mdev; 5496 priv->netdev = netdev; 5497 priv->msglevel = MLX5E_MSG_LEVEL; 5498 priv->max_nch = nch; 5499 priv->max_opened_tc = 1; 5500 5501 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL)) 5502 return -ENOMEM; 5503 5504 mutex_init(&priv->state_lock); 5505 5506 err = mlx5e_selq_init(&priv->selq, &priv->state_lock); 5507 if (err) 5508 goto err_free_cpumask; 5509 5510 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 5511 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 5512 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); 5513 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 5514 5515 priv->wq = create_singlethread_workqueue("mlx5e"); 5516 if (!priv->wq) 5517 goto err_free_selq; 5518 5519 priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node); 5520 if (!priv->txq2sq) 5521 goto err_destroy_workqueue; 5522 5523 priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node); 5524 if (!priv->tx_rates) 5525 goto err_free_txq2sq; 5526 5527 priv->channel_stats = 5528 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node); 5529 if (!priv->channel_stats) 5530 goto err_free_tx_rates; 5531 5532 return 0; 5533 5534 err_free_tx_rates: 5535 kfree(priv->tx_rates); 5536 err_free_txq2sq: 5537 kfree(priv->txq2sq); 5538 err_destroy_workqueue: 5539 destroy_workqueue(priv->wq); 5540 err_free_selq: 5541 mlx5e_selq_cleanup(&priv->selq); 5542 err_free_cpumask: 5543 free_cpumask_var(priv->scratchpad.cpumask); 5544 return -ENOMEM; 5545 } 5546 5547 void mlx5e_priv_cleanup(struct mlx5e_priv *priv) 5548 { 5549 int i; 5550 5551 /* bail if change profile failed and also rollback failed */ 5552 if (!priv->mdev) 5553 return; 5554 5555 for (i = 0; i < priv->stats_nch; i++) 5556 kvfree(priv->channel_stats[i]); 5557 kfree(priv->channel_stats); 5558 kfree(priv->tx_rates); 5559 kfree(priv->txq2sq); 5560 destroy_workqueue(priv->wq); 5561 mutex_lock(&priv->state_lock); 5562 mlx5e_selq_cleanup(&priv->selq); 5563 mutex_unlock(&priv->state_lock); 5564 free_cpumask_var(priv->scratchpad.cpumask); 5565 5566 for (i = 0; i < priv->htb_max_qos_sqs; i++) 5567 kfree(priv->htb_qos_sq_stats[i]); 5568 kvfree(priv->htb_qos_sq_stats); 5569 5570 memset(priv, 0, sizeof(*priv)); 5571 } 5572 5573 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev, 5574 const struct mlx5e_profile *profile) 5575 { 5576 unsigned int nch, ptp_txqs, qos_txqs; 5577 5578 nch = mlx5e_profile_max_num_channels(mdev, profile); 5579 5580 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) && 5581 mlx5e_profile_feature_cap(profile, PTP_TX) ? 5582 profile->max_tc : 0; 5583 5584 qos_txqs = mlx5_qos_is_supported(mdev) && 5585 mlx5e_profile_feature_cap(profile, QOS_HTB) ? 5586 mlx5e_qos_max_leaf_nodes(mdev) : 0; 5587 5588 return nch * profile->max_tc + ptp_txqs + qos_txqs; 5589 } 5590 5591 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev, 5592 const struct mlx5e_profile *profile) 5593 { 5594 return mlx5e_profile_max_num_channels(mdev, profile); 5595 } 5596 5597 struct net_device * 5598 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile) 5599 { 5600 struct net_device *netdev; 5601 unsigned int txqs, rxqs; 5602 int err; 5603 5604 txqs = mlx5e_get_max_num_txqs(mdev, profile); 5605 rxqs = mlx5e_get_max_num_rxqs(mdev, profile); 5606 5607 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs); 5608 if (!netdev) { 5609 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); 5610 return NULL; 5611 } 5612 5613 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev); 5614 if (err) { 5615 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5616 goto err_free_netdev; 5617 } 5618 5619 netif_carrier_off(netdev); 5620 netif_tx_disable(netdev); 5621 dev_net_set(netdev, mlx5_core_net(mdev)); 5622 5623 return netdev; 5624 5625 err_free_netdev: 5626 free_netdev(netdev); 5627 5628 return NULL; 5629 } 5630 5631 static void mlx5e_update_features(struct net_device *netdev) 5632 { 5633 if (netdev->reg_state != NETREG_REGISTERED) 5634 return; /* features will be updated on netdev registration */ 5635 5636 rtnl_lock(); 5637 netdev_update_features(netdev); 5638 rtnl_unlock(); 5639 } 5640 5641 static void mlx5e_reset_channels(struct net_device *netdev) 5642 { 5643 netdev_reset_tc(netdev); 5644 } 5645 5646 int mlx5e_attach_netdev(struct mlx5e_priv *priv) 5647 { 5648 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED; 5649 const struct mlx5e_profile *profile = priv->profile; 5650 int max_nch; 5651 int err; 5652 5653 clear_bit(MLX5E_STATE_DESTROYING, &priv->state); 5654 if (priv->fs) 5655 mlx5e_fs_set_state_destroy(priv->fs, 5656 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5657 5658 /* Validate the max_wqe_size_sq capability. */ 5659 if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) { 5660 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %lu\n", 5661 mlx5e_get_max_sq_wqebbs(priv->mdev), MLX5E_MAX_TX_WQEBBS); 5662 return -EIO; 5663 } 5664 5665 /* max number of channels may have changed */ 5666 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile); 5667 if (priv->channels.params.num_channels > max_nch) { 5668 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); 5669 /* Reducing the number of channels - RXFH has to be reset, and 5670 * mlx5e_num_channels_changed below will build the RQT. 5671 */ 5672 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; 5673 priv->channels.params.num_channels = max_nch; 5674 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 5675 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n"); 5676 mlx5e_params_mqprio_reset(&priv->channels.params); 5677 } 5678 } 5679 if (max_nch != priv->max_nch) { 5680 mlx5_core_warn(priv->mdev, 5681 "MLX5E: Updating max number of channels from %u to %u\n", 5682 priv->max_nch, max_nch); 5683 priv->max_nch = max_nch; 5684 } 5685 5686 /* 1. Set the real number of queues in the kernel the first time. 5687 * 2. Set our default XPS cpumask. 5688 * 3. Build the RQT. 5689 * 5690 * rtnl_lock is required by netif_set_real_num_*_queues in case the 5691 * netdev has been registered by this point (if this function was called 5692 * in the reload or resume flow). 5693 */ 5694 if (take_rtnl) 5695 rtnl_lock(); 5696 err = mlx5e_num_channels_changed(priv); 5697 if (take_rtnl) 5698 rtnl_unlock(); 5699 if (err) 5700 goto out; 5701 5702 err = profile->init_tx(priv); 5703 if (err) 5704 goto out; 5705 5706 err = profile->init_rx(priv); 5707 if (err) 5708 goto err_cleanup_tx; 5709 5710 if (profile->enable) 5711 profile->enable(priv); 5712 5713 mlx5e_update_features(priv->netdev); 5714 5715 return 0; 5716 5717 err_cleanup_tx: 5718 profile->cleanup_tx(priv); 5719 5720 out: 5721 mlx5e_reset_channels(priv->netdev); 5722 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5723 if (priv->fs) 5724 mlx5e_fs_set_state_destroy(priv->fs, 5725 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5726 cancel_work_sync(&priv->update_stats_work); 5727 return err; 5728 } 5729 5730 void mlx5e_detach_netdev(struct mlx5e_priv *priv) 5731 { 5732 const struct mlx5e_profile *profile = priv->profile; 5733 5734 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5735 if (priv->fs) 5736 mlx5e_fs_set_state_destroy(priv->fs, 5737 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5738 5739 if (profile->disable) 5740 profile->disable(priv); 5741 flush_workqueue(priv->wq); 5742 5743 profile->cleanup_rx(priv); 5744 profile->cleanup_tx(priv); 5745 mlx5e_reset_channels(priv->netdev); 5746 cancel_work_sync(&priv->update_stats_work); 5747 } 5748 5749 static int 5750 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev, 5751 const struct mlx5e_profile *new_profile, void *new_ppriv) 5752 { 5753 struct mlx5e_priv *priv = netdev_priv(netdev); 5754 int err; 5755 5756 err = mlx5e_priv_init(priv, new_profile, netdev, mdev); 5757 if (err) { 5758 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5759 return err; 5760 } 5761 netif_carrier_off(netdev); 5762 priv->profile = new_profile; 5763 priv->ppriv = new_ppriv; 5764 err = new_profile->init(priv->mdev, priv->netdev); 5765 if (err) 5766 goto priv_cleanup; 5767 err = mlx5e_attach_netdev(priv); 5768 if (err) 5769 goto profile_cleanup; 5770 return err; 5771 5772 profile_cleanup: 5773 new_profile->cleanup(priv); 5774 priv_cleanup: 5775 mlx5e_priv_cleanup(priv); 5776 return err; 5777 } 5778 5779 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 5780 const struct mlx5e_profile *new_profile, void *new_ppriv) 5781 { 5782 const struct mlx5e_profile *orig_profile = priv->profile; 5783 struct net_device *netdev = priv->netdev; 5784 struct mlx5_core_dev *mdev = priv->mdev; 5785 void *orig_ppriv = priv->ppriv; 5786 int err, rollback_err; 5787 5788 /* cleanup old profile */ 5789 mlx5e_detach_netdev(priv); 5790 priv->profile->cleanup(priv); 5791 mlx5e_priv_cleanup(priv); 5792 5793 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv); 5794 if (err) { /* roll back to original profile */ 5795 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err); 5796 goto rollback; 5797 } 5798 5799 return 0; 5800 5801 rollback: 5802 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv); 5803 if (rollback_err) 5804 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n", 5805 __func__, rollback_err); 5806 return err; 5807 } 5808 5809 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv) 5810 { 5811 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL); 5812 } 5813 5814 void mlx5e_destroy_netdev(struct mlx5e_priv *priv) 5815 { 5816 struct net_device *netdev = priv->netdev; 5817 5818 mlx5e_priv_cleanup(priv); 5819 free_netdev(netdev); 5820 } 5821 5822 static int mlx5e_resume(struct auxiliary_device *adev) 5823 { 5824 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5825 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5826 struct net_device *netdev = priv->netdev; 5827 struct mlx5_core_dev *mdev = edev->mdev; 5828 int err; 5829 5830 if (netif_device_present(netdev)) 5831 return 0; 5832 5833 err = mlx5e_create_mdev_resources(mdev); 5834 if (err) 5835 return err; 5836 5837 err = mlx5e_attach_netdev(priv); 5838 if (err) { 5839 mlx5e_destroy_mdev_resources(mdev); 5840 return err; 5841 } 5842 5843 return 0; 5844 } 5845 5846 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) 5847 { 5848 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5849 struct net_device *netdev = priv->netdev; 5850 struct mlx5_core_dev *mdev = priv->mdev; 5851 5852 if (!netif_device_present(netdev)) 5853 return -ENODEV; 5854 5855 mlx5e_detach_netdev(priv); 5856 mlx5e_destroy_mdev_resources(mdev); 5857 return 0; 5858 } 5859 5860 static int mlx5e_probe(struct auxiliary_device *adev, 5861 const struct auxiliary_device_id *id) 5862 { 5863 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5864 const struct mlx5e_profile *profile = &mlx5e_nic_profile; 5865 struct mlx5_core_dev *mdev = edev->mdev; 5866 struct net_device *netdev; 5867 pm_message_t state = {}; 5868 struct mlx5e_priv *priv; 5869 int err; 5870 5871 netdev = mlx5e_create_netdev(mdev, profile); 5872 if (!netdev) { 5873 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); 5874 return -ENOMEM; 5875 } 5876 5877 mlx5e_build_nic_netdev(netdev); 5878 5879 priv = netdev_priv(netdev); 5880 auxiliary_set_drvdata(adev, priv); 5881 5882 priv->profile = profile; 5883 priv->ppriv = NULL; 5884 5885 err = mlx5e_devlink_port_register(priv); 5886 if (err) { 5887 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err); 5888 goto err_destroy_netdev; 5889 } 5890 5891 err = profile->init(mdev, netdev); 5892 if (err) { 5893 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err); 5894 goto err_devlink_cleanup; 5895 } 5896 5897 err = mlx5e_resume(adev); 5898 if (err) { 5899 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err); 5900 goto err_profile_cleanup; 5901 } 5902 5903 SET_NETDEV_DEVLINK_PORT(netdev, mlx5e_devlink_get_dl_port(priv)); 5904 err = register_netdev(netdev); 5905 if (err) { 5906 mlx5_core_err(mdev, "register_netdev failed, %d\n", err); 5907 goto err_resume; 5908 } 5909 5910 mlx5e_dcbnl_init_app(priv); 5911 mlx5_uplink_netdev_set(mdev, netdev); 5912 mlx5e_params_print_info(mdev, &priv->channels.params); 5913 return 0; 5914 5915 err_resume: 5916 mlx5e_suspend(adev, state); 5917 err_profile_cleanup: 5918 profile->cleanup(priv); 5919 err_devlink_cleanup: 5920 mlx5e_devlink_port_unregister(priv); 5921 err_destroy_netdev: 5922 mlx5e_destroy_netdev(priv); 5923 return err; 5924 } 5925 5926 static void mlx5e_remove(struct auxiliary_device *adev) 5927 { 5928 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5929 pm_message_t state = {}; 5930 5931 mlx5e_dcbnl_delete_app(priv); 5932 unregister_netdev(priv->netdev); 5933 mlx5e_suspend(adev, state); 5934 priv->profile->cleanup(priv); 5935 mlx5e_devlink_port_unregister(priv); 5936 mlx5e_destroy_netdev(priv); 5937 } 5938 5939 static const struct auxiliary_device_id mlx5e_id_table[] = { 5940 { .name = MLX5_ADEV_NAME ".eth", }, 5941 {}, 5942 }; 5943 5944 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table); 5945 5946 static struct auxiliary_driver mlx5e_driver = { 5947 .name = "eth", 5948 .probe = mlx5e_probe, 5949 .remove = mlx5e_remove, 5950 .suspend = mlx5e_suspend, 5951 .resume = mlx5e_resume, 5952 .id_table = mlx5e_id_table, 5953 }; 5954 5955 int mlx5e_init(void) 5956 { 5957 int ret; 5958 5959 mlx5e_build_ptys2ethtool_map(); 5960 ret = auxiliary_driver_register(&mlx5e_driver); 5961 if (ret) 5962 return ret; 5963 5964 ret = mlx5e_rep_init(); 5965 if (ret) 5966 auxiliary_driver_unregister(&mlx5e_driver); 5967 return ret; 5968 } 5969 5970 void mlx5e_cleanup(void) 5971 { 5972 mlx5e_rep_cleanup(); 5973 auxiliary_driver_unregister(&mlx5e_driver); 5974 } 5975