1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/indirect_call_wrapper.h> 38 #include <net/ip6_checksum.h> 39 #include <net/page_pool.h> 40 #include <net/inet_ecn.h> 41 #include "en.h" 42 #include "en_tc.h" 43 #include "eswitch.h" 44 #include "en_rep.h" 45 #include "ipoib/ipoib.h" 46 #include "en_accel/ipsec_rxtx.h" 47 #include "en_accel/tls_rxtx.h" 48 #include "lib/clock.h" 49 #include "en/xdp.h" 50 #include "en/xsk/rx.h" 51 #include "en/health.h" 52 53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 54 { 55 return config->rx_filter == HWTSTAMP_FILTER_ALL; 56 } 57 58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq, 59 u32 cqcc, void *data) 60 { 61 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 62 63 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64)); 64 } 65 66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 67 struct mlx5_cqwq *wq, 68 u32 cqcc) 69 { 70 struct mlx5e_cq_decomp *cqd = &rq->cqd; 71 struct mlx5_cqe64 *title = &cqd->title; 72 73 mlx5e_read_cqe_slot(wq, cqcc, title); 74 cqd->left = be32_to_cpu(title->byte_cnt); 75 cqd->wqe_counter = be16_to_cpu(title->wqe_counter); 76 rq->stats->cqe_compress_blks++; 77 } 78 79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq, 80 struct mlx5e_cq_decomp *cqd, 81 u32 cqcc) 82 { 83 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr); 84 cqd->mini_arr_idx = 0; 85 } 86 87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n) 88 { 89 u32 cqcc = wq->cc; 90 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1; 91 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 92 u32 wq_sz = mlx5_cqwq_get_size(wq); 93 u32 ci_top = min_t(u32, wq_sz, ci + n); 94 95 for (; ci < ci_top; ci++, n--) { 96 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 97 98 cqe->op_own = op_own; 99 } 100 101 if (unlikely(ci == wq_sz)) { 102 op_own = !op_own; 103 for (ci = 0; ci < n; ci++) { 104 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 105 106 cqe->op_own = op_own; 107 } 108 } 109 } 110 111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 112 struct mlx5_cqwq *wq, 113 u32 cqcc) 114 { 115 struct mlx5e_cq_decomp *cqd = &rq->cqd; 116 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx]; 117 struct mlx5_cqe64 *title = &cqd->title; 118 119 title->byte_cnt = mini_cqe->byte_cnt; 120 title->check_sum = mini_cqe->checksum; 121 title->op_own &= 0xf0; 122 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz); 123 title->wqe_counter = cpu_to_be16(cqd->wqe_counter); 124 125 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 126 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title); 127 else 128 cqd->wqe_counter = 129 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1); 130 } 131 132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 133 struct mlx5_cqwq *wq, 134 u32 cqcc) 135 { 136 struct mlx5e_cq_decomp *cqd = &rq->cqd; 137 138 mlx5e_decompress_cqe(rq, wq, cqcc); 139 cqd->title.rss_hash_type = 0; 140 cqd->title.rss_hash_result = 0; 141 } 142 143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 144 struct mlx5_cqwq *wq, 145 int update_owner_only, 146 int budget_rem) 147 { 148 struct mlx5e_cq_decomp *cqd = &rq->cqd; 149 u32 cqcc = wq->cc + update_owner_only; 150 u32 cqe_count; 151 u32 i; 152 153 cqe_count = min_t(u32, cqd->left, budget_rem); 154 155 for (i = update_owner_only; i < cqe_count; 156 i++, cqd->mini_arr_idx++, cqcc++) { 157 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 158 mlx5e_read_mini_arr_slot(wq, cqd, cqcc); 159 160 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc); 161 rq->handle_rx_cqe(rq, &cqd->title); 162 } 163 mlx5e_cqes_update_owner(wq, cqcc - wq->cc); 164 wq->cc = cqcc; 165 cqd->left -= cqe_count; 166 rq->stats->cqe_compress_pkts += cqe_count; 167 168 return cqe_count; 169 } 170 171 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 172 struct mlx5_cqwq *wq, 173 int budget_rem) 174 { 175 struct mlx5e_cq_decomp *cqd = &rq->cqd; 176 u32 cc = wq->cc; 177 178 mlx5e_read_title_slot(rq, wq, cc); 179 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1); 180 mlx5e_decompress_cqe(rq, wq, cc); 181 rq->handle_rx_cqe(rq, &cqd->title); 182 cqd->mini_arr_idx++; 183 184 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1; 185 } 186 187 static inline bool mlx5e_page_is_reserved(struct page *page) 188 { 189 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 190 } 191 192 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 193 struct mlx5e_dma_info *dma_info) 194 { 195 struct mlx5e_page_cache *cache = &rq->page_cache; 196 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 197 struct mlx5e_rq_stats *stats = rq->stats; 198 199 if (tail_next == cache->head) { 200 stats->cache_full++; 201 return false; 202 } 203 204 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 205 stats->cache_waive++; 206 return false; 207 } 208 209 cache->page_cache[cache->tail] = *dma_info; 210 cache->tail = tail_next; 211 return true; 212 } 213 214 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 215 struct mlx5e_dma_info *dma_info) 216 { 217 struct mlx5e_page_cache *cache = &rq->page_cache; 218 struct mlx5e_rq_stats *stats = rq->stats; 219 220 if (unlikely(cache->head == cache->tail)) { 221 stats->cache_empty++; 222 return false; 223 } 224 225 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 226 stats->cache_busy++; 227 return false; 228 } 229 230 *dma_info = cache->page_cache[cache->head]; 231 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 232 stats->cache_reuse++; 233 234 dma_sync_single_for_device(rq->pdev, dma_info->addr, 235 PAGE_SIZE, 236 DMA_FROM_DEVICE); 237 return true; 238 } 239 240 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq, 241 struct mlx5e_dma_info *dma_info) 242 { 243 if (mlx5e_rx_cache_get(rq, dma_info)) 244 return 0; 245 246 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool); 247 if (unlikely(!dma_info->page)) 248 return -ENOMEM; 249 250 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, 251 PAGE_SIZE, rq->buff.map_dir); 252 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 253 page_pool_recycle_direct(rq->page_pool, dma_info->page); 254 dma_info->page = NULL; 255 return -ENOMEM; 256 } 257 258 return 0; 259 } 260 261 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq, 262 struct mlx5e_dma_info *dma_info) 263 { 264 if (rq->umem) 265 return mlx5e_xsk_page_alloc_umem(rq, dma_info); 266 else 267 return mlx5e_page_alloc_pool(rq, dma_info); 268 } 269 270 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info) 271 { 272 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir); 273 } 274 275 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq, 276 struct mlx5e_dma_info *dma_info, 277 bool recycle) 278 { 279 if (likely(recycle)) { 280 if (mlx5e_rx_cache_put(rq, dma_info)) 281 return; 282 283 mlx5e_page_dma_unmap(rq, dma_info); 284 page_pool_recycle_direct(rq->page_pool, dma_info->page); 285 } else { 286 mlx5e_page_dma_unmap(rq, dma_info); 287 page_pool_release_page(rq->page_pool, dma_info->page); 288 put_page(dma_info->page); 289 } 290 } 291 292 static inline void mlx5e_page_release(struct mlx5e_rq *rq, 293 struct mlx5e_dma_info *dma_info, 294 bool recycle) 295 { 296 if (rq->umem) 297 /* The `recycle` parameter is ignored, and the page is always 298 * put into the Reuse Ring, because there is no way to return 299 * the page to the userspace when the interface goes down. 300 */ 301 mlx5e_xsk_page_release(rq, dma_info); 302 else 303 mlx5e_page_release_dynamic(rq, dma_info, recycle); 304 } 305 306 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, 307 struct mlx5e_wqe_frag_info *frag) 308 { 309 int err = 0; 310 311 if (!frag->offset) 312 /* On first frag (offset == 0), replenish page (dma_info actually). 313 * Other frags that point to the same dma_info (with a different 314 * offset) should just use the new one without replenishing again 315 * by themselves. 316 */ 317 err = mlx5e_page_alloc(rq, frag->di); 318 319 return err; 320 } 321 322 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq, 323 struct mlx5e_wqe_frag_info *frag, 324 bool recycle) 325 { 326 if (frag->last_in_page) 327 mlx5e_page_release(rq, frag->di, recycle); 328 } 329 330 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix) 331 { 332 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags]; 333 } 334 335 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe, 336 u16 ix) 337 { 338 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix); 339 int err; 340 int i; 341 342 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) { 343 err = mlx5e_get_rx_frag(rq, frag); 344 if (unlikely(err)) 345 goto free_frags; 346 347 wqe->data[i].addr = cpu_to_be64(frag->di->addr + 348 frag->offset + rq->buff.headroom); 349 } 350 351 return 0; 352 353 free_frags: 354 while (--i >= 0) 355 mlx5e_put_rx_frag(rq, --frag, true); 356 357 return err; 358 } 359 360 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 361 struct mlx5e_wqe_frag_info *wi, 362 bool recycle) 363 { 364 int i; 365 366 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++) 367 mlx5e_put_rx_frag(rq, wi, recycle); 368 } 369 370 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 371 { 372 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix); 373 374 mlx5e_free_rx_wqe(rq, wi, false); 375 } 376 377 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk) 378 { 379 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 380 int err; 381 int i; 382 383 if (rq->umem) { 384 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags; 385 386 if (unlikely(!mlx5e_xsk_pages_enough_umem(rq, pages_desired))) 387 return -ENOMEM; 388 } 389 390 for (i = 0; i < wqe_bulk; i++) { 391 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i); 392 393 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i); 394 if (unlikely(err)) 395 goto free_wqes; 396 } 397 398 return 0; 399 400 free_wqes: 401 while (--i >= 0) 402 mlx5e_dealloc_rx_wqe(rq, ix + i); 403 404 return err; 405 } 406 407 static inline void 408 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb, 409 struct mlx5e_dma_info *di, u32 frag_offset, u32 len, 410 unsigned int truesize) 411 { 412 dma_sync_single_for_cpu(rq->pdev, 413 di->addr + frag_offset, 414 len, DMA_FROM_DEVICE); 415 page_ref_inc(di->page); 416 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 417 di->page, frag_offset, len, truesize); 418 } 419 420 static inline void 421 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb, 422 struct mlx5e_dma_info *dma_info, 423 int offset_from, u32 headlen) 424 { 425 const void *from = page_address(dma_info->page) + offset_from; 426 /* Aligning len to sizeof(long) optimizes memcpy performance */ 427 unsigned int len = ALIGN(headlen, sizeof(long)); 428 429 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len, 430 DMA_FROM_DEVICE); 431 skb_copy_to_linear_data(skb, from, len); 432 } 433 434 static void 435 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle) 436 { 437 bool no_xdp_xmit; 438 struct mlx5e_dma_info *dma_info = wi->umr.dma_info; 439 int i; 440 441 /* A common case for AF_XDP. */ 442 if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE)) 443 return; 444 445 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap, 446 MLX5_MPWRQ_PAGES_PER_WQE); 447 448 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) 449 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) 450 mlx5e_page_release(rq, &dma_info[i], recycle); 451 } 452 453 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n) 454 { 455 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 456 457 do { 458 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head); 459 460 mlx5_wq_ll_push(wq, next_wqe_index); 461 } while (--n); 462 463 /* ensure wqes are visible to device before updating doorbell record */ 464 dma_wmb(); 465 466 mlx5_wq_ll_update_db_record(wq); 467 } 468 469 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq, 470 struct mlx5_wq_cyc *wq, 471 u16 pi, u16 nnops) 472 { 473 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi]; 474 475 edge_wi = wi + nnops; 476 477 /* fill sq frag edge with nops to avoid wqe wrapping two pages */ 478 for (; wi < edge_wi; wi++) { 479 wi->opcode = MLX5_OPCODE_NOP; 480 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 481 } 482 } 483 484 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 485 { 486 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 487 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 488 struct mlx5e_icosq *sq = &rq->channel->icosq; 489 struct mlx5_wq_cyc *wq = &sq->wq; 490 struct mlx5e_umr_wqe *umr_wqe; 491 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1); 492 u16 pi, contig_wqebbs_room; 493 int err; 494 int i; 495 496 if (rq->umem && 497 unlikely(!mlx5e_xsk_pages_enough_umem(rq, MLX5_MPWRQ_PAGES_PER_WQE))) { 498 err = -ENOMEM; 499 goto err; 500 } 501 502 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 503 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); 504 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) { 505 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room); 506 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 507 } 508 509 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi); 510 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts)); 511 512 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 513 err = mlx5e_page_alloc(rq, dma_info); 514 if (unlikely(err)) 515 goto err_unmap; 516 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 517 } 518 519 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 520 wi->consumed_strides = 0; 521 522 umr_wqe->ctrl.opmod_idx_opcode = 523 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 524 MLX5_OPCODE_UMR); 525 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset); 526 527 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 528 sq->db.ico_wqe[pi].umr.rq = rq; 529 sq->pc += MLX5E_UMR_WQEBBS; 530 531 sq->doorbell_cseg = &umr_wqe->ctrl; 532 533 return 0; 534 535 err_unmap: 536 while (--i >= 0) { 537 dma_info--; 538 mlx5e_page_release(rq, dma_info, true); 539 } 540 541 err: 542 rq->stats->buff_alloc_err++; 543 544 return err; 545 } 546 547 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 548 { 549 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 550 /* Don't recycle, this function is called on rq/netdev close */ 551 mlx5e_free_rx_mpwqe(rq, wi, false); 552 } 553 554 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 555 { 556 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 557 u8 wqe_bulk; 558 int err; 559 560 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 561 return false; 562 563 wqe_bulk = rq->wqe.info.wqe_bulk; 564 565 if (mlx5_wq_cyc_missing(wq) < wqe_bulk) 566 return false; 567 568 do { 569 u16 head = mlx5_wq_cyc_get_head(wq); 570 571 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk); 572 if (unlikely(err)) { 573 rq->stats->buff_alloc_err++; 574 break; 575 } 576 577 mlx5_wq_cyc_push_n(wq, wqe_bulk); 578 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk); 579 580 /* ensure wqes are visible to device before updating doorbell record */ 581 dma_wmb(); 582 583 mlx5_wq_cyc_update_db_record(wq); 584 585 return !!err; 586 } 587 588 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq) 589 { 590 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 591 struct mlx5_cqe64 *cqe; 592 u16 sqcc; 593 int i; 594 595 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) 596 return; 597 598 cqe = mlx5_cqwq_get_cqe(&cq->wq); 599 if (likely(!cqe)) 600 return; 601 602 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 603 * otherwise a cq overrun may occur 604 */ 605 sqcc = sq->cc; 606 607 i = 0; 608 do { 609 u16 wqe_counter; 610 bool last_wqe; 611 612 mlx5_cqwq_pop(&cq->wq); 613 614 wqe_counter = be16_to_cpu(cqe->wqe_counter); 615 616 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) { 617 netdev_WARN_ONCE(cq->channel->netdev, 618 "Bad OP in ICOSQ CQE: 0x%x\n", get_cqe_opcode(cqe)); 619 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) 620 queue_work(cq->channel->priv->wq, &sq->recover_work); 621 break; 622 } 623 do { 624 struct mlx5e_sq_wqe_info *wi; 625 u16 ci; 626 627 last_wqe = (sqcc == wqe_counter); 628 629 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); 630 wi = &sq->db.ico_wqe[ci]; 631 632 if (likely(wi->opcode == MLX5_OPCODE_UMR)) { 633 sqcc += MLX5E_UMR_WQEBBS; 634 wi->umr.rq->mpwqe.umr_completed++; 635 } else if (likely(wi->opcode == MLX5_OPCODE_NOP)) { 636 sqcc++; 637 } else { 638 netdev_WARN_ONCE(cq->channel->netdev, 639 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", 640 wi->opcode); 641 } 642 643 } while (!last_wqe); 644 645 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 646 647 sq->cc = sqcc; 648 649 mlx5_cqwq_update_db_record(&cq->wq); 650 } 651 652 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 653 { 654 struct mlx5e_icosq *sq = &rq->channel->icosq; 655 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 656 u8 umr_completed = rq->mpwqe.umr_completed; 657 int alloc_err = 0; 658 u8 missing, i; 659 u16 head; 660 661 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 662 return false; 663 664 if (umr_completed) { 665 mlx5e_post_rx_mpwqe(rq, umr_completed); 666 rq->mpwqe.umr_in_progress -= umr_completed; 667 rq->mpwqe.umr_completed = 0; 668 } 669 670 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress; 671 672 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk)) 673 rq->stats->congst_umr++; 674 675 #define UMR_WQE_BULK (2) 676 if (likely(missing < UMR_WQE_BULK)) 677 return false; 678 679 head = rq->mpwqe.actual_wq_head; 680 i = missing; 681 do { 682 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head); 683 684 if (unlikely(alloc_err)) 685 break; 686 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 687 } while (--i); 688 689 rq->mpwqe.umr_last_bulk = missing - i; 690 if (sq->doorbell_cseg) { 691 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg); 692 sq->doorbell_cseg = NULL; 693 } 694 695 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk; 696 rq->mpwqe.actual_wq_head = head; 697 698 /* If XSK Fill Ring doesn't have enough frames, report the error, so 699 * that one of the actions can be performed: 700 * 1. If need_wakeup is used, signal that the application has to kick 701 * the driver when it refills the Fill Ring. 702 * 2. Otherwise, busy poll by rescheduling the NAPI poll. 703 */ 704 if (unlikely(alloc_err == -ENOMEM && rq->umem)) 705 return true; 706 707 return false; 708 } 709 710 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) 711 { 712 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 713 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 714 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 715 716 tcp->check = 0; 717 tcp->psh = get_cqe_lro_tcppsh(cqe); 718 719 if (tcp_ack) { 720 tcp->ack = 1; 721 tcp->ack_seq = cqe->lro_ack_seq_num; 722 tcp->window = cqe->lro_tcp_win; 723 } 724 } 725 726 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 727 u32 cqe_bcnt) 728 { 729 struct ethhdr *eth = (struct ethhdr *)(skb->data); 730 struct tcphdr *tcp; 731 int network_depth = 0; 732 __wsum check; 733 __be16 proto; 734 u16 tot_len; 735 void *ip_p; 736 737 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 738 739 tot_len = cqe_bcnt - network_depth; 740 ip_p = skb->data + network_depth; 741 742 if (proto == htons(ETH_P_IP)) { 743 struct iphdr *ipv4 = ip_p; 744 745 tcp = ip_p + sizeof(struct iphdr); 746 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 747 748 ipv4->ttl = cqe->lro_min_ttl; 749 ipv4->tot_len = cpu_to_be16(tot_len); 750 ipv4->check = 0; 751 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 752 ipv4->ihl); 753 754 mlx5e_lro_update_tcp_hdr(cqe, tcp); 755 check = csum_partial(tcp, tcp->doff * 4, 756 csum_unfold((__force __sum16)cqe->check_sum)); 757 /* Almost done, don't forget the pseudo header */ 758 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, 759 tot_len - sizeof(struct iphdr), 760 IPPROTO_TCP, check); 761 } else { 762 u16 payload_len = tot_len - sizeof(struct ipv6hdr); 763 struct ipv6hdr *ipv6 = ip_p; 764 765 tcp = ip_p + sizeof(struct ipv6hdr); 766 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 767 768 ipv6->hop_limit = cqe->lro_min_ttl; 769 ipv6->payload_len = cpu_to_be16(payload_len); 770 771 mlx5e_lro_update_tcp_hdr(cqe, tcp); 772 check = csum_partial(tcp, tcp->doff * 4, 773 csum_unfold((__force __sum16)cqe->check_sum)); 774 /* Almost done, don't forget the pseudo header */ 775 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, 776 IPPROTO_TCP, check); 777 } 778 } 779 780 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 781 struct sk_buff *skb) 782 { 783 u8 cht = cqe->rss_hash_type; 784 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 785 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 786 PKT_HASH_TYPE_NONE; 787 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 788 } 789 790 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth, 791 __be16 *proto) 792 { 793 *proto = ((struct ethhdr *)skb->data)->h_proto; 794 *proto = __vlan_get_protocol(skb, *proto, network_depth); 795 796 if (*proto == htons(ETH_P_IP)) 797 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr)); 798 799 if (*proto == htons(ETH_P_IPV6)) 800 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr)); 801 802 return false; 803 } 804 805 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb) 806 { 807 int network_depth = 0; 808 __be16 proto; 809 void *ip; 810 int rc; 811 812 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto))) 813 return; 814 815 ip = skb->data + network_depth; 816 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) : 817 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip)); 818 819 rq->stats->ecn_mark += !!rc; 820 } 821 822 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto) 823 { 824 void *ip_p = skb->data + network_depth; 825 826 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol : 827 ((struct ipv6hdr *)ip_p)->nexthdr; 828 } 829 830 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN) 831 832 #define MAX_PADDING 8 833 834 static void 835 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len, 836 struct mlx5e_rq_stats *stats) 837 { 838 stats->csum_complete_tail_slow++; 839 skb->csum = csum_block_add(skb->csum, 840 skb_checksum(skb, offset, len, 0), 841 offset); 842 } 843 844 static void 845 tail_padding_csum(struct sk_buff *skb, int offset, 846 struct mlx5e_rq_stats *stats) 847 { 848 u8 tail_padding[MAX_PADDING]; 849 int len = skb->len - offset; 850 void *tail; 851 852 if (unlikely(len > MAX_PADDING)) { 853 tail_padding_csum_slow(skb, offset, len, stats); 854 return; 855 } 856 857 tail = skb_header_pointer(skb, offset, len, tail_padding); 858 if (unlikely(!tail)) { 859 tail_padding_csum_slow(skb, offset, len, stats); 860 return; 861 } 862 863 stats->csum_complete_tail++; 864 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset); 865 } 866 867 static void 868 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto, 869 struct mlx5e_rq_stats *stats) 870 { 871 struct ipv6hdr *ip6; 872 struct iphdr *ip4; 873 int pkt_len; 874 875 /* Fixup vlan headers, if any */ 876 if (network_depth > ETH_HLEN) 877 /* CQE csum is calculated from the IP header and does 878 * not cover VLAN headers (if present). This will add 879 * the checksum manually. 880 */ 881 skb->csum = csum_partial(skb->data + ETH_HLEN, 882 network_depth - ETH_HLEN, 883 skb->csum); 884 885 /* Fixup tail padding, if any */ 886 switch (proto) { 887 case htons(ETH_P_IP): 888 ip4 = (struct iphdr *)(skb->data + network_depth); 889 pkt_len = network_depth + ntohs(ip4->tot_len); 890 break; 891 case htons(ETH_P_IPV6): 892 ip6 = (struct ipv6hdr *)(skb->data + network_depth); 893 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len); 894 break; 895 default: 896 return; 897 } 898 899 if (likely(pkt_len >= skb->len)) 900 return; 901 902 tail_padding_csum(skb, pkt_len, stats); 903 } 904 905 static inline void mlx5e_handle_csum(struct net_device *netdev, 906 struct mlx5_cqe64 *cqe, 907 struct mlx5e_rq *rq, 908 struct sk_buff *skb, 909 bool lro) 910 { 911 struct mlx5e_rq_stats *stats = rq->stats; 912 int network_depth = 0; 913 __be16 proto; 914 915 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 916 goto csum_none; 917 918 if (lro) { 919 skb->ip_summed = CHECKSUM_UNNECESSARY; 920 stats->csum_unnecessary++; 921 return; 922 } 923 924 /* True when explicitly set via priv flag, or XDP prog is loaded */ 925 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state)) 926 goto csum_unnecessary; 927 928 /* CQE csum doesn't cover padding octets in short ethernet 929 * frames. And the pad field is appended prior to calculating 930 * and appending the FCS field. 931 * 932 * Detecting these padded frames requires to verify and parse 933 * IP headers, so we simply force all those small frames to be 934 * CHECKSUM_UNNECESSARY even if they are not padded. 935 */ 936 if (short_frame(skb->len)) 937 goto csum_unnecessary; 938 939 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) { 940 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP)) 941 goto csum_unnecessary; 942 943 stats->csum_complete++; 944 skb->ip_summed = CHECKSUM_COMPLETE; 945 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 946 947 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state)) 948 return; /* CQE csum covers all received bytes */ 949 950 /* csum might need some fixups ...*/ 951 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats); 952 return; 953 } 954 955 csum_unnecessary: 956 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 957 (cqe->hds_ip_ext & CQE_L4_OK))) { 958 skb->ip_summed = CHECKSUM_UNNECESSARY; 959 if (cqe_is_tunneled(cqe)) { 960 skb->csum_level = 1; 961 skb->encapsulation = 1; 962 stats->csum_unnecessary_inner++; 963 return; 964 } 965 stats->csum_unnecessary++; 966 return; 967 } 968 csum_none: 969 skb->ip_summed = CHECKSUM_NONE; 970 stats->csum_none++; 971 } 972 973 #define MLX5E_CE_BIT_MASK 0x80 974 975 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 976 u32 cqe_bcnt, 977 struct mlx5e_rq *rq, 978 struct sk_buff *skb) 979 { 980 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 981 struct mlx5e_rq_stats *stats = rq->stats; 982 struct net_device *netdev = rq->netdev; 983 984 skb->mac_len = ETH_HLEN; 985 986 #ifdef CONFIG_MLX5_EN_TLS 987 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt); 988 #endif 989 990 if (lro_num_seg > 1) { 991 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 992 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 993 /* Subtract one since we already counted this as one 994 * "regular" packet in mlx5e_complete_rx_cqe() 995 */ 996 stats->packets += lro_num_seg - 1; 997 stats->lro_packets++; 998 stats->lro_bytes += cqe_bcnt; 999 } 1000 1001 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 1002 skb_hwtstamps(skb)->hwtstamp = 1003 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1004 1005 skb_record_rx_queue(skb, rq->ix); 1006 1007 if (likely(netdev->features & NETIF_F_RXHASH)) 1008 mlx5e_skb_set_hash(cqe, skb); 1009 1010 if (cqe_has_vlan(cqe)) { 1011 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1012 be16_to_cpu(cqe->vlan_info)); 1013 stats->removed_vlan_packets++; 1014 } 1015 1016 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 1017 1018 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 1019 /* checking CE bit in cqe - MSB in ml_path field */ 1020 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK)) 1021 mlx5e_enable_ecn(rq, skb); 1022 1023 skb->protocol = eth_type_trans(skb, netdev); 1024 } 1025 1026 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 1027 struct mlx5_cqe64 *cqe, 1028 u32 cqe_bcnt, 1029 struct sk_buff *skb) 1030 { 1031 struct mlx5e_rq_stats *stats = rq->stats; 1032 1033 stats->packets++; 1034 stats->bytes += cqe_bcnt; 1035 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 1036 } 1037 1038 static inline 1039 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, 1040 u32 frag_size, u16 headroom, 1041 u32 cqe_bcnt) 1042 { 1043 struct sk_buff *skb = build_skb(va, frag_size); 1044 1045 if (unlikely(!skb)) { 1046 rq->stats->buff_alloc_err++; 1047 return NULL; 1048 } 1049 1050 skb_reserve(skb, headroom); 1051 skb_put(skb, cqe_bcnt); 1052 1053 return skb; 1054 } 1055 1056 struct sk_buff * 1057 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 1058 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 1059 { 1060 struct mlx5e_dma_info *di = wi->di; 1061 u16 rx_headroom = rq->buff.headroom; 1062 struct sk_buff *skb; 1063 void *va, *data; 1064 bool consumed; 1065 u32 frag_size; 1066 1067 va = page_address(di->page) + wi->offset; 1068 data = va + rx_headroom; 1069 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1070 1071 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, 1072 frag_size, DMA_FROM_DEVICE); 1073 prefetchw(va); /* xdp_frame data area */ 1074 prefetch(data); 1075 1076 rcu_read_lock(); 1077 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt, false); 1078 rcu_read_unlock(); 1079 if (consumed) 1080 return NULL; /* page/packet was consumed by XDP */ 1081 1082 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); 1083 if (unlikely(!skb)) 1084 return NULL; 1085 1086 /* queue up for recycling/reuse */ 1087 page_ref_inc(di->page); 1088 1089 return skb; 1090 } 1091 1092 struct sk_buff * 1093 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 1094 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 1095 { 1096 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 1097 struct mlx5e_wqe_frag_info *head_wi = wi; 1098 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt); 1099 u16 frag_headlen = headlen; 1100 u16 byte_cnt = cqe_bcnt - headlen; 1101 struct sk_buff *skb; 1102 1103 /* XDP is not supported in this configuration, as incoming packets 1104 * might spread among multiple pages. 1105 */ 1106 skb = napi_alloc_skb(rq->cq.napi, 1107 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); 1108 if (unlikely(!skb)) { 1109 rq->stats->buff_alloc_err++; 1110 return NULL; 1111 } 1112 1113 prefetchw(skb->data); 1114 1115 while (byte_cnt) { 1116 u16 frag_consumed_bytes = 1117 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt); 1118 1119 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen, 1120 frag_consumed_bytes, frag_info->frag_stride); 1121 byte_cnt -= frag_consumed_bytes; 1122 frag_headlen = 0; 1123 frag_info++; 1124 wi++; 1125 } 1126 1127 /* copy header */ 1128 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen); 1129 /* skb linear part was allocated with headlen and aligned to long */ 1130 skb->tail += headlen; 1131 skb->len += headlen; 1132 1133 return skb; 1134 } 1135 1136 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1137 { 1138 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe; 1139 1140 if (cqe_syndrome_needs_recover(err_cqe->syndrome) && 1141 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) 1142 queue_work(rq->channel->priv->wq, &rq->recover_work); 1143 } 1144 1145 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1146 { 1147 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1148 struct mlx5e_wqe_frag_info *wi; 1149 struct sk_buff *skb; 1150 u32 cqe_bcnt; 1151 u16 ci; 1152 1153 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1154 wi = get_frag(rq, ci); 1155 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1156 1157 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1158 trigger_report(rq, cqe); 1159 rq->stats->wqe_err++; 1160 goto free_wqe; 1161 } 1162 1163 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe, 1164 mlx5e_skb_from_cqe_linear, 1165 mlx5e_skb_from_cqe_nonlinear, 1166 rq, cqe, wi, cqe_bcnt); 1167 if (!skb) { 1168 /* probably for XDP */ 1169 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1170 /* do not return page to cache, 1171 * it will be returned on XDP_TX completion. 1172 */ 1173 goto wq_cyc_pop; 1174 } 1175 goto free_wqe; 1176 } 1177 1178 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1179 napi_gro_receive(rq->cq.napi, skb); 1180 1181 free_wqe: 1182 mlx5e_free_rx_wqe(rq, wi, true); 1183 wq_cyc_pop: 1184 mlx5_wq_cyc_pop(wq); 1185 } 1186 1187 #ifdef CONFIG_MLX5_ESWITCH 1188 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1189 { 1190 struct net_device *netdev = rq->netdev; 1191 struct mlx5e_priv *priv = netdev_priv(netdev); 1192 struct mlx5e_rep_priv *rpriv = priv->ppriv; 1193 struct mlx5_eswitch_rep *rep = rpriv->rep; 1194 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1195 struct mlx5e_wqe_frag_info *wi; 1196 struct sk_buff *skb; 1197 u32 cqe_bcnt; 1198 u16 ci; 1199 1200 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1201 wi = get_frag(rq, ci); 1202 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1203 1204 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1205 rq->stats->wqe_err++; 1206 goto free_wqe; 1207 } 1208 1209 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1210 if (!skb) { 1211 /* probably for XDP */ 1212 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1213 /* do not return page to cache, 1214 * it will be returned on XDP_TX completion. 1215 */ 1216 goto wq_cyc_pop; 1217 } 1218 goto free_wqe; 1219 } 1220 1221 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1222 1223 if (rep->vlan && skb_vlan_tag_present(skb)) 1224 skb_vlan_pop(skb); 1225 1226 napi_gro_receive(rq->cq.napi, skb); 1227 1228 free_wqe: 1229 mlx5e_free_rx_wqe(rq, wi, true); 1230 wq_cyc_pop: 1231 mlx5_wq_cyc_pop(wq); 1232 } 1233 #endif 1234 1235 struct sk_buff * 1236 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1237 u16 cqe_bcnt, u32 head_offset, u32 page_idx) 1238 { 1239 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); 1240 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; 1241 u32 frag_offset = head_offset + headlen; 1242 u32 byte_cnt = cqe_bcnt - headlen; 1243 struct mlx5e_dma_info *head_di = di; 1244 struct sk_buff *skb; 1245 1246 skb = napi_alloc_skb(rq->cq.napi, 1247 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); 1248 if (unlikely(!skb)) { 1249 rq->stats->buff_alloc_err++; 1250 return NULL; 1251 } 1252 1253 prefetchw(skb->data); 1254 1255 if (unlikely(frag_offset >= PAGE_SIZE)) { 1256 di++; 1257 frag_offset -= PAGE_SIZE; 1258 } 1259 1260 while (byte_cnt) { 1261 u32 pg_consumed_bytes = 1262 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 1263 unsigned int truesize = 1264 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); 1265 1266 mlx5e_add_skb_frag(rq, skb, di, frag_offset, 1267 pg_consumed_bytes, truesize); 1268 byte_cnt -= pg_consumed_bytes; 1269 frag_offset = 0; 1270 di++; 1271 } 1272 /* copy header */ 1273 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen); 1274 /* skb linear part was allocated with headlen and aligned to long */ 1275 skb->tail += headlen; 1276 skb->len += headlen; 1277 1278 return skb; 1279 } 1280 1281 struct sk_buff * 1282 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1283 u16 cqe_bcnt, u32 head_offset, u32 page_idx) 1284 { 1285 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; 1286 u16 rx_headroom = rq->buff.headroom; 1287 u32 cqe_bcnt32 = cqe_bcnt; 1288 struct sk_buff *skb; 1289 void *va, *data; 1290 u32 frag_size; 1291 bool consumed; 1292 1293 /* Check packet size. Note LRO doesn't use linear SKB */ 1294 if (unlikely(cqe_bcnt > rq->hw_mtu)) { 1295 rq->stats->oversize_pkts_sw_drop++; 1296 return NULL; 1297 } 1298 1299 va = page_address(di->page) + head_offset; 1300 data = va + rx_headroom; 1301 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32); 1302 1303 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset, 1304 frag_size, DMA_FROM_DEVICE); 1305 prefetchw(va); /* xdp_frame data area */ 1306 prefetch(data); 1307 1308 rcu_read_lock(); 1309 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32, false); 1310 rcu_read_unlock(); 1311 if (consumed) { 1312 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) 1313 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */ 1314 return NULL; /* page/packet was consumed by XDP */ 1315 } 1316 1317 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32); 1318 if (unlikely(!skb)) 1319 return NULL; 1320 1321 /* queue up for recycling/reuse */ 1322 page_ref_inc(di->page); 1323 1324 return skb; 1325 } 1326 1327 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1328 { 1329 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1330 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1331 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1332 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 1333 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 1334 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 1335 u32 page_idx = wqe_offset >> PAGE_SHIFT; 1336 struct mlx5e_rx_wqe_ll *wqe; 1337 struct mlx5_wq_ll *wq; 1338 struct sk_buff *skb; 1339 u16 cqe_bcnt; 1340 1341 wi->consumed_strides += cstrides; 1342 1343 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1344 trigger_report(rq, cqe); 1345 rq->stats->wqe_err++; 1346 goto mpwrq_cqe_out; 1347 } 1348 1349 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1350 struct mlx5e_rq_stats *stats = rq->stats; 1351 1352 stats->mpwqe_filler_cqes++; 1353 stats->mpwqe_filler_strides += cstrides; 1354 goto mpwrq_cqe_out; 1355 } 1356 1357 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1358 1359 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq, 1360 mlx5e_skb_from_cqe_mpwrq_linear, 1361 mlx5e_skb_from_cqe_mpwrq_nonlinear, 1362 rq, wi, cqe_bcnt, head_offset, page_idx); 1363 if (!skb) 1364 goto mpwrq_cqe_out; 1365 1366 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1367 napi_gro_receive(rq->cq.napi, skb); 1368 1369 mpwrq_cqe_out: 1370 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1371 return; 1372 1373 wq = &rq->mpwqe.wq; 1374 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id); 1375 mlx5e_free_rx_mpwqe(rq, wi, true); 1376 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1377 } 1378 1379 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1380 { 1381 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1382 struct mlx5_cqwq *cqwq = &cq->wq; 1383 struct mlx5_cqe64 *cqe; 1384 int work_done = 0; 1385 1386 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 1387 return 0; 1388 1389 if (rq->page_pool) 1390 page_pool_nid_changed(rq->page_pool, numa_mem_id()); 1391 1392 if (rq->cqd.left) { 1393 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget); 1394 if (rq->cqd.left || work_done >= budget) 1395 goto out; 1396 } 1397 1398 cqe = mlx5_cqwq_get_cqe(cqwq); 1399 if (!cqe) { 1400 if (unlikely(work_done)) 1401 goto out; 1402 return 0; 1403 } 1404 1405 do { 1406 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1407 work_done += 1408 mlx5e_decompress_cqes_start(rq, cqwq, 1409 budget - work_done); 1410 continue; 1411 } 1412 1413 mlx5_cqwq_pop(cqwq); 1414 1415 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 1416 mlx5e_handle_rx_cqe, rq, cqe); 1417 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq))); 1418 1419 out: 1420 if (rq->xdp_prog) 1421 mlx5e_xdp_rx_poll_complete(rq); 1422 1423 mlx5_cqwq_update_db_record(cqwq); 1424 1425 /* ensure cq space is freed before enabling more cqes */ 1426 wmb(); 1427 1428 return work_done; 1429 } 1430 1431 #ifdef CONFIG_MLX5_CORE_IPOIB 1432 1433 #define MLX5_IB_GRH_DGID_OFFSET 24 1434 #define MLX5_GID_SIZE 16 1435 1436 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1437 struct mlx5_cqe64 *cqe, 1438 u32 cqe_bcnt, 1439 struct sk_buff *skb) 1440 { 1441 struct hwtstamp_config *tstamp; 1442 struct mlx5e_rq_stats *stats; 1443 struct net_device *netdev; 1444 struct mlx5e_priv *priv; 1445 char *pseudo_header; 1446 u32 qpn; 1447 u8 *dgid; 1448 u8 g; 1449 1450 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1451 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1452 1453 /* No mapping present, cannot process SKB. This might happen if a child 1454 * interface is going down while having unprocessed CQEs on parent RQ 1455 */ 1456 if (unlikely(!netdev)) { 1457 /* TODO: add drop counters support */ 1458 skb->dev = NULL; 1459 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1460 return; 1461 } 1462 1463 priv = mlx5i_epriv(netdev); 1464 tstamp = &priv->tstamp; 1465 stats = &priv->channel_stats[rq->ix].rq; 1466 1467 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1468 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1469 if ((!g) || dgid[0] != 0xff) 1470 skb->pkt_type = PACKET_HOST; 1471 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1472 skb->pkt_type = PACKET_BROADCAST; 1473 else 1474 skb->pkt_type = PACKET_MULTICAST; 1475 1476 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1477 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1478 */ 1479 1480 skb_pull(skb, MLX5_IB_GRH_BYTES); 1481 1482 skb->protocol = *((__be16 *)(skb->data)); 1483 1484 if (netdev->features & NETIF_F_RXCSUM) { 1485 skb->ip_summed = CHECKSUM_COMPLETE; 1486 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1487 stats->csum_complete++; 1488 } else { 1489 skb->ip_summed = CHECKSUM_NONE; 1490 stats->csum_none++; 1491 } 1492 1493 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1494 skb_hwtstamps(skb)->hwtstamp = 1495 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1496 1497 skb_record_rx_queue(skb, rq->ix); 1498 1499 if (likely(netdev->features & NETIF_F_RXHASH)) 1500 mlx5e_skb_set_hash(cqe, skb); 1501 1502 /* 20 bytes of ipoib header and 4 for encap existing */ 1503 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1504 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1505 skb_reset_mac_header(skb); 1506 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1507 1508 skb->dev = netdev; 1509 1510 stats->packets++; 1511 stats->bytes += cqe_bcnt; 1512 } 1513 1514 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1515 { 1516 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1517 struct mlx5e_wqe_frag_info *wi; 1518 struct sk_buff *skb; 1519 u32 cqe_bcnt; 1520 u16 ci; 1521 1522 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1523 wi = get_frag(rq, ci); 1524 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1525 1526 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1527 rq->stats->wqe_err++; 1528 goto wq_free_wqe; 1529 } 1530 1531 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe, 1532 mlx5e_skb_from_cqe_linear, 1533 mlx5e_skb_from_cqe_nonlinear, 1534 rq, cqe, wi, cqe_bcnt); 1535 if (!skb) 1536 goto wq_free_wqe; 1537 1538 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1539 if (unlikely(!skb->dev)) { 1540 dev_kfree_skb_any(skb); 1541 goto wq_free_wqe; 1542 } 1543 napi_gro_receive(rq->cq.napi, skb); 1544 1545 wq_free_wqe: 1546 mlx5e_free_rx_wqe(rq, wi, true); 1547 mlx5_wq_cyc_pop(wq); 1548 } 1549 1550 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1551 1552 #ifdef CONFIG_MLX5_EN_IPSEC 1553 1554 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1555 { 1556 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1557 struct mlx5e_wqe_frag_info *wi; 1558 struct sk_buff *skb; 1559 u32 cqe_bcnt; 1560 u16 ci; 1561 1562 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1563 wi = get_frag(rq, ci); 1564 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1565 1566 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1567 rq->stats->wqe_err++; 1568 goto wq_free_wqe; 1569 } 1570 1571 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe, 1572 mlx5e_skb_from_cqe_linear, 1573 mlx5e_skb_from_cqe_nonlinear, 1574 rq, cqe, wi, cqe_bcnt); 1575 if (unlikely(!skb)) /* a DROP, save the page-reuse checks */ 1576 goto wq_free_wqe; 1577 1578 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt); 1579 if (unlikely(!skb)) 1580 goto wq_free_wqe; 1581 1582 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1583 napi_gro_receive(rq->cq.napi, skb); 1584 1585 wq_free_wqe: 1586 mlx5e_free_rx_wqe(rq, wi, true); 1587 mlx5_wq_cyc_pop(wq); 1588 } 1589 1590 #endif /* CONFIG_MLX5_EN_IPSEC */ 1591