1 /* 2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "lib/mlx5.h" 34 #include "en.h" 35 #include "en_accel/ipsec.h" 36 #include "en_accel/tls.h" 37 38 static const struct counter_desc sw_stats_desc[] = { 39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) }, 40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) }, 41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) }, 42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) }, 43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) }, 44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) }, 45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) }, 46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) }, 47 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) }, 48 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) }, 49 50 #ifdef CONFIG_MLX5_EN_TLS 51 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) }, 52 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) }, 53 #endif 54 55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) }, 56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) }, 57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) }, 58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) }, 59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) }, 60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) }, 61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) }, 62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) }, 63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) }, 64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) }, 65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) }, 66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) }, 67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) }, 68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_mpwqe) }, 69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_inlnw) }, 70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) }, 71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) }, 72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) }, 73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) }, 74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) }, 75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) }, 76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) }, 77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) }, 78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) }, 79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) }, 80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) }, 81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) }, 82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) }, 83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) }, 84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_mpwqe) }, 85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_inlnw) }, 86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) }, 87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) }, 88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) }, 89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) }, 90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) }, 91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) }, 92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) }, 93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) }, 94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) }, 97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) }, 98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) }, 99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) }, 100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) }, 101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) }, 102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) }, 103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) }, 104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) }, 105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) }, 106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) }, 107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) }, 108 }; 109 110 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc) 111 112 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv) 113 { 114 return NUM_SW_COUNTERS; 115 } 116 117 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 118 { 119 int i; 120 121 for (i = 0; i < NUM_SW_COUNTERS; i++) 122 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format); 123 return idx; 124 } 125 126 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 127 { 128 int i; 129 130 for (i = 0; i < NUM_SW_COUNTERS; i++) 131 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i); 132 return idx; 133 } 134 135 static void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv) 136 { 137 struct mlx5e_sw_stats *s = &priv->stats.sw; 138 int i; 139 140 memset(s, 0, sizeof(*s)); 141 142 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) { 143 struct mlx5e_channel_stats *channel_stats = 144 &priv->channel_stats[i]; 145 struct mlx5e_xdpsq_stats *xdpsq_red_stats = &channel_stats->xdpsq; 146 struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq; 147 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 148 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch; 149 int j; 150 151 s->rx_packets += rq_stats->packets; 152 s->rx_bytes += rq_stats->bytes; 153 s->rx_lro_packets += rq_stats->lro_packets; 154 s->rx_lro_bytes += rq_stats->lro_bytes; 155 s->rx_ecn_mark += rq_stats->ecn_mark; 156 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets; 157 s->rx_csum_none += rq_stats->csum_none; 158 s->rx_csum_complete += rq_stats->csum_complete; 159 s->rx_csum_complete_tail += rq_stats->csum_complete_tail; 160 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow; 161 s->rx_csum_unnecessary += rq_stats->csum_unnecessary; 162 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; 163 s->rx_xdp_drop += rq_stats->xdp_drop; 164 s->rx_xdp_redirect += rq_stats->xdp_redirect; 165 s->rx_xdp_tx_xmit += xdpsq_stats->xmit; 166 s->rx_xdp_tx_mpwqe += xdpsq_stats->mpwqe; 167 s->rx_xdp_tx_inlnw += xdpsq_stats->inlnw; 168 s->rx_xdp_tx_full += xdpsq_stats->full; 169 s->rx_xdp_tx_err += xdpsq_stats->err; 170 s->rx_xdp_tx_cqe += xdpsq_stats->cqes; 171 s->rx_wqe_err += rq_stats->wqe_err; 172 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes; 173 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides; 174 s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop; 175 s->rx_buff_alloc_err += rq_stats->buff_alloc_err; 176 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; 177 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; 178 s->rx_cache_reuse += rq_stats->cache_reuse; 179 s->rx_cache_full += rq_stats->cache_full; 180 s->rx_cache_empty += rq_stats->cache_empty; 181 s->rx_cache_busy += rq_stats->cache_busy; 182 s->rx_cache_waive += rq_stats->cache_waive; 183 s->rx_congst_umr += rq_stats->congst_umr; 184 s->rx_arfs_err += rq_stats->arfs_err; 185 s->ch_events += ch_stats->events; 186 s->ch_poll += ch_stats->poll; 187 s->ch_arm += ch_stats->arm; 188 s->ch_aff_change += ch_stats->aff_change; 189 s->ch_eq_rearm += ch_stats->eq_rearm; 190 /* xdp redirect */ 191 s->tx_xdp_xmit += xdpsq_red_stats->xmit; 192 s->tx_xdp_mpwqe += xdpsq_red_stats->mpwqe; 193 s->tx_xdp_inlnw += xdpsq_red_stats->inlnw; 194 s->tx_xdp_full += xdpsq_red_stats->full; 195 s->tx_xdp_err += xdpsq_red_stats->err; 196 s->tx_xdp_cqes += xdpsq_red_stats->cqes; 197 198 for (j = 0; j < priv->max_opened_tc; j++) { 199 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 200 201 s->tx_packets += sq_stats->packets; 202 s->tx_bytes += sq_stats->bytes; 203 s->tx_tso_packets += sq_stats->tso_packets; 204 s->tx_tso_bytes += sq_stats->tso_bytes; 205 s->tx_tso_inner_packets += sq_stats->tso_inner_packets; 206 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; 207 s->tx_added_vlan_packets += sq_stats->added_vlan_packets; 208 s->tx_nop += sq_stats->nop; 209 s->tx_queue_stopped += sq_stats->stopped; 210 s->tx_queue_wake += sq_stats->wake; 211 s->tx_queue_dropped += sq_stats->dropped; 212 s->tx_cqe_err += sq_stats->cqe_err; 213 s->tx_recover += sq_stats->recover; 214 s->tx_xmit_more += sq_stats->xmit_more; 215 s->tx_csum_partial_inner += sq_stats->csum_partial_inner; 216 s->tx_csum_none += sq_stats->csum_none; 217 s->tx_csum_partial += sq_stats->csum_partial; 218 #ifdef CONFIG_MLX5_EN_TLS 219 s->tx_tls_ooo += sq_stats->tls_ooo; 220 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes; 221 #endif 222 s->tx_cqes += sq_stats->cqes; 223 } 224 } 225 } 226 227 static const struct counter_desc q_stats_desc[] = { 228 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) }, 229 }; 230 231 static const struct counter_desc drop_rq_stats_desc[] = { 232 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) }, 233 }; 234 235 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc) 236 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc) 237 238 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv) 239 { 240 int num_stats = 0; 241 242 if (priv->q_counter) 243 num_stats += NUM_Q_COUNTERS; 244 245 if (priv->drop_rq_q_counter) 246 num_stats += NUM_DROP_RQ_COUNTERS; 247 248 return num_stats; 249 } 250 251 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx) 252 { 253 int i; 254 255 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 256 strcpy(data + (idx++) * ETH_GSTRING_LEN, 257 q_stats_desc[i].format); 258 259 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 260 strcpy(data + (idx++) * ETH_GSTRING_LEN, 261 drop_rq_stats_desc[i].format); 262 263 return idx; 264 } 265 266 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 267 { 268 int i; 269 270 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++) 271 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 272 q_stats_desc, i); 273 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++) 274 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, 275 drop_rq_stats_desc, i); 276 return idx; 277 } 278 279 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv) 280 { 281 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; 282 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; 283 284 if (priv->q_counter && 285 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, 286 sizeof(out))) 287 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, 288 out, out_of_buffer); 289 if (priv->drop_rq_q_counter && 290 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0, 291 out, sizeof(out))) 292 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out, 293 out_of_buffer); 294 } 295 296 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c) 297 static const struct counter_desc vnic_env_stats_desc[] = { 298 { "rx_steer_missed_packets", 299 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) }, 300 }; 301 302 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc) 303 304 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv) 305 { 306 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ? 307 NUM_VNIC_ENV_COUNTERS : 0; 308 } 309 310 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data, 311 int idx) 312 { 313 int i; 314 315 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 316 return idx; 317 318 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 319 strcpy(data + (idx++) * ETH_GSTRING_LEN, 320 vnic_env_stats_desc[i].format); 321 return idx; 322 } 323 324 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data, 325 int idx) 326 { 327 int i; 328 329 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 330 return idx; 331 332 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) 333 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out, 334 vnic_env_stats_desc, i); 335 return idx; 336 } 337 338 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 339 { 340 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out; 341 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out); 342 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; 343 struct mlx5_core_dev *mdev = priv->mdev; 344 345 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 346 return; 347 348 MLX5_SET(query_vnic_env_in, in, opcode, 349 MLX5_CMD_OP_QUERY_VNIC_ENV); 350 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 351 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 352 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 353 } 354 355 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) 356 static const struct counter_desc vport_stats_desc[] = { 357 { "rx_vport_unicast_packets", 358 VPORT_COUNTER_OFF(received_eth_unicast.packets) }, 359 { "rx_vport_unicast_bytes", 360 VPORT_COUNTER_OFF(received_eth_unicast.octets) }, 361 { "tx_vport_unicast_packets", 362 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) }, 363 { "tx_vport_unicast_bytes", 364 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) }, 365 { "rx_vport_multicast_packets", 366 VPORT_COUNTER_OFF(received_eth_multicast.packets) }, 367 { "rx_vport_multicast_bytes", 368 VPORT_COUNTER_OFF(received_eth_multicast.octets) }, 369 { "tx_vport_multicast_packets", 370 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) }, 371 { "tx_vport_multicast_bytes", 372 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) }, 373 { "rx_vport_broadcast_packets", 374 VPORT_COUNTER_OFF(received_eth_broadcast.packets) }, 375 { "rx_vport_broadcast_bytes", 376 VPORT_COUNTER_OFF(received_eth_broadcast.octets) }, 377 { "tx_vport_broadcast_packets", 378 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) }, 379 { "tx_vport_broadcast_bytes", 380 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) }, 381 { "rx_vport_rdma_unicast_packets", 382 VPORT_COUNTER_OFF(received_ib_unicast.packets) }, 383 { "rx_vport_rdma_unicast_bytes", 384 VPORT_COUNTER_OFF(received_ib_unicast.octets) }, 385 { "tx_vport_rdma_unicast_packets", 386 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) }, 387 { "tx_vport_rdma_unicast_bytes", 388 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) }, 389 { "rx_vport_rdma_multicast_packets", 390 VPORT_COUNTER_OFF(received_ib_multicast.packets) }, 391 { "rx_vport_rdma_multicast_bytes", 392 VPORT_COUNTER_OFF(received_ib_multicast.octets) }, 393 { "tx_vport_rdma_multicast_packets", 394 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) }, 395 { "tx_vport_rdma_multicast_bytes", 396 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) }, 397 }; 398 399 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc) 400 401 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv) 402 { 403 return NUM_VPORT_COUNTERS; 404 } 405 406 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data, 407 int idx) 408 { 409 int i; 410 411 for (i = 0; i < NUM_VPORT_COUNTERS; i++) 412 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format); 413 return idx; 414 } 415 416 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data, 417 int idx) 418 { 419 int i; 420 421 for (i = 0; i < NUM_VPORT_COUNTERS; i++) 422 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out, 423 vport_stats_desc, i); 424 return idx; 425 } 426 427 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv) 428 { 429 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 430 u32 *out = (u32 *)priv->stats.vport.query_vport_out; 431 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; 432 struct mlx5_core_dev *mdev = priv->mdev; 433 434 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER); 435 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 436 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 437 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); 438 } 439 440 #define PPORT_802_3_OFF(c) \ 441 MLX5_BYTE_OFF(ppcnt_reg, \ 442 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 443 static const struct counter_desc pport_802_3_stats_desc[] = { 444 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) }, 445 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) }, 446 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) }, 447 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) }, 448 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) }, 449 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) }, 450 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) }, 451 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) }, 452 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) }, 453 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) }, 454 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) }, 455 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) }, 456 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) }, 457 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) }, 458 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) }, 459 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) }, 460 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) }, 461 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) }, 462 }; 463 464 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc) 465 466 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv) 467 { 468 return NUM_PPORT_802_3_COUNTERS; 469 } 470 471 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data, 472 int idx) 473 { 474 int i; 475 476 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 477 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format); 478 return idx; 479 } 480 481 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data, 482 int idx) 483 { 484 int i; 485 486 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) 487 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters, 488 pport_802_3_stats_desc, i); 489 return idx; 490 } 491 492 #define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \ 493 (MLX5_CAP_GEN(mdev, pcam_reg) ? MLX5_CAP_PCAM_REG(mdev, ppcnt) : 1) 494 495 void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv) 496 { 497 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 498 struct mlx5_core_dev *mdev = priv->mdev; 499 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 500 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 501 void *out; 502 503 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 504 return; 505 506 MLX5_SET(ppcnt_reg, in, local_port, 1); 507 out = pstats->IEEE_802_3_counters; 508 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 509 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 510 } 511 512 #define PPORT_2863_OFF(c) \ 513 MLX5_BYTE_OFF(ppcnt_reg, \ 514 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 515 static const struct counter_desc pport_2863_stats_desc[] = { 516 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) }, 517 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) }, 518 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) }, 519 }; 520 521 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc) 522 523 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv) 524 { 525 return NUM_PPORT_2863_COUNTERS; 526 } 527 528 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data, 529 int idx) 530 { 531 int i; 532 533 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 534 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format); 535 return idx; 536 } 537 538 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data, 539 int idx) 540 { 541 int i; 542 543 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) 544 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters, 545 pport_2863_stats_desc, i); 546 return idx; 547 } 548 549 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv) 550 { 551 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 552 struct mlx5_core_dev *mdev = priv->mdev; 553 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 554 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 555 void *out; 556 557 MLX5_SET(ppcnt_reg, in, local_port, 1); 558 out = pstats->RFC_2863_counters; 559 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 560 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 561 } 562 563 #define PPORT_2819_OFF(c) \ 564 MLX5_BYTE_OFF(ppcnt_reg, \ 565 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 566 static const struct counter_desc pport_2819_stats_desc[] = { 567 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) }, 568 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) }, 569 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) }, 570 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) }, 571 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) }, 572 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) }, 573 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) }, 574 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) }, 575 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) }, 576 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) }, 577 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) }, 578 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) }, 579 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) }, 580 }; 581 582 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc) 583 584 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv) 585 { 586 return NUM_PPORT_2819_COUNTERS; 587 } 588 589 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data, 590 int idx) 591 { 592 int i; 593 594 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 595 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format); 596 return idx; 597 } 598 599 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data, 600 int idx) 601 { 602 int i; 603 604 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) 605 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters, 606 pport_2819_stats_desc, i); 607 return idx; 608 } 609 610 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv) 611 { 612 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 613 struct mlx5_core_dev *mdev = priv->mdev; 614 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 615 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 616 void *out; 617 618 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 619 return; 620 621 MLX5_SET(ppcnt_reg, in, local_port, 1); 622 out = pstats->RFC_2819_counters; 623 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 624 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 625 } 626 627 #define PPORT_PHY_STATISTICAL_OFF(c) \ 628 MLX5_BYTE_OFF(ppcnt_reg, \ 629 counter_set.phys_layer_statistical_cntrs.c##_high) 630 static const struct counter_desc pport_phy_statistical_stats_desc[] = { 631 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) }, 632 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) }, 633 }; 634 635 static const struct counter_desc 636 pport_phy_statistical_err_lanes_stats_desc[] = { 637 { "rx_err_lane_0_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane0) }, 638 { "rx_err_lane_1_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane1) }, 639 { "rx_err_lane_2_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane2) }, 640 { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, 641 }; 642 643 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ 644 ARRAY_SIZE(pport_phy_statistical_stats_desc) 645 #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ 646 ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) 647 648 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv) 649 { 650 struct mlx5_core_dev *mdev = priv->mdev; 651 int num_stats; 652 653 /* "1" for link_down_events special counter */ 654 num_stats = 1; 655 656 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? 657 NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; 658 659 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ? 660 NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0; 661 662 return num_stats; 663 } 664 665 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data, 666 int idx) 667 { 668 struct mlx5_core_dev *mdev = priv->mdev; 669 int i; 670 671 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy"); 672 673 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 674 return idx; 675 676 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 677 strcpy(data + (idx++) * ETH_GSTRING_LEN, 678 pport_phy_statistical_stats_desc[i].format); 679 680 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) 681 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) 682 strcpy(data + (idx++) * ETH_GSTRING_LEN, 683 pport_phy_statistical_err_lanes_stats_desc[i].format); 684 685 return idx; 686 } 687 688 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 689 { 690 struct mlx5_core_dev *mdev = priv->mdev; 691 int i; 692 693 /* link_down_events_phy has special handling since it is not stored in __be64 format */ 694 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters, 695 counter_set.phys_layer_cntrs.link_down_events); 696 697 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 698 return idx; 699 700 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) 701 data[idx++] = 702 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 703 pport_phy_statistical_stats_desc, i); 704 705 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) 706 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) 707 data[idx++] = 708 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters, 709 pport_phy_statistical_err_lanes_stats_desc, 710 i); 711 return idx; 712 } 713 714 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv) 715 { 716 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 717 struct mlx5_core_dev *mdev = priv->mdev; 718 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 719 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 720 void *out; 721 722 MLX5_SET(ppcnt_reg, in, local_port, 1); 723 out = pstats->phy_counters; 724 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 725 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 726 727 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) 728 return; 729 730 out = pstats->phy_statistical_counters; 731 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 732 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 733 } 734 735 #define PPORT_ETH_EXT_OFF(c) \ 736 MLX5_BYTE_OFF(ppcnt_reg, \ 737 counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 738 static const struct counter_desc pport_eth_ext_stats_desc[] = { 739 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) }, 740 }; 741 742 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc) 743 744 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv) 745 { 746 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 747 return NUM_PPORT_ETH_EXT_COUNTERS; 748 749 return 0; 750 } 751 752 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data, 753 int idx) 754 { 755 int i; 756 757 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 758 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 759 strcpy(data + (idx++) * ETH_GSTRING_LEN, 760 pport_eth_ext_stats_desc[i].format); 761 return idx; 762 } 763 764 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data, 765 int idx) 766 { 767 int i; 768 769 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters)) 770 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++) 771 data[idx++] = 772 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters, 773 pport_eth_ext_stats_desc, i); 774 return idx; 775 } 776 777 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv) 778 { 779 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 780 struct mlx5_core_dev *mdev = priv->mdev; 781 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 782 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 783 void *out; 784 785 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) 786 return; 787 788 MLX5_SET(ppcnt_reg, in, local_port, 1); 789 out = pstats->eth_ext_counters; 790 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 791 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 792 } 793 794 #define PCIE_PERF_OFF(c) \ 795 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c) 796 static const struct counter_desc pcie_perf_stats_desc[] = { 797 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) }, 798 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) }, 799 }; 800 801 #define PCIE_PERF_OFF64(c) \ 802 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 803 static const struct counter_desc pcie_perf_stats_desc64[] = { 804 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) }, 805 }; 806 807 static const struct counter_desc pcie_perf_stall_stats_desc[] = { 808 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) }, 809 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) }, 810 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) }, 811 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) }, 812 }; 813 814 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc) 815 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64) 816 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc) 817 818 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv) 819 { 820 int num_stats = 0; 821 822 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 823 num_stats += NUM_PCIE_PERF_COUNTERS; 824 825 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 826 num_stats += NUM_PCIE_PERF_COUNTERS64; 827 828 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 829 num_stats += NUM_PCIE_PERF_STALL_COUNTERS; 830 831 return num_stats; 832 } 833 834 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data, 835 int idx) 836 { 837 int i; 838 839 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 840 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 841 strcpy(data + (idx++) * ETH_GSTRING_LEN, 842 pcie_perf_stats_desc[i].format); 843 844 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 845 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 846 strcpy(data + (idx++) * ETH_GSTRING_LEN, 847 pcie_perf_stats_desc64[i].format); 848 849 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 850 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 851 strcpy(data + (idx++) * ETH_GSTRING_LEN, 852 pcie_perf_stall_stats_desc[i].format); 853 return idx; 854 } 855 856 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data, 857 int idx) 858 { 859 int i; 860 861 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group)) 862 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++) 863 data[idx++] = 864 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 865 pcie_perf_stats_desc, i); 866 867 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt)) 868 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++) 869 data[idx++] = 870 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters, 871 pcie_perf_stats_desc64, i); 872 873 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled)) 874 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++) 875 data[idx++] = 876 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters, 877 pcie_perf_stall_stats_desc, i); 878 return idx; 879 } 880 881 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv) 882 { 883 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; 884 struct mlx5_core_dev *mdev = priv->mdev; 885 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; 886 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 887 void *out; 888 889 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) 890 return; 891 892 out = pcie_stats->pcie_perf_counters; 893 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 894 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 895 } 896 897 #define PPORT_PER_PRIO_OFF(c) \ 898 MLX5_BYTE_OFF(ppcnt_reg, \ 899 counter_set.eth_per_prio_grp_data_layout.c##_high) 900 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = { 901 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) }, 902 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) }, 903 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) }, 904 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) }, 905 }; 906 907 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc) 908 909 static int mlx5e_grp_per_prio_traffic_get_num_stats(void) 910 { 911 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO; 912 } 913 914 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv, 915 u8 *data, 916 int idx) 917 { 918 int i, prio; 919 920 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 921 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 922 sprintf(data + (idx++) * ETH_GSTRING_LEN, 923 pport_per_prio_traffic_stats_desc[i].format, prio); 924 } 925 926 return idx; 927 } 928 929 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv, 930 u64 *data, 931 int idx) 932 { 933 int i, prio; 934 935 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 936 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) 937 data[idx++] = 938 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 939 pport_per_prio_traffic_stats_desc, i); 940 } 941 942 return idx; 943 } 944 945 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 946 /* %s is "global" or "prio{i}" */ 947 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) }, 948 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) }, 949 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) }, 950 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) }, 951 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, 952 }; 953 954 static const struct counter_desc pport_pfc_stall_stats_desc[] = { 955 { "tx_pause_storm_warning_events", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) }, 956 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) }, 957 }; 958 959 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc) 960 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \ 961 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \ 962 MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 963 964 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) 965 { 966 struct mlx5_core_dev *mdev = priv->mdev; 967 u8 pfc_en_tx; 968 u8 pfc_en_rx; 969 int err; 970 971 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 972 return 0; 973 974 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx); 975 976 return err ? 0 : pfc_en_tx | pfc_en_rx; 977 } 978 979 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv) 980 { 981 struct mlx5_core_dev *mdev = priv->mdev; 982 u32 rx_pause; 983 u32 tx_pause; 984 int err; 985 986 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 987 return false; 988 989 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 990 991 return err ? false : rx_pause | tx_pause; 992 } 993 994 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) 995 { 996 return (mlx5e_query_global_pause_combined(priv) + 997 hweight8(mlx5e_query_pfc_combined(priv))) * 998 NUM_PPORT_PER_PRIO_PFC_COUNTERS + 999 NUM_PPORT_PFC_STALL_COUNTERS(priv); 1000 } 1001 1002 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, 1003 u8 *data, 1004 int idx) 1005 { 1006 unsigned long pfc_combined; 1007 int i, prio; 1008 1009 pfc_combined = mlx5e_query_pfc_combined(priv); 1010 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 1011 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 1012 char pfc_string[ETH_GSTRING_LEN]; 1013 1014 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio); 1015 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1016 pport_per_prio_pfc_stats_desc[i].format, pfc_string); 1017 } 1018 } 1019 1020 if (mlx5e_query_global_pause_combined(priv)) { 1021 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 1022 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1023 pport_per_prio_pfc_stats_desc[i].format, "global"); 1024 } 1025 } 1026 1027 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 1028 strcpy(data + (idx++) * ETH_GSTRING_LEN, 1029 pport_pfc_stall_stats_desc[i].format); 1030 1031 return idx; 1032 } 1033 1034 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, 1035 u64 *data, 1036 int idx) 1037 { 1038 unsigned long pfc_combined; 1039 int i, prio; 1040 1041 pfc_combined = mlx5e_query_pfc_combined(priv); 1042 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { 1043 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 1044 data[idx++] = 1045 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], 1046 pport_per_prio_pfc_stats_desc, i); 1047 } 1048 } 1049 1050 if (mlx5e_query_global_pause_combined(priv)) { 1051 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { 1052 data[idx++] = 1053 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 1054 pport_per_prio_pfc_stats_desc, i); 1055 } 1056 } 1057 1058 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) 1059 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], 1060 pport_pfc_stall_stats_desc, i); 1061 1062 return idx; 1063 } 1064 1065 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv) 1066 { 1067 return mlx5e_grp_per_prio_traffic_get_num_stats() + 1068 mlx5e_grp_per_prio_pfc_get_num_stats(priv); 1069 } 1070 1071 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data, 1072 int idx) 1073 { 1074 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx); 1075 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx); 1076 return idx; 1077 } 1078 1079 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data, 1080 int idx) 1081 { 1082 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx); 1083 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx); 1084 return idx; 1085 } 1086 1087 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv) 1088 { 1089 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 1090 struct mlx5_core_dev *mdev = priv->mdev; 1091 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; 1092 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 1093 int prio; 1094 void *out; 1095 1096 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev)) 1097 return; 1098 1099 MLX5_SET(ppcnt_reg, in, local_port, 1); 1100 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 1101 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { 1102 out = pstats->per_prio_counters[prio]; 1103 MLX5_SET(ppcnt_reg, in, prio_tc, prio); 1104 mlx5_core_access_reg(mdev, in, sz, out, sz, 1105 MLX5_REG_PPCNT, 0, 0); 1106 } 1107 } 1108 1109 static const struct counter_desc mlx5e_pme_status_desc[] = { 1110 { "module_unplug", sizeof(u64) * MLX5_MODULE_STATUS_UNPLUGGED }, 1111 }; 1112 1113 static const struct counter_desc mlx5e_pme_error_desc[] = { 1114 { "module_bus_stuck", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BUS_STUCK }, 1115 { "module_high_temp", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE }, 1116 { "module_bad_shorted", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BAD_CABLE }, 1117 }; 1118 1119 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc) 1120 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc) 1121 1122 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv) 1123 { 1124 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS; 1125 } 1126 1127 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data, 1128 int idx) 1129 { 1130 int i; 1131 1132 for (i = 0; i < NUM_PME_STATUS_STATS; i++) 1133 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format); 1134 1135 for (i = 0; i < NUM_PME_ERR_STATS; i++) 1136 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format); 1137 1138 return idx; 1139 } 1140 1141 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data, 1142 int idx) 1143 { 1144 struct mlx5_pme_stats pme_stats; 1145 int i; 1146 1147 mlx5_get_pme_stats(priv->mdev, &pme_stats); 1148 1149 for (i = 0; i < NUM_PME_STATUS_STATS; i++) 1150 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.status_counters, 1151 mlx5e_pme_status_desc, i); 1152 1153 for (i = 0; i < NUM_PME_ERR_STATS; i++) 1154 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.error_counters, 1155 mlx5e_pme_error_desc, i); 1156 1157 return idx; 1158 } 1159 1160 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv) 1161 { 1162 return mlx5e_ipsec_get_count(priv); 1163 } 1164 1165 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data, 1166 int idx) 1167 { 1168 return idx + mlx5e_ipsec_get_strings(priv, 1169 data + idx * ETH_GSTRING_LEN); 1170 } 1171 1172 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data, 1173 int idx) 1174 { 1175 return idx + mlx5e_ipsec_get_stats(priv, data + idx); 1176 } 1177 1178 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv) 1179 { 1180 mlx5e_ipsec_update_stats(priv); 1181 } 1182 1183 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv) 1184 { 1185 return mlx5e_tls_get_count(priv); 1186 } 1187 1188 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data, 1189 int idx) 1190 { 1191 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN); 1192 } 1193 1194 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx) 1195 { 1196 return idx + mlx5e_tls_get_stats(priv, data + idx); 1197 } 1198 1199 static const struct counter_desc rq_stats_desc[] = { 1200 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) }, 1201 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) }, 1202 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) }, 1203 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) }, 1204 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) }, 1205 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) }, 1206 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) }, 1207 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) }, 1208 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) }, 1209 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) }, 1210 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) }, 1211 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) }, 1212 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) }, 1213 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) }, 1214 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) }, 1215 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) }, 1216 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) }, 1217 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) }, 1218 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) }, 1219 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 1220 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 1221 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) }, 1222 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) }, 1223 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) }, 1224 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) }, 1225 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) }, 1226 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) }, 1227 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) }, 1228 }; 1229 1230 static const struct counter_desc sq_stats_desc[] = { 1231 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) }, 1232 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) }, 1233 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) }, 1234 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) }, 1235 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) }, 1236 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) }, 1237 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) }, 1238 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) }, 1239 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) }, 1240 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) }, 1241 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) }, 1242 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) }, 1243 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) }, 1244 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) }, 1245 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) }, 1246 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) }, 1247 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) }, 1248 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) }, 1249 }; 1250 1251 static const struct counter_desc rq_xdpsq_stats_desc[] = { 1252 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 1253 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) }, 1254 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) }, 1255 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 1256 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 1257 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 1258 }; 1259 1260 static const struct counter_desc xdpsq_stats_desc[] = { 1261 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) }, 1262 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) }, 1263 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) }, 1264 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) }, 1265 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) }, 1266 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) }, 1267 }; 1268 1269 static const struct counter_desc ch_stats_desc[] = { 1270 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) }, 1271 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) }, 1272 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) }, 1273 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) }, 1274 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) }, 1275 }; 1276 1277 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc) 1278 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc) 1279 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc) 1280 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc) 1281 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc) 1282 1283 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv) 1284 { 1285 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev); 1286 1287 return (NUM_RQ_STATS * max_nch) + 1288 (NUM_CH_STATS * max_nch) + 1289 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) + 1290 (NUM_RQ_XDPSQ_STATS * max_nch) + 1291 (NUM_XDPSQ_STATS * max_nch); 1292 } 1293 1294 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data, 1295 int idx) 1296 { 1297 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev); 1298 int i, j, tc; 1299 1300 for (i = 0; i < max_nch; i++) 1301 for (j = 0; j < NUM_CH_STATS; j++) 1302 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1303 ch_stats_desc[j].format, i); 1304 1305 for (i = 0; i < max_nch; i++) { 1306 for (j = 0; j < NUM_RQ_STATS; j++) 1307 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1308 rq_stats_desc[j].format, i); 1309 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1310 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1311 rq_xdpsq_stats_desc[j].format, i); 1312 } 1313 1314 for (tc = 0; tc < priv->max_opened_tc; tc++) 1315 for (i = 0; i < max_nch; i++) 1316 for (j = 0; j < NUM_SQ_STATS; j++) 1317 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1318 sq_stats_desc[j].format, 1319 priv->channel_tc2txq[i][tc]); 1320 1321 for (i = 0; i < max_nch; i++) 1322 for (j = 0; j < NUM_XDPSQ_STATS; j++) 1323 sprintf(data + (idx++) * ETH_GSTRING_LEN, 1324 xdpsq_stats_desc[j].format, i); 1325 1326 return idx; 1327 } 1328 1329 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data, 1330 int idx) 1331 { 1332 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev); 1333 int i, j, tc; 1334 1335 for (i = 0; i < max_nch; i++) 1336 for (j = 0; j < NUM_CH_STATS; j++) 1337 data[idx++] = 1338 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch, 1339 ch_stats_desc, j); 1340 1341 for (i = 0; i < max_nch; i++) { 1342 for (j = 0; j < NUM_RQ_STATS; j++) 1343 data[idx++] = 1344 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq, 1345 rq_stats_desc, j); 1346 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++) 1347 data[idx++] = 1348 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq, 1349 rq_xdpsq_stats_desc, j); 1350 } 1351 1352 for (tc = 0; tc < priv->max_opened_tc; tc++) 1353 for (i = 0; i < max_nch; i++) 1354 for (j = 0; j < NUM_SQ_STATS; j++) 1355 data[idx++] = 1356 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc], 1357 sq_stats_desc, j); 1358 1359 for (i = 0; i < max_nch; i++) 1360 for (j = 0; j < NUM_XDPSQ_STATS; j++) 1361 data[idx++] = 1362 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xdpsq, 1363 xdpsq_stats_desc, j); 1364 1365 return idx; 1366 } 1367 1368 /* The stats groups order is opposite to the update_stats() order calls */ 1369 const struct mlx5e_stats_grp mlx5e_stats_grps[] = { 1370 { 1371 .get_num_stats = mlx5e_grp_sw_get_num_stats, 1372 .fill_strings = mlx5e_grp_sw_fill_strings, 1373 .fill_stats = mlx5e_grp_sw_fill_stats, 1374 .update_stats = mlx5e_grp_sw_update_stats, 1375 }, 1376 { 1377 .get_num_stats = mlx5e_grp_q_get_num_stats, 1378 .fill_strings = mlx5e_grp_q_fill_strings, 1379 .fill_stats = mlx5e_grp_q_fill_stats, 1380 .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 1381 .update_stats = mlx5e_grp_q_update_stats, 1382 }, 1383 { 1384 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats, 1385 .fill_strings = mlx5e_grp_vnic_env_fill_strings, 1386 .fill_stats = mlx5e_grp_vnic_env_fill_stats, 1387 .update_stats = mlx5e_grp_vnic_env_update_stats, 1388 }, 1389 { 1390 .get_num_stats = mlx5e_grp_vport_get_num_stats, 1391 .fill_strings = mlx5e_grp_vport_fill_strings, 1392 .fill_stats = mlx5e_grp_vport_fill_stats, 1393 .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 1394 .update_stats = mlx5e_grp_vport_update_stats, 1395 }, 1396 { 1397 .get_num_stats = mlx5e_grp_802_3_get_num_stats, 1398 .fill_strings = mlx5e_grp_802_3_fill_strings, 1399 .fill_stats = mlx5e_grp_802_3_fill_stats, 1400 .update_stats_mask = MLX5E_NDO_UPDATE_STATS, 1401 .update_stats = mlx5e_grp_802_3_update_stats, 1402 }, 1403 { 1404 .get_num_stats = mlx5e_grp_2863_get_num_stats, 1405 .fill_strings = mlx5e_grp_2863_fill_strings, 1406 .fill_stats = mlx5e_grp_2863_fill_stats, 1407 .update_stats = mlx5e_grp_2863_update_stats, 1408 }, 1409 { 1410 .get_num_stats = mlx5e_grp_2819_get_num_stats, 1411 .fill_strings = mlx5e_grp_2819_fill_strings, 1412 .fill_stats = mlx5e_grp_2819_fill_stats, 1413 .update_stats = mlx5e_grp_2819_update_stats, 1414 }, 1415 { 1416 .get_num_stats = mlx5e_grp_phy_get_num_stats, 1417 .fill_strings = mlx5e_grp_phy_fill_strings, 1418 .fill_stats = mlx5e_grp_phy_fill_stats, 1419 .update_stats = mlx5e_grp_phy_update_stats, 1420 }, 1421 { 1422 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats, 1423 .fill_strings = mlx5e_grp_eth_ext_fill_strings, 1424 .fill_stats = mlx5e_grp_eth_ext_fill_stats, 1425 .update_stats = mlx5e_grp_eth_ext_update_stats, 1426 }, 1427 { 1428 .get_num_stats = mlx5e_grp_pcie_get_num_stats, 1429 .fill_strings = mlx5e_grp_pcie_fill_strings, 1430 .fill_stats = mlx5e_grp_pcie_fill_stats, 1431 .update_stats = mlx5e_grp_pcie_update_stats, 1432 }, 1433 { 1434 .get_num_stats = mlx5e_grp_per_prio_get_num_stats, 1435 .fill_strings = mlx5e_grp_per_prio_fill_strings, 1436 .fill_stats = mlx5e_grp_per_prio_fill_stats, 1437 .update_stats = mlx5e_grp_per_prio_update_stats, 1438 }, 1439 { 1440 .get_num_stats = mlx5e_grp_pme_get_num_stats, 1441 .fill_strings = mlx5e_grp_pme_fill_strings, 1442 .fill_stats = mlx5e_grp_pme_fill_stats, 1443 }, 1444 { 1445 .get_num_stats = mlx5e_grp_ipsec_get_num_stats, 1446 .fill_strings = mlx5e_grp_ipsec_fill_strings, 1447 .fill_stats = mlx5e_grp_ipsec_fill_stats, 1448 .update_stats = mlx5e_grp_ipsec_update_stats, 1449 }, 1450 { 1451 .get_num_stats = mlx5e_grp_tls_get_num_stats, 1452 .fill_strings = mlx5e_grp_tls_fill_strings, 1453 .fill_stats = mlx5e_grp_tls_fill_stats, 1454 }, 1455 { 1456 .get_num_stats = mlx5e_grp_channels_get_num_stats, 1457 .fill_strings = mlx5e_grp_channels_fill_strings, 1458 .fill_stats = mlx5e_grp_channels_fill_stats, 1459 } 1460 }; 1461 1462 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps); 1463