1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_STATS_H__ 33 #define __MLX5_EN_STATS_H__ 34 35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ 36 (*(u64 *)((char *)ptr + dsc[i].offset)) 37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ 38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) 39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ 40 (*(u32 *)((char *)ptr + dsc[i].offset)) 41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ 42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) 43 44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) 45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) 46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) 47 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld) 48 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld) 49 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld) 50 51 struct counter_desc { 52 char format[ETH_GSTRING_LEN]; 53 size_t offset; /* Byte offset */ 54 }; 55 56 struct mlx5e_sw_stats { 57 u64 rx_packets; 58 u64 rx_bytes; 59 u64 tx_packets; 60 u64 tx_bytes; 61 u64 tx_tso_packets; 62 u64 tx_tso_bytes; 63 u64 tx_tso_inner_packets; 64 u64 tx_tso_inner_bytes; 65 u64 tx_added_vlan_packets; 66 u64 tx_nop; 67 u64 rx_lro_packets; 68 u64 rx_lro_bytes; 69 u64 rx_ecn_mark; 70 u64 rx_removed_vlan_packets; 71 u64 rx_csum_unnecessary; 72 u64 rx_csum_none; 73 u64 rx_csum_complete; 74 u64 rx_csum_complete_tail; 75 u64 rx_csum_complete_tail_slow; 76 u64 rx_csum_unnecessary_inner; 77 u64 rx_xdp_drop; 78 u64 rx_xdp_redirect; 79 u64 rx_xdp_tx_xmit; 80 u64 rx_xdp_tx_mpwqe; 81 u64 rx_xdp_tx_inlnw; 82 u64 rx_xdp_tx_full; 83 u64 rx_xdp_tx_err; 84 u64 rx_xdp_tx_cqe; 85 u64 tx_csum_none; 86 u64 tx_csum_partial; 87 u64 tx_csum_partial_inner; 88 u64 tx_queue_stopped; 89 u64 tx_queue_dropped; 90 u64 tx_xmit_more; 91 u64 tx_recover; 92 u64 tx_cqes; 93 u64 tx_queue_wake; 94 u64 tx_cqe_err; 95 u64 tx_xdp_xmit; 96 u64 tx_xdp_mpwqe; 97 u64 tx_xdp_inlnw; 98 u64 tx_xdp_full; 99 u64 tx_xdp_err; 100 u64 tx_xdp_cqes; 101 u64 rx_wqe_err; 102 u64 rx_mpwqe_filler_cqes; 103 u64 rx_mpwqe_filler_strides; 104 u64 rx_oversize_pkts_sw_drop; 105 u64 rx_buff_alloc_err; 106 u64 rx_cqe_compress_blks; 107 u64 rx_cqe_compress_pkts; 108 u64 rx_cache_reuse; 109 u64 rx_cache_full; 110 u64 rx_cache_empty; 111 u64 rx_cache_busy; 112 u64 rx_cache_waive; 113 u64 rx_congst_umr; 114 u64 rx_arfs_err; 115 u64 ch_events; 116 u64 ch_poll; 117 u64 ch_arm; 118 u64 ch_aff_change; 119 u64 ch_eq_rearm; 120 121 #ifdef CONFIG_MLX5_EN_TLS 122 u64 tx_tls_ooo; 123 u64 tx_tls_resync_bytes; 124 #endif 125 }; 126 127 struct mlx5e_qcounter_stats { 128 u32 rx_out_of_buffer; 129 u32 rx_if_down_packets; 130 }; 131 132 struct mlx5e_vnic_env_stats { 133 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)]; 134 }; 135 136 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ 137 vstats->query_vport_out, c) 138 139 struct mlx5e_vport_stats { 140 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)]; 141 }; 142 143 #define PPORT_802_3_GET(pstats, c) \ 144 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \ 145 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high) 146 #define PPORT_2863_GET(pstats, c) \ 147 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \ 148 counter_set.eth_2863_cntrs_grp_data_layout.c##_high) 149 #define PPORT_2819_GET(pstats, c) \ 150 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \ 151 counter_set.eth_2819_cntrs_grp_data_layout.c##_high) 152 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ 153 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ 154 counter_set.phys_layer_statistical_cntrs.c##_high) 155 #define PPORT_PER_PRIO_GET(pstats, prio, c) \ 156 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ 157 counter_set.eth_per_prio_grp_data_layout.c##_high) 158 #define NUM_PPORT_PRIO 8 159 #define PPORT_ETH_EXT_GET(pstats, c) \ 160 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \ 161 counter_set.eth_extended_cntrs_grp_data_layout.c##_high) 162 163 struct mlx5e_pport_stats { 164 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 165 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 166 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 167 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; 168 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 169 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 170 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; 171 }; 172 173 #define PCIE_PERF_GET(pcie_stats, c) \ 174 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 175 counter_set.pcie_perf_cntrs_grp_data_layout.c) 176 177 #define PCIE_PERF_GET64(pcie_stats, c) \ 178 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \ 179 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high) 180 181 struct mlx5e_pcie_stats { 182 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)]; 183 }; 184 185 struct mlx5e_rq_stats { 186 u64 packets; 187 u64 bytes; 188 u64 csum_complete; 189 u64 csum_complete_tail; 190 u64 csum_complete_tail_slow; 191 u64 csum_unnecessary; 192 u64 csum_unnecessary_inner; 193 u64 csum_none; 194 u64 lro_packets; 195 u64 lro_bytes; 196 u64 ecn_mark; 197 u64 removed_vlan_packets; 198 u64 xdp_drop; 199 u64 xdp_redirect; 200 u64 wqe_err; 201 u64 mpwqe_filler_cqes; 202 u64 mpwqe_filler_strides; 203 u64 oversize_pkts_sw_drop; 204 u64 buff_alloc_err; 205 u64 cqe_compress_blks; 206 u64 cqe_compress_pkts; 207 u64 cache_reuse; 208 u64 cache_full; 209 u64 cache_empty; 210 u64 cache_busy; 211 u64 cache_waive; 212 u64 congst_umr; 213 u64 arfs_err; 214 }; 215 216 struct mlx5e_sq_stats { 217 /* commonly accessed in data path */ 218 u64 packets; 219 u64 bytes; 220 u64 xmit_more; 221 u64 tso_packets; 222 u64 tso_bytes; 223 u64 tso_inner_packets; 224 u64 tso_inner_bytes; 225 u64 csum_partial; 226 u64 csum_partial_inner; 227 u64 added_vlan_packets; 228 u64 nop; 229 #ifdef CONFIG_MLX5_EN_TLS 230 u64 tls_ooo; 231 u64 tls_resync_bytes; 232 #endif 233 /* less likely accessed in data path */ 234 u64 csum_none; 235 u64 stopped; 236 u64 dropped; 237 u64 recover; 238 /* dirtied @completion */ 239 u64 cqes ____cacheline_aligned_in_smp; 240 u64 wake; 241 u64 cqe_err; 242 }; 243 244 struct mlx5e_xdpsq_stats { 245 u64 xmit; 246 u64 mpwqe; 247 u64 inlnw; 248 u64 full; 249 u64 err; 250 /* dirtied @completion */ 251 u64 cqes ____cacheline_aligned_in_smp; 252 }; 253 254 struct mlx5e_ch_stats { 255 u64 events; 256 u64 poll; 257 u64 arm; 258 u64 aff_change; 259 u64 eq_rearm; 260 }; 261 262 struct mlx5e_stats { 263 struct mlx5e_sw_stats sw; 264 struct mlx5e_qcounter_stats qcnt; 265 struct mlx5e_vnic_env_stats vnic; 266 struct mlx5e_vport_stats vport; 267 struct mlx5e_pport_stats pport; 268 struct rtnl_link_stats64 vf_vport; 269 struct mlx5e_pcie_stats pcie; 270 }; 271 272 enum { 273 MLX5E_NDO_UPDATE_STATS = BIT(0x1), 274 }; 275 276 struct mlx5e_priv; 277 struct mlx5e_stats_grp { 278 u16 update_stats_mask; 279 int (*get_num_stats)(struct mlx5e_priv *priv); 280 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx); 281 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx); 282 void (*update_stats)(struct mlx5e_priv *priv); 283 }; 284 285 extern const struct mlx5e_stats_grp mlx5e_stats_grps[]; 286 extern const int mlx5e_num_stats_grps; 287 288 void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv); 289 290 #endif /* __MLX5_EN_STATS_H__ */ 291