1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */ 3 4 #include <devlink.h> 5 6 #include "fw_reset.h" 7 #include "diag/fw_tracer.h" 8 #include "lib/tout.h" 9 10 enum { 11 MLX5_FW_RESET_FLAGS_RESET_REQUESTED, 12 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 13 MLX5_FW_RESET_FLAGS_PENDING_COMP, 14 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, 15 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED 16 }; 17 18 struct mlx5_fw_reset { 19 struct mlx5_core_dev *dev; 20 struct mlx5_nb nb; 21 struct workqueue_struct *wq; 22 struct work_struct fw_live_patch_work; 23 struct work_struct reset_request_work; 24 struct work_struct reset_unload_work; 25 struct work_struct reset_reload_work; 26 struct work_struct reset_now_work; 27 struct work_struct reset_abort_work; 28 unsigned long reset_flags; 29 struct timer_list timer; 30 struct completion done; 31 int ret; 32 }; 33 34 enum { 35 MLX5_FW_RST_STATE_IDLE = 0, 36 MLX5_FW_RST_STATE_TOGGLE_REQ = 4, 37 }; 38 39 enum { 40 MLX5_RST_STATE_BIT_NUM = 12, 41 MLX5_RST_ACK_BIT_NUM = 22, 42 }; 43 44 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev) 45 { 46 return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF; 47 } 48 49 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev) 50 { 51 iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing); 52 } 53 54 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id, 55 struct devlink_param_gset_ctx *ctx) 56 { 57 struct mlx5_core_dev *dev = devlink_priv(devlink); 58 struct mlx5_fw_reset *fw_reset; 59 60 fw_reset = dev->priv.fw_reset; 61 62 if (ctx->val.vbool) 63 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 64 else 65 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 66 return 0; 67 } 68 69 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id, 70 struct devlink_param_gset_ctx *ctx) 71 { 72 struct mlx5_core_dev *dev = devlink_priv(devlink); 73 struct mlx5_fw_reset *fw_reset; 74 75 fw_reset = dev->priv.fw_reset; 76 77 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 78 &fw_reset->reset_flags); 79 return 0; 80 } 81 82 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level, 83 u8 reset_type_sel, u8 sync_resp, bool sync_start) 84 { 85 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 86 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 87 88 MLX5_SET(mfrl_reg, in, reset_level, reset_level); 89 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 90 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp); 91 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start); 92 93 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1); 94 } 95 96 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level, 97 u8 *reset_type, u8 *reset_state) 98 { 99 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 100 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 101 int err; 102 103 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0); 104 if (err) 105 return err; 106 107 if (reset_level) 108 *reset_level = MLX5_GET(mfrl_reg, out, reset_level); 109 if (reset_type) 110 *reset_type = MLX5_GET(mfrl_reg, out, reset_type); 111 if (reset_state) 112 *reset_state = MLX5_GET(mfrl_reg, out, reset_state); 113 114 return 0; 115 } 116 117 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type) 118 { 119 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL); 120 } 121 122 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev, 123 struct netlink_ext_ack *extack) 124 { 125 u8 reset_state; 126 127 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state)) 128 goto out; 129 130 if (!reset_state) 131 return 0; 132 133 switch (reset_state) { 134 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION: 135 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS: 136 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress"); 137 return -EBUSY; 138 case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT: 139 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout"); 140 return -ETIMEDOUT; 141 case MLX5_MFRL_REG_RESET_STATE_NACK: 142 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset"); 143 return -EPERM; 144 case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT: 145 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout"); 146 return -ETIMEDOUT; 147 } 148 149 out: 150 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed"); 151 return -EIO; 152 } 153 154 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel, 155 struct netlink_ext_ack *extack) 156 { 157 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 158 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 159 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 160 int err, rst_res; 161 162 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 163 164 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3); 165 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 166 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1); 167 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out), 168 MLX5_REG_MFRL, 0, 1, false); 169 if (!err) 170 return 0; 171 172 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 173 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) { 174 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack); 175 return rst_res ? rst_res : err; 176 } 177 178 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed"); 179 return mlx5_cmd_check(dev, err, in, out); 180 } 181 182 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev, 183 struct netlink_ext_ack *extack) 184 { 185 u8 rst_state; 186 int err; 187 188 err = mlx5_fw_reset_get_reset_state_err(dev, extack); 189 if (err) 190 return err; 191 192 rst_state = mlx5_get_fw_rst_state(dev); 193 if (!rst_state) 194 return 0; 195 196 mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state); 197 NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully"); 198 return rst_state; 199 } 200 201 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev) 202 { 203 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false); 204 } 205 206 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded) 207 { 208 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 209 210 /* if this is the driver that initiated the fw reset, devlink completed the reload */ 211 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { 212 complete(&fw_reset->done); 213 } else { 214 if (!unloaded) 215 mlx5_unload_one(dev, false); 216 if (mlx5_health_wait_pci_up(dev)) 217 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n"); 218 else 219 mlx5_load_one(dev, true); 220 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0, 221 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 222 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE)); 223 } 224 } 225 226 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev) 227 { 228 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 229 230 del_timer_sync(&fw_reset->timer); 231 } 232 233 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health) 234 { 235 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 236 237 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 238 mlx5_core_warn(dev, "Reset request was already cleared\n"); 239 return -EALREADY; 240 } 241 242 mlx5_stop_sync_reset_poll(dev); 243 if (poll_health) 244 mlx5_start_health_poll(dev); 245 return 0; 246 } 247 248 static void mlx5_sync_reset_reload_work(struct work_struct *work) 249 { 250 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 251 reset_reload_work); 252 struct mlx5_core_dev *dev = fw_reset->dev; 253 254 mlx5_sync_reset_clear_reset_requested(dev, false); 255 mlx5_enter_error_state(dev, true); 256 mlx5_fw_reset_complete_reload(dev, false); 257 } 258 259 #define MLX5_RESET_POLL_INTERVAL (HZ / 10) 260 static void poll_sync_reset(struct timer_list *t) 261 { 262 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer); 263 struct mlx5_core_dev *dev = fw_reset->dev; 264 u32 fatal_error; 265 266 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) 267 return; 268 269 fatal_error = mlx5_health_check_fatal_sensors(dev); 270 271 if (fatal_error) { 272 mlx5_core_warn(dev, "Got Device Reset\n"); 273 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 274 queue_work(fw_reset->wq, &fw_reset->reset_reload_work); 275 else 276 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n"); 277 return; 278 } 279 280 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL)); 281 } 282 283 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev) 284 { 285 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 286 287 timer_setup(&fw_reset->timer, poll_sync_reset, 0); 288 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL); 289 add_timer(&fw_reset->timer); 290 } 291 292 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev) 293 { 294 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false); 295 } 296 297 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev) 298 { 299 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false); 300 } 301 302 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev) 303 { 304 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 305 306 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 307 mlx5_core_warn(dev, "Reset request was already set\n"); 308 return -EALREADY; 309 } 310 mlx5_stop_health_poll(dev, true); 311 mlx5_start_sync_reset_poll(dev); 312 return 0; 313 } 314 315 static void mlx5_fw_live_patch_event(struct work_struct *work) 316 { 317 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 318 fw_live_patch_work); 319 struct mlx5_core_dev *dev = fw_reset->dev; 320 321 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev), 322 fw_rev_min(dev), fw_rev_sub(dev)); 323 324 if (mlx5_fw_tracer_reload(dev->tracer)) 325 mlx5_core_err(dev, "Failed to reload FW tracer\n"); 326 } 327 328 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id) 329 { 330 struct pci_bus *bridge_bus = dev->pdev->bus; 331 struct pci_dev *sdev; 332 u16 sdev_id; 333 int err; 334 335 /* Check that all functions under the pci bridge are PFs of 336 * this device otherwise fail this function. 337 */ 338 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 339 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id); 340 if (err) 341 return pcibios_err_to_errno(err); 342 if (sdev_id != dev_id) { 343 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id); 344 return -EPERM; 345 } 346 } 347 return 0; 348 } 349 350 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev) 351 { 352 u16 dev_id; 353 int err; 354 355 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 356 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n"); 357 return false; 358 } 359 360 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id); 361 if (err) 362 return false; 363 return (!mlx5_check_dev_ids(dev, dev_id)); 364 } 365 366 static void mlx5_sync_reset_request_event(struct work_struct *work) 367 { 368 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 369 reset_request_work); 370 struct mlx5_core_dev *dev = fw_reset->dev; 371 int err; 372 373 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) || 374 !mlx5_is_reset_now_capable(dev)) { 375 err = mlx5_fw_reset_set_reset_sync_nack(dev); 376 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s", 377 err ? "Failed" : "Sent"); 378 return; 379 } 380 if (mlx5_sync_reset_set_reset_requested(dev)) 381 return; 382 383 err = mlx5_fw_reset_set_reset_sync_ack(dev); 384 if (err) 385 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err); 386 else 387 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n"); 388 } 389 390 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) 391 { 392 struct pci_bus *bridge_bus = dev->pdev->bus; 393 struct pci_dev *bridge = bridge_bus->self; 394 unsigned long timeout; 395 struct pci_dev *sdev; 396 u16 reg16, dev_id; 397 int cap, err; 398 399 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id); 400 if (err) 401 return pcibios_err_to_errno(err); 402 err = mlx5_check_dev_ids(dev, dev_id); 403 if (err) 404 return err; 405 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); 406 if (!cap) 407 return -EOPNOTSUPP; 408 409 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 410 pci_save_state(sdev); 411 pci_cfg_access_lock(sdev); 412 } 413 /* PCI link toggle */ 414 err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); 415 if (err) 416 return pcibios_err_to_errno(err); 417 msleep(500); 418 err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); 419 if (err) 420 return pcibios_err_to_errno(err); 421 422 /* Check link */ 423 if (!bridge->link_active_reporting) { 424 mlx5_core_warn(dev, "No PCI link reporting capability\n"); 425 msleep(1000); 426 goto restore; 427 } 428 429 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE)); 430 do { 431 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16); 432 if (err) 433 return pcibios_err_to_errno(err); 434 if (reg16 & PCI_EXP_LNKSTA_DLLLA) 435 break; 436 msleep(20); 437 } while (!time_after(jiffies, timeout)); 438 439 if (reg16 & PCI_EXP_LNKSTA_DLLLA) { 440 mlx5_core_info(dev, "PCI Link up\n"); 441 } else { 442 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n", 443 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 444 err = -ETIMEDOUT; 445 goto restore; 446 } 447 448 do { 449 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16); 450 if (err) 451 return pcibios_err_to_errno(err); 452 if (reg16 == dev_id) 453 break; 454 msleep(20); 455 } while (!time_after(jiffies, timeout)); 456 457 if (reg16 == dev_id) { 458 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n"); 459 } else { 460 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n", 461 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 462 err = -ETIMEDOUT; 463 } 464 465 restore: 466 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 467 pci_cfg_access_unlock(sdev); 468 pci_restore_state(sdev); 469 } 470 471 return err; 472 } 473 474 static void mlx5_sync_reset_now_event(struct work_struct *work) 475 { 476 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 477 reset_now_work); 478 struct mlx5_core_dev *dev = fw_reset->dev; 479 int err; 480 481 if (mlx5_sync_reset_clear_reset_requested(dev, false)) 482 return; 483 484 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n"); 485 486 err = mlx5_cmd_fast_teardown_hca(dev); 487 if (err) { 488 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err); 489 goto done; 490 } 491 492 err = mlx5_pci_link_toggle(dev); 493 if (err) { 494 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err); 495 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags); 496 } 497 498 mlx5_enter_error_state(dev, true); 499 done: 500 fw_reset->ret = err; 501 mlx5_fw_reset_complete_reload(dev, false); 502 } 503 504 static void mlx5_sync_reset_unload_event(struct work_struct *work) 505 { 506 struct mlx5_fw_reset *fw_reset; 507 struct mlx5_core_dev *dev; 508 unsigned long timeout; 509 bool reset_action; 510 u8 rst_state; 511 int err; 512 513 fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work); 514 dev = fw_reset->dev; 515 516 if (mlx5_sync_reset_clear_reset_requested(dev, false)) 517 return; 518 519 mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n"); 520 521 err = mlx5_cmd_fast_teardown_hca(dev); 522 if (err) 523 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err); 524 else 525 mlx5_enter_error_state(dev, true); 526 527 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) 528 mlx5_unload_one_devl_locked(dev, false); 529 else 530 mlx5_unload_one(dev, false); 531 532 mlx5_set_fw_rst_ack(dev); 533 mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n"); 534 535 reset_action = false; 536 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD)); 537 do { 538 rst_state = mlx5_get_fw_rst_state(dev); 539 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ || 540 rst_state == MLX5_FW_RST_STATE_IDLE) { 541 reset_action = true; 542 break; 543 } 544 msleep(20); 545 } while (!time_after(jiffies, timeout)); 546 547 if (!reset_action) { 548 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n", 549 rst_state); 550 fw_reset->ret = -ETIMEDOUT; 551 goto done; 552 } 553 554 mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state); 555 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) { 556 err = mlx5_pci_link_toggle(dev); 557 if (err) { 558 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err); 559 fw_reset->ret = err; 560 } 561 } 562 563 done: 564 mlx5_fw_reset_complete_reload(dev, true); 565 } 566 567 static void mlx5_sync_reset_abort_event(struct work_struct *work) 568 { 569 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 570 reset_abort_work); 571 struct mlx5_core_dev *dev = fw_reset->dev; 572 573 if (mlx5_sync_reset_clear_reset_requested(dev, true)) 574 return; 575 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n"); 576 } 577 578 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe) 579 { 580 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe; 581 u8 sync_event_rst_type; 582 583 sync_fw_update_eqe = &eqe->data.sync_fw_update; 584 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK; 585 switch (sync_event_rst_type) { 586 case MLX5_SYNC_RST_STATE_RESET_REQUEST: 587 queue_work(fw_reset->wq, &fw_reset->reset_request_work); 588 break; 589 case MLX5_SYNC_RST_STATE_RESET_UNLOAD: 590 queue_work(fw_reset->wq, &fw_reset->reset_unload_work); 591 break; 592 case MLX5_SYNC_RST_STATE_RESET_NOW: 593 queue_work(fw_reset->wq, &fw_reset->reset_now_work); 594 break; 595 case MLX5_SYNC_RST_STATE_RESET_ABORT: 596 queue_work(fw_reset->wq, &fw_reset->reset_abort_work); 597 break; 598 } 599 } 600 601 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data) 602 { 603 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb); 604 struct mlx5_eqe *eqe = data; 605 606 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 607 return NOTIFY_DONE; 608 609 switch (eqe->sub_type) { 610 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT: 611 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work); 612 break; 613 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT: 614 mlx5_sync_reset_events_handle(fw_reset, eqe); 615 break; 616 default: 617 return NOTIFY_DONE; 618 } 619 620 return NOTIFY_OK; 621 } 622 623 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev) 624 { 625 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE); 626 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 627 unsigned long timeout; 628 int err; 629 630 if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload)) 631 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD); 632 timeout = msecs_to_jiffies(pci_sync_update_timeout); 633 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) { 634 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n", 635 pci_sync_update_timeout / 1000); 636 err = -ETIMEDOUT; 637 goto out; 638 } 639 err = fw_reset->ret; 640 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) { 641 mlx5_unload_one_devl_locked(dev, false); 642 mlx5_load_one_devl_locked(dev, true); 643 } 644 out: 645 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 646 return err; 647 } 648 649 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev) 650 { 651 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 652 653 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT); 654 mlx5_eq_notifier_register(dev, &fw_reset->nb); 655 } 656 657 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev) 658 { 659 mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb); 660 } 661 662 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev) 663 { 664 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 665 666 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags); 667 cancel_work_sync(&fw_reset->fw_live_patch_work); 668 cancel_work_sync(&fw_reset->reset_request_work); 669 cancel_work_sync(&fw_reset->reset_unload_work); 670 cancel_work_sync(&fw_reset->reset_reload_work); 671 cancel_work_sync(&fw_reset->reset_now_work); 672 cancel_work_sync(&fw_reset->reset_abort_work); 673 } 674 675 static const struct devlink_param mlx5_fw_reset_devlink_params[] = { 676 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME), 677 mlx5_fw_reset_enable_remote_dev_reset_get, 678 mlx5_fw_reset_enable_remote_dev_reset_set, NULL), 679 }; 680 681 int mlx5_fw_reset_init(struct mlx5_core_dev *dev) 682 { 683 struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL); 684 int err; 685 686 if (!fw_reset) 687 return -ENOMEM; 688 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events"); 689 if (!fw_reset->wq) { 690 kfree(fw_reset); 691 return -ENOMEM; 692 } 693 694 fw_reset->dev = dev; 695 dev->priv.fw_reset = fw_reset; 696 697 err = devl_params_register(priv_to_devlink(dev), 698 mlx5_fw_reset_devlink_params, 699 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 700 if (err) { 701 destroy_workqueue(fw_reset->wq); 702 kfree(fw_reset); 703 return err; 704 } 705 706 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event); 707 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event); 708 INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event); 709 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work); 710 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event); 711 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event); 712 713 init_completion(&fw_reset->done); 714 return 0; 715 } 716 717 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev) 718 { 719 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 720 721 devl_params_unregister(priv_to_devlink(dev), 722 mlx5_fw_reset_devlink_params, 723 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 724 destroy_workqueue(fw_reset->wq); 725 kfree(dev->priv.fw_reset); 726 } 727