1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_CORE_H__ 34 #define __MLX5_CORE_H__ 35 36 #include <linux/types.h> 37 #include <linux/kernel.h> 38 #include <linux/sched.h> 39 #include <linux/if_link.h> 40 #include <linux/firmware.h> 41 #include <linux/ptp_clock_kernel.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/driver.h> 45 46 #define DRIVER_NAME "mlx5_core" 47 #define DRIVER_VERSION "5.0-0" 48 49 extern uint mlx5_core_debug_mask; 50 51 #define mlx5_core_dbg(__dev, format, ...) \ 52 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \ 53 __func__, __LINE__, current->pid, \ 54 ##__VA_ARGS__) 55 56 #define mlx5_core_dbg_once(__dev, format, ...) \ 57 dev_dbg_once((__dev)->device, \ 58 "%s:%d:(pid %d): " format, \ 59 __func__, __LINE__, current->pid, \ 60 ##__VA_ARGS__) 61 62 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \ 63 do { \ 64 if ((mask) & mlx5_core_debug_mask) \ 65 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \ 66 } while (0) 67 68 #define mlx5_core_err(__dev, format, ...) \ 69 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \ 70 __func__, __LINE__, current->pid, \ 71 ##__VA_ARGS__) 72 73 #define mlx5_core_err_rl(__dev, format, ...) \ 74 dev_err_ratelimited((__dev)->device, \ 75 "%s:%d:(pid %d): " format, \ 76 __func__, __LINE__, current->pid, \ 77 ##__VA_ARGS__) 78 79 #define mlx5_core_warn(__dev, format, ...) \ 80 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \ 81 __func__, __LINE__, current->pid, \ 82 ##__VA_ARGS__) 83 84 #define mlx5_core_warn_once(__dev, format, ...) \ 85 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \ 86 __func__, __LINE__, current->pid, \ 87 ##__VA_ARGS__) 88 89 #define mlx5_core_warn_rl(__dev, format, ...) \ 90 dev_warn_ratelimited((__dev)->device, \ 91 "%s:%d:(pid %d): " format, \ 92 __func__, __LINE__, current->pid, \ 93 ##__VA_ARGS__) 94 95 #define mlx5_core_info(__dev, format, ...) \ 96 dev_info((__dev)->device, format, ##__VA_ARGS__) 97 98 #define mlx5_core_info_rl(__dev, format, ...) \ 99 dev_info_ratelimited((__dev)->device, \ 100 "%s:%d:(pid %d): " format, \ 101 __func__, __LINE__, current->pid, \ 102 ##__VA_ARGS__) 103 104 enum { 105 MLX5_CMD_DATA, /* print command payload only */ 106 MLX5_CMD_TIME, /* print command execution time */ 107 }; 108 109 enum { 110 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 111 MLX5_DRIVER_SYND = 0xbadd00de, 112 }; 113 114 enum mlx5_semaphore_space_address { 115 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA, 116 MLX5_SEMAPHORE_SW_RESET = 0x20, 117 }; 118 119 int mlx5_query_hca_caps(struct mlx5_core_dev *dev); 120 int mlx5_query_board_id(struct mlx5_core_dev *dev); 121 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id); 122 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); 123 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); 124 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); 125 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); 126 void mlx5_error_sw_reset(struct mlx5_core_dev *dev); 127 void mlx5_disable_device(struct mlx5_core_dev *dev); 128 void mlx5_recover_device(struct mlx5_core_dev *dev); 129 int mlx5_sriov_init(struct mlx5_core_dev *dev); 130 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev); 131 int mlx5_sriov_attach(struct mlx5_core_dev *dev); 132 void mlx5_sriov_detach(struct mlx5_core_dev *dev); 133 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs); 134 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id); 135 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id); 136 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 137 void *context, u32 *element_id); 138 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 139 void *context, u32 element_id, 140 u32 modify_bitmask); 141 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 142 u32 element_id); 143 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages); 144 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, 145 struct ptp_system_timestamp *sts); 146 147 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev); 148 void mlx5_cmd_flush(struct mlx5_core_dev *dev); 149 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 150 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 151 152 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 153 u8 access_reg_group); 154 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group, 155 u8 access_reg_group); 156 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 157 u8 feature_group, u8 access_reg_group); 158 159 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev); 160 void mlx5_lag_remove(struct mlx5_core_dev *dev); 161 162 int mlx5_irq_table_init(struct mlx5_core_dev *dev); 163 void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev); 164 int mlx5_irq_table_create(struct mlx5_core_dev *dev); 165 void mlx5_irq_table_destroy(struct mlx5_core_dev *dev); 166 int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx, 167 struct notifier_block *nb); 168 int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx, 169 struct notifier_block *nb); 170 struct cpumask * 171 mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx); 172 struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table); 173 int mlx5_irq_get_num_comp(struct mlx5_irq_table *table); 174 175 int mlx5_events_init(struct mlx5_core_dev *dev); 176 void mlx5_events_cleanup(struct mlx5_core_dev *dev); 177 void mlx5_events_start(struct mlx5_core_dev *dev); 178 void mlx5_events_stop(struct mlx5_core_dev *dev); 179 180 void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv); 181 void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv); 182 void mlx5_attach_device(struct mlx5_core_dev *dev); 183 void mlx5_detach_device(struct mlx5_core_dev *dev); 184 bool mlx5_device_registered(struct mlx5_core_dev *dev); 185 int mlx5_register_device(struct mlx5_core_dev *dev); 186 void mlx5_unregister_device(struct mlx5_core_dev *dev); 187 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol); 188 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol); 189 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev); 190 void mlx5_dev_list_lock(void); 191 void mlx5_dev_list_unlock(void); 192 int mlx5_dev_list_trylock(void); 193 194 bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv); 195 196 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size); 197 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size); 198 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode); 199 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode); 200 201 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev); 202 void mlx5_dm_cleanup(struct mlx5_core_dev *dev); 203 204 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ 205 MLX5_CAP_GEN((mdev), pps_modify) && \ 206 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \ 207 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj)) 208 209 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw, 210 struct netlink_ext_ack *extack); 211 int mlx5_fw_version_query(struct mlx5_core_dev *dev, 212 u32 *running_ver, u32 *stored_ver); 213 214 void mlx5e_init(void); 215 void mlx5e_cleanup(void); 216 217 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev) 218 { 219 return pci_num_vf(dev->pdev) ? true : false; 220 } 221 222 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev) 223 { 224 /* LACP owner conditions: 225 * 1) Function is physical. 226 * 2) LAG is supported by FW. 227 * 3) LAG is managed by driver (currently the only option). 228 */ 229 return MLX5_CAP_GEN(dev, vport_group_manager) && 230 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && 231 MLX5_CAP_GEN(dev, lag_master); 232 } 233 234 void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol); 235 void mlx5_lag_update(struct mlx5_core_dev *dev); 236 237 enum { 238 MLX5_NIC_IFC_FULL = 0, 239 MLX5_NIC_IFC_DISABLED = 1, 240 MLX5_NIC_IFC_NO_DRAM_NIC = 2, 241 MLX5_NIC_IFC_SW_RESET = 7 242 }; 243 244 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); 245 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); 246 #endif /* __MLX5_CORE_H__ */ 247