1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_CORE_H__ 34 #define __MLX5_CORE_H__ 35 36 #include <linux/types.h> 37 #include <linux/kernel.h> 38 #include <linux/sched.h> 39 #include <linux/if_link.h> 40 #include <linux/firmware.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/fs.h> 43 #include <linux/mlx5/driver.h> 44 45 extern uint mlx5_core_debug_mask; 46 47 #define mlx5_core_dbg(__dev, format, ...) \ 48 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \ 49 __func__, __LINE__, current->pid, \ 50 ##__VA_ARGS__) 51 52 #define mlx5_core_dbg_once(__dev, format, ...) \ 53 dev_dbg_once((__dev)->device, \ 54 "%s:%d:(pid %d): " format, \ 55 __func__, __LINE__, current->pid, \ 56 ##__VA_ARGS__) 57 58 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \ 59 do { \ 60 if ((mask) & mlx5_core_debug_mask) \ 61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \ 62 } while (0) 63 64 #define mlx5_core_err(__dev, format, ...) \ 65 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \ 66 __func__, __LINE__, current->pid, \ 67 ##__VA_ARGS__) 68 69 #define mlx5_core_err_rl(__dev, format, ...) \ 70 dev_err_ratelimited((__dev)->device, \ 71 "%s:%d:(pid %d): " format, \ 72 __func__, __LINE__, current->pid, \ 73 ##__VA_ARGS__) 74 75 #define mlx5_core_warn(__dev, format, ...) \ 76 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \ 77 __func__, __LINE__, current->pid, \ 78 ##__VA_ARGS__) 79 80 #define mlx5_core_warn_once(__dev, format, ...) \ 81 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \ 82 __func__, __LINE__, current->pid, \ 83 ##__VA_ARGS__) 84 85 #define mlx5_core_warn_rl(__dev, format, ...) \ 86 dev_warn_ratelimited((__dev)->device, \ 87 "%s:%d:(pid %d): " format, \ 88 __func__, __LINE__, current->pid, \ 89 ##__VA_ARGS__) 90 91 #define mlx5_core_info(__dev, format, ...) \ 92 dev_info((__dev)->device, format, ##__VA_ARGS__) 93 94 #define mlx5_core_info_rl(__dev, format, ...) \ 95 dev_info_ratelimited((__dev)->device, \ 96 "%s:%d:(pid %d): " format, \ 97 __func__, __LINE__, current->pid, \ 98 ##__VA_ARGS__) 99 100 static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...) 101 { 102 struct device *device = dev->device; 103 struct va_format vaf; 104 va_list args; 105 106 if (WARN_ONCE(level < LOGLEVEL_EMERG || level > LOGLEVEL_DEBUG, 107 "Level %d is out of range, set to default level\n", level)) 108 level = LOGLEVEL_DEFAULT; 109 110 va_start(args, format); 111 vaf.fmt = format; 112 vaf.va = &args; 113 114 dev_printk_emit(level, device, "%s %s: %pV", dev_driver_string(device), dev_name(device), 115 &vaf); 116 va_end(args); 117 } 118 119 #define mlx5_log(__dev, level, format, ...) \ 120 mlx5_printk(__dev, level, "%s:%d:(pid %d): " format, \ 121 __func__, __LINE__, current->pid, \ 122 ##__VA_ARGS__) 123 124 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev) 125 { 126 return &dev->pdev->dev; 127 } 128 129 enum { 130 MLX5_CMD_DATA, /* print command payload only */ 131 MLX5_CMD_TIME, /* print command execution time */ 132 }; 133 134 enum { 135 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 136 MLX5_DRIVER_SYND = 0xbadd00de, 137 }; 138 139 enum mlx5_semaphore_space_address { 140 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA, 141 MLX5_SEMAPHORE_SW_RESET = 0x20, 142 }; 143 144 #define MLX5_DEFAULT_PROF 2 145 146 static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed, 147 size_t item_size, size_t num_items, 148 const char *func, int line) 149 { 150 int inlen; 151 152 if (fixed > INT_MAX || item_size > INT_MAX || num_items > INT_MAX) { 153 mlx5_core_err(dev, "%s: %s:%d: input values too big: %zu + %zu * %zu\n", 154 __func__, func, line, fixed, item_size, num_items); 155 return -ENOMEM; 156 } 157 158 if (check_mul_overflow((int)item_size, (int)num_items, &inlen)) { 159 mlx5_core_err(dev, "%s: %s:%d: multiplication overflow: %zu + %zu * %zu\n", 160 __func__, func, line, fixed, item_size, num_items); 161 return -ENOMEM; 162 } 163 164 if (check_add_overflow((int)fixed, inlen, &inlen)) { 165 mlx5_core_err(dev, "%s: %s:%d: addition overflow: %zu + %zu * %zu\n", 166 __func__, func, line, fixed, item_size, num_items); 167 return -ENOMEM; 168 } 169 170 return inlen; 171 } 172 173 #define MLX5_FLEXIBLE_INLEN(dev, fixed, item_size, num_items) \ 174 mlx5_flexible_inlen(dev, fixed, item_size, num_items, __func__, __LINE__) 175 176 int mlx5_query_hca_caps(struct mlx5_core_dev *dev); 177 int mlx5_query_board_id(struct mlx5_core_dev *dev); 178 int mlx5_cmd_init(struct mlx5_core_dev *dev); 179 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 180 void mlx5_cmd_set_state(struct mlx5_core_dev *dev, 181 enum mlx5_cmdif_state cmdif_state); 182 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id); 183 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); 184 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); 185 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); 186 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); 187 void mlx5_error_sw_reset(struct mlx5_core_dev *dev); 188 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev); 189 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev); 190 void mlx5_disable_device(struct mlx5_core_dev *dev); 191 int mlx5_recover_device(struct mlx5_core_dev *dev); 192 int mlx5_sriov_init(struct mlx5_core_dev *dev); 193 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev); 194 int mlx5_sriov_attach(struct mlx5_core_dev *dev); 195 void mlx5_sriov_detach(struct mlx5_core_dev *dev); 196 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs); 197 void mlx5_sriov_disable(struct pci_dev *pdev); 198 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count); 199 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id); 200 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id); 201 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 202 void *context, u32 *element_id); 203 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 204 void *context, u32 element_id, 205 u32 modify_bitmask); 206 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 207 u32 element_id); 208 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages); 209 210 void mlx5_cmd_flush(struct mlx5_core_dev *dev); 211 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 212 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 213 214 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 215 u8 access_reg_group); 216 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group, 217 u8 access_reg_group); 218 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 219 u8 feature_group, u8 access_reg_group); 220 221 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev); 222 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev); 223 void mlx5_lag_add_mdev(struct mlx5_core_dev *dev); 224 void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev); 225 void mlx5_lag_disable_change(struct mlx5_core_dev *dev); 226 void mlx5_lag_enable_change(struct mlx5_core_dev *dev); 227 228 int mlx5_events_init(struct mlx5_core_dev *dev); 229 void mlx5_events_cleanup(struct mlx5_core_dev *dev); 230 void mlx5_events_start(struct mlx5_core_dev *dev); 231 void mlx5_events_stop(struct mlx5_core_dev *dev); 232 233 int mlx5_adev_idx_alloc(void); 234 void mlx5_adev_idx_free(int idx); 235 void mlx5_adev_cleanup(struct mlx5_core_dev *dev); 236 int mlx5_adev_init(struct mlx5_core_dev *dev); 237 238 int mlx5_attach_device(struct mlx5_core_dev *dev); 239 void mlx5_detach_device(struct mlx5_core_dev *dev); 240 int mlx5_register_device(struct mlx5_core_dev *dev); 241 void mlx5_unregister_device(struct mlx5_core_dev *dev); 242 struct mlx5_core_dev *mlx5_get_next_phys_dev_lag(struct mlx5_core_dev *dev); 243 void mlx5_dev_list_lock(void); 244 void mlx5_dev_list_unlock(void); 245 int mlx5_dev_list_trylock(void); 246 247 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size); 248 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size); 249 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode); 250 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode); 251 252 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev); 253 void mlx5_dm_cleanup(struct mlx5_core_dev *dev); 254 255 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ 256 MLX5_CAP_GEN((mdev), pps_modify) && \ 257 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \ 258 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj)) 259 260 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw, 261 struct netlink_ext_ack *extack); 262 int mlx5_fw_version_query(struct mlx5_core_dev *dev, 263 u32 *running_ver, u32 *stored_ver); 264 265 #ifdef CONFIG_MLX5_CORE_EN 266 int mlx5e_init(void); 267 void mlx5e_cleanup(void); 268 #else 269 static inline int mlx5e_init(void){ return 0; } 270 static inline void mlx5e_cleanup(void){} 271 #endif 272 273 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev) 274 { 275 return pci_num_vf(dev->pdev) ? true : false; 276 } 277 278 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev) 279 { 280 /* LACP owner conditions: 281 * 1) Function is physical. 282 * 2) LAG is supported by FW. 283 * 3) LAG is managed by driver (currently the only option). 284 */ 285 return MLX5_CAP_GEN(dev, vport_group_manager) && 286 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && 287 MLX5_CAP_GEN(dev, lag_master); 288 } 289 290 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev); 291 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev) 292 { 293 int ret; 294 295 mlx5_dev_list_lock(); 296 ret = mlx5_rescan_drivers_locked(dev); 297 mlx5_dev_list_unlock(); 298 return ret; 299 } 300 301 void mlx5_lag_update(struct mlx5_core_dev *dev); 302 303 enum { 304 MLX5_NIC_IFC_FULL = 0, 305 MLX5_NIC_IFC_DISABLED = 1, 306 MLX5_NIC_IFC_NO_DRAM_NIC = 2, 307 MLX5_NIC_IFC_SW_RESET = 7 308 }; 309 310 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); 311 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); 312 313 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev) 314 { 315 return dev->coredev_type == MLX5_COREDEV_SF; 316 } 317 318 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); 319 void mlx5_mdev_uninit(struct mlx5_core_dev *dev); 320 int mlx5_init_one(struct mlx5_core_dev *dev); 321 void mlx5_uninit_one(struct mlx5_core_dev *dev); 322 void mlx5_unload_one(struct mlx5_core_dev *dev); 323 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev); 324 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery); 325 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery); 326 327 int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *hca_cap, u16 function_id, 328 u16 opmod); 329 #define mlx5_vport_get_other_func_general_cap(dev, fid, out) \ 330 mlx5_vport_get_other_func_cap(dev, fid, out, MLX5_CAP_GENERAL) 331 332 void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work); 333 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev) 334 { 335 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 336 337 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix); 338 } 339 340 bool mlx5_eth_supported(struct mlx5_core_dev *dev); 341 bool mlx5_rdma_supported(struct mlx5_core_dev *dev); 342 bool mlx5_vnet_supported(struct mlx5_core_dev *dev); 343 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev); 344 345 #endif /* __MLX5_CORE_H__ */ 346