1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 6 enum dr_action_domain { 7 DR_ACTION_DOMAIN_NIC_INGRESS, 8 DR_ACTION_DOMAIN_NIC_EGRESS, 9 DR_ACTION_DOMAIN_FDB_INGRESS, 10 DR_ACTION_DOMAIN_FDB_EGRESS, 11 DR_ACTION_DOMAIN_MAX, 12 }; 13 14 enum dr_action_valid_state { 15 DR_ACTION_STATE_ERR, 16 DR_ACTION_STATE_NO_ACTION, 17 DR_ACTION_STATE_REFORMAT, 18 DR_ACTION_STATE_MODIFY_HDR, 19 DR_ACTION_STATE_MODIFY_VLAN, 20 DR_ACTION_STATE_NON_TERM, 21 DR_ACTION_STATE_TERM, 22 DR_ACTION_STATE_MAX, 23 }; 24 25 static const enum dr_action_valid_state 26 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 27 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 28 [DR_ACTION_STATE_NO_ACTION] = { 29 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 30 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 31 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 32 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 33 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 34 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT, 35 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT, 36 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 37 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 38 }, 39 [DR_ACTION_STATE_REFORMAT] = { 40 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 41 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 42 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 43 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_REFORMAT, 44 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT, 45 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 46 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 47 }, 48 [DR_ACTION_STATE_MODIFY_HDR] = { 49 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 50 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 51 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 52 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 53 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 54 }, 55 [DR_ACTION_STATE_MODIFY_VLAN] = { 56 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 57 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 58 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 59 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_VLAN, 60 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN, 61 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 62 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 63 }, 64 [DR_ACTION_STATE_NON_TERM] = { 65 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 66 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 67 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 68 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 69 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 70 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT, 71 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT, 72 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 73 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 74 }, 75 [DR_ACTION_STATE_TERM] = { 76 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 77 }, 78 }, 79 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 80 [DR_ACTION_STATE_NO_ACTION] = { 81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 82 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 83 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 84 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 85 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 86 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 87 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 88 }, 89 [DR_ACTION_STATE_REFORMAT] = { 90 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 91 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 92 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT, 93 }, 94 [DR_ACTION_STATE_MODIFY_HDR] = { 95 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 96 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 97 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 98 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 99 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 100 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 101 }, 102 [DR_ACTION_STATE_MODIFY_VLAN] = { 103 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 104 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 105 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN, 106 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 107 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 108 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 109 }, 110 [DR_ACTION_STATE_NON_TERM] = { 111 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 112 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 116 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 118 }, 119 [DR_ACTION_STATE_TERM] = { 120 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 121 }, 122 }, 123 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 124 [DR_ACTION_STATE_NO_ACTION] = { 125 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 126 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 128 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT, 129 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT, 130 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 131 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 132 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 133 }, 134 [DR_ACTION_STATE_REFORMAT] = { 135 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 136 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 137 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT, 138 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 139 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 140 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 141 }, 142 [DR_ACTION_STATE_MODIFY_HDR] = { 143 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 144 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 145 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 146 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 147 }, 148 [DR_ACTION_STATE_MODIFY_VLAN] = { 149 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 151 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 152 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN, 153 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 154 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 155 }, 156 [DR_ACTION_STATE_NON_TERM] = { 157 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 158 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 159 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 160 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT, 161 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT, 162 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 163 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 164 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 165 }, 166 [DR_ACTION_STATE_TERM] = { 167 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 168 }, 169 }, 170 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 171 [DR_ACTION_STATE_NO_ACTION] = { 172 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 173 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 175 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 176 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 177 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 178 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 179 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 180 }, 181 [DR_ACTION_STATE_REFORMAT] = { 182 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 183 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 184 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT, 185 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 186 }, 187 [DR_ACTION_STATE_MODIFY_HDR] = { 188 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 189 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 190 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 191 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 192 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 193 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 194 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 195 }, 196 [DR_ACTION_STATE_MODIFY_VLAN] = { 197 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 198 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 199 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 200 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN, 201 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 202 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 203 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 204 }, 205 [DR_ACTION_STATE_NON_TERM] = { 206 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 207 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 208 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 209 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 210 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT, 211 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT, 212 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN, 213 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 214 }, 215 [DR_ACTION_STATE_TERM] = { 216 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 217 }, 218 }, 219 }; 220 221 struct dr_action_modify_field_conv { 222 u16 hw_field; 223 u8 start; 224 u8 end; 225 u8 l3_type; 226 u8 l4_type; 227 }; 228 229 static const struct dr_action_modify_field_conv dr_action_conv_arr[] = { 230 [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = { 231 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 16, .end = 47, 232 }, 233 [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = { 234 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 0, .end = 15, 235 }, 236 [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = { 237 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 32, .end = 47, 238 }, 239 [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = { 240 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 16, .end = 47, 241 }, 242 [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = { 243 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 0, .end = 15, 244 }, 245 [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = { 246 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 0, .end = 5, 247 }, 248 [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = { 249 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 48, .end = 56, 250 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP, 251 }, 252 [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = { 253 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15, 254 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP, 255 }, 256 [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = { 257 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31, 258 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP, 259 }, 260 [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = { 261 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15, 262 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4, 263 }, 264 [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = { 265 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15, 266 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 267 }, 268 [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = { 269 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15, 270 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP, 271 }, 272 [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = { 273 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31, 274 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP, 275 }, 276 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = { 277 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 32, .end = 63, 278 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 279 }, 280 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = { 281 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 0, .end = 31, 282 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 283 }, 284 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = { 285 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 32, .end = 63, 286 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 287 }, 288 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = { 289 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 0, .end = 31, 290 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 291 }, 292 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = { 293 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63, 294 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 295 }, 296 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = { 297 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31, 298 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 299 }, 300 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = { 301 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 32, .end = 63, 302 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 303 }, 304 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = { 305 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 0, .end = 31, 306 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6, 307 }, 308 [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = { 309 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31, 310 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4, 311 }, 312 [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = { 313 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63, 314 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4, 315 }, 316 [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = { 317 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 0, .end = 31, 318 }, 319 [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = { 320 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 32, .end = 63, 321 }, 322 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = { 323 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 32, .end = 63, 324 }, 325 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = { 326 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 0, .end = 31, 327 }, 328 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = { 329 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 32, .end = 63, 330 }, 331 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = { 332 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 0, .end = 31, 333 }, 334 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = { 335 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 32, .end = 63, 336 }, 337 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = { 338 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 0, .end = 31, 339 }, 340 [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = { 341 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 32, .end = 63, 342 }, 343 [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = { 344 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 0, .end = 31, 345 }, 346 [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = { 347 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 0, .end = 15, 348 }, 349 }; 350 351 #define MAX_VLANS 2 352 struct dr_action_vlan_info { 353 int count; 354 u32 headers[MAX_VLANS]; 355 }; 356 357 struct dr_action_apply_attr { 358 u32 modify_index; 359 u16 modify_actions; 360 u32 decap_index; 361 u16 decap_actions; 362 u8 decap_with_vlan:1; 363 u64 final_icm_addr; 364 u32 flow_tag; 365 u32 ctr_id; 366 u16 gvmi; 367 u16 hit_gvmi; 368 u32 reformat_id; 369 u32 reformat_size; 370 struct dr_action_vlan_info vlans; 371 }; 372 373 static int 374 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 375 enum mlx5dr_action_type *action_type) 376 { 377 switch (reformat_type) { 378 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 379 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 380 break; 381 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 382 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 383 break; 384 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 385 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 386 break; 387 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 388 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 389 break; 390 default: 391 return -EINVAL; 392 } 393 394 return 0; 395 } 396 397 static void dr_actions_init_next_ste(u8 **last_ste, 398 u32 *added_stes, 399 enum mlx5dr_ste_entry_type entry_type, 400 u16 gvmi) 401 { 402 (*added_stes)++; 403 *last_ste += DR_STE_SIZE; 404 mlx5dr_ste_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, entry_type, gvmi); 405 } 406 407 static void dr_actions_apply_tx(struct mlx5dr_domain *dmn, 408 u8 *action_type_set, 409 u8 *last_ste, 410 struct dr_action_apply_attr *attr, 411 u32 *added_stes) 412 { 413 bool encap = action_type_set[DR_ACTION_TYP_L2_TO_TNL_L2] || 414 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]; 415 416 /* We want to make sure the modify header comes before L2 417 * encapsulation. The reason for that is that we support 418 * modify headers for outer headers only 419 */ 420 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) { 421 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT); 422 mlx5dr_ste_set_rewrite_actions(last_ste, 423 attr->modify_actions, 424 attr->modify_index); 425 } 426 427 if (action_type_set[DR_ACTION_TYP_PUSH_VLAN]) { 428 int i; 429 430 for (i = 0; i < attr->vlans.count; i++) { 431 if (i || action_type_set[DR_ACTION_TYP_MODIFY_HDR]) 432 dr_actions_init_next_ste(&last_ste, 433 added_stes, 434 MLX5DR_STE_TYPE_TX, 435 attr->gvmi); 436 437 mlx5dr_ste_set_tx_push_vlan(last_ste, 438 attr->vlans.headers[i], 439 encap); 440 } 441 } 442 443 if (encap) { 444 /* Modify header and encapsulation require a different STEs. 445 * Since modify header STE format doesn't support encapsulation 446 * tunneling_action. 447 */ 448 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR] || 449 action_type_set[DR_ACTION_TYP_PUSH_VLAN]) 450 dr_actions_init_next_ste(&last_ste, 451 added_stes, 452 MLX5DR_STE_TYPE_TX, 453 attr->gvmi); 454 455 mlx5dr_ste_set_tx_encap(last_ste, 456 attr->reformat_id, 457 attr->reformat_size, 458 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]); 459 /* Whenever prio_tag_required enabled, we can be sure that the 460 * previous table (ACL) already push vlan to our packet, 461 * And due to HW limitation we need to set this bit, otherwise 462 * push vlan + reformat will not work. 463 */ 464 if (MLX5_CAP_GEN(dmn->mdev, prio_tag_required)) 465 mlx5dr_ste_set_go_back_bit(last_ste); 466 } 467 468 if (action_type_set[DR_ACTION_TYP_CTR]) 469 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id); 470 } 471 472 static void dr_actions_apply_rx(u8 *action_type_set, 473 u8 *last_ste, 474 struct dr_action_apply_attr *attr, 475 u32 *added_stes) 476 { 477 if (action_type_set[DR_ACTION_TYP_CTR]) 478 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id); 479 480 if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) { 481 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT); 482 mlx5dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan); 483 mlx5dr_ste_set_rewrite_actions(last_ste, 484 attr->decap_actions, 485 attr->decap_index); 486 } 487 488 if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2]) 489 mlx5dr_ste_set_rx_decap(last_ste); 490 491 if (action_type_set[DR_ACTION_TYP_POP_VLAN]) { 492 int i; 493 494 for (i = 0; i < attr->vlans.count; i++) { 495 if (i || 496 action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2] || 497 action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) 498 dr_actions_init_next_ste(&last_ste, 499 added_stes, 500 MLX5DR_STE_TYPE_RX, 501 attr->gvmi); 502 503 mlx5dr_ste_set_rx_pop_vlan(last_ste); 504 } 505 } 506 507 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) { 508 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT) 509 dr_actions_init_next_ste(&last_ste, 510 added_stes, 511 MLX5DR_STE_TYPE_MODIFY_PKT, 512 attr->gvmi); 513 else 514 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT); 515 516 mlx5dr_ste_set_rewrite_actions(last_ste, 517 attr->modify_actions, 518 attr->modify_index); 519 } 520 521 if (action_type_set[DR_ACTION_TYP_TAG]) { 522 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT) 523 dr_actions_init_next_ste(&last_ste, 524 added_stes, 525 MLX5DR_STE_TYPE_RX, 526 attr->gvmi); 527 528 mlx5dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag); 529 } 530 } 531 532 /* Apply the actions on the rule STE array starting from the last_ste. 533 * Actions might require more than one STE, new_num_stes will return 534 * the new size of the STEs array, rule with actions. 535 */ 536 static void dr_actions_apply(struct mlx5dr_domain *dmn, 537 enum mlx5dr_ste_entry_type ste_type, 538 u8 *action_type_set, 539 u8 *last_ste, 540 struct dr_action_apply_attr *attr, 541 u32 *new_num_stes) 542 { 543 u32 added_stes = 0; 544 545 if (ste_type == MLX5DR_STE_TYPE_RX) 546 dr_actions_apply_rx(action_type_set, last_ste, attr, &added_stes); 547 else 548 dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes); 549 550 last_ste += added_stes * DR_STE_SIZE; 551 *new_num_stes += added_stes; 552 553 mlx5dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); 554 mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); 555 } 556 557 static enum dr_action_domain 558 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 559 enum mlx5dr_ste_entry_type ste_type) 560 { 561 switch (domain) { 562 case MLX5DR_DOMAIN_TYPE_NIC_RX: 563 return DR_ACTION_DOMAIN_NIC_INGRESS; 564 case MLX5DR_DOMAIN_TYPE_NIC_TX: 565 return DR_ACTION_DOMAIN_NIC_EGRESS; 566 case MLX5DR_DOMAIN_TYPE_FDB: 567 if (ste_type == MLX5DR_STE_TYPE_RX) 568 return DR_ACTION_DOMAIN_FDB_INGRESS; 569 return DR_ACTION_DOMAIN_FDB_EGRESS; 570 default: 571 WARN_ON(true); 572 return DR_ACTION_DOMAIN_MAX; 573 } 574 } 575 576 static 577 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 578 u32 action_type, 579 u32 *state) 580 { 581 u32 cur_state = *state; 582 583 /* Check action state machine is valid */ 584 *state = next_action_state[action_domain][cur_state][action_type]; 585 586 if (*state == DR_ACTION_STATE_ERR) 587 return -EOPNOTSUPP; 588 589 return 0; 590 } 591 592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 593 struct mlx5dr_action *dest_action, 594 u64 *final_icm_addr) 595 { 596 int ret; 597 598 switch (dest_action->action_type) { 599 case DR_ACTION_TYP_FT: 600 /* Allow destination flow table only if table is a terminating 601 * table, since there is an *assumption* that in such case FW 602 * will recalculate the CS. 603 */ 604 if (dest_action->dest_tbl.is_fw_tbl) { 605 *final_icm_addr = dest_action->dest_tbl.fw_tbl.rx_icm_addr; 606 } else { 607 mlx5dr_dbg(dmn, 608 "Destination FT should be terminating when modify TTL is used\n"); 609 return -EINVAL; 610 } 611 break; 612 613 case DR_ACTION_TYP_VPORT: 614 /* If destination is vport we will get the FW flow table 615 * that recalculates the CS and forwards to the vport. 616 */ 617 ret = mlx5dr_domain_cache_get_recalc_cs_ft_addr(dest_action->vport.dmn, 618 dest_action->vport.caps->num, 619 final_icm_addr); 620 if (ret) { 621 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 622 return ret; 623 } 624 break; 625 626 default: 627 break; 628 } 629 630 return 0; 631 } 632 633 #define WITH_VLAN_NUM_HW_ACTIONS 6 634 635 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 636 struct mlx5dr_matcher_rx_tx *nic_matcher, 637 struct mlx5dr_action *actions[], 638 u32 num_actions, 639 u8 *ste_arr, 640 u32 *new_hw_ste_arr_sz) 641 { 642 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 643 bool rx_rule = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX; 644 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 645 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 646 struct mlx5dr_action *dest_action = NULL; 647 u32 state = DR_ACTION_STATE_NO_ACTION; 648 struct dr_action_apply_attr attr = {}; 649 enum dr_action_domain action_domain; 650 bool recalc_cs_required = false; 651 u8 *last_ste; 652 int i, ret; 653 654 attr.gvmi = dmn->info.caps.gvmi; 655 attr.hit_gvmi = dmn->info.caps.gvmi; 656 attr.final_icm_addr = nic_dmn->default_icm_addr; 657 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->ste_type); 658 659 for (i = 0; i < num_actions; i++) { 660 struct mlx5dr_action *action; 661 int max_actions_type = 1; 662 u32 action_type; 663 664 action = actions[i]; 665 action_type = action->action_type; 666 667 switch (action_type) { 668 case DR_ACTION_TYP_DROP: 669 attr.final_icm_addr = nic_dmn->drop_icm_addr; 670 break; 671 case DR_ACTION_TYP_FT: 672 dest_action = action; 673 if (!action->dest_tbl.is_fw_tbl) { 674 if (action->dest_tbl.tbl->dmn != dmn) { 675 mlx5dr_dbg(dmn, 676 "Destination table belongs to a different domain\n"); 677 goto out_invalid_arg; 678 } 679 if (action->dest_tbl.tbl->level <= matcher->tbl->level) { 680 mlx5_core_warn_once(dmn->mdev, 681 "Connecting table to a lower/same level destination table\n"); 682 mlx5dr_dbg(dmn, 683 "Connecting table at level %d to a destination table at level %d\n", 684 matcher->tbl->level, 685 action->dest_tbl.tbl->level); 686 } 687 attr.final_icm_addr = rx_rule ? 688 action->dest_tbl.tbl->rx.s_anchor->chunk->icm_addr : 689 action->dest_tbl.tbl->tx.s_anchor->chunk->icm_addr; 690 } else { 691 struct mlx5dr_cmd_query_flow_table_details output; 692 int ret; 693 694 /* get the relevant addresses */ 695 if (!action->dest_tbl.fw_tbl.rx_icm_addr) { 696 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 697 action->dest_tbl.fw_tbl.type, 698 action->dest_tbl.fw_tbl.id, 699 &output); 700 if (!ret) { 701 action->dest_tbl.fw_tbl.tx_icm_addr = 702 output.sw_owner_icm_root_1; 703 action->dest_tbl.fw_tbl.rx_icm_addr = 704 output.sw_owner_icm_root_0; 705 } else { 706 mlx5dr_dbg(dmn, 707 "Failed mlx5_cmd_query_flow_table ret: %d\n", 708 ret); 709 return ret; 710 } 711 } 712 attr.final_icm_addr = rx_rule ? 713 action->dest_tbl.fw_tbl.rx_icm_addr : 714 action->dest_tbl.fw_tbl.tx_icm_addr; 715 } 716 break; 717 case DR_ACTION_TYP_QP: 718 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 719 goto out_invalid_arg; 720 case DR_ACTION_TYP_CTR: 721 attr.ctr_id = action->ctr.ctr_id + 722 action->ctr.offeset; 723 break; 724 case DR_ACTION_TYP_TAG: 725 attr.flow_tag = action->flow_tag; 726 break; 727 case DR_ACTION_TYP_TNL_L2_TO_L2: 728 break; 729 case DR_ACTION_TYP_TNL_L3_TO_L2: 730 attr.decap_index = action->rewrite.index; 731 attr.decap_actions = action->rewrite.num_of_actions; 732 attr.decap_with_vlan = 733 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 734 break; 735 case DR_ACTION_TYP_MODIFY_HDR: 736 attr.modify_index = action->rewrite.index; 737 attr.modify_actions = action->rewrite.num_of_actions; 738 recalc_cs_required = action->rewrite.modify_ttl; 739 break; 740 case DR_ACTION_TYP_L2_TO_TNL_L2: 741 case DR_ACTION_TYP_L2_TO_TNL_L3: 742 attr.reformat_size = action->reformat.reformat_size; 743 attr.reformat_id = action->reformat.reformat_id; 744 break; 745 case DR_ACTION_TYP_VPORT: 746 attr.hit_gvmi = action->vport.caps->vhca_gvmi; 747 dest_action = action; 748 if (rx_rule) { 749 /* Loopback on WIRE vport is not supported */ 750 if (action->vport.caps->num == WIRE_PORT) 751 goto out_invalid_arg; 752 753 attr.final_icm_addr = action->vport.caps->icm_address_rx; 754 } else { 755 attr.final_icm_addr = action->vport.caps->icm_address_tx; 756 } 757 break; 758 case DR_ACTION_TYP_POP_VLAN: 759 max_actions_type = MAX_VLANS; 760 attr.vlans.count++; 761 break; 762 case DR_ACTION_TYP_PUSH_VLAN: 763 max_actions_type = MAX_VLANS; 764 if (attr.vlans.count == MAX_VLANS) 765 return -EINVAL; 766 767 attr.vlans.headers[attr.vlans.count++] = action->push_vlan.vlan_hdr; 768 break; 769 default: 770 goto out_invalid_arg; 771 } 772 773 /* Check action duplication */ 774 if (++action_type_set[action_type] > max_actions_type) { 775 mlx5dr_dbg(dmn, "Action type %d supports only max %d time(s)\n", 776 action_type, max_actions_type); 777 goto out_invalid_arg; 778 } 779 780 /* Check action state machine is valid */ 781 if (dr_action_validate_and_get_next_state(action_domain, 782 action_type, 783 &state)) { 784 mlx5dr_dbg(dmn, "Invalid action sequence provided\n"); 785 return -EOPNOTSUPP; 786 } 787 } 788 789 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 790 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 791 792 /* Due to a HW bug, modifying TTL on RX flows will cause an incorrect 793 * checksum calculation. In this case we will use a FW table to 794 * recalculate. 795 */ 796 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB && 797 rx_rule && recalc_cs_required && dest_action) { 798 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 799 if (ret) { 800 mlx5dr_dbg(dmn, 801 "Failed to handle checksum recalculation err %d\n", 802 ret); 803 return ret; 804 } 805 } 806 807 dr_actions_apply(dmn, 808 nic_dmn->ste_type, 809 action_type_set, 810 last_ste, 811 &attr, 812 new_hw_ste_arr_sz); 813 814 return 0; 815 816 out_invalid_arg: 817 return -EINVAL; 818 } 819 820 #define CVLAN_ETHERTYPE 0x8100 821 #define SVLAN_ETHERTYPE 0x88a8 822 #define HDR_LEN_L2_ONLY 14 823 #define HDR_LEN_L2_VLAN 18 824 #define REWRITE_HW_ACTION_NUM 6 825 826 static int dr_actions_l2_rewrite(struct mlx5dr_domain *dmn, 827 struct mlx5dr_action *action, 828 void *data, size_t data_sz) 829 { 830 struct mlx5_ifc_l2_hdr_bits *l2_hdr = data; 831 u64 ops[REWRITE_HW_ACTION_NUM] = {}; 832 u32 hdr_fld_4b; 833 u16 hdr_fld_2b; 834 u16 vlan_type; 835 bool vlan; 836 int i = 0; 837 int ret; 838 839 vlan = (data_sz != HDR_LEN_L2_ONLY); 840 841 /* dmac_47_16 */ 842 MLX5_SET(dr_action_hw_set, ops + i, 843 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 844 MLX5_SET(dr_action_hw_set, ops + i, 845 destination_length, 0); 846 MLX5_SET(dr_action_hw_set, ops + i, 847 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0); 848 MLX5_SET(dr_action_hw_set, ops + i, 849 destination_left_shifter, 16); 850 hdr_fld_4b = MLX5_GET(l2_hdr, l2_hdr, dmac_47_16); 851 MLX5_SET(dr_action_hw_set, ops + i, 852 inline_data, hdr_fld_4b); 853 i++; 854 855 /* smac_47_16 */ 856 MLX5_SET(dr_action_hw_set, ops + i, 857 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 858 MLX5_SET(dr_action_hw_set, ops + i, 859 destination_length, 0); 860 MLX5_SET(dr_action_hw_set, ops + i, 861 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1); 862 MLX5_SET(dr_action_hw_set, ops + i, 863 destination_left_shifter, 16); 864 hdr_fld_4b = (MLX5_GET(l2_hdr, l2_hdr, smac_31_0) >> 16 | 865 MLX5_GET(l2_hdr, l2_hdr, smac_47_32) << 16); 866 MLX5_SET(dr_action_hw_set, ops + i, 867 inline_data, hdr_fld_4b); 868 i++; 869 870 /* dmac_15_0 */ 871 MLX5_SET(dr_action_hw_set, ops + i, 872 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 873 MLX5_SET(dr_action_hw_set, ops + i, 874 destination_length, 16); 875 MLX5_SET(dr_action_hw_set, ops + i, 876 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0); 877 MLX5_SET(dr_action_hw_set, ops + i, 878 destination_left_shifter, 0); 879 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, dmac_15_0); 880 MLX5_SET(dr_action_hw_set, ops + i, 881 inline_data, hdr_fld_2b); 882 i++; 883 884 /* ethertype + (optional) vlan */ 885 MLX5_SET(dr_action_hw_set, ops + i, 886 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 887 MLX5_SET(dr_action_hw_set, ops + i, 888 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2); 889 MLX5_SET(dr_action_hw_set, ops + i, 890 destination_left_shifter, 32); 891 if (!vlan) { 892 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype); 893 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_2b); 894 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 16); 895 } else { 896 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype); 897 vlan_type = hdr_fld_2b == SVLAN_ETHERTYPE ? DR_STE_SVLAN : DR_STE_CVLAN; 898 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan); 899 hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b; 900 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_4b); 901 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 18); 902 } 903 i++; 904 905 /* smac_15_0 */ 906 MLX5_SET(dr_action_hw_set, ops + i, 907 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 908 MLX5_SET(dr_action_hw_set, ops + i, 909 destination_length, 16); 910 MLX5_SET(dr_action_hw_set, ops + i, 911 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1); 912 MLX5_SET(dr_action_hw_set, ops + i, 913 destination_left_shifter, 0); 914 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, smac_31_0); 915 MLX5_SET(dr_action_hw_set, ops + i, 916 inline_data, hdr_fld_2b); 917 i++; 918 919 if (vlan) { 920 MLX5_SET(dr_action_hw_set, ops + i, 921 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 922 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan_type); 923 MLX5_SET(dr_action_hw_set, ops + i, 924 inline_data, hdr_fld_2b); 925 MLX5_SET(dr_action_hw_set, ops + i, 926 destination_length, 16); 927 MLX5_SET(dr_action_hw_set, ops + i, 928 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2); 929 MLX5_SET(dr_action_hw_set, ops + i, 930 destination_left_shifter, 0); 931 i++; 932 } 933 934 action->rewrite.data = (void *)ops; 935 action->rewrite.num_of_actions = i; 936 action->rewrite.chunk->byte_size = i * sizeof(*ops); 937 938 ret = mlx5dr_send_postsend_action(dmn, action); 939 if (ret) { 940 mlx5dr_dbg(dmn, "Writing encapsulation action to ICM failed\n"); 941 return ret; 942 } 943 944 return 0; 945 } 946 947 static struct mlx5dr_action * 948 dr_action_create_generic(enum mlx5dr_action_type action_type) 949 { 950 struct mlx5dr_action *action; 951 952 action = kzalloc(sizeof(*action), GFP_KERNEL); 953 if (!action) 954 return NULL; 955 956 action->action_type = action_type; 957 refcount_set(&action->refcount, 1); 958 959 return action; 960 } 961 962 struct mlx5dr_action *mlx5dr_action_create_drop(void) 963 { 964 return dr_action_create_generic(DR_ACTION_TYP_DROP); 965 } 966 967 struct mlx5dr_action * 968 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 969 { 970 struct mlx5dr_action *action; 971 972 refcount_inc(&tbl->refcount); 973 974 action = dr_action_create_generic(DR_ACTION_TYP_FT); 975 if (!action) 976 goto dec_ref; 977 978 action->dest_tbl.tbl = tbl; 979 980 return action; 981 982 dec_ref: 983 refcount_dec(&tbl->refcount); 984 return NULL; 985 } 986 987 struct mlx5dr_action * 988 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 989 struct mlx5dr_action_dest *dests, 990 u32 num_of_dests) 991 { 992 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 993 struct mlx5dr_action **ref_actions; 994 struct mlx5dr_action *action; 995 bool reformat_req = false; 996 u32 num_of_ref = 0; 997 int ret; 998 int i; 999 1000 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1001 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 1002 return NULL; 1003 } 1004 1005 hw_dests = kzalloc(sizeof(*hw_dests) * num_of_dests, GFP_KERNEL); 1006 if (!hw_dests) 1007 return NULL; 1008 1009 ref_actions = kzalloc(sizeof(*ref_actions) * num_of_dests * 2, GFP_KERNEL); 1010 if (!ref_actions) 1011 goto free_hw_dests; 1012 1013 for (i = 0; i < num_of_dests; i++) { 1014 struct mlx5dr_action *reformat_action = dests[i].reformat; 1015 struct mlx5dr_action *dest_action = dests[i].dest; 1016 1017 ref_actions[num_of_ref++] = dest_action; 1018 1019 switch (dest_action->action_type) { 1020 case DR_ACTION_TYP_VPORT: 1021 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 1022 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 1023 hw_dests[i].vport.num = dest_action->vport.caps->num; 1024 hw_dests[i].vport.vhca_id = dest_action->vport.caps->vhca_gvmi; 1025 if (reformat_action) { 1026 reformat_req = true; 1027 hw_dests[i].vport.reformat_id = 1028 reformat_action->reformat.reformat_id; 1029 ref_actions[num_of_ref++] = reformat_action; 1030 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 1031 } 1032 break; 1033 1034 case DR_ACTION_TYP_FT: 1035 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 1036 if (dest_action->dest_tbl.is_fw_tbl) 1037 hw_dests[i].ft_id = dest_action->dest_tbl.fw_tbl.id; 1038 else 1039 hw_dests[i].ft_id = dest_action->dest_tbl.tbl->table_id; 1040 break; 1041 1042 default: 1043 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 1044 goto free_ref_actions; 1045 } 1046 } 1047 1048 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1049 if (!action) 1050 goto free_ref_actions; 1051 1052 ret = mlx5dr_fw_create_md_tbl(dmn, 1053 hw_dests, 1054 num_of_dests, 1055 reformat_req, 1056 &action->dest_tbl.fw_tbl.id, 1057 &action->dest_tbl.fw_tbl.group_id); 1058 if (ret) 1059 goto free_action; 1060 1061 refcount_inc(&dmn->refcount); 1062 1063 for (i = 0; i < num_of_ref; i++) 1064 refcount_inc(&ref_actions[i]->refcount); 1065 1066 action->dest_tbl.is_fw_tbl = true; 1067 action->dest_tbl.fw_tbl.dmn = dmn; 1068 action->dest_tbl.fw_tbl.type = FS_FT_FDB; 1069 action->dest_tbl.fw_tbl.ref_actions = ref_actions; 1070 action->dest_tbl.fw_tbl.num_of_ref_actions = num_of_ref; 1071 1072 kfree(hw_dests); 1073 1074 return action; 1075 1076 free_action: 1077 kfree(action); 1078 free_ref_actions: 1079 kfree(ref_actions); 1080 free_hw_dests: 1081 kfree(hw_dests); 1082 return NULL; 1083 } 1084 1085 struct mlx5dr_action * 1086 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 1087 struct mlx5_flow_table *ft) 1088 { 1089 struct mlx5dr_action *action; 1090 1091 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1092 if (!action) 1093 return NULL; 1094 1095 action->dest_tbl.is_fw_tbl = 1; 1096 action->dest_tbl.fw_tbl.type = ft->type; 1097 action->dest_tbl.fw_tbl.id = ft->id; 1098 action->dest_tbl.fw_tbl.dmn = dmn; 1099 1100 refcount_inc(&dmn->refcount); 1101 1102 return action; 1103 } 1104 1105 struct mlx5dr_action * 1106 mlx5dr_action_create_flow_counter(u32 counter_id) 1107 { 1108 struct mlx5dr_action *action; 1109 1110 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 1111 if (!action) 1112 return NULL; 1113 1114 action->ctr.ctr_id = counter_id; 1115 1116 return action; 1117 } 1118 1119 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 1120 { 1121 struct mlx5dr_action *action; 1122 1123 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 1124 if (!action) 1125 return NULL; 1126 1127 action->flow_tag = tag_value & 0xffffff; 1128 1129 return action; 1130 } 1131 1132 static int 1133 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1134 struct mlx5dr_domain *dmn, 1135 size_t data_sz, 1136 void *data) 1137 { 1138 if ((!data && data_sz) || (data && !data_sz) || reformat_type > 1139 DR_ACTION_TYP_L2_TO_TNL_L3) { 1140 mlx5dr_dbg(dmn, "Invalid reformat parameter!\n"); 1141 goto out_err; 1142 } 1143 1144 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1145 return 0; 1146 1147 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1148 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1149 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1150 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1151 goto out_err; 1152 } 1153 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1154 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1155 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1156 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1157 goto out_err; 1158 } 1159 } 1160 1161 return 0; 1162 1163 out_err: 1164 return -EINVAL; 1165 } 1166 1167 #define ACTION_CACHE_LINE_SIZE 64 1168 1169 static int 1170 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1171 size_t data_sz, void *data, 1172 struct mlx5dr_action *action) 1173 { 1174 u32 reformat_id; 1175 int ret; 1176 1177 switch (action->action_type) { 1178 case DR_ACTION_TYP_L2_TO_TNL_L2: 1179 case DR_ACTION_TYP_L2_TO_TNL_L3: 1180 { 1181 enum mlx5_reformat_ctx_type rt; 1182 1183 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1184 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1185 else 1186 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1187 1188 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, data_sz, data, 1189 &reformat_id); 1190 if (ret) 1191 return ret; 1192 1193 action->reformat.reformat_id = reformat_id; 1194 action->reformat.reformat_size = data_sz; 1195 return 0; 1196 } 1197 case DR_ACTION_TYP_TNL_L2_TO_L2: 1198 { 1199 return 0; 1200 } 1201 case DR_ACTION_TYP_TNL_L3_TO_L2: 1202 { 1203 /* Only Ethernet frame is supported, with VLAN (18) or without (14) */ 1204 if (data_sz != HDR_LEN_L2_ONLY && data_sz != HDR_LEN_L2_VLAN) 1205 return -EINVAL; 1206 1207 action->rewrite.chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, 1208 DR_CHUNK_SIZE_8); 1209 if (!action->rewrite.chunk) 1210 return -ENOMEM; 1211 1212 action->rewrite.index = (action->rewrite.chunk->icm_addr - 1213 dmn->info.caps.hdr_modify_icm_addr) / 1214 ACTION_CACHE_LINE_SIZE; 1215 1216 ret = dr_actions_l2_rewrite(dmn, action, data, data_sz); 1217 if (ret) { 1218 mlx5dr_icm_free_chunk(action->rewrite.chunk); 1219 return ret; 1220 } 1221 return 0; 1222 } 1223 default: 1224 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1225 return -EINVAL; 1226 } 1227 } 1228 1229 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1230 { 1231 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1232 } 1233 1234 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1235 __be32 vlan_hdr) 1236 { 1237 u32 vlan_hdr_h = ntohl(vlan_hdr); 1238 u16 ethertype = vlan_hdr_h >> 16; 1239 struct mlx5dr_action *action; 1240 1241 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1242 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1243 return NULL; 1244 } 1245 1246 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1247 if (!action) 1248 return NULL; 1249 1250 action->push_vlan.vlan_hdr = vlan_hdr_h; 1251 return action; 1252 } 1253 1254 struct mlx5dr_action * 1255 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1256 enum mlx5dr_action_reformat_type reformat_type, 1257 size_t data_sz, 1258 void *data) 1259 { 1260 enum mlx5dr_action_type action_type; 1261 struct mlx5dr_action *action; 1262 int ret; 1263 1264 refcount_inc(&dmn->refcount); 1265 1266 /* General checks */ 1267 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1268 if (ret) { 1269 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1270 goto dec_ref; 1271 } 1272 1273 ret = dr_action_verify_reformat_params(action_type, dmn, data_sz, data); 1274 if (ret) 1275 goto dec_ref; 1276 1277 action = dr_action_create_generic(action_type); 1278 if (!action) 1279 goto dec_ref; 1280 1281 action->reformat.dmn = dmn; 1282 1283 ret = dr_action_create_reformat_action(dmn, 1284 data_sz, 1285 data, 1286 action); 1287 if (ret) { 1288 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1289 goto free_action; 1290 } 1291 1292 return action; 1293 1294 free_action: 1295 kfree(action); 1296 dec_ref: 1297 refcount_dec(&dmn->refcount); 1298 return NULL; 1299 } 1300 1301 static const struct dr_action_modify_field_conv * 1302 dr_action_modify_get_hw_info(u16 sw_field) 1303 { 1304 const struct dr_action_modify_field_conv *hw_action_info; 1305 1306 if (sw_field >= ARRAY_SIZE(dr_action_conv_arr)) 1307 goto not_found; 1308 1309 hw_action_info = &dr_action_conv_arr[sw_field]; 1310 if (!hw_action_info->end && !hw_action_info->start) 1311 goto not_found; 1312 1313 return hw_action_info; 1314 1315 not_found: 1316 return NULL; 1317 } 1318 1319 static int 1320 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1321 __be64 *sw_action, 1322 __be64 *hw_action, 1323 const struct dr_action_modify_field_conv **ret_hw_info) 1324 { 1325 const struct dr_action_modify_field_conv *hw_action_info; 1326 u8 max_length; 1327 u16 sw_field; 1328 u32 data; 1329 1330 /* Get SW modify action data */ 1331 sw_field = MLX5_GET(set_action_in, sw_action, field); 1332 data = MLX5_GET(set_action_in, sw_action, data); 1333 1334 /* Convert SW data to HW modify action format */ 1335 hw_action_info = dr_action_modify_get_hw_info(sw_field); 1336 if (!hw_action_info) { 1337 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1338 return -EINVAL; 1339 } 1340 1341 max_length = hw_action_info->end - hw_action_info->start + 1; 1342 1343 MLX5_SET(dr_action_hw_set, hw_action, 1344 opcode, MLX5DR_ACTION_MDFY_HW_OP_ADD); 1345 1346 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code, 1347 hw_action_info->hw_field); 1348 1349 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter, 1350 hw_action_info->start); 1351 1352 /* PRM defines that length zero specific length of 32bits */ 1353 MLX5_SET(dr_action_hw_set, hw_action, destination_length, 1354 max_length == 32 ? 0 : max_length); 1355 1356 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data); 1357 1358 *ret_hw_info = hw_action_info; 1359 1360 return 0; 1361 } 1362 1363 static int 1364 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1365 __be64 *sw_action, 1366 __be64 *hw_action, 1367 const struct dr_action_modify_field_conv **ret_hw_info) 1368 { 1369 const struct dr_action_modify_field_conv *hw_action_info; 1370 u8 offset, length, max_length; 1371 u16 sw_field; 1372 u32 data; 1373 1374 /* Get SW modify action data */ 1375 length = MLX5_GET(set_action_in, sw_action, length); 1376 offset = MLX5_GET(set_action_in, sw_action, offset); 1377 sw_field = MLX5_GET(set_action_in, sw_action, field); 1378 data = MLX5_GET(set_action_in, sw_action, data); 1379 1380 /* Convert SW data to HW modify action format */ 1381 hw_action_info = dr_action_modify_get_hw_info(sw_field); 1382 if (!hw_action_info) { 1383 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1384 return -EINVAL; 1385 } 1386 1387 /* PRM defines that length zero specific length of 32bits */ 1388 length = length ? length : 32; 1389 1390 max_length = hw_action_info->end - hw_action_info->start + 1; 1391 1392 if (length + offset > max_length) { 1393 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1394 return -EINVAL; 1395 } 1396 1397 MLX5_SET(dr_action_hw_set, hw_action, 1398 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET); 1399 1400 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code, 1401 hw_action_info->hw_field); 1402 1403 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter, 1404 hw_action_info->start + offset); 1405 1406 MLX5_SET(dr_action_hw_set, hw_action, destination_length, 1407 length == 32 ? 0 : length); 1408 1409 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data); 1410 1411 *ret_hw_info = hw_action_info; 1412 1413 return 0; 1414 } 1415 1416 static int 1417 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1418 __be64 *sw_action, 1419 __be64 *hw_action, 1420 const struct dr_action_modify_field_conv **ret_dst_hw_info, 1421 const struct dr_action_modify_field_conv **ret_src_hw_info) 1422 { 1423 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1424 const struct dr_action_modify_field_conv *hw_dst_action_info; 1425 const struct dr_action_modify_field_conv *hw_src_action_info; 1426 u16 src_field, dst_field; 1427 1428 /* Get SW modify action data */ 1429 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1430 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1431 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1432 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1433 length = MLX5_GET(copy_action_in, sw_action, length); 1434 1435 /* Convert SW data to HW modify action format */ 1436 hw_src_action_info = dr_action_modify_get_hw_info(src_field); 1437 hw_dst_action_info = dr_action_modify_get_hw_info(dst_field); 1438 if (!hw_src_action_info || !hw_dst_action_info) { 1439 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1440 return -EINVAL; 1441 } 1442 1443 /* PRM defines that length zero specific length of 32bits */ 1444 length = length ? length : 32; 1445 1446 src_max_length = hw_src_action_info->end - 1447 hw_src_action_info->start + 1; 1448 dst_max_length = hw_dst_action_info->end - 1449 hw_dst_action_info->start + 1; 1450 1451 if (length + src_offset > src_max_length || 1452 length + dst_offset > dst_max_length) { 1453 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1454 return -EINVAL; 1455 } 1456 1457 MLX5_SET(dr_action_hw_copy, hw_action, 1458 opcode, MLX5DR_ACTION_MDFY_HW_OP_COPY); 1459 1460 MLX5_SET(dr_action_hw_copy, hw_action, destination_field_code, 1461 hw_dst_action_info->hw_field); 1462 1463 MLX5_SET(dr_action_hw_copy, hw_action, destination_left_shifter, 1464 hw_dst_action_info->start + dst_offset); 1465 1466 MLX5_SET(dr_action_hw_copy, hw_action, destination_length, 1467 length == 32 ? 0 : length); 1468 1469 MLX5_SET(dr_action_hw_copy, hw_action, source_field_code, 1470 hw_src_action_info->hw_field); 1471 1472 MLX5_SET(dr_action_hw_copy, hw_action, source_left_shifter, 1473 hw_src_action_info->start + dst_offset); 1474 1475 *ret_dst_hw_info = hw_dst_action_info; 1476 *ret_src_hw_info = hw_src_action_info; 1477 1478 return 0; 1479 } 1480 1481 static int 1482 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1483 __be64 *sw_action, 1484 __be64 *hw_action, 1485 const struct dr_action_modify_field_conv **ret_dst_hw_info, 1486 const struct dr_action_modify_field_conv **ret_src_hw_info) 1487 { 1488 u8 action; 1489 int ret; 1490 1491 *hw_action = 0; 1492 *ret_src_hw_info = NULL; 1493 1494 /* Get SW modify action type */ 1495 action = MLX5_GET(set_action_in, sw_action, action_type); 1496 1497 switch (action) { 1498 case MLX5_ACTION_TYPE_SET: 1499 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1500 hw_action, 1501 ret_dst_hw_info); 1502 break; 1503 1504 case MLX5_ACTION_TYPE_ADD: 1505 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1506 hw_action, 1507 ret_dst_hw_info); 1508 break; 1509 1510 case MLX5_ACTION_TYPE_COPY: 1511 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1512 hw_action, 1513 ret_dst_hw_info, 1514 ret_src_hw_info); 1515 break; 1516 1517 default: 1518 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1519 ret = -EOPNOTSUPP; 1520 } 1521 1522 return ret; 1523 } 1524 1525 static int 1526 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1527 const __be64 *sw_action) 1528 { 1529 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1530 struct mlx5dr_domain *dmn = action->rewrite.dmn; 1531 1532 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1533 action->rewrite.allow_rx = 0; 1534 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1535 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1536 sw_field); 1537 return -EINVAL; 1538 } 1539 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1540 action->rewrite.allow_tx = 0; 1541 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1542 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1543 sw_field); 1544 return -EINVAL; 1545 } 1546 } 1547 1548 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) { 1549 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1550 return -EINVAL; 1551 } 1552 1553 return 0; 1554 } 1555 1556 static int 1557 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1558 const __be64 *sw_action) 1559 { 1560 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1561 struct mlx5dr_domain *dmn = action->rewrite.dmn; 1562 1563 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1564 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1565 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1566 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1567 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1568 sw_field); 1569 return -EINVAL; 1570 } 1571 1572 return 0; 1573 } 1574 1575 static int 1576 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1577 const __be64 *sw_action) 1578 { 1579 struct mlx5dr_domain *dmn = action->rewrite.dmn; 1580 u16 sw_fields[2]; 1581 int i; 1582 1583 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1584 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1585 1586 for (i = 0; i < 2; i++) { 1587 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1588 action->rewrite.allow_rx = 0; 1589 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1590 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1591 sw_fields[i]); 1592 return -EINVAL; 1593 } 1594 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1595 action->rewrite.allow_tx = 0; 1596 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1597 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1598 sw_fields[i]); 1599 return -EINVAL; 1600 } 1601 } 1602 } 1603 1604 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) { 1605 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1606 return -EINVAL; 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int 1613 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1614 const __be64 *sw_action) 1615 { 1616 struct mlx5dr_domain *dmn = action->rewrite.dmn; 1617 u8 action_type; 1618 int ret; 1619 1620 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1621 1622 switch (action_type) { 1623 case MLX5_ACTION_TYPE_SET: 1624 ret = dr_action_modify_check_set_field_limitation(action, 1625 sw_action); 1626 break; 1627 1628 case MLX5_ACTION_TYPE_ADD: 1629 ret = dr_action_modify_check_add_field_limitation(action, 1630 sw_action); 1631 break; 1632 1633 case MLX5_ACTION_TYPE_COPY: 1634 ret = dr_action_modify_check_copy_field_limitation(action, 1635 sw_action); 1636 break; 1637 1638 default: 1639 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1640 action_type); 1641 ret = -EOPNOTSUPP; 1642 } 1643 1644 return ret; 1645 } 1646 1647 static bool 1648 dr_action_modify_check_is_ttl_modify(const u64 *sw_action) 1649 { 1650 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1651 1652 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1653 } 1654 1655 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1656 u32 max_hw_actions, 1657 u32 num_sw_actions, 1658 __be64 sw_actions[], 1659 __be64 hw_actions[], 1660 u32 *num_hw_actions, 1661 bool *modify_ttl) 1662 { 1663 const struct dr_action_modify_field_conv *hw_dst_action_info; 1664 const struct dr_action_modify_field_conv *hw_src_action_info; 1665 u16 hw_field = MLX5DR_ACTION_MDFY_HW_FLD_RESERVED; 1666 u32 l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE; 1667 u32 l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE; 1668 struct mlx5dr_domain *dmn = action->rewrite.dmn; 1669 int ret, i, hw_idx = 0; 1670 __be64 *sw_action; 1671 __be64 hw_action; 1672 1673 *modify_ttl = false; 1674 1675 action->rewrite.allow_rx = 1; 1676 action->rewrite.allow_tx = 1; 1677 1678 for (i = 0; i < num_sw_actions; i++) { 1679 sw_action = &sw_actions[i]; 1680 1681 ret = dr_action_modify_check_field_limitation(action, 1682 sw_action); 1683 if (ret) 1684 return ret; 1685 1686 if (!(*modify_ttl)) 1687 *modify_ttl = dr_action_modify_check_is_ttl_modify(sw_action); 1688 1689 /* Convert SW action to HW action */ 1690 ret = dr_action_modify_sw_to_hw(dmn, 1691 sw_action, 1692 &hw_action, 1693 &hw_dst_action_info, 1694 &hw_src_action_info); 1695 if (ret) 1696 return ret; 1697 1698 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1699 if (l3_type && hw_dst_action_info->l3_type && 1700 hw_dst_action_info->l3_type != l3_type) { 1701 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1702 return -EINVAL; 1703 } 1704 if (hw_dst_action_info->l3_type) 1705 l3_type = hw_dst_action_info->l3_type; 1706 1707 /* Due to a HW limitation we cannot modify two different L4 types */ 1708 if (l4_type && hw_dst_action_info->l4_type && 1709 hw_dst_action_info->l4_type != l4_type) { 1710 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1711 return -EINVAL; 1712 } 1713 if (hw_dst_action_info->l4_type) 1714 l4_type = hw_dst_action_info->l4_type; 1715 1716 /* HW reads and executes two actions at once this means we 1717 * need to create a gap if two actions access the same field 1718 */ 1719 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1720 (hw_src_action_info && 1721 hw_field == hw_src_action_info->hw_field))) { 1722 /* Check if after gap insertion the total number of HW 1723 * modify actions doesn't exceeds the limit 1724 */ 1725 hw_idx++; 1726 if ((num_sw_actions + hw_idx - i) >= max_hw_actions) { 1727 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1728 return -EINVAL; 1729 } 1730 } 1731 hw_field = hw_dst_action_info->hw_field; 1732 1733 hw_actions[hw_idx] = hw_action; 1734 hw_idx++; 1735 } 1736 1737 *num_hw_actions = hw_idx; 1738 1739 return 0; 1740 } 1741 1742 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 1743 size_t actions_sz, 1744 __be64 actions[], 1745 struct mlx5dr_action *action) 1746 { 1747 struct mlx5dr_icm_chunk *chunk; 1748 u32 max_hw_actions; 1749 u32 num_hw_actions; 1750 u32 num_sw_actions; 1751 __be64 *hw_actions; 1752 bool modify_ttl; 1753 int ret; 1754 1755 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 1756 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 1757 1758 if (num_sw_actions > max_hw_actions) { 1759 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 1760 num_sw_actions, max_hw_actions); 1761 return -EINVAL; 1762 } 1763 1764 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16); 1765 if (!chunk) 1766 return -ENOMEM; 1767 1768 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 1769 if (!hw_actions) { 1770 ret = -ENOMEM; 1771 goto free_chunk; 1772 } 1773 1774 ret = dr_actions_convert_modify_header(action, 1775 max_hw_actions, 1776 num_sw_actions, 1777 actions, 1778 hw_actions, 1779 &num_hw_actions, 1780 &modify_ttl); 1781 if (ret) 1782 goto free_hw_actions; 1783 1784 action->rewrite.chunk = chunk; 1785 action->rewrite.modify_ttl = modify_ttl; 1786 action->rewrite.data = (u8 *)hw_actions; 1787 action->rewrite.num_of_actions = num_hw_actions; 1788 action->rewrite.index = (chunk->icm_addr - 1789 dmn->info.caps.hdr_modify_icm_addr) / 1790 ACTION_CACHE_LINE_SIZE; 1791 1792 ret = mlx5dr_send_postsend_action(dmn, action); 1793 if (ret) 1794 goto free_hw_actions; 1795 1796 return 0; 1797 1798 free_hw_actions: 1799 kfree(hw_actions); 1800 free_chunk: 1801 mlx5dr_icm_free_chunk(chunk); 1802 return ret; 1803 } 1804 1805 struct mlx5dr_action * 1806 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 1807 u32 flags, 1808 size_t actions_sz, 1809 __be64 actions[]) 1810 { 1811 struct mlx5dr_action *action; 1812 int ret = 0; 1813 1814 refcount_inc(&dmn->refcount); 1815 1816 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 1817 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 1818 goto dec_ref; 1819 } 1820 1821 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 1822 if (!action) 1823 goto dec_ref; 1824 1825 action->rewrite.dmn = dmn; 1826 1827 ret = dr_action_create_modify_action(dmn, 1828 actions_sz, 1829 actions, 1830 action); 1831 if (ret) { 1832 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 1833 goto free_action; 1834 } 1835 1836 return action; 1837 1838 free_action: 1839 kfree(action); 1840 dec_ref: 1841 refcount_dec(&dmn->refcount); 1842 return NULL; 1843 } 1844 1845 struct mlx5dr_action * 1846 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 1847 u32 vport, u8 vhca_id_valid, 1848 u16 vhca_id) 1849 { 1850 struct mlx5dr_cmd_vport_cap *vport_cap; 1851 struct mlx5dr_domain *vport_dmn; 1852 struct mlx5dr_action *action; 1853 u8 peer_vport; 1854 1855 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi); 1856 vport_dmn = peer_vport ? dmn->peer_dmn : dmn; 1857 if (!vport_dmn) { 1858 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 1859 return NULL; 1860 } 1861 1862 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1863 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 1864 return NULL; 1865 } 1866 1867 vport_cap = mlx5dr_get_vport_cap(&vport_dmn->info.caps, vport); 1868 if (!vport_cap) { 1869 mlx5dr_dbg(dmn, "Failed to get vport %d caps\n", vport); 1870 return NULL; 1871 } 1872 1873 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 1874 if (!action) 1875 return NULL; 1876 1877 action->vport.dmn = vport_dmn; 1878 action->vport.caps = vport_cap; 1879 1880 return action; 1881 } 1882 1883 int mlx5dr_action_destroy(struct mlx5dr_action *action) 1884 { 1885 if (refcount_read(&action->refcount) > 1) 1886 return -EBUSY; 1887 1888 switch (action->action_type) { 1889 case DR_ACTION_TYP_FT: 1890 if (action->dest_tbl.is_fw_tbl) 1891 refcount_dec(&action->dest_tbl.fw_tbl.dmn->refcount); 1892 else 1893 refcount_dec(&action->dest_tbl.tbl->refcount); 1894 1895 if (action->dest_tbl.is_fw_tbl && 1896 action->dest_tbl.fw_tbl.num_of_ref_actions) { 1897 struct mlx5dr_action **ref_actions; 1898 int i; 1899 1900 ref_actions = action->dest_tbl.fw_tbl.ref_actions; 1901 for (i = 0; i < action->dest_tbl.fw_tbl.num_of_ref_actions; i++) 1902 refcount_dec(&ref_actions[i]->refcount); 1903 1904 kfree(ref_actions); 1905 1906 mlx5dr_fw_destroy_md_tbl(action->dest_tbl.fw_tbl.dmn, 1907 action->dest_tbl.fw_tbl.id, 1908 action->dest_tbl.fw_tbl.group_id); 1909 } 1910 break; 1911 case DR_ACTION_TYP_TNL_L2_TO_L2: 1912 refcount_dec(&action->reformat.dmn->refcount); 1913 break; 1914 case DR_ACTION_TYP_TNL_L3_TO_L2: 1915 mlx5dr_icm_free_chunk(action->rewrite.chunk); 1916 refcount_dec(&action->reformat.dmn->refcount); 1917 break; 1918 case DR_ACTION_TYP_L2_TO_TNL_L2: 1919 case DR_ACTION_TYP_L2_TO_TNL_L3: 1920 mlx5dr_cmd_destroy_reformat_ctx((action->reformat.dmn)->mdev, 1921 action->reformat.reformat_id); 1922 refcount_dec(&action->reformat.dmn->refcount); 1923 break; 1924 case DR_ACTION_TYP_MODIFY_HDR: 1925 mlx5dr_icm_free_chunk(action->rewrite.chunk); 1926 kfree(action->rewrite.data); 1927 refcount_dec(&action->rewrite.dmn->refcount); 1928 break; 1929 default: 1930 break; 1931 } 1932 1933 kfree(action); 1934 return 0; 1935 } 1936