1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, u16 vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 393 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 394 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 395 } 396 397 /* reg_sfd_uc_lag_sub_port 398 * LAG sub port. 399 * Must be 0 if multichannel VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_lag_set_vid 406 * Set VID. 407 * 0 - Do not update VID. 408 * 1 - Set VID. 409 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 410 * Access: RW 411 * 412 * Note: Reserved when legacy bridge model is used. 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_lag_fid_vid 418 * Filtering ID or VLAN ID 419 * For SwitchX and SwitchX-2: 420 * - Dynamic entries (policy 2,3) use FID 421 * - Static entries (policy 0) use VID 422 * - When independent learning is configured, VID=FID 423 * For Spectrum: use FID for both Dynamic and Static entries. 424 * VID should not be used. 425 * Access: Index 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x08, false); 429 430 /* reg_sfd_uc_lag_lag_vid 431 * New vlan ID. 432 * Access: RW 433 * 434 * Note: Reserved when legacy bridge model is used and set_vid=0. 435 */ 436 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 437 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 438 439 /* reg_sfd_uc_lag_lag_id 440 * LAG Identifier - pointer into the LAG descriptor table. 441 * Access: RW 442 */ 443 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 444 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 445 446 static inline void 447 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 448 enum mlxsw_reg_sfd_rec_policy policy, 449 const char *mac, u16 fid_vid, 450 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 451 u16 lag_id) 452 { 453 mlxsw_reg_sfd_rec_pack(payload, rec_index, 454 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 455 mac, action); 456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 457 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 458 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 459 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 460 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 461 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 462 } 463 464 /* reg_sfd_mc_pgi 465 * 466 * Multicast port group index - index into the port group table. 467 * Value 0x1FFF indicates the pgi should point to the MID entry. 468 * For Spectrum this value must be set to 0x1FFF 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 472 MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_mc_fid_vid 475 * 476 * Filtering ID or VLAN ID 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_mc_mid 483 * 484 * Multicast identifier - global identifier that represents the multicast 485 * group across all devices. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 static inline void 492 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 493 const char *mac, u16 fid_vid, 494 enum mlxsw_reg_sfd_rec_action action, u16 mid) 495 { 496 mlxsw_reg_sfd_rec_pack(payload, rec_index, 497 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 498 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 499 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 500 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 501 } 502 503 /* reg_sfd_uc_tunnel_uip_msb 504 * When protocol is IPv4, the most significant byte of the underlay IPv4 505 * destination IP. 506 * When protocol is IPv6, reserved. 507 * Access: RW 508 */ 509 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 510 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 511 512 /* reg_sfd_uc_tunnel_fid 513 * Filtering ID. 514 * Access: Index 515 */ 516 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 517 MLXSW_REG_SFD_REC_LEN, 0x08, false); 518 519 enum mlxsw_reg_sfd_uc_tunnel_protocol { 520 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 521 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 522 }; 523 524 /* reg_sfd_uc_tunnel_protocol 525 * IP protocol. 526 * Access: RW 527 */ 528 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 529 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 530 531 /* reg_sfd_uc_tunnel_uip_lsb 532 * When protocol is IPv4, the least significant bytes of the underlay 533 * IPv4 destination IP. 534 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 535 * which is configured by RIPS. 536 * Access: RW 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 539 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 540 541 static inline void 542 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 543 enum mlxsw_reg_sfd_rec_policy policy, 544 const char *mac, u16 fid, 545 enum mlxsw_reg_sfd_rec_action action, 546 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 547 { 548 mlxsw_reg_sfd_rec_pack(payload, rec_index, 549 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 550 action); 551 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 552 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 553 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 554 } 555 556 static inline void 557 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 558 enum mlxsw_reg_sfd_rec_policy policy, 559 const char *mac, u16 fid, 560 enum mlxsw_reg_sfd_rec_action action, u32 uip) 561 { 562 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 563 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 564 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 565 action, 566 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 567 } 568 569 static inline void 570 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 571 u16 fid, enum mlxsw_reg_sfd_rec_action action, 572 u32 uip_ptr) 573 { 574 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 575 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 576 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 577 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 578 mac, fid, action, 579 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 580 } 581 582 enum mlxsw_reg_tunnel_port { 583 MLXSW_REG_TUNNEL_PORT_NVE, 584 MLXSW_REG_TUNNEL_PORT_VPLS, 585 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 586 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 587 }; 588 589 /* SFN - Switch FDB Notification Register 590 * ------------------------------------------- 591 * The switch provides notifications on newly learned FDB entries and 592 * aged out entries. The notifications can be polled by software. 593 */ 594 #define MLXSW_REG_SFN_ID 0x200B 595 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 596 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 597 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 598 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 599 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 600 601 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 602 603 /* reg_sfn_swid 604 * Switch partition ID. 605 * Access: Index 606 */ 607 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 608 609 /* reg_sfn_end 610 * Forces the current session to end. 611 * Access: OP 612 */ 613 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 614 615 /* reg_sfn_num_rec 616 * Request: Number of learned notifications and aged-out notification 617 * records requested. 618 * Response: Number of notification records returned (must be smaller 619 * than or equal to the value requested) 620 * Ranges 0..64 621 * Access: OP 622 */ 623 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 624 625 static inline void mlxsw_reg_sfn_pack(char *payload) 626 { 627 MLXSW_REG_ZERO(sfn, payload); 628 mlxsw_reg_sfn_swid_set(payload, 0); 629 mlxsw_reg_sfn_end_set(payload, 0); 630 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 631 } 632 633 /* reg_sfn_rec_swid 634 * Switch partition ID. 635 * Access: RO 636 */ 637 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 638 MLXSW_REG_SFN_REC_LEN, 0x00, false); 639 640 enum mlxsw_reg_sfn_rec_type { 641 /* MAC addresses learned on a regular port. */ 642 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 643 /* MAC addresses learned on a LAG port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 645 /* Aged-out MAC address on a regular port. */ 646 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 647 /* Aged-out MAC address on a LAG port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 649 /* Learned unicast tunnel record. */ 650 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 651 /* Aged-out unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 653 }; 654 655 /* reg_sfn_rec_type 656 * Notification record type. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 660 MLXSW_REG_SFN_REC_LEN, 0x00, false); 661 662 /* reg_sfn_rec_mac 663 * MAC address. 664 * Access: RO 665 */ 666 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 667 MLXSW_REG_SFN_REC_LEN, 0x02); 668 669 /* reg_sfn_mac_sub_port 670 * VEPA channel on the local port. 671 * 0 if multichannel VEPA is not enabled. 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 675 MLXSW_REG_SFN_REC_LEN, 0x08, false); 676 677 /* reg_sfn_mac_fid 678 * Filtering identifier. 679 * Access: RO 680 */ 681 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 682 MLXSW_REG_SFN_REC_LEN, 0x08, false); 683 684 /* reg_sfn_mac_system_port 685 * Unique port identifier for the final destination of the packet. 686 * Access: RO 687 */ 688 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 689 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 690 691 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 692 char *mac, u16 *p_vid, 693 u16 *p_local_port) 694 { 695 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 696 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 697 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 698 } 699 700 /* reg_sfn_mac_lag_lag_id 701 * LAG ID (pointer into the LAG descriptor table). 702 * Access: RO 703 */ 704 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 705 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 706 707 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 708 char *mac, u16 *p_vid, 709 u16 *p_lag_id) 710 { 711 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 712 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 713 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 714 } 715 716 /* reg_sfn_uc_tunnel_uip_msb 717 * When protocol is IPv4, the most significant byte of the underlay IPv4 718 * address of the remote VTEP. 719 * When protocol is IPv6, reserved. 720 * Access: RO 721 */ 722 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 723 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 724 725 enum mlxsw_reg_sfn_uc_tunnel_protocol { 726 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 727 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 728 }; 729 730 /* reg_sfn_uc_tunnel_protocol 731 * IP protocol. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 735 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_uip_lsb 738 * When protocol is IPv4, the least significant bytes of the underlay 739 * IPv4 address of the remote VTEP. 740 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 741 * Access: RO 742 */ 743 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 744 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 745 746 /* reg_sfn_uc_tunnel_port 747 * Tunnel port. 748 * Reserved on Spectrum. 749 * Access: RO 750 */ 751 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 752 MLXSW_REG_SFN_REC_LEN, 0x10, false); 753 754 static inline void 755 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 756 u16 *p_fid, u32 *p_uip, 757 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 758 { 759 u32 uip_msb, uip_lsb; 760 761 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 762 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 763 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 764 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 765 *p_uip = uip_msb << 24 | uip_lsb; 766 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 767 } 768 769 /* SPMS - Switch Port MSTP/RSTP State Register 770 * ------------------------------------------- 771 * Configures the spanning tree state of a physical port. 772 */ 773 #define MLXSW_REG_SPMS_ID 0x200D 774 #define MLXSW_REG_SPMS_LEN 0x404 775 776 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 777 778 /* reg_spms_local_port 779 * Local port number. 780 * Access: Index 781 */ 782 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 783 784 enum mlxsw_reg_spms_state { 785 MLXSW_REG_SPMS_STATE_NO_CHANGE, 786 MLXSW_REG_SPMS_STATE_DISCARDING, 787 MLXSW_REG_SPMS_STATE_LEARNING, 788 MLXSW_REG_SPMS_STATE_FORWARDING, 789 }; 790 791 /* reg_spms_state 792 * Spanning tree state of each VLAN ID (VID) of the local port. 793 * 0 - Do not change spanning tree state (used only when writing). 794 * 1 - Discarding. No learning or forwarding to/from this port (default). 795 * 2 - Learning. Port is learning, but not forwarding. 796 * 3 - Forwarding. Port is learning and forwarding. 797 * Access: RW 798 */ 799 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 800 801 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 802 { 803 MLXSW_REG_ZERO(spms, payload); 804 mlxsw_reg_spms_local_port_set(payload, local_port); 805 } 806 807 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 808 enum mlxsw_reg_spms_state state) 809 { 810 mlxsw_reg_spms_state_set(payload, vid, state); 811 } 812 813 /* SPVID - Switch Port VID 814 * ----------------------- 815 * The switch port VID configures the default VID for a port. 816 */ 817 #define MLXSW_REG_SPVID_ID 0x200E 818 #define MLXSW_REG_SPVID_LEN 0x08 819 820 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 821 822 /* reg_spvid_tport 823 * Port is tunnel port. 824 * Reserved when SwitchX/-2 or Spectrum-1. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 828 829 /* reg_spvid_local_port 830 * When tport = 0: Local port number. Not supported for CPU port. 831 * When tport = 1: Tunnel port. 832 * Access: Index 833 */ 834 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 835 836 /* reg_spvid_sub_port 837 * Virtual port within the physical port. 838 * Should be set to 0 when virtual ports are not enabled on the port. 839 * Access: Index 840 */ 841 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 842 843 /* reg_spvid_egr_et_set 844 * When VLAN is pushed at ingress (for untagged packets or for 845 * QinQ push mode) then the EtherType is decided at the egress port. 846 * Reserved when Spectrum-1. 847 * Access: RW 848 */ 849 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 850 851 /* reg_spvid_et_vlan 852 * EtherType used for when VLAN is pushed at ingress (for untagged 853 * packets or for QinQ push mode). 854 * 0: ether_type0 - (default) 855 * 1: ether_type1 856 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 857 * Ethertype IDs are configured by SVER. 858 * Reserved when egr_et_set = 1. 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 862 863 /* reg_spvid_pvid 864 * Port default VID 865 * Access: RW 866 */ 867 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 868 869 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 870 u8 et_vlan) 871 { 872 MLXSW_REG_ZERO(spvid, payload); 873 mlxsw_reg_spvid_local_port_set(payload, local_port); 874 mlxsw_reg_spvid_pvid_set(payload, pvid); 875 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 876 } 877 878 /* SPVM - Switch Port VLAN Membership 879 * ---------------------------------- 880 * The Switch Port VLAN Membership register configures the VLAN membership 881 * of a port in a VLAN denoted by VID. VLAN membership is managed per 882 * virtual port. The register can be used to add and remove VID(s) from a port. 883 */ 884 #define MLXSW_REG_SPVM_ID 0x200F 885 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 886 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 887 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 888 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 889 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 890 891 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 892 893 /* reg_spvm_pt 894 * Priority tagged. If this bit is set, packets forwarded to the port with 895 * untagged VLAN membership (u bit is set) will be tagged with priority tag 896 * (VID=0) 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 900 901 /* reg_spvm_pte 902 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 903 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 904 * Access: WO 905 */ 906 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 907 908 /* reg_spvm_local_port 909 * Local port number. 910 * Access: Index 911 */ 912 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 913 914 /* reg_spvm_sub_port 915 * Virtual port within the physical port. 916 * Should be set to 0 when virtual ports are not enabled on the port. 917 * Access: Index 918 */ 919 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 920 921 /* reg_spvm_num_rec 922 * Number of records to update. Each record contains: i, e, u, vid. 923 * Access: OP 924 */ 925 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 926 927 /* reg_spvm_rec_i 928 * Ingress membership in VLAN ID. 929 * Access: Index 930 */ 931 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 932 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 933 MLXSW_REG_SPVM_REC_LEN, 0, false); 934 935 /* reg_spvm_rec_e 936 * Egress membership in VLAN ID. 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 940 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_u 944 * Untagged - port is an untagged member - egress transmission uses untagged 945 * frames on VID<n> 946 * Access: Index 947 */ 948 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 949 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 950 MLXSW_REG_SPVM_REC_LEN, 0, false); 951 952 /* reg_spvm_rec_vid 953 * Egress membership in VLAN ID. 954 * Access: Index 955 */ 956 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 957 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 958 MLXSW_REG_SPVM_REC_LEN, 0, false); 959 960 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 961 u16 vid_begin, u16 vid_end, 962 bool is_member, bool untagged) 963 { 964 int size = vid_end - vid_begin + 1; 965 int i; 966 967 MLXSW_REG_ZERO(spvm, payload); 968 mlxsw_reg_spvm_local_port_set(payload, local_port); 969 mlxsw_reg_spvm_num_rec_set(payload, size); 970 971 for (i = 0; i < size; i++) { 972 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 973 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 974 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 975 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 976 } 977 } 978 979 /* SPAFT - Switch Port Acceptable Frame Types 980 * ------------------------------------------ 981 * The Switch Port Acceptable Frame Types register configures the frame 982 * admittance of the port. 983 */ 984 #define MLXSW_REG_SPAFT_ID 0x2010 985 #define MLXSW_REG_SPAFT_LEN 0x08 986 987 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 988 989 /* reg_spaft_local_port 990 * Local port number. 991 * Access: Index 992 * 993 * Note: CPU port is not supported (all tag types are allowed). 994 */ 995 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 996 997 /* reg_spaft_sub_port 998 * Virtual port within the physical port. 999 * Should be set to 0 when virtual ports are not enabled on the port. 1000 * Access: RW 1001 */ 1002 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1003 1004 /* reg_spaft_allow_untagged 1005 * When set, untagged frames on the ingress are allowed (default). 1006 * Access: RW 1007 */ 1008 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1009 1010 /* reg_spaft_allow_prio_tagged 1011 * When set, priority tagged frames on the ingress are allowed (default). 1012 * Access: RW 1013 */ 1014 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1015 1016 /* reg_spaft_allow_tagged 1017 * When set, tagged frames on the ingress are allowed (default). 1018 * Access: RW 1019 */ 1020 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1021 1022 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1023 bool allow_untagged) 1024 { 1025 MLXSW_REG_ZERO(spaft, payload); 1026 mlxsw_reg_spaft_local_port_set(payload, local_port); 1027 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1028 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1029 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1030 } 1031 1032 /* SFGC - Switch Flooding Group Configuration 1033 * ------------------------------------------ 1034 * The following register controls the association of flooding tables and MIDs 1035 * to packet types used for flooding. 1036 */ 1037 #define MLXSW_REG_SFGC_ID 0x2011 1038 #define MLXSW_REG_SFGC_LEN 0x14 1039 1040 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1041 1042 enum mlxsw_reg_sfgc_type { 1043 MLXSW_REG_SFGC_TYPE_BROADCAST, 1044 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1046 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1047 MLXSW_REG_SFGC_TYPE_RESERVED, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1049 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1050 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1051 MLXSW_REG_SFGC_TYPE_MAX, 1052 }; 1053 1054 /* reg_sfgc_type 1055 * The traffic type to reach the flooding table. 1056 * Access: Index 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1059 1060 /* bridge_type is used in SFGC and SFMR. */ 1061 enum mlxsw_reg_bridge_type { 1062 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1063 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1064 }; 1065 1066 /* reg_sfgc_bridge_type 1067 * Access: Index 1068 * 1069 * Note: SwitchX-2 only supports 802.1Q mode. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1072 1073 enum mlxsw_flood_table_type { 1074 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1075 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1076 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1077 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1079 }; 1080 1081 /* reg_sfgc_table_type 1082 * See mlxsw_flood_table_type 1083 * Access: RW 1084 * 1085 * Note: FID offset and FID types are not supported in SwitchX-2. 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1088 1089 /* reg_sfgc_flood_table 1090 * Flooding table index to associate with the specific type on the specific 1091 * switch partition. 1092 * Access: RW 1093 */ 1094 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1095 1096 /* reg_sfgc_counter_set_type 1097 * Counter Set Type for flow counters. 1098 * Access: RW 1099 */ 1100 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1101 1102 /* reg_sfgc_counter_index 1103 * Counter Index for flow counters. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1107 1108 /* reg_sfgc_mid_base 1109 * MID Base. 1110 * Access: RW 1111 * 1112 * Note: Reserved when legacy bridge model is used. 1113 */ 1114 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1115 1116 static inline void 1117 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1118 enum mlxsw_reg_bridge_type bridge_type, 1119 enum mlxsw_flood_table_type table_type, 1120 unsigned int flood_table, u16 mid_base) 1121 { 1122 MLXSW_REG_ZERO(sfgc, payload); 1123 mlxsw_reg_sfgc_type_set(payload, type); 1124 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1125 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1126 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1127 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1128 } 1129 1130 /* SFDF - Switch Filtering DB Flush 1131 * -------------------------------- 1132 * The switch filtering DB flush register is used to flush the FDB. 1133 * Note that FDB notifications are flushed as well. 1134 */ 1135 #define MLXSW_REG_SFDF_ID 0x2013 1136 #define MLXSW_REG_SFDF_LEN 0x14 1137 1138 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1139 1140 /* reg_sfdf_swid 1141 * Switch partition ID. 1142 * Access: Index 1143 */ 1144 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1145 1146 enum mlxsw_reg_sfdf_flush_type { 1147 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1148 MLXSW_REG_SFDF_FLUSH_PER_FID, 1149 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1150 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1151 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1152 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1153 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1154 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1155 }; 1156 1157 /* reg_sfdf_flush_type 1158 * Flush type. 1159 * 0 - All SWID dynamic entries are flushed. 1160 * 1 - All FID dynamic entries are flushed. 1161 * 2 - All dynamic entries pointing to port are flushed. 1162 * 3 - All FID dynamic entries pointing to port are flushed. 1163 * 4 - All dynamic entries pointing to LAG are flushed. 1164 * 5 - All FID dynamic entries pointing to LAG are flushed. 1165 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1166 * flushed. 1167 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1168 * flushed, per FID. 1169 * Access: RW 1170 */ 1171 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1172 1173 /* reg_sfdf_flush_static 1174 * Static. 1175 * 0 - Flush only dynamic entries. 1176 * 1 - Flush both dynamic and static entries. 1177 * Access: RW 1178 */ 1179 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1180 1181 static inline void mlxsw_reg_sfdf_pack(char *payload, 1182 enum mlxsw_reg_sfdf_flush_type type) 1183 { 1184 MLXSW_REG_ZERO(sfdf, payload); 1185 mlxsw_reg_sfdf_flush_type_set(payload, type); 1186 mlxsw_reg_sfdf_flush_static_set(payload, true); 1187 } 1188 1189 /* reg_sfdf_fid 1190 * FID to flush. 1191 * Access: RW 1192 */ 1193 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1194 1195 /* reg_sfdf_system_port 1196 * Port to flush. 1197 * Access: RW 1198 */ 1199 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1200 1201 /* reg_sfdf_port_fid_system_port 1202 * Port to flush, pointed to by FID. 1203 * Access: RW 1204 */ 1205 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1206 1207 /* reg_sfdf_lag_id 1208 * LAG ID to flush. 1209 * Access: RW 1210 */ 1211 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1212 1213 /* reg_sfdf_lag_fid_lag_id 1214 * LAG ID to flush, pointed to by FID. 1215 * Access: RW 1216 */ 1217 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1218 1219 /* SLDR - Switch LAG Descriptor Register 1220 * ----------------------------------------- 1221 * The switch LAG descriptor register is populated by LAG descriptors. 1222 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1223 * max_lag-1. 1224 */ 1225 #define MLXSW_REG_SLDR_ID 0x2014 1226 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1227 1228 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1229 1230 enum mlxsw_reg_sldr_op { 1231 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1232 MLXSW_REG_SLDR_OP_LAG_CREATE, 1233 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1234 /* Ports that appear in the list have the Distributor enabled */ 1235 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1236 /* Removes ports from the disributor list */ 1237 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1238 }; 1239 1240 /* reg_sldr_op 1241 * Operation. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1245 1246 /* reg_sldr_lag_id 1247 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1248 * Access: Index 1249 */ 1250 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1251 1252 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1260 { 1261 MLXSW_REG_ZERO(sldr, payload); 1262 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1263 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1264 } 1265 1266 /* reg_sldr_num_ports 1267 * The number of member ports of the LAG. 1268 * Reserved for Create / Destroy operations 1269 * For Add / Remove operations - indicates the number of ports in the list. 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1273 1274 /* reg_sldr_system_port 1275 * System port. 1276 * Access: RW 1277 */ 1278 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1279 1280 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1281 u16 local_port) 1282 { 1283 MLXSW_REG_ZERO(sldr, payload); 1284 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1285 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1286 mlxsw_reg_sldr_num_ports_set(payload, 1); 1287 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1288 } 1289 1290 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1291 u16 local_port) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 mlxsw_reg_sldr_num_ports_set(payload, 1); 1297 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1298 } 1299 1300 /* SLCR - Switch LAG Configuration 2 Register 1301 * ------------------------------------------- 1302 * The Switch LAG Configuration register is used for configuring the 1303 * LAG properties of the switch. 1304 */ 1305 #define MLXSW_REG_SLCR_ID 0x2015 1306 #define MLXSW_REG_SLCR_LEN 0x10 1307 1308 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1309 1310 enum mlxsw_reg_slcr_pp { 1311 /* Global Configuration (for all ports) */ 1312 MLXSW_REG_SLCR_PP_GLOBAL, 1313 /* Per port configuration, based on local_port field */ 1314 MLXSW_REG_SLCR_PP_PER_PORT, 1315 }; 1316 1317 /* reg_slcr_pp 1318 * Per Port Configuration 1319 * Note: Reading at Global mode results in reading port 1 configuration. 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1323 1324 /* reg_slcr_local_port 1325 * Local port number 1326 * Supported from CPU port 1327 * Not supported from router port 1328 * Reserved when pp = Global Configuration 1329 * Access: Index 1330 */ 1331 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1332 1333 enum mlxsw_reg_slcr_type { 1334 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1335 MLXSW_REG_SLCR_TYPE_XOR, 1336 MLXSW_REG_SLCR_TYPE_RANDOM, 1337 }; 1338 1339 /* reg_slcr_type 1340 * Hash type 1341 * Access: RW 1342 */ 1343 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1344 1345 /* Ingress port */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1347 /* SMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1349 /* SMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1351 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1354 /* DMAC - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1356 /* DMAC - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1358 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1359 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1361 /* Ethertype - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1363 /* Ethertype - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1365 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1366 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1368 /* VLAN ID - for IPv4 and IPv6 packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1370 /* VLAN ID - for non-IP packets */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1372 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1373 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1374 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1375 /* Source IP address (can be IPv4 or IPv6) */ 1376 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1377 /* Destination IP address (can be IPv4 or IPv6) */ 1378 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1379 /* TCP/UDP source port */ 1380 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1381 /* TCP/UDP destination port*/ 1382 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1383 /* IPv4 Protocol/IPv6 Next Header */ 1384 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1385 /* IPv6 Flow label */ 1386 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1387 /* SID - FCoE source ID */ 1388 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1389 /* DID - FCoE destination ID */ 1390 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1391 /* OXID - FCoE originator exchange ID */ 1392 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1393 /* Destination QP number - for RoCE packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1395 1396 /* reg_slcr_lag_hash 1397 * LAG hashing configuration. This is a bitmask, in which each set 1398 * bit includes the corresponding item in the LAG hash calculation. 1399 * The default lag_hash contains SMAC, DMAC, VLANID and 1400 * Ethertype (for all packet types). 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1404 1405 /* reg_slcr_seed 1406 * LAG seed value. The seed is the same for all ports. 1407 * Access: RW 1408 */ 1409 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1410 1411 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1412 { 1413 MLXSW_REG_ZERO(slcr, payload); 1414 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1415 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1416 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1417 mlxsw_reg_slcr_seed_set(payload, seed); 1418 } 1419 1420 /* SLCOR - Switch LAG Collector Register 1421 * ------------------------------------- 1422 * The Switch LAG Collector register controls the Local Port membership 1423 * in a LAG and enablement of the collector. 1424 */ 1425 #define MLXSW_REG_SLCOR_ID 0x2016 1426 #define MLXSW_REG_SLCOR_LEN 0x10 1427 1428 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1429 1430 enum mlxsw_reg_slcor_col { 1431 /* Port is added with collector disabled */ 1432 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1435 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1436 }; 1437 1438 /* reg_slcor_col 1439 * Collector configuration 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1443 1444 /* reg_slcor_local_port 1445 * Local port number 1446 * Not supported for CPU port 1447 * Access: Index 1448 */ 1449 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1450 1451 /* reg_slcor_lag_id 1452 * LAG Identifier. Index into the LAG descriptor table. 1453 * Access: Index 1454 */ 1455 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1456 1457 /* reg_slcor_port_index 1458 * Port index in the LAG list. Only valid on Add Port to LAG col. 1459 * Valid range is from 0 to cap_max_lag_members-1 1460 * Access: RW 1461 */ 1462 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1463 1464 static inline void mlxsw_reg_slcor_pack(char *payload, 1465 u16 local_port, u16 lag_id, 1466 enum mlxsw_reg_slcor_col col) 1467 { 1468 MLXSW_REG_ZERO(slcor, payload); 1469 mlxsw_reg_slcor_col_set(payload, col); 1470 mlxsw_reg_slcor_local_port_set(payload, local_port); 1471 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1475 u16 local_port, u16 lag_id, 1476 u8 port_index) 1477 { 1478 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1479 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1480 mlxsw_reg_slcor_port_index_set(payload, port_index); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1498 u16 local_port, u16 lag_id) 1499 { 1500 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1501 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1502 } 1503 1504 /* SPMLR - Switch Port MAC Learning Register 1505 * ----------------------------------------- 1506 * Controls the Switch MAC learning policy per port. 1507 */ 1508 #define MLXSW_REG_SPMLR_ID 0x2018 1509 #define MLXSW_REG_SPMLR_LEN 0x8 1510 1511 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1512 1513 /* reg_spmlr_local_port 1514 * Local port number. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1518 1519 /* reg_spmlr_sub_port 1520 * Virtual port within the physical port. 1521 * Should be set to 0 when virtual ports are not enabled on the port. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1525 1526 enum mlxsw_reg_spmlr_learn_mode { 1527 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1528 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1529 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1530 }; 1531 1532 /* reg_spmlr_learn_mode 1533 * Learning mode on the port. 1534 * 0 - Learning disabled. 1535 * 2 - Learning enabled. 1536 * 3 - Security mode. 1537 * 1538 * In security mode the switch does not learn MACs on the port, but uses the 1539 * SMAC to see if it exists on another ingress port. If so, the packet is 1540 * classified as a bad packet and is discarded unless the software registers 1541 * to receive port security error packets usign HPKT. 1542 */ 1543 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1544 1545 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1546 enum mlxsw_reg_spmlr_learn_mode mode) 1547 { 1548 MLXSW_REG_ZERO(spmlr, payload); 1549 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1550 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1551 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1552 } 1553 1554 /* SVFA - Switch VID to FID Allocation Register 1555 * -------------------------------------------- 1556 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1557 * virtualized ports. 1558 */ 1559 #define MLXSW_REG_SVFA_ID 0x201C 1560 #define MLXSW_REG_SVFA_LEN 0x18 1561 1562 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1563 1564 /* reg_svfa_swid 1565 * Switch partition ID. 1566 * Access: Index 1567 */ 1568 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1569 1570 /* reg_svfa_local_port 1571 * Local port number. 1572 * Access: Index 1573 * 1574 * Note: Reserved for 802.1Q FIDs. 1575 */ 1576 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1577 1578 enum mlxsw_reg_svfa_mt { 1579 MLXSW_REG_SVFA_MT_VID_TO_FID, 1580 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1581 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1582 }; 1583 1584 /* reg_svfa_mapping_table 1585 * Mapping table: 1586 * 0 - VID to FID 1587 * 1 - {Port, VID} to FID 1588 * Access: Index 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1593 1594 /* reg_svfa_v 1595 * Valid. 1596 * Valid if set. 1597 * Access: RW 1598 * 1599 * Note: Reserved for SwitchX-2. 1600 */ 1601 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1602 1603 /* reg_svfa_fid 1604 * Filtering ID. 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1608 1609 /* reg_svfa_vid 1610 * VLAN ID. 1611 * Access: Index 1612 */ 1613 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1614 1615 /* reg_svfa_counter_set_type 1616 * Counter set type for flow counters. 1617 * Access: RW 1618 * 1619 * Note: Reserved for SwitchX-2. 1620 */ 1621 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1622 1623 /* reg_svfa_counter_index 1624 * Counter index for flow counters. 1625 * Access: RW 1626 * 1627 * Note: Reserved for SwitchX-2. 1628 */ 1629 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1630 1631 /* reg_svfa_vni 1632 * Virtual Network Identifier. 1633 * Access: Index 1634 * 1635 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1636 */ 1637 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1638 1639 /* reg_svfa_irif_v 1640 * Ingress RIF valid. 1641 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1642 * 1 - Ingress RIF valid. 1643 * Must not be set for a non enabled RIF. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1649 1650 /* reg_svfa_irif 1651 * Ingress RIF (Router Interface). 1652 * Range is 0..cap_max_router_interfaces-1. 1653 * Access: RW 1654 * 1655 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1656 */ 1657 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1658 1659 static inline void __mlxsw_reg_svfa_pack(char *payload, 1660 enum mlxsw_reg_svfa_mt mt, bool valid, 1661 u16 fid, bool irif_v, u16 irif) 1662 { 1663 MLXSW_REG_ZERO(svfa, payload); 1664 mlxsw_reg_svfa_swid_set(payload, 0); 1665 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1666 mlxsw_reg_svfa_v_set(payload, valid); 1667 mlxsw_reg_svfa_fid_set(payload, fid); 1668 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1669 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1670 } 1671 1672 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1673 bool valid, u16 fid, u16 vid, 1674 bool irif_v, u16 irif) 1675 { 1676 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1677 1678 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1679 mlxsw_reg_svfa_local_port_set(payload, local_port); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1684 u16 vid, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vid_set(payload, vid); 1690 } 1691 1692 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1693 u32 vni, bool irif_v, u16 irif) 1694 { 1695 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1696 1697 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1698 mlxsw_reg_svfa_vni_set(payload, vni); 1699 } 1700 1701 /* SPVTR - Switch Port VLAN Stacking Register 1702 * ------------------------------------------ 1703 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1704 * to enable VLAN stacking. 1705 */ 1706 #define MLXSW_REG_SPVTR_ID 0x201D 1707 #define MLXSW_REG_SPVTR_LEN 0x10 1708 1709 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1710 1711 /* reg_spvtr_tport 1712 * Port is tunnel port. 1713 * Access: Index 1714 * 1715 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1716 */ 1717 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1718 1719 /* reg_spvtr_local_port 1720 * When tport = 0: local port number (Not supported from/to CPU). 1721 * When tport = 1: tunnel port. 1722 * Access: Index 1723 */ 1724 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1725 1726 /* reg_spvtr_ippe 1727 * Ingress Port Prio Mode Update Enable. 1728 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1733 1734 /* reg_spvtr_ipve 1735 * Ingress Port VID Mode Update Enable. 1736 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1737 * field. 1738 * Reserved on Get operations. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1742 1743 /* reg_spvtr_epve 1744 * Egress Port VID Mode Update Enable. 1745 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1746 * field. 1747 * Access: OP 1748 */ 1749 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1750 1751 /* reg_spvtr_ipprio_mode 1752 * Ingress Port Priority Mode. 1753 * This controls the PCP and DEI of the new outer VLAN 1754 * Note: for SwitchX/-2 the DEI is not affected. 1755 * 0: use port default PCP and DEI (configured by QPDPC). 1756 * 1: use C-VLAN PCP and DEI. 1757 * Has no effect when ipvid_mode = 0. 1758 * Reserved when tport = 1. 1759 * Access: RW 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1762 1763 enum mlxsw_reg_spvtr_ipvid_mode { 1764 /* IEEE Compliant PVID (default) */ 1765 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1766 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1767 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1768 /* Always push VLAN (also for prio tagged packets) */ 1769 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1770 }; 1771 1772 /* reg_spvtr_ipvid_mode 1773 * Ingress Port VLAN-ID Mode. 1774 * For Spectrum family, this affects the values of SPVM.i 1775 * Access: RW 1776 */ 1777 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1778 1779 enum mlxsw_reg_spvtr_epvid_mode { 1780 /* IEEE Compliant VLAN membership */ 1781 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1782 /* Pop VLAN (for VLAN stacking) */ 1783 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1784 }; 1785 1786 /* reg_spvtr_epvid_mode 1787 * Egress Port VLAN-ID Mode. 1788 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1789 * Access: WO 1790 */ 1791 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1792 1793 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1794 u16 local_port, 1795 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1796 { 1797 MLXSW_REG_ZERO(spvtr, payload); 1798 mlxsw_reg_spvtr_tport_set(payload, tport); 1799 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1800 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1801 mlxsw_reg_spvtr_ipve_set(payload, true); 1802 } 1803 1804 /* SVPE - Switch Virtual-Port Enabling Register 1805 * -------------------------------------------- 1806 * Enables port virtualization. 1807 */ 1808 #define MLXSW_REG_SVPE_ID 0x201E 1809 #define MLXSW_REG_SVPE_LEN 0x4 1810 1811 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1812 1813 /* reg_svpe_local_port 1814 * Local port number 1815 * Access: Index 1816 * 1817 * Note: CPU port is not supported (uses VLAN mode only). 1818 */ 1819 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1820 1821 /* reg_svpe_vp_en 1822 * Virtual port enable. 1823 * 0 - Disable, VLAN mode (VID to FID). 1824 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1825 * Access: RW 1826 */ 1827 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1828 1829 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1830 bool enable) 1831 { 1832 MLXSW_REG_ZERO(svpe, payload); 1833 mlxsw_reg_svpe_local_port_set(payload, local_port); 1834 mlxsw_reg_svpe_vp_en_set(payload, enable); 1835 } 1836 1837 /* SFMR - Switch FID Management Register 1838 * ------------------------------------- 1839 * Creates and configures FIDs. 1840 */ 1841 #define MLXSW_REG_SFMR_ID 0x201F 1842 #define MLXSW_REG_SFMR_LEN 0x30 1843 1844 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1845 1846 enum mlxsw_reg_sfmr_op { 1847 MLXSW_REG_SFMR_OP_CREATE_FID, 1848 MLXSW_REG_SFMR_OP_DESTROY_FID, 1849 }; 1850 1851 /* reg_sfmr_op 1852 * Operation. 1853 * 0 - Create or edit FID. 1854 * 1 - Destroy FID. 1855 * Access: WO 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1858 1859 /* reg_sfmr_fid 1860 * Filtering ID. 1861 * Access: Index 1862 */ 1863 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1864 1865 /* reg_sfmr_flood_rsp 1866 * Router sub-port flooding table. 1867 * 0 - Regular flooding table. 1868 * 1 - Router sub-port flooding table. For this FID the flooding is per 1869 * router-sub-port local_port. Must not be set for a FID which is not a 1870 * router-sub-port and must be set prior to enabling the relevant RIF. 1871 * Access: RW 1872 * 1873 * Note: Reserved when legacy bridge model is used. 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1876 1877 /* reg_sfmr_flood_bridge_type 1878 * Flood bridge type (see SFGC.bridge_type). 1879 * 0 - type_0. 1880 * 1 - type_1. 1881 * Access: RW 1882 * 1883 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1886 1887 /* reg_sfmr_fid_offset 1888 * FID offset. 1889 * Used to point into the flooding table selected by SFGC register if 1890 * the table is of type FID-Offset. Otherwise, this field is reserved. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1894 1895 /* reg_sfmr_vtfp 1896 * Valid Tunnel Flood Pointer. 1897 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1898 * Access: RW 1899 * 1900 * Note: Reserved for 802.1Q FIDs. 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1903 1904 /* reg_sfmr_nve_tunnel_flood_ptr 1905 * Underlay Flooding and BC Pointer. 1906 * Used as a pointer to the first entry of the group based link lists of 1907 * flooding or BC entries (for NVE tunnels). 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1911 1912 /* reg_sfmr_vv 1913 * VNI Valid. 1914 * If not set, then vni is reserved. 1915 * Access: RW 1916 * 1917 * Note: Reserved for 802.1Q FIDs. 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1920 1921 /* reg_sfmr_vni 1922 * Virtual Network Identifier. 1923 * When legacy bridge model is used, a given VNI can only be assigned to one 1924 * FID. When unified bridge model is used, it configures only the FID->VNI, 1925 * the VNI->FID is done by SVFA. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1929 1930 /* reg_sfmr_irif_v 1931 * Ingress RIF valid. 1932 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1933 * 1 - Ingress RIF valid. 1934 * Must not be set for a non valid RIF. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1940 1941 /* reg_sfmr_irif 1942 * Ingress RIF (Router Interface). 1943 * Range is 0..cap_max_router_interfaces-1. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1949 1950 /* reg_sfmr_smpe_valid 1951 * SMPE is valid. 1952 * Access: RW 1953 * 1954 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1955 * Spectrum-1. 1956 */ 1957 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1958 1959 /* reg_sfmr_smpe 1960 * Switch multicast port to egress VID. 1961 * Range is 0..cap_max_rmpe-1 1962 * Access: RW 1963 * 1964 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1965 * Spectrum-1. 1966 */ 1967 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1968 1969 static inline void mlxsw_reg_sfmr_pack(char *payload, 1970 enum mlxsw_reg_sfmr_op op, u16 fid, 1971 u16 fid_offset, bool flood_rsp, 1972 enum mlxsw_reg_bridge_type bridge_type, 1973 bool smpe_valid, u16 smpe) 1974 { 1975 MLXSW_REG_ZERO(sfmr, payload); 1976 mlxsw_reg_sfmr_op_set(payload, op); 1977 mlxsw_reg_sfmr_fid_set(payload, fid); 1978 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1979 mlxsw_reg_sfmr_vtfp_set(payload, false); 1980 mlxsw_reg_sfmr_vv_set(payload, false); 1981 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1982 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1983 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1984 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1985 } 1986 1987 /* SPVMLR - Switch Port VLAN MAC Learning Register 1988 * ----------------------------------------------- 1989 * Controls the switch MAC learning policy per {Port, VID}. 1990 */ 1991 #define MLXSW_REG_SPVMLR_ID 0x2020 1992 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1993 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1994 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1995 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1996 MLXSW_REG_SPVMLR_REC_LEN * \ 1997 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1998 1999 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2000 2001 /* reg_spvmlr_local_port 2002 * Local ingress port. 2003 * Access: Index 2004 * 2005 * Note: CPU port is not supported. 2006 */ 2007 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2008 2009 /* reg_spvmlr_num_rec 2010 * Number of records to update. 2011 * Access: OP 2012 */ 2013 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2014 2015 /* reg_spvmlr_rec_learn_enable 2016 * 0 - Disable learning for {Port, VID}. 2017 * 1 - Enable learning for {Port, VID}. 2018 * Access: RW 2019 */ 2020 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2021 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2022 2023 /* reg_spvmlr_rec_vid 2024 * VLAN ID to be added/removed from port or for querying. 2025 * Access: Index 2026 */ 2027 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2028 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2029 2030 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2031 u16 vid_begin, u16 vid_end, 2032 bool learn_enable) 2033 { 2034 int num_rec = vid_end - vid_begin + 1; 2035 int i; 2036 2037 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2038 2039 MLXSW_REG_ZERO(spvmlr, payload); 2040 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2041 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2042 2043 for (i = 0; i < num_rec; i++) { 2044 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2045 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2046 } 2047 } 2048 2049 /* SPFSR - Switch Port FDB Security Register 2050 * ----------------------------------------- 2051 * Configures the security mode per port. 2052 */ 2053 #define MLXSW_REG_SPFSR_ID 0x2023 2054 #define MLXSW_REG_SPFSR_LEN 0x08 2055 2056 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN); 2057 2058 /* reg_spfsr_local_port 2059 * Local port. 2060 * Access: Index 2061 * 2062 * Note: not supported for CPU port. 2063 */ 2064 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12); 2065 2066 /* reg_spfsr_security 2067 * Security checks. 2068 * 0: disabled (default) 2069 * 1: enabled 2070 * Access: RW 2071 */ 2072 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1); 2073 2074 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port, 2075 bool security) 2076 { 2077 MLXSW_REG_ZERO(spfsr, payload); 2078 mlxsw_reg_spfsr_local_port_set(payload, local_port); 2079 mlxsw_reg_spfsr_security_set(payload, security); 2080 } 2081 2082 /* SPVC - Switch Port VLAN Classification Register 2083 * ----------------------------------------------- 2084 * Configures the port to identify packets as untagged / single tagged / 2085 * double packets based on the packet EtherTypes. 2086 * Ethertype IDs are configured by SVER. 2087 */ 2088 #define MLXSW_REG_SPVC_ID 0x2026 2089 #define MLXSW_REG_SPVC_LEN 0x0C 2090 2091 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2092 2093 /* reg_spvc_local_port 2094 * Local port. 2095 * Access: Index 2096 * 2097 * Note: applies both to Rx port and Tx port, so if a packet traverses 2098 * through Rx port i and a Tx port j then port i and port j must have the 2099 * same configuration. 2100 */ 2101 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2102 2103 /* reg_spvc_inner_et2 2104 * Vlan Tag1 EtherType2 enable. 2105 * Packet is initially classified as double VLAN Tag if in addition to 2106 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2107 * equal to ether_type2. 2108 * 0: disable (default) 2109 * 1: enable 2110 * Access: RW 2111 */ 2112 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2113 2114 /* reg_spvc_et2 2115 * Vlan Tag0 EtherType2 enable. 2116 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2117 * equal to ether_type2. 2118 * 0: disable (default) 2119 * 1: enable 2120 * Access: RW 2121 */ 2122 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2123 2124 /* reg_spvc_inner_et1 2125 * Vlan Tag1 EtherType1 enable. 2126 * Packet is initially classified as double VLAN Tag if in addition to 2127 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2128 * equal to ether_type1. 2129 * 0: disable 2130 * 1: enable (default) 2131 * Access: RW 2132 */ 2133 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2134 2135 /* reg_spvc_et1 2136 * Vlan Tag0 EtherType1 enable. 2137 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2138 * equal to ether_type1. 2139 * 0: disable 2140 * 1: enable (default) 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2144 2145 /* reg_inner_et0 2146 * Vlan Tag1 EtherType0 enable. 2147 * Packet is initially classified as double VLAN Tag if in addition to 2148 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2149 * equal to ether_type0. 2150 * 0: disable 2151 * 1: enable (default) 2152 * Access: RW 2153 */ 2154 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2155 2156 /* reg_et0 2157 * Vlan Tag0 EtherType0 enable. 2158 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2159 * equal to ether_type0. 2160 * 0: disable 2161 * 1: enable (default) 2162 * Access: RW 2163 */ 2164 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2165 2166 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2167 bool et0) 2168 { 2169 MLXSW_REG_ZERO(spvc, payload); 2170 mlxsw_reg_spvc_local_port_set(payload, local_port); 2171 /* Enable inner_et1 and inner_et0 to enable identification of double 2172 * tagged packets. 2173 */ 2174 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2175 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2176 mlxsw_reg_spvc_et1_set(payload, et1); 2177 mlxsw_reg_spvc_et0_set(payload, et0); 2178 } 2179 2180 /* SPEVET - Switch Port Egress VLAN EtherType 2181 * ------------------------------------------ 2182 * The switch port egress VLAN EtherType configures which EtherType to push at 2183 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2184 * is set. 2185 */ 2186 #define MLXSW_REG_SPEVET_ID 0x202A 2187 #define MLXSW_REG_SPEVET_LEN 0x08 2188 2189 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2190 2191 /* reg_spevet_local_port 2192 * Egress Local port number. 2193 * Not supported to CPU port. 2194 * Access: Index 2195 */ 2196 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2197 2198 /* reg_spevet_et_vlan 2199 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2200 * 0: ether_type0 - (default) 2201 * 1: ether_type1 2202 * 2: ether_type2 2203 * Access: RW 2204 */ 2205 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2206 2207 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2208 u8 et_vlan) 2209 { 2210 MLXSW_REG_ZERO(spevet, payload); 2211 mlxsw_reg_spevet_local_port_set(payload, local_port); 2212 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2213 } 2214 2215 /* SMPE - Switch Multicast Port to Egress VID 2216 * ------------------------------------------ 2217 * The switch multicast port to egress VID maps 2218 * {egress_port, SMPE index} -> {VID}. 2219 */ 2220 #define MLXSW_REG_SMPE_ID 0x202B 2221 #define MLXSW_REG_SMPE_LEN 0x0C 2222 2223 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2224 2225 /* reg_smpe_local_port 2226 * Local port number. 2227 * CPU port is not supported. 2228 * Access: Index 2229 */ 2230 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2231 2232 /* reg_smpe_smpe_index 2233 * Switch multicast port to egress VID. 2234 * Range is 0..cap_max_rmpe-1. 2235 * Access: Index 2236 */ 2237 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2238 2239 /* reg_smpe_evid 2240 * Egress VID. 2241 * Access: RW 2242 */ 2243 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2244 2245 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2246 u16 smpe_index, u16 evid) 2247 { 2248 MLXSW_REG_ZERO(smpe, payload); 2249 mlxsw_reg_smpe_local_port_set(payload, local_port); 2250 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2251 mlxsw_reg_smpe_evid_set(payload, evid); 2252 } 2253 2254 /* SMID-V2 - Switch Multicast ID Version 2 Register 2255 * ------------------------------------------------ 2256 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2257 * of the multicast group within the stacking domain, into a list of local 2258 * ports into which the packet is replicated. 2259 */ 2260 #define MLXSW_REG_SMID2_ID 0x2034 2261 #define MLXSW_REG_SMID2_LEN 0x120 2262 2263 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2264 2265 /* reg_smid2_swid 2266 * Switch partition ID. 2267 * Access: Index 2268 */ 2269 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2270 2271 /* reg_smid2_mid 2272 * Multicast identifier - global identifier that represents the multicast group 2273 * across all devices. 2274 * Access: Index 2275 */ 2276 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2277 2278 /* reg_smid2_smpe_valid 2279 * SMPE is valid. 2280 * When not valid, the egress VID will not be modified by the SMPE table. 2281 * Access: RW 2282 * 2283 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2284 */ 2285 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2286 2287 /* reg_smid2_smpe 2288 * Switch multicast port to egress VID. 2289 * Access: RW 2290 * 2291 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2292 */ 2293 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2294 2295 /* reg_smid2_port 2296 * Local port memebership (1 bit per port). 2297 * Access: RW 2298 */ 2299 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2300 2301 /* reg_smid2_port_mask 2302 * Local port mask (1 bit per port). 2303 * Access: WO 2304 */ 2305 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2306 2307 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2308 bool set, bool smpe_valid, u16 smpe) 2309 { 2310 MLXSW_REG_ZERO(smid2, payload); 2311 mlxsw_reg_smid2_swid_set(payload, 0); 2312 mlxsw_reg_smid2_mid_set(payload, mid); 2313 mlxsw_reg_smid2_port_set(payload, port, set); 2314 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2315 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2316 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2317 } 2318 2319 /* CWTP - Congetion WRED ECN TClass Profile 2320 * ---------------------------------------- 2321 * Configures the profiles for queues of egress port and traffic class 2322 */ 2323 #define MLXSW_REG_CWTP_ID 0x2802 2324 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2325 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2326 #define MLXSW_REG_CWTP_LEN 0x40 2327 2328 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2329 2330 /* reg_cwtp_local_port 2331 * Local port number 2332 * Not supported for CPU port 2333 * Access: Index 2334 */ 2335 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2336 2337 /* reg_cwtp_traffic_class 2338 * Traffic Class to configure 2339 * Access: Index 2340 */ 2341 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2342 2343 /* reg_cwtp_profile_min 2344 * Minimum Average Queue Size of the profile in cells. 2345 * Access: RW 2346 */ 2347 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2348 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2349 2350 /* reg_cwtp_profile_percent 2351 * Percentage of WRED and ECN marking for maximum Average Queue size 2352 * Range is 0 to 100, units of integer percentage 2353 * Access: RW 2354 */ 2355 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2356 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2357 2358 /* reg_cwtp_profile_max 2359 * Maximum Average Queue size of the profile in cells 2360 * Access: RW 2361 */ 2362 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2363 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2364 2365 #define MLXSW_REG_CWTP_MIN_VALUE 64 2366 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2367 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2368 2369 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2370 u8 traffic_class) 2371 { 2372 int i; 2373 2374 MLXSW_REG_ZERO(cwtp, payload); 2375 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2376 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2377 2378 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2379 mlxsw_reg_cwtp_profile_min_set(payload, i, 2380 MLXSW_REG_CWTP_MIN_VALUE); 2381 mlxsw_reg_cwtp_profile_max_set(payload, i, 2382 MLXSW_REG_CWTP_MIN_VALUE); 2383 } 2384 } 2385 2386 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2387 2388 static inline void 2389 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2390 u32 probability) 2391 { 2392 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2393 2394 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2395 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2396 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2397 } 2398 2399 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2400 * --------------------------------------------------- 2401 * The CWTPM register maps each egress port and traffic class to profile num. 2402 */ 2403 #define MLXSW_REG_CWTPM_ID 0x2803 2404 #define MLXSW_REG_CWTPM_LEN 0x44 2405 2406 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2407 2408 /* reg_cwtpm_local_port 2409 * Local port number 2410 * Not supported for CPU port 2411 * Access: Index 2412 */ 2413 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2414 2415 /* reg_cwtpm_traffic_class 2416 * Traffic Class to configure 2417 * Access: Index 2418 */ 2419 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2420 2421 /* reg_cwtpm_ew 2422 * Control enablement of WRED for traffic class: 2423 * 0 - Disable 2424 * 1 - Enable 2425 * Access: RW 2426 */ 2427 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2428 2429 /* reg_cwtpm_ee 2430 * Control enablement of ECN for traffic class: 2431 * 0 - Disable 2432 * 1 - Enable 2433 * Access: RW 2434 */ 2435 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2436 2437 /* reg_cwtpm_tcp_g 2438 * TCP Green Profile. 2439 * Index of the profile within {port, traffic class} to use. 2440 * 0 for disabling both WRED and ECN for this type of traffic. 2441 * Access: RW 2442 */ 2443 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2444 2445 /* reg_cwtpm_tcp_y 2446 * TCP Yellow Profile. 2447 * Index of the profile within {port, traffic class} to use. 2448 * 0 for disabling both WRED and ECN for this type of traffic. 2449 * Access: RW 2450 */ 2451 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2452 2453 /* reg_cwtpm_tcp_r 2454 * TCP Red Profile. 2455 * Index of the profile within {port, traffic class} to use. 2456 * 0 for disabling both WRED and ECN for this type of traffic. 2457 * Access: RW 2458 */ 2459 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2460 2461 /* reg_cwtpm_ntcp_g 2462 * Non-TCP Green Profile. 2463 * Index of the profile within {port, traffic class} to use. 2464 * 0 for disabling both WRED and ECN for this type of traffic. 2465 * Access: RW 2466 */ 2467 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2468 2469 /* reg_cwtpm_ntcp_y 2470 * Non-TCP Yellow Profile. 2471 * Index of the profile within {port, traffic class} to use. 2472 * 0 for disabling both WRED and ECN for this type of traffic. 2473 * Access: RW 2474 */ 2475 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2476 2477 /* reg_cwtpm_ntcp_r 2478 * Non-TCP Red Profile. 2479 * Index of the profile within {port, traffic class} to use. 2480 * 0 for disabling both WRED and ECN for this type of traffic. 2481 * Access: RW 2482 */ 2483 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2484 2485 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2486 2487 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2488 u8 traffic_class, u8 profile, 2489 bool wred, bool ecn) 2490 { 2491 MLXSW_REG_ZERO(cwtpm, payload); 2492 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2493 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2494 mlxsw_reg_cwtpm_ew_set(payload, wred); 2495 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2496 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2497 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2498 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2499 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2500 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2501 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2502 } 2503 2504 /* PGCR - Policy-Engine General Configuration Register 2505 * --------------------------------------------------- 2506 * This register configures general Policy-Engine settings. 2507 */ 2508 #define MLXSW_REG_PGCR_ID 0x3001 2509 #define MLXSW_REG_PGCR_LEN 0x20 2510 2511 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2512 2513 /* reg_pgcr_default_action_pointer_base 2514 * Default action pointer base. Each region has a default action pointer 2515 * which is equal to default_action_pointer_base + region_id. 2516 * Access: RW 2517 */ 2518 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2519 2520 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2521 { 2522 MLXSW_REG_ZERO(pgcr, payload); 2523 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2524 } 2525 2526 /* PPBT - Policy-Engine Port Binding Table 2527 * --------------------------------------- 2528 * This register is used for configuration of the Port Binding Table. 2529 */ 2530 #define MLXSW_REG_PPBT_ID 0x3002 2531 #define MLXSW_REG_PPBT_LEN 0x14 2532 2533 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2534 2535 enum mlxsw_reg_pxbt_e { 2536 MLXSW_REG_PXBT_E_IACL, 2537 MLXSW_REG_PXBT_E_EACL, 2538 }; 2539 2540 /* reg_ppbt_e 2541 * Access: Index 2542 */ 2543 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2544 2545 enum mlxsw_reg_pxbt_op { 2546 MLXSW_REG_PXBT_OP_BIND, 2547 MLXSW_REG_PXBT_OP_UNBIND, 2548 }; 2549 2550 /* reg_ppbt_op 2551 * Access: RW 2552 */ 2553 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2554 2555 /* reg_ppbt_local_port 2556 * Local port. Not including CPU port. 2557 * Access: Index 2558 */ 2559 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2560 2561 /* reg_ppbt_g 2562 * group - When set, the binding is of an ACL group. When cleared, 2563 * the binding is of an ACL. 2564 * Must be set to 1 for Spectrum. 2565 * Access: RW 2566 */ 2567 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2568 2569 /* reg_ppbt_acl_info 2570 * ACL/ACL group identifier. If the g bit is set, this field should hold 2571 * the acl_group_id, else it should hold the acl_id. 2572 * Access: RW 2573 */ 2574 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2575 2576 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2577 enum mlxsw_reg_pxbt_op op, 2578 u16 local_port, u16 acl_info) 2579 { 2580 MLXSW_REG_ZERO(ppbt, payload); 2581 mlxsw_reg_ppbt_e_set(payload, e); 2582 mlxsw_reg_ppbt_op_set(payload, op); 2583 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2584 mlxsw_reg_ppbt_g_set(payload, true); 2585 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2586 } 2587 2588 /* PACL - Policy-Engine ACL Register 2589 * --------------------------------- 2590 * This register is used for configuration of the ACL. 2591 */ 2592 #define MLXSW_REG_PACL_ID 0x3004 2593 #define MLXSW_REG_PACL_LEN 0x70 2594 2595 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2596 2597 /* reg_pacl_v 2598 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2599 * while the ACL is bounded to either a port, VLAN or ACL rule. 2600 * Access: RW 2601 */ 2602 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2603 2604 /* reg_pacl_acl_id 2605 * An identifier representing the ACL (managed by software) 2606 * Range 0 .. cap_max_acl_regions - 1 2607 * Access: Index 2608 */ 2609 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2610 2611 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2612 2613 /* reg_pacl_tcam_region_info 2614 * Opaque object that represents a TCAM region. 2615 * Obtained through PTAR register. 2616 * Access: RW 2617 */ 2618 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2619 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2620 2621 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2622 bool valid, const char *tcam_region_info) 2623 { 2624 MLXSW_REG_ZERO(pacl, payload); 2625 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2626 mlxsw_reg_pacl_v_set(payload, valid); 2627 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2628 } 2629 2630 /* PAGT - Policy-Engine ACL Group Table 2631 * ------------------------------------ 2632 * This register is used for configuration of the ACL Group Table. 2633 */ 2634 #define MLXSW_REG_PAGT_ID 0x3005 2635 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2636 #define MLXSW_REG_PAGT_ACL_LEN 4 2637 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2638 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2639 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2640 2641 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2642 2643 /* reg_pagt_size 2644 * Number of ACLs in the group. 2645 * Size 0 invalidates a group. 2646 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2647 * Total number of ACLs in all groups must be lower or equal 2648 * to cap_max_acl_tot_groups 2649 * Note: a group which is binded must not be invalidated 2650 * Access: Index 2651 */ 2652 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2653 2654 /* reg_pagt_acl_group_id 2655 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2656 * the ACL Group identifier (managed by software). 2657 * Access: Index 2658 */ 2659 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2660 2661 /* reg_pagt_multi 2662 * Multi-ACL 2663 * 0 - This ACL is the last ACL in the multi-ACL 2664 * 1 - This ACL is part of a multi-ACL 2665 * Access: RW 2666 */ 2667 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2668 2669 /* reg_pagt_acl_id 2670 * ACL identifier 2671 * Access: RW 2672 */ 2673 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2674 2675 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2676 { 2677 MLXSW_REG_ZERO(pagt, payload); 2678 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2679 } 2680 2681 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2682 u16 acl_id, bool multi) 2683 { 2684 u8 size = mlxsw_reg_pagt_size_get(payload); 2685 2686 if (index >= size) 2687 mlxsw_reg_pagt_size_set(payload, index + 1); 2688 mlxsw_reg_pagt_multi_set(payload, index, multi); 2689 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2690 } 2691 2692 /* PTAR - Policy-Engine TCAM Allocation Register 2693 * --------------------------------------------- 2694 * This register is used for allocation of regions in the TCAM. 2695 * Note: Query method is not supported on this register. 2696 */ 2697 #define MLXSW_REG_PTAR_ID 0x3006 2698 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2699 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2700 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2701 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2702 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2703 2704 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2705 2706 enum mlxsw_reg_ptar_op { 2707 /* allocate a TCAM region */ 2708 MLXSW_REG_PTAR_OP_ALLOC, 2709 /* resize a TCAM region */ 2710 MLXSW_REG_PTAR_OP_RESIZE, 2711 /* deallocate TCAM region */ 2712 MLXSW_REG_PTAR_OP_FREE, 2713 /* test allocation */ 2714 MLXSW_REG_PTAR_OP_TEST, 2715 }; 2716 2717 /* reg_ptar_op 2718 * Access: OP 2719 */ 2720 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2721 2722 /* reg_ptar_action_set_type 2723 * Type of action set to be used on this region. 2724 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2725 * Access: WO 2726 */ 2727 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2728 2729 enum mlxsw_reg_ptar_key_type { 2730 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2731 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2732 }; 2733 2734 /* reg_ptar_key_type 2735 * TCAM key type for the region. 2736 * Access: WO 2737 */ 2738 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2739 2740 /* reg_ptar_region_size 2741 * TCAM region size. When allocating/resizing this is the requested size, 2742 * the response is the actual size. Note that actual size may be 2743 * larger than requested. 2744 * Allowed range 1 .. cap_max_rules-1 2745 * Reserved during op deallocate. 2746 * Access: WO 2747 */ 2748 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2749 2750 /* reg_ptar_region_id 2751 * Region identifier 2752 * Range 0 .. cap_max_regions-1 2753 * Access: Index 2754 */ 2755 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2756 2757 /* reg_ptar_tcam_region_info 2758 * Opaque object that represents the TCAM region. 2759 * Returned when allocating a region. 2760 * Provided by software for ACL generation and region deallocation and resize. 2761 * Access: RW 2762 */ 2763 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2764 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2765 2766 /* reg_ptar_flexible_key_id 2767 * Identifier of the Flexible Key. 2768 * Only valid if key_type == "FLEX_KEY" 2769 * The key size will be rounded up to one of the following values: 2770 * 9B, 18B, 36B, 54B. 2771 * This field is reserved for in resize operation. 2772 * Access: WO 2773 */ 2774 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2775 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2776 2777 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2778 enum mlxsw_reg_ptar_key_type key_type, 2779 u16 region_size, u16 region_id, 2780 const char *tcam_region_info) 2781 { 2782 MLXSW_REG_ZERO(ptar, payload); 2783 mlxsw_reg_ptar_op_set(payload, op); 2784 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2785 mlxsw_reg_ptar_key_type_set(payload, key_type); 2786 mlxsw_reg_ptar_region_size_set(payload, region_size); 2787 mlxsw_reg_ptar_region_id_set(payload, region_id); 2788 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2789 } 2790 2791 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2792 u16 key_id) 2793 { 2794 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2795 } 2796 2797 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2798 { 2799 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2800 } 2801 2802 /* PPBS - Policy-Engine Policy Based Switching Register 2803 * ---------------------------------------------------- 2804 * This register retrieves and sets Policy Based Switching Table entries. 2805 */ 2806 #define MLXSW_REG_PPBS_ID 0x300C 2807 #define MLXSW_REG_PPBS_LEN 0x14 2808 2809 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2810 2811 /* reg_ppbs_pbs_ptr 2812 * Index into the PBS table. 2813 * For Spectrum, the index points to the KVD Linear. 2814 * Access: Index 2815 */ 2816 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2817 2818 /* reg_ppbs_system_port 2819 * Unique port identifier for the final destination of the packet. 2820 * Access: RW 2821 */ 2822 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2823 2824 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2825 u16 system_port) 2826 { 2827 MLXSW_REG_ZERO(ppbs, payload); 2828 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2829 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2830 } 2831 2832 /* PRCR - Policy-Engine Rules Copy Register 2833 * ---------------------------------------- 2834 * This register is used for accessing rules within a TCAM region. 2835 */ 2836 #define MLXSW_REG_PRCR_ID 0x300D 2837 #define MLXSW_REG_PRCR_LEN 0x40 2838 2839 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2840 2841 enum mlxsw_reg_prcr_op { 2842 /* Move rules. Moves the rules from "tcam_region_info" starting 2843 * at offset "offset" to "dest_tcam_region_info" 2844 * at offset "dest_offset." 2845 */ 2846 MLXSW_REG_PRCR_OP_MOVE, 2847 /* Copy rules. Copies the rules from "tcam_region_info" starting 2848 * at offset "offset" to "dest_tcam_region_info" 2849 * at offset "dest_offset." 2850 */ 2851 MLXSW_REG_PRCR_OP_COPY, 2852 }; 2853 2854 /* reg_prcr_op 2855 * Access: OP 2856 */ 2857 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2858 2859 /* reg_prcr_offset 2860 * Offset within the source region to copy/move from. 2861 * Access: Index 2862 */ 2863 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2864 2865 /* reg_prcr_size 2866 * The number of rules to copy/move. 2867 * Access: WO 2868 */ 2869 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2870 2871 /* reg_prcr_tcam_region_info 2872 * Opaque object that represents the source TCAM region. 2873 * Access: Index 2874 */ 2875 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2876 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2877 2878 /* reg_prcr_dest_offset 2879 * Offset within the source region to copy/move to. 2880 * Access: Index 2881 */ 2882 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2883 2884 /* reg_prcr_dest_tcam_region_info 2885 * Opaque object that represents the destination TCAM region. 2886 * Access: Index 2887 */ 2888 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2889 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2890 2891 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2892 const char *src_tcam_region_info, 2893 u16 src_offset, 2894 const char *dest_tcam_region_info, 2895 u16 dest_offset, u16 size) 2896 { 2897 MLXSW_REG_ZERO(prcr, payload); 2898 mlxsw_reg_prcr_op_set(payload, op); 2899 mlxsw_reg_prcr_offset_set(payload, src_offset); 2900 mlxsw_reg_prcr_size_set(payload, size); 2901 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2902 src_tcam_region_info); 2903 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2904 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2905 dest_tcam_region_info); 2906 } 2907 2908 /* PEFA - Policy-Engine Extended Flexible Action Register 2909 * ------------------------------------------------------ 2910 * This register is used for accessing an extended flexible action entry 2911 * in the central KVD Linear Database. 2912 */ 2913 #define MLXSW_REG_PEFA_ID 0x300F 2914 #define MLXSW_REG_PEFA_LEN 0xB0 2915 2916 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2917 2918 /* reg_pefa_index 2919 * Index in the KVD Linear Centralized Database. 2920 * Access: Index 2921 */ 2922 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2923 2924 /* reg_pefa_a 2925 * Index in the KVD Linear Centralized Database. 2926 * Activity 2927 * For a new entry: set if ca=0, clear if ca=1 2928 * Set if a packet lookup has hit on the specific entry 2929 * Access: RO 2930 */ 2931 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2932 2933 /* reg_pefa_ca 2934 * Clear activity 2935 * When write: activity is according to this field 2936 * When read: after reading the activity is cleared according to ca 2937 * Access: OP 2938 */ 2939 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2940 2941 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2942 2943 /* reg_pefa_flex_action_set 2944 * Action-set to perform when rule is matched. 2945 * Must be zero padded if action set is shorter. 2946 * Access: RW 2947 */ 2948 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2949 2950 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2951 const char *flex_action_set) 2952 { 2953 MLXSW_REG_ZERO(pefa, payload); 2954 mlxsw_reg_pefa_index_set(payload, index); 2955 mlxsw_reg_pefa_ca_set(payload, ca); 2956 if (flex_action_set) 2957 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2958 flex_action_set); 2959 } 2960 2961 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2962 { 2963 *p_a = mlxsw_reg_pefa_a_get(payload); 2964 } 2965 2966 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2967 * -------------------------------------------------------------- 2968 * This register is used for binding Multicast router to an ACL group 2969 * that serves the MC router. 2970 * This register is not supported by SwitchX/-2 and Spectrum. 2971 */ 2972 #define MLXSW_REG_PEMRBT_ID 0x3014 2973 #define MLXSW_REG_PEMRBT_LEN 0x14 2974 2975 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2976 2977 enum mlxsw_reg_pemrbt_protocol { 2978 MLXSW_REG_PEMRBT_PROTO_IPV4, 2979 MLXSW_REG_PEMRBT_PROTO_IPV6, 2980 }; 2981 2982 /* reg_pemrbt_protocol 2983 * Access: Index 2984 */ 2985 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2986 2987 /* reg_pemrbt_group_id 2988 * ACL group identifier. 2989 * Range 0..cap_max_acl_groups-1 2990 * Access: RW 2991 */ 2992 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2993 2994 static inline void 2995 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2996 u16 group_id) 2997 { 2998 MLXSW_REG_ZERO(pemrbt, payload); 2999 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3000 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3001 } 3002 3003 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3004 * ----------------------------------------------------- 3005 * This register is used for accessing rules within a TCAM region. 3006 * It is a new version of PTCE in order to support wider key, 3007 * mask and action within a TCAM region. This register is not supported 3008 * by SwitchX and SwitchX-2. 3009 */ 3010 #define MLXSW_REG_PTCE2_ID 0x3017 3011 #define MLXSW_REG_PTCE2_LEN 0x1D8 3012 3013 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3014 3015 /* reg_ptce2_v 3016 * Valid. 3017 * Access: RW 3018 */ 3019 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3020 3021 /* reg_ptce2_a 3022 * Activity. Set if a packet lookup has hit on the specific entry. 3023 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3024 * Access: RO 3025 */ 3026 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3027 3028 enum mlxsw_reg_ptce2_op { 3029 /* Read operation. */ 3030 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3031 /* clear on read operation. Used to read entry 3032 * and clear Activity bit. 3033 */ 3034 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3035 /* Write operation. Used to write a new entry to the table. 3036 * All R/W fields are relevant for new entry. Activity bit is set 3037 * for new entries - Note write with v = 0 will delete the entry. 3038 */ 3039 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3040 /* Update action. Only action set will be updated. */ 3041 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3042 /* Clear activity. A bit is cleared for the entry. */ 3043 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3044 }; 3045 3046 /* reg_ptce2_op 3047 * Access: OP 3048 */ 3049 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3050 3051 /* reg_ptce2_offset 3052 * Access: Index 3053 */ 3054 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3055 3056 /* reg_ptce2_priority 3057 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3058 * Note: priority does not have to be unique per rule. 3059 * Within a region, higher priority should have lower offset (no limitation 3060 * between regions in a multi-region). 3061 * Access: RW 3062 */ 3063 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3064 3065 /* reg_ptce2_tcam_region_info 3066 * Opaque object that represents the TCAM region. 3067 * Access: Index 3068 */ 3069 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3070 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3071 3072 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3073 3074 /* reg_ptce2_flex_key_blocks 3075 * ACL Key. 3076 * Access: RW 3077 */ 3078 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3079 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3080 3081 /* reg_ptce2_mask 3082 * mask- in the same size as key. A bit that is set directs the TCAM 3083 * to compare the corresponding bit in key. A bit that is clear directs 3084 * the TCAM to ignore the corresponding bit in key. 3085 * Access: RW 3086 */ 3087 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3088 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3089 3090 /* reg_ptce2_flex_action_set 3091 * ACL action set. 3092 * Access: RW 3093 */ 3094 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3095 MLXSW_REG_FLEX_ACTION_SET_LEN); 3096 3097 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3098 enum mlxsw_reg_ptce2_op op, 3099 const char *tcam_region_info, 3100 u16 offset, u32 priority) 3101 { 3102 MLXSW_REG_ZERO(ptce2, payload); 3103 mlxsw_reg_ptce2_v_set(payload, valid); 3104 mlxsw_reg_ptce2_op_set(payload, op); 3105 mlxsw_reg_ptce2_offset_set(payload, offset); 3106 mlxsw_reg_ptce2_priority_set(payload, priority); 3107 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3108 } 3109 3110 /* PERPT - Policy-Engine ERP Table Register 3111 * ---------------------------------------- 3112 * This register adds and removes eRPs from the eRP table. 3113 */ 3114 #define MLXSW_REG_PERPT_ID 0x3021 3115 #define MLXSW_REG_PERPT_LEN 0x80 3116 3117 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3118 3119 /* reg_perpt_erpt_bank 3120 * eRP table bank. 3121 * Range 0 .. cap_max_erp_table_banks - 1 3122 * Access: Index 3123 */ 3124 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3125 3126 /* reg_perpt_erpt_index 3127 * Index to eRP table within the eRP bank. 3128 * Range is 0 .. cap_max_erp_table_bank_size - 1 3129 * Access: Index 3130 */ 3131 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3132 3133 enum mlxsw_reg_perpt_key_size { 3134 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3135 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3136 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3137 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3138 }; 3139 3140 /* reg_perpt_key_size 3141 * Access: OP 3142 */ 3143 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3144 3145 /* reg_perpt_bf_bypass 3146 * 0 - The eRP is used only if bloom filter state is set for the given 3147 * rule. 3148 * 1 - The eRP is used regardless of bloom filter state. 3149 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3150 * Access: RW 3151 */ 3152 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3153 3154 /* reg_perpt_erp_id 3155 * eRP ID for use by the rules. 3156 * Access: RW 3157 */ 3158 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3159 3160 /* reg_perpt_erpt_base_bank 3161 * Base eRP table bank, points to head of erp_vector 3162 * Range is 0 .. cap_max_erp_table_banks - 1 3163 * Access: OP 3164 */ 3165 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3166 3167 /* reg_perpt_erpt_base_index 3168 * Base index to eRP table within the eRP bank 3169 * Range is 0 .. cap_max_erp_table_bank_size - 1 3170 * Access: OP 3171 */ 3172 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3173 3174 /* reg_perpt_erp_index_in_vector 3175 * eRP index in the vector. 3176 * Access: OP 3177 */ 3178 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3179 3180 /* reg_perpt_erp_vector 3181 * eRP vector. 3182 * Access: OP 3183 */ 3184 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3185 3186 /* reg_perpt_mask 3187 * Mask 3188 * 0 - A-TCAM will ignore the bit in key 3189 * 1 - A-TCAM will compare the bit in key 3190 * Access: RW 3191 */ 3192 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3193 3194 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3195 unsigned long *erp_vector, 3196 unsigned long size) 3197 { 3198 unsigned long bit; 3199 3200 for_each_set_bit(bit, erp_vector, size) 3201 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3202 } 3203 3204 static inline void 3205 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3206 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3207 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3208 char *mask) 3209 { 3210 MLXSW_REG_ZERO(perpt, payload); 3211 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3212 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3213 mlxsw_reg_perpt_key_size_set(payload, key_size); 3214 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3215 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3216 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3217 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3218 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3219 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3220 } 3221 3222 /* PERAR - Policy-Engine Region Association Register 3223 * ------------------------------------------------- 3224 * This register associates a hw region for region_id's. Changing on the fly 3225 * is supported by the device. 3226 */ 3227 #define MLXSW_REG_PERAR_ID 0x3026 3228 #define MLXSW_REG_PERAR_LEN 0x08 3229 3230 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3231 3232 /* reg_perar_region_id 3233 * Region identifier 3234 * Range 0 .. cap_max_regions-1 3235 * Access: Index 3236 */ 3237 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3238 3239 static inline unsigned int 3240 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3241 { 3242 return DIV_ROUND_UP(block_num, 4); 3243 } 3244 3245 /* reg_perar_hw_region 3246 * HW Region 3247 * Range 0 .. cap_max_regions-1 3248 * Default: hw_region = region_id 3249 * For a 8 key block region, 2 consecutive regions are used 3250 * For a 12 key block region, 3 consecutive regions are used 3251 * Access: RW 3252 */ 3253 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3254 3255 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3256 u16 hw_region) 3257 { 3258 MLXSW_REG_ZERO(perar, payload); 3259 mlxsw_reg_perar_region_id_set(payload, region_id); 3260 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3261 } 3262 3263 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3264 * ----------------------------------------------------- 3265 * This register is a new version of PTCE-V2 in order to support the 3266 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3267 */ 3268 #define MLXSW_REG_PTCE3_ID 0x3027 3269 #define MLXSW_REG_PTCE3_LEN 0xF0 3270 3271 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3272 3273 /* reg_ptce3_v 3274 * Valid. 3275 * Access: RW 3276 */ 3277 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3278 3279 enum mlxsw_reg_ptce3_op { 3280 /* Write operation. Used to write a new entry to the table. 3281 * All R/W fields are relevant for new entry. Activity bit is set 3282 * for new entries. Write with v = 0 will delete the entry. Must 3283 * not be used if an entry exists. 3284 */ 3285 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3286 /* Update operation */ 3287 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3288 /* Read operation */ 3289 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3290 }; 3291 3292 /* reg_ptce3_op 3293 * Access: OP 3294 */ 3295 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3296 3297 /* reg_ptce3_priority 3298 * Priority of the rule. Higher values win. 3299 * For Spectrum-2 range is 1..cap_kvd_size - 1 3300 * Note: Priority does not have to be unique per rule. 3301 * Access: RW 3302 */ 3303 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3304 3305 /* reg_ptce3_tcam_region_info 3306 * Opaque object that represents the TCAM region. 3307 * Access: Index 3308 */ 3309 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3310 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3311 3312 /* reg_ptce3_flex2_key_blocks 3313 * ACL key. The key must be masked according to eRP (if exists) or 3314 * according to master mask. 3315 * Access: Index 3316 */ 3317 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3318 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3319 3320 /* reg_ptce3_erp_id 3321 * eRP ID. 3322 * Access: Index 3323 */ 3324 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3325 3326 /* reg_ptce3_delta_start 3327 * Start point of delta_value and delta_mask, in bits. Must not exceed 3328 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3329 * Access: Index 3330 */ 3331 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3332 3333 /* reg_ptce3_delta_mask 3334 * Delta mask. 3335 * 0 - Ignore relevant bit in delta_value 3336 * 1 - Compare relevant bit in delta_value 3337 * Delta mask must not be set for reserved fields in the key blocks. 3338 * Note: No delta when no eRPs. Thus, for regions with 3339 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3340 * Access: Index 3341 */ 3342 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3343 3344 /* reg_ptce3_delta_value 3345 * Delta value. 3346 * Bits which are masked by delta_mask must be 0. 3347 * Access: Index 3348 */ 3349 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3350 3351 /* reg_ptce3_prune_vector 3352 * Pruning vector relative to the PERPT.erp_id. 3353 * Used for reducing lookups. 3354 * 0 - NEED: Do a lookup using the eRP. 3355 * 1 - PRUNE: Do not perform a lookup using the eRP. 3356 * Maybe be modified by PEAPBL and PEAPBM. 3357 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3358 * all 1's or all 0's. 3359 * Access: RW 3360 */ 3361 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3362 3363 /* reg_ptce3_prune_ctcam 3364 * Pruning on C-TCAM. Used for reducing lookups. 3365 * 0 - NEED: Do a lookup in the C-TCAM. 3366 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3367 * Access: RW 3368 */ 3369 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3370 3371 /* reg_ptce3_large_exists 3372 * Large entry key ID exists. 3373 * Within the region: 3374 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3375 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3376 * For rule delete: The MSB of the key will be removed. 3377 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3378 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3379 * For rule delete: The MSB of the key will not be removed. 3380 * Access: WO 3381 */ 3382 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3383 3384 /* reg_ptce3_large_entry_key_id 3385 * Large entry key ID. 3386 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3387 * blocks. Must be different for different keys which have the same common 3388 * 6 key blocks (MSB, blocks 6..11) key within a region. 3389 * Range is 0..cap_max_pe_large_key_id - 1 3390 * Access: RW 3391 */ 3392 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3393 3394 /* reg_ptce3_action_pointer 3395 * Pointer to action. 3396 * Range is 0..cap_max_kvd_action_sets - 1 3397 * Access: RW 3398 */ 3399 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3400 3401 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3402 enum mlxsw_reg_ptce3_op op, 3403 u32 priority, 3404 const char *tcam_region_info, 3405 const char *key, u8 erp_id, 3406 u16 delta_start, u8 delta_mask, 3407 u8 delta_value, bool large_exists, 3408 u32 lkey_id, u32 action_pointer) 3409 { 3410 MLXSW_REG_ZERO(ptce3, payload); 3411 mlxsw_reg_ptce3_v_set(payload, valid); 3412 mlxsw_reg_ptce3_op_set(payload, op); 3413 mlxsw_reg_ptce3_priority_set(payload, priority); 3414 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3415 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3416 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3417 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3418 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3419 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3420 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3421 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3422 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3423 } 3424 3425 /* PERCR - Policy-Engine Region Configuration Register 3426 * --------------------------------------------------- 3427 * This register configures the region parameters. The region_id must be 3428 * allocated. 3429 */ 3430 #define MLXSW_REG_PERCR_ID 0x302A 3431 #define MLXSW_REG_PERCR_LEN 0x80 3432 3433 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3434 3435 /* reg_percr_region_id 3436 * Region identifier. 3437 * Range 0..cap_max_regions-1 3438 * Access: Index 3439 */ 3440 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3441 3442 /* reg_percr_atcam_ignore_prune 3443 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3444 * Access: RW 3445 */ 3446 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3447 3448 /* reg_percr_ctcam_ignore_prune 3449 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3450 * Access: RW 3451 */ 3452 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3453 3454 /* reg_percr_bf_bypass 3455 * Bloom filter bypass. 3456 * 0 - Bloom filter is used (default) 3457 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3458 * region_id or eRP. See PERPT.bf_bypass 3459 * Access: RW 3460 */ 3461 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3462 3463 /* reg_percr_master_mask 3464 * Master mask. Logical OR mask of all masks of all rules of a region 3465 * (both A-TCAM and C-TCAM). When there are no eRPs 3466 * (erpt_pointer_valid = 0), then this provides the mask. 3467 * Access: RW 3468 */ 3469 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3470 3471 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3472 { 3473 MLXSW_REG_ZERO(percr, payload); 3474 mlxsw_reg_percr_region_id_set(payload, region_id); 3475 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3476 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3477 mlxsw_reg_percr_bf_bypass_set(payload, false); 3478 } 3479 3480 /* PERERP - Policy-Engine Region eRP Register 3481 * ------------------------------------------ 3482 * This register configures the region eRP. The region_id must be 3483 * allocated. 3484 */ 3485 #define MLXSW_REG_PERERP_ID 0x302B 3486 #define MLXSW_REG_PERERP_LEN 0x1C 3487 3488 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3489 3490 /* reg_pererp_region_id 3491 * Region identifier. 3492 * Range 0..cap_max_regions-1 3493 * Access: Index 3494 */ 3495 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3496 3497 /* reg_pererp_ctcam_le 3498 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3499 * Access: RW 3500 */ 3501 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3502 3503 /* reg_pererp_erpt_pointer_valid 3504 * erpt_pointer is valid. 3505 * Access: RW 3506 */ 3507 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3508 3509 /* reg_pererp_erpt_bank_pointer 3510 * Pointer to eRP table bank. May be modified at any time. 3511 * Range 0..cap_max_erp_table_banks-1 3512 * Reserved when erpt_pointer_valid = 0 3513 */ 3514 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3515 3516 /* reg_pererp_erpt_pointer 3517 * Pointer to eRP table within the eRP bank. Can be changed for an 3518 * existing region. 3519 * Range 0..cap_max_erp_table_size-1 3520 * Reserved when erpt_pointer_valid = 0 3521 * Access: RW 3522 */ 3523 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3524 3525 /* reg_pererp_erpt_vector 3526 * Vector of allowed eRP indexes starting from erpt_pointer within the 3527 * erpt_bank_pointer. Next entries will be in next bank. 3528 * Note that eRP index is used and not eRP ID. 3529 * Reserved when erpt_pointer_valid = 0 3530 * Access: RW 3531 */ 3532 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3533 3534 /* reg_pererp_master_rp_id 3535 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3536 * for the lookup. Can be changed for an existing region. 3537 * Reserved when erpt_pointer_valid = 1 3538 * Access: RW 3539 */ 3540 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3541 3542 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3543 unsigned long *erp_vector, 3544 unsigned long size) 3545 { 3546 unsigned long bit; 3547 3548 for_each_set_bit(bit, erp_vector, size) 3549 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3550 } 3551 3552 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3553 bool ctcam_le, bool erpt_pointer_valid, 3554 u8 erpt_bank_pointer, u8 erpt_pointer, 3555 u8 master_rp_id) 3556 { 3557 MLXSW_REG_ZERO(pererp, payload); 3558 mlxsw_reg_pererp_region_id_set(payload, region_id); 3559 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3560 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3561 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3562 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3563 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3564 } 3565 3566 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3567 * ---------------------------------------------------------------- 3568 * This register configures the Bloom filter entries. 3569 */ 3570 #define MLXSW_REG_PEABFE_ID 0x3022 3571 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3572 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3573 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3574 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3575 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3576 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3577 3578 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3579 3580 /* reg_peabfe_size 3581 * Number of BF entries to be updated. 3582 * Range 1..256 3583 * Access: Op 3584 */ 3585 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3586 3587 /* reg_peabfe_bf_entry_state 3588 * Bloom filter state 3589 * 0 - Clear 3590 * 1 - Set 3591 * Access: RW 3592 */ 3593 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3594 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3595 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3596 3597 /* reg_peabfe_bf_entry_bank 3598 * Bloom filter bank ID 3599 * Range 0..cap_max_erp_table_banks-1 3600 * Access: Index 3601 */ 3602 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3603 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3604 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3605 3606 /* reg_peabfe_bf_entry_index 3607 * Bloom filter entry index 3608 * Range 0..2^cap_max_bf_log-1 3609 * Access: Index 3610 */ 3611 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3612 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3613 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3614 3615 static inline void mlxsw_reg_peabfe_pack(char *payload) 3616 { 3617 MLXSW_REG_ZERO(peabfe, payload); 3618 } 3619 3620 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3621 u8 state, u8 bank, u32 bf_index) 3622 { 3623 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3624 3625 if (rec_index >= num_rec) 3626 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3627 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3628 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3629 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3630 } 3631 3632 /* IEDR - Infrastructure Entry Delete Register 3633 * ---------------------------------------------------- 3634 * This register is used for deleting entries from the entry tables. 3635 * It is legitimate to attempt to delete a nonexisting entry (the device will 3636 * respond as a good flow). 3637 */ 3638 #define MLXSW_REG_IEDR_ID 0x3804 3639 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3640 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3641 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3642 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3643 MLXSW_REG_IEDR_REC_LEN * \ 3644 MLXSW_REG_IEDR_REC_MAX_COUNT) 3645 3646 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3647 3648 /* reg_iedr_num_rec 3649 * Number of records. 3650 * Access: OP 3651 */ 3652 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3653 3654 /* reg_iedr_rec_type 3655 * Resource type. 3656 * Access: OP 3657 */ 3658 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3659 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3660 3661 /* reg_iedr_rec_size 3662 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3663 * Access: OP 3664 */ 3665 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3666 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3667 3668 /* reg_iedr_rec_index_start 3669 * Resource index start. 3670 * Access: OP 3671 */ 3672 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3673 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3674 3675 static inline void mlxsw_reg_iedr_pack(char *payload) 3676 { 3677 MLXSW_REG_ZERO(iedr, payload); 3678 } 3679 3680 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3681 u8 rec_type, u16 rec_size, 3682 u32 rec_index_start) 3683 { 3684 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3685 3686 if (rec_index >= num_rec) 3687 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3688 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3689 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3690 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3691 } 3692 3693 /* QPTS - QoS Priority Trust State Register 3694 * ---------------------------------------- 3695 * This register controls the port policy to calculate the switch priority and 3696 * packet color based on incoming packet fields. 3697 */ 3698 #define MLXSW_REG_QPTS_ID 0x4002 3699 #define MLXSW_REG_QPTS_LEN 0x8 3700 3701 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3702 3703 /* reg_qpts_local_port 3704 * Local port number. 3705 * Access: Index 3706 * 3707 * Note: CPU port is supported. 3708 */ 3709 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3710 3711 enum mlxsw_reg_qpts_trust_state { 3712 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3713 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3714 }; 3715 3716 /* reg_qpts_trust_state 3717 * Trust state for a given port. 3718 * Access: RW 3719 */ 3720 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3721 3722 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3723 enum mlxsw_reg_qpts_trust_state ts) 3724 { 3725 MLXSW_REG_ZERO(qpts, payload); 3726 3727 mlxsw_reg_qpts_local_port_set(payload, local_port); 3728 mlxsw_reg_qpts_trust_state_set(payload, ts); 3729 } 3730 3731 /* QPCR - QoS Policer Configuration Register 3732 * ----------------------------------------- 3733 * The QPCR register is used to create policers - that limit 3734 * the rate of bytes or packets via some trap group. 3735 */ 3736 #define MLXSW_REG_QPCR_ID 0x4004 3737 #define MLXSW_REG_QPCR_LEN 0x28 3738 3739 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3740 3741 enum mlxsw_reg_qpcr_g { 3742 MLXSW_REG_QPCR_G_GLOBAL = 2, 3743 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3744 }; 3745 3746 /* reg_qpcr_g 3747 * The policer type. 3748 * Access: Index 3749 */ 3750 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3751 3752 /* reg_qpcr_pid 3753 * Policer ID. 3754 * Access: Index 3755 */ 3756 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3757 3758 /* reg_qpcr_clear_counter 3759 * Clear counters. 3760 * Access: OP 3761 */ 3762 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3763 3764 /* reg_qpcr_color_aware 3765 * Is the policer aware of colors. 3766 * Must be 0 (unaware) for cpu port. 3767 * Access: RW for unbounded policer. RO for bounded policer. 3768 */ 3769 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3770 3771 /* reg_qpcr_bytes 3772 * Is policer limit is for bytes per sec or packets per sec. 3773 * 0 - packets 3774 * 1 - bytes 3775 * Access: RW for unbounded policer. RO for bounded policer. 3776 */ 3777 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3778 3779 enum mlxsw_reg_qpcr_ir_units { 3780 MLXSW_REG_QPCR_IR_UNITS_M, 3781 MLXSW_REG_QPCR_IR_UNITS_K, 3782 }; 3783 3784 /* reg_qpcr_ir_units 3785 * Policer's units for cir and eir fields (for bytes limits only) 3786 * 1 - 10^3 3787 * 0 - 10^6 3788 * Access: OP 3789 */ 3790 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3791 3792 enum mlxsw_reg_qpcr_rate_type { 3793 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3794 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3795 }; 3796 3797 /* reg_qpcr_rate_type 3798 * Policer can have one limit (single rate) or 2 limits with specific operation 3799 * for packets that exceed the lower rate but not the upper one. 3800 * (For cpu port must be single rate) 3801 * Access: RW for unbounded policer. RO for bounded policer. 3802 */ 3803 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3804 3805 /* reg_qpc_cbs 3806 * Policer's committed burst size. 3807 * The policer is working with time slices of 50 nano sec. By default every 3808 * slice is granted the proportionate share of the committed rate. If we want to 3809 * allow a slice to exceed that share (while still keeping the rate per sec) we 3810 * can allow burst. The burst size is between the default proportionate share 3811 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3812 * committed rate will result in exceeding the rate). The burst size must be a 3813 * log of 2 and will be determined by 2^cbs. 3814 * Access: RW 3815 */ 3816 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3817 3818 /* reg_qpcr_cir 3819 * Policer's committed rate. 3820 * The rate used for sungle rate, the lower rate for double rate. 3821 * For bytes limits, the rate will be this value * the unit from ir_units. 3822 * (Resolution error is up to 1%). 3823 * Access: RW 3824 */ 3825 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3826 3827 /* reg_qpcr_eir 3828 * Policer's exceed rate. 3829 * The higher rate for double rate, reserved for single rate. 3830 * Lower rate for double rate policer. 3831 * For bytes limits, the rate will be this value * the unit from ir_units. 3832 * (Resolution error is up to 1%). 3833 * Access: RW 3834 */ 3835 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3836 3837 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3838 3839 /* reg_qpcr_exceed_action. 3840 * What to do with packets between the 2 limits for double rate. 3841 * Access: RW for unbounded policer. RO for bounded policer. 3842 */ 3843 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3844 3845 enum mlxsw_reg_qpcr_action { 3846 /* Discard */ 3847 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3848 /* Forward and set color to red. 3849 * If the packet is intended to cpu port, it will be dropped. 3850 */ 3851 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3852 }; 3853 3854 /* reg_qpcr_violate_action 3855 * What to do with packets that cross the cir limit (for single rate) or the eir 3856 * limit (for double rate). 3857 * Access: RW for unbounded policer. RO for bounded policer. 3858 */ 3859 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3860 3861 /* reg_qpcr_violate_count 3862 * Counts the number of times violate_action happened on this PID. 3863 * Access: RW 3864 */ 3865 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3866 3867 /* Packets */ 3868 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3869 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3870 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3871 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3872 3873 /* Bandwidth */ 3874 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3875 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3876 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3877 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3878 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3879 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3880 3881 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3882 enum mlxsw_reg_qpcr_ir_units ir_units, 3883 bool bytes, u32 cir, u16 cbs) 3884 { 3885 MLXSW_REG_ZERO(qpcr, payload); 3886 mlxsw_reg_qpcr_pid_set(payload, pid); 3887 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3888 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3889 mlxsw_reg_qpcr_violate_action_set(payload, 3890 MLXSW_REG_QPCR_ACTION_DISCARD); 3891 mlxsw_reg_qpcr_cir_set(payload, cir); 3892 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3893 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3894 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3895 } 3896 3897 /* QTCT - QoS Switch Traffic Class Table 3898 * ------------------------------------- 3899 * Configures the mapping between the packet switch priority and the 3900 * traffic class on the transmit port. 3901 */ 3902 #define MLXSW_REG_QTCT_ID 0x400A 3903 #define MLXSW_REG_QTCT_LEN 0x08 3904 3905 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3906 3907 /* reg_qtct_local_port 3908 * Local port number. 3909 * Access: Index 3910 * 3911 * Note: CPU port is not supported. 3912 */ 3913 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3914 3915 /* reg_qtct_sub_port 3916 * Virtual port within the physical port. 3917 * Should be set to 0 when virtual ports are not enabled on the port. 3918 * Access: Index 3919 */ 3920 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3921 3922 /* reg_qtct_switch_prio 3923 * Switch priority. 3924 * Access: Index 3925 */ 3926 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3927 3928 /* reg_qtct_tclass 3929 * Traffic class. 3930 * Default values: 3931 * switch_prio 0 : tclass 1 3932 * switch_prio 1 : tclass 0 3933 * switch_prio i : tclass i, for i > 1 3934 * Access: RW 3935 */ 3936 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3937 3938 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3939 u8 switch_prio, u8 tclass) 3940 { 3941 MLXSW_REG_ZERO(qtct, payload); 3942 mlxsw_reg_qtct_local_port_set(payload, local_port); 3943 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3944 mlxsw_reg_qtct_tclass_set(payload, tclass); 3945 } 3946 3947 /* QEEC - QoS ETS Element Configuration Register 3948 * --------------------------------------------- 3949 * Configures the ETS elements. 3950 */ 3951 #define MLXSW_REG_QEEC_ID 0x400D 3952 #define MLXSW_REG_QEEC_LEN 0x20 3953 3954 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3955 3956 /* reg_qeec_local_port 3957 * Local port number. 3958 * Access: Index 3959 * 3960 * Note: CPU port is supported. 3961 */ 3962 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3963 3964 enum mlxsw_reg_qeec_hr { 3965 MLXSW_REG_QEEC_HR_PORT, 3966 MLXSW_REG_QEEC_HR_GROUP, 3967 MLXSW_REG_QEEC_HR_SUBGROUP, 3968 MLXSW_REG_QEEC_HR_TC, 3969 }; 3970 3971 /* reg_qeec_element_hierarchy 3972 * 0 - Port 3973 * 1 - Group 3974 * 2 - Subgroup 3975 * 3 - Traffic Class 3976 * Access: Index 3977 */ 3978 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3979 3980 /* reg_qeec_element_index 3981 * The index of the element in the hierarchy. 3982 * Access: Index 3983 */ 3984 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3985 3986 /* reg_qeec_next_element_index 3987 * The index of the next (lower) element in the hierarchy. 3988 * Access: RW 3989 * 3990 * Note: Reserved for element_hierarchy 0. 3991 */ 3992 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3993 3994 /* reg_qeec_mise 3995 * Min shaper configuration enable. Enables configuration of the min 3996 * shaper on this ETS element 3997 * 0 - Disable 3998 * 1 - Enable 3999 * Access: RW 4000 */ 4001 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4002 4003 /* reg_qeec_ptps 4004 * PTP shaper 4005 * 0: regular shaper mode 4006 * 1: PTP oriented shaper 4007 * Allowed only for hierarchy 0 4008 * Not supported for CPU port 4009 * Note that ptps mode may affect the shaper rates of all hierarchies 4010 * Supported only on Spectrum-1 4011 * Access: RW 4012 */ 4013 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4014 4015 enum { 4016 MLXSW_REG_QEEC_BYTES_MODE, 4017 MLXSW_REG_QEEC_PACKETS_MODE, 4018 }; 4019 4020 /* reg_qeec_pb 4021 * Packets or bytes mode. 4022 * 0 - Bytes mode 4023 * 1 - Packets mode 4024 * Access: RW 4025 * 4026 * Note: Used for max shaper configuration. For Spectrum, packets mode 4027 * is supported only for traffic classes of CPU port. 4028 */ 4029 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4030 4031 /* The smallest permitted min shaper rate. */ 4032 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4033 4034 /* reg_qeec_min_shaper_rate 4035 * Min shaper information rate. 4036 * For CPU port, can only be configured for port hierarchy. 4037 * When in bytes mode, value is specified in units of 1000bps. 4038 * Access: RW 4039 */ 4040 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4041 4042 /* reg_qeec_mase 4043 * Max shaper configuration enable. Enables configuration of the max 4044 * shaper on this ETS element. 4045 * 0 - Disable 4046 * 1 - Enable 4047 * Access: RW 4048 */ 4049 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4050 4051 /* The largest max shaper value possible to disable the shaper. */ 4052 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4053 4054 /* reg_qeec_max_shaper_rate 4055 * Max shaper information rate. 4056 * For CPU port, can only be configured for port hierarchy. 4057 * When in bytes mode, value is specified in units of 1000bps. 4058 * Access: RW 4059 */ 4060 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4061 4062 /* reg_qeec_de 4063 * DWRR configuration enable. Enables configuration of the dwrr and 4064 * dwrr_weight. 4065 * 0 - Disable 4066 * 1 - Enable 4067 * Access: RW 4068 */ 4069 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4070 4071 /* reg_qeec_dwrr 4072 * Transmission selection algorithm to use on the link going down from 4073 * the ETS element. 4074 * 0 - Strict priority 4075 * 1 - DWRR 4076 * Access: RW 4077 */ 4078 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4079 4080 /* reg_qeec_dwrr_weight 4081 * DWRR weight on the link going down from the ETS element. The 4082 * percentage of bandwidth guaranteed to an ETS element within 4083 * its hierarchy. The sum of all weights across all ETS elements 4084 * within one hierarchy should be equal to 100. Reserved when 4085 * transmission selection algorithm is strict priority. 4086 * Access: RW 4087 */ 4088 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4089 4090 /* reg_qeec_max_shaper_bs 4091 * Max shaper burst size 4092 * Burst size is 2^max_shaper_bs * 512 bits 4093 * For Spectrum-1: Range is: 5..25 4094 * For Spectrum-2: Range is: 11..25 4095 * Reserved when ptps = 1 4096 * Access: RW 4097 */ 4098 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4099 4100 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4101 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4102 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4103 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4104 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4105 4106 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4107 enum mlxsw_reg_qeec_hr hr, u8 index, 4108 u8 next_index) 4109 { 4110 MLXSW_REG_ZERO(qeec, payload); 4111 mlxsw_reg_qeec_local_port_set(payload, local_port); 4112 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4113 mlxsw_reg_qeec_element_index_set(payload, index); 4114 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4115 } 4116 4117 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4118 bool ptps) 4119 { 4120 MLXSW_REG_ZERO(qeec, payload); 4121 mlxsw_reg_qeec_local_port_set(payload, local_port); 4122 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4123 mlxsw_reg_qeec_ptps_set(payload, ptps); 4124 } 4125 4126 /* QRWE - QoS ReWrite Enable 4127 * ------------------------- 4128 * This register configures the rewrite enable per receive port. 4129 */ 4130 #define MLXSW_REG_QRWE_ID 0x400F 4131 #define MLXSW_REG_QRWE_LEN 0x08 4132 4133 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4134 4135 /* reg_qrwe_local_port 4136 * Local port number. 4137 * Access: Index 4138 * 4139 * Note: CPU port is supported. No support for router port. 4140 */ 4141 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4142 4143 /* reg_qrwe_dscp 4144 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4145 * Access: RW 4146 */ 4147 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4148 4149 /* reg_qrwe_pcp 4150 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4151 * Access: RW 4152 */ 4153 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4154 4155 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4156 bool rewrite_pcp, bool rewrite_dscp) 4157 { 4158 MLXSW_REG_ZERO(qrwe, payload); 4159 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4160 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4161 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4162 } 4163 4164 /* QPDSM - QoS Priority to DSCP Mapping 4165 * ------------------------------------ 4166 * QoS Priority to DSCP Mapping Register 4167 */ 4168 #define MLXSW_REG_QPDSM_ID 0x4011 4169 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4170 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4171 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4172 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4173 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4174 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4175 4176 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4177 4178 /* reg_qpdsm_local_port 4179 * Local Port. Supported for data packets from CPU port. 4180 * Access: Index 4181 */ 4182 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4183 4184 /* reg_qpdsm_prio_entry_color0_e 4185 * Enable update of the entry for color 0 and a given port. 4186 * Access: WO 4187 */ 4188 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4189 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4190 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4191 4192 /* reg_qpdsm_prio_entry_color0_dscp 4193 * DSCP field in the outer label of the packet for color 0 and a given port. 4194 * Reserved when e=0. 4195 * Access: RW 4196 */ 4197 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4198 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4199 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4200 4201 /* reg_qpdsm_prio_entry_color1_e 4202 * Enable update of the entry for color 1 and a given port. 4203 * Access: WO 4204 */ 4205 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4206 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4207 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4208 4209 /* reg_qpdsm_prio_entry_color1_dscp 4210 * DSCP field in the outer label of the packet for color 1 and a given port. 4211 * Reserved when e=0. 4212 * Access: RW 4213 */ 4214 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4215 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4216 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4217 4218 /* reg_qpdsm_prio_entry_color2_e 4219 * Enable update of the entry for color 2 and a given port. 4220 * Access: WO 4221 */ 4222 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4223 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4224 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4225 4226 /* reg_qpdsm_prio_entry_color2_dscp 4227 * DSCP field in the outer label of the packet for color 2 and a given port. 4228 * Reserved when e=0. 4229 * Access: RW 4230 */ 4231 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4232 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4233 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4234 4235 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4236 { 4237 MLXSW_REG_ZERO(qpdsm, payload); 4238 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4239 } 4240 4241 static inline void 4242 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4243 { 4244 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4245 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4246 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4247 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4248 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4249 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4250 } 4251 4252 /* QPDP - QoS Port DSCP to Priority Mapping Register 4253 * ------------------------------------------------- 4254 * This register controls the port default Switch Priority and Color. The 4255 * default Switch Priority and Color are used for frames where the trust state 4256 * uses default values. All member ports of a LAG should be configured with the 4257 * same default values. 4258 */ 4259 #define MLXSW_REG_QPDP_ID 0x4007 4260 #define MLXSW_REG_QPDP_LEN 0x8 4261 4262 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4263 4264 /* reg_qpdp_local_port 4265 * Local Port. Supported for data packets from CPU port. 4266 * Access: Index 4267 */ 4268 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4269 4270 /* reg_qpdp_switch_prio 4271 * Default port Switch Priority (default 0) 4272 * Access: RW 4273 */ 4274 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4275 4276 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4277 u8 switch_prio) 4278 { 4279 MLXSW_REG_ZERO(qpdp, payload); 4280 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4281 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4282 } 4283 4284 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4285 * -------------------------------------------------- 4286 * This register controls the mapping from DSCP field to 4287 * Switch Priority for IP packets. 4288 */ 4289 #define MLXSW_REG_QPDPM_ID 0x4013 4290 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4291 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4292 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4293 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4294 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4295 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4296 4297 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4298 4299 /* reg_qpdpm_local_port 4300 * Local Port. Supported for data packets from CPU port. 4301 * Access: Index 4302 */ 4303 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4304 4305 /* reg_qpdpm_dscp_e 4306 * Enable update of the specific entry. When cleared, the switch_prio and color 4307 * fields are ignored and the previous switch_prio and color values are 4308 * preserved. 4309 * Access: WO 4310 */ 4311 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4312 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4313 4314 /* reg_qpdpm_dscp_prio 4315 * The new Switch Priority value for the relevant DSCP value. 4316 * Access: RW 4317 */ 4318 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4319 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4320 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4321 4322 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4323 { 4324 MLXSW_REG_ZERO(qpdpm, payload); 4325 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4326 } 4327 4328 static inline void 4329 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4330 { 4331 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4332 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4333 } 4334 4335 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4336 * ------------------------------------------------------------------ 4337 * This register configures if the Switch Priority to Traffic Class mapping is 4338 * based on Multicast packet indication. If so, then multicast packets will get 4339 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4340 * QTCT. 4341 * By default, Switch Priority to Traffic Class mapping is not based on 4342 * Multicast packet indication. 4343 */ 4344 #define MLXSW_REG_QTCTM_ID 0x401A 4345 #define MLXSW_REG_QTCTM_LEN 0x08 4346 4347 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4348 4349 /* reg_qtctm_local_port 4350 * Local port number. 4351 * No support for CPU port. 4352 * Access: Index 4353 */ 4354 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4355 4356 /* reg_qtctm_mc 4357 * Multicast Mode 4358 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4359 * indication (default is 0, not based on Multicast packet indication). 4360 */ 4361 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4362 4363 static inline void 4364 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4365 { 4366 MLXSW_REG_ZERO(qtctm, payload); 4367 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4368 mlxsw_reg_qtctm_mc_set(payload, mc); 4369 } 4370 4371 /* QPSC - QoS PTP Shaper Configuration Register 4372 * -------------------------------------------- 4373 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4374 * Supported only on Spectrum-1. 4375 */ 4376 #define MLXSW_REG_QPSC_ID 0x401B 4377 #define MLXSW_REG_QPSC_LEN 0x28 4378 4379 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4380 4381 enum mlxsw_reg_qpsc_port_speed { 4382 MLXSW_REG_QPSC_PORT_SPEED_100M, 4383 MLXSW_REG_QPSC_PORT_SPEED_1G, 4384 MLXSW_REG_QPSC_PORT_SPEED_10G, 4385 MLXSW_REG_QPSC_PORT_SPEED_25G, 4386 }; 4387 4388 /* reg_qpsc_port_speed 4389 * Port speed. 4390 * Access: Index 4391 */ 4392 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4393 4394 /* reg_qpsc_shaper_time_exp 4395 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4396 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4397 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4398 * Access: RW 4399 */ 4400 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4401 4402 /* reg_qpsc_shaper_time_mantissa 4403 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4404 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4405 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4406 * Access: RW 4407 */ 4408 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4409 4410 /* reg_qpsc_shaper_inc 4411 * Number of tokens added to shaper on each update. 4412 * Units of 8B. 4413 * Access: RW 4414 */ 4415 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4416 4417 /* reg_qpsc_shaper_bs 4418 * Max shaper Burst size. 4419 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4420 * Range is: 5..25 (from 2KB..2GB) 4421 * Access: RW 4422 */ 4423 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4424 4425 /* reg_qpsc_ptsc_we 4426 * Write enable to port_to_shaper_credits. 4427 * Access: WO 4428 */ 4429 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4430 4431 /* reg_qpsc_port_to_shaper_credits 4432 * For split ports: range 1..57 4433 * For non-split ports: range 1..112 4434 * Written only when ptsc_we is set. 4435 * Access: RW 4436 */ 4437 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4438 4439 /* reg_qpsc_ing_timestamp_inc 4440 * Ingress timestamp increment. 4441 * 2's complement. 4442 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4443 * value for all ports. 4444 * Same units as used by MTPPTR. 4445 * Access: RW 4446 */ 4447 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4448 4449 /* reg_qpsc_egr_timestamp_inc 4450 * Egress timestamp increment. 4451 * 2's complement. 4452 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4453 * value for all ports. 4454 * Same units as used by MTPPTR. 4455 * Access: RW 4456 */ 4457 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4458 4459 static inline void 4460 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4461 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4462 u8 shaper_bs, u8 port_to_shaper_credits, 4463 int ing_timestamp_inc, int egr_timestamp_inc) 4464 { 4465 MLXSW_REG_ZERO(qpsc, payload); 4466 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4467 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4468 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4469 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4470 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4471 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4472 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4473 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4474 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4475 } 4476 4477 /* PMLP - Ports Module to Local Port Register 4478 * ------------------------------------------ 4479 * Configures the assignment of modules to local ports. 4480 */ 4481 #define MLXSW_REG_PMLP_ID 0x5002 4482 #define MLXSW_REG_PMLP_LEN 0x40 4483 4484 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4485 4486 /* reg_pmlp_rxtx 4487 * 0 - Tx value is used for both Tx and Rx. 4488 * 1 - Rx value is taken from a separte field. 4489 * Access: RW 4490 */ 4491 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4492 4493 /* reg_pmlp_local_port 4494 * Local port number. 4495 * Access: Index 4496 */ 4497 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4498 4499 /* reg_pmlp_width 4500 * 0 - Unmap local port. 4501 * 1 - Lane 0 is used. 4502 * 2 - Lanes 0 and 1 are used. 4503 * 4 - Lanes 0, 1, 2 and 3 are used. 4504 * 8 - Lanes 0-7 are used. 4505 * Access: RW 4506 */ 4507 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4508 4509 /* reg_pmlp_module 4510 * Module number. 4511 * Access: RW 4512 */ 4513 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4514 4515 /* reg_pmlp_slot_index 4516 * Module number. 4517 * Slot_index 4518 * Slot_index = 0 represent the onboard (motherboard). 4519 * In case of non-modular system only slot_index = 0 is available. 4520 * Access: RW 4521 */ 4522 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4523 4524 /* reg_pmlp_tx_lane 4525 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4526 * Access: RW 4527 */ 4528 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4529 4530 /* reg_pmlp_rx_lane 4531 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4532 * equal to Tx lane. 4533 * Access: RW 4534 */ 4535 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4536 4537 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4538 { 4539 MLXSW_REG_ZERO(pmlp, payload); 4540 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4541 } 4542 4543 /* PMTU - Port MTU Register 4544 * ------------------------ 4545 * Configures and reports the port MTU. 4546 */ 4547 #define MLXSW_REG_PMTU_ID 0x5003 4548 #define MLXSW_REG_PMTU_LEN 0x10 4549 4550 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4551 4552 /* reg_pmtu_local_port 4553 * Local port number. 4554 * Access: Index 4555 */ 4556 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4557 4558 /* reg_pmtu_max_mtu 4559 * Maximum MTU. 4560 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4561 * reported, otherwise the minimum between the max_mtu of the different 4562 * types is reported. 4563 * Access: RO 4564 */ 4565 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4566 4567 /* reg_pmtu_admin_mtu 4568 * MTU value to set port to. Must be smaller or equal to max_mtu. 4569 * Note: If port type is Infiniband, then port must be disabled, when its 4570 * MTU is set. 4571 * Access: RW 4572 */ 4573 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4574 4575 /* reg_pmtu_oper_mtu 4576 * The actual MTU configured on the port. Packets exceeding this size 4577 * will be dropped. 4578 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4579 * oper_mtu might be smaller than admin_mtu. 4580 * Access: RO 4581 */ 4582 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4583 4584 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4585 u16 new_mtu) 4586 { 4587 MLXSW_REG_ZERO(pmtu, payload); 4588 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4589 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4590 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4591 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4592 } 4593 4594 /* PTYS - Port Type and Speed Register 4595 * ----------------------------------- 4596 * Configures and reports the port speed type. 4597 * 4598 * Note: When set while the link is up, the changes will not take effect 4599 * until the port transitions from down to up state. 4600 */ 4601 #define MLXSW_REG_PTYS_ID 0x5004 4602 #define MLXSW_REG_PTYS_LEN 0x40 4603 4604 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4605 4606 /* an_disable_admin 4607 * Auto negotiation disable administrative configuration 4608 * 0 - Device doesn't support AN disable. 4609 * 1 - Device supports AN disable. 4610 * Access: RW 4611 */ 4612 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4613 4614 /* reg_ptys_local_port 4615 * Local port number. 4616 * Access: Index 4617 */ 4618 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4619 4620 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4621 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4622 4623 /* reg_ptys_proto_mask 4624 * Protocol mask. Indicates which protocol is used. 4625 * 0 - Infiniband. 4626 * 1 - Fibre Channel. 4627 * 2 - Ethernet. 4628 * Access: Index 4629 */ 4630 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4631 4632 enum { 4633 MLXSW_REG_PTYS_AN_STATUS_NA, 4634 MLXSW_REG_PTYS_AN_STATUS_OK, 4635 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4636 }; 4637 4638 /* reg_ptys_an_status 4639 * Autonegotiation status. 4640 * Access: RO 4641 */ 4642 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4643 4644 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4645 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4646 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4647 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4648 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4649 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4650 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4651 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4652 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4653 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4654 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4655 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4656 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4657 4658 /* reg_ptys_ext_eth_proto_cap 4659 * Extended Ethernet port supported speeds and protocols. 4660 * Access: RO 4661 */ 4662 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4663 4664 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4665 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4666 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4667 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4668 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4669 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4670 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4671 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4672 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4673 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4674 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4675 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4676 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4677 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4678 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4679 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4680 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4681 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4682 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4683 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4684 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4685 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4686 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4687 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4688 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4689 4690 /* reg_ptys_eth_proto_cap 4691 * Ethernet port supported speeds and protocols. 4692 * Access: RO 4693 */ 4694 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4695 4696 /* reg_ptys_ext_eth_proto_admin 4697 * Extended speed and protocol to set port to. 4698 * Access: RW 4699 */ 4700 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4701 4702 /* reg_ptys_eth_proto_admin 4703 * Speed and protocol to set port to. 4704 * Access: RW 4705 */ 4706 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4707 4708 /* reg_ptys_ext_eth_proto_oper 4709 * The extended current speed and protocol configured for the port. 4710 * Access: RO 4711 */ 4712 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4713 4714 /* reg_ptys_eth_proto_oper 4715 * The current speed and protocol configured for the port. 4716 * Access: RO 4717 */ 4718 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4719 4720 enum mlxsw_reg_ptys_connector_type { 4721 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4722 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4723 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4724 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4725 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4726 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4727 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4728 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4729 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4730 }; 4731 4732 /* reg_ptys_connector_type 4733 * Connector type indication. 4734 * Access: RO 4735 */ 4736 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4737 4738 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4739 u32 proto_admin, bool autoneg) 4740 { 4741 MLXSW_REG_ZERO(ptys, payload); 4742 mlxsw_reg_ptys_local_port_set(payload, local_port); 4743 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4744 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4745 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4746 } 4747 4748 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4749 u32 proto_admin, bool autoneg) 4750 { 4751 MLXSW_REG_ZERO(ptys, payload); 4752 mlxsw_reg_ptys_local_port_set(payload, local_port); 4753 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4754 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4755 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4756 } 4757 4758 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4759 u32 *p_eth_proto_cap, 4760 u32 *p_eth_proto_admin, 4761 u32 *p_eth_proto_oper) 4762 { 4763 if (p_eth_proto_cap) 4764 *p_eth_proto_cap = 4765 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4766 if (p_eth_proto_admin) 4767 *p_eth_proto_admin = 4768 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4769 if (p_eth_proto_oper) 4770 *p_eth_proto_oper = 4771 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4772 } 4773 4774 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4775 u32 *p_eth_proto_cap, 4776 u32 *p_eth_proto_admin, 4777 u32 *p_eth_proto_oper) 4778 { 4779 if (p_eth_proto_cap) 4780 *p_eth_proto_cap = 4781 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4782 if (p_eth_proto_admin) 4783 *p_eth_proto_admin = 4784 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4785 if (p_eth_proto_oper) 4786 *p_eth_proto_oper = 4787 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4788 } 4789 4790 /* PPAD - Port Physical Address Register 4791 * ------------------------------------- 4792 * The PPAD register configures the per port physical MAC address. 4793 */ 4794 #define MLXSW_REG_PPAD_ID 0x5005 4795 #define MLXSW_REG_PPAD_LEN 0x10 4796 4797 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4798 4799 /* reg_ppad_single_base_mac 4800 * 0: base_mac, local port should be 0 and mac[7:0] is 4801 * reserved. HW will set incremental 4802 * 1: single_mac - mac of the local_port 4803 * Access: RW 4804 */ 4805 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4806 4807 /* reg_ppad_local_port 4808 * port number, if single_base_mac = 0 then local_port is reserved 4809 * Access: RW 4810 */ 4811 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4812 4813 /* reg_ppad_mac 4814 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4815 * If single_base_mac = 1 - the per port MAC address 4816 * Access: RW 4817 */ 4818 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4819 4820 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4821 u16 local_port) 4822 { 4823 MLXSW_REG_ZERO(ppad, payload); 4824 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4825 mlxsw_reg_ppad_local_port_set(payload, local_port); 4826 } 4827 4828 /* PAOS - Ports Administrative and Operational Status Register 4829 * ----------------------------------------------------------- 4830 * Configures and retrieves per port administrative and operational status. 4831 */ 4832 #define MLXSW_REG_PAOS_ID 0x5006 4833 #define MLXSW_REG_PAOS_LEN 0x10 4834 4835 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4836 4837 /* reg_paos_swid 4838 * Switch partition ID with which to associate the port. 4839 * Note: while external ports uses unique local port numbers (and thus swid is 4840 * redundant), router ports use the same local port number where swid is the 4841 * only indication for the relevant port. 4842 * Access: Index 4843 */ 4844 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4845 4846 /* reg_paos_local_port 4847 * Local port number. 4848 * Access: Index 4849 */ 4850 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4851 4852 /* reg_paos_admin_status 4853 * Port administrative state (the desired state of the port): 4854 * 1 - Up. 4855 * 2 - Down. 4856 * 3 - Up once. This means that in case of link failure, the port won't go 4857 * into polling mode, but will wait to be re-enabled by software. 4858 * 4 - Disabled by system. Can only be set by hardware. 4859 * Access: RW 4860 */ 4861 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4862 4863 /* reg_paos_oper_status 4864 * Port operational state (the current state): 4865 * 1 - Up. 4866 * 2 - Down. 4867 * 3 - Down by port failure. This means that the device will not let the 4868 * port up again until explicitly specified by software. 4869 * Access: RO 4870 */ 4871 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4872 4873 /* reg_paos_ase 4874 * Admin state update enabled. 4875 * Access: WO 4876 */ 4877 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4878 4879 /* reg_paos_ee 4880 * Event update enable. If this bit is set, event generation will be 4881 * updated based on the e field. 4882 * Access: WO 4883 */ 4884 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4885 4886 /* reg_paos_e 4887 * Event generation on operational state change: 4888 * 0 - Do not generate event. 4889 * 1 - Generate Event. 4890 * 2 - Generate Single Event. 4891 * Access: RW 4892 */ 4893 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4894 4895 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4896 enum mlxsw_port_admin_status status) 4897 { 4898 MLXSW_REG_ZERO(paos, payload); 4899 mlxsw_reg_paos_swid_set(payload, 0); 4900 mlxsw_reg_paos_local_port_set(payload, local_port); 4901 mlxsw_reg_paos_admin_status_set(payload, status); 4902 mlxsw_reg_paos_oper_status_set(payload, 0); 4903 mlxsw_reg_paos_ase_set(payload, 1); 4904 mlxsw_reg_paos_ee_set(payload, 1); 4905 mlxsw_reg_paos_e_set(payload, 1); 4906 } 4907 4908 /* PFCC - Ports Flow Control Configuration Register 4909 * ------------------------------------------------ 4910 * Configures and retrieves the per port flow control configuration. 4911 */ 4912 #define MLXSW_REG_PFCC_ID 0x5007 4913 #define MLXSW_REG_PFCC_LEN 0x20 4914 4915 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4916 4917 /* reg_pfcc_local_port 4918 * Local port number. 4919 * Access: Index 4920 */ 4921 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4922 4923 /* reg_pfcc_pnat 4924 * Port number access type. Determines the way local_port is interpreted: 4925 * 0 - Local port number. 4926 * 1 - IB / label port number. 4927 * Access: Index 4928 */ 4929 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4930 4931 /* reg_pfcc_shl_cap 4932 * Send to higher layers capabilities: 4933 * 0 - No capability of sending Pause and PFC frames to higher layers. 4934 * 1 - Device has capability of sending Pause and PFC frames to higher 4935 * layers. 4936 * Access: RO 4937 */ 4938 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4939 4940 /* reg_pfcc_shl_opr 4941 * Send to higher layers operation: 4942 * 0 - Pause and PFC frames are handled by the port (default). 4943 * 1 - Pause and PFC frames are handled by the port and also sent to 4944 * higher layers. Only valid if shl_cap = 1. 4945 * Access: RW 4946 */ 4947 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4948 4949 /* reg_pfcc_ppan 4950 * Pause policy auto negotiation. 4951 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4952 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4953 * based on the auto-negotiation resolution. 4954 * Access: RW 4955 * 4956 * Note: The auto-negotiation advertisement is set according to pptx and 4957 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4958 */ 4959 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4960 4961 /* reg_pfcc_prio_mask_tx 4962 * Bit per priority indicating if Tx flow control policy should be 4963 * updated based on bit pfctx. 4964 * Access: WO 4965 */ 4966 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4967 4968 /* reg_pfcc_prio_mask_rx 4969 * Bit per priority indicating if Rx flow control policy should be 4970 * updated based on bit pfcrx. 4971 * Access: WO 4972 */ 4973 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4974 4975 /* reg_pfcc_pptx 4976 * Admin Pause policy on Tx. 4977 * 0 - Never generate Pause frames (default). 4978 * 1 - Generate Pause frames according to Rx buffer threshold. 4979 * Access: RW 4980 */ 4981 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4982 4983 /* reg_pfcc_aptx 4984 * Active (operational) Pause policy on Tx. 4985 * 0 - Never generate Pause frames. 4986 * 1 - Generate Pause frames according to Rx buffer threshold. 4987 * Access: RO 4988 */ 4989 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4990 4991 /* reg_pfcc_pfctx 4992 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4993 * 0 - Never generate priority Pause frames on the specified priority 4994 * (default). 4995 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4996 * the specified priority. 4997 * Access: RW 4998 * 4999 * Note: pfctx and pptx must be mutually exclusive. 5000 */ 5001 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5002 5003 /* reg_pfcc_pprx 5004 * Admin Pause policy on Rx. 5005 * 0 - Ignore received Pause frames (default). 5006 * 1 - Respect received Pause frames. 5007 * Access: RW 5008 */ 5009 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5010 5011 /* reg_pfcc_aprx 5012 * Active (operational) Pause policy on Rx. 5013 * 0 - Ignore received Pause frames. 5014 * 1 - Respect received Pause frames. 5015 * Access: RO 5016 */ 5017 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5018 5019 /* reg_pfcc_pfcrx 5020 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5021 * 0 - Ignore incoming priority Pause frames on the specified priority 5022 * (default). 5023 * 1 - Respect incoming priority Pause frames on the specified priority. 5024 * Access: RW 5025 */ 5026 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5027 5028 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5029 5030 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5031 { 5032 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5033 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5034 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5035 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5036 } 5037 5038 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5039 { 5040 MLXSW_REG_ZERO(pfcc, payload); 5041 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5042 } 5043 5044 /* PPCNT - Ports Performance Counters Register 5045 * ------------------------------------------- 5046 * The PPCNT register retrieves per port performance counters. 5047 */ 5048 #define MLXSW_REG_PPCNT_ID 0x5008 5049 #define MLXSW_REG_PPCNT_LEN 0x100 5050 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5051 5052 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5053 5054 /* reg_ppcnt_swid 5055 * For HCA: must be always 0. 5056 * Switch partition ID to associate port with. 5057 * Switch partitions are numbered from 0 to 7 inclusively. 5058 * Switch partition 254 indicates stacking ports. 5059 * Switch partition 255 indicates all switch partitions. 5060 * Only valid on Set() operation with local_port=255. 5061 * Access: Index 5062 */ 5063 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5064 5065 /* reg_ppcnt_local_port 5066 * Local port number. 5067 * Access: Index 5068 */ 5069 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5070 5071 /* reg_ppcnt_pnat 5072 * Port number access type: 5073 * 0 - Local port number 5074 * 1 - IB port number 5075 * Access: Index 5076 */ 5077 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5078 5079 enum mlxsw_reg_ppcnt_grp { 5080 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5081 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5082 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5083 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5084 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5085 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5086 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5087 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5088 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5089 }; 5090 5091 /* reg_ppcnt_grp 5092 * Performance counter group. 5093 * Group 63 indicates all groups. Only valid on Set() operation with 5094 * clr bit set. 5095 * 0x0: IEEE 802.3 Counters 5096 * 0x1: RFC 2863 Counters 5097 * 0x2: RFC 2819 Counters 5098 * 0x3: RFC 3635 Counters 5099 * 0x5: Ethernet Extended Counters 5100 * 0x6: Ethernet Discard Counters 5101 * 0x8: Link Level Retransmission Counters 5102 * 0x10: Per Priority Counters 5103 * 0x11: Per Traffic Class Counters 5104 * 0x12: Physical Layer Counters 5105 * 0x13: Per Traffic Class Congestion Counters 5106 * Access: Index 5107 */ 5108 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5109 5110 /* reg_ppcnt_clr 5111 * Clear counters. Setting the clr bit will reset the counter value 5112 * for all counters in the counter group. This bit can be set 5113 * for both Set() and Get() operation. 5114 * Access: OP 5115 */ 5116 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5117 5118 /* reg_ppcnt_lp_gl 5119 * Local port global variable. 5120 * 0: local_port 255 = all ports of the device. 5121 * 1: local_port indicates local port number for all ports. 5122 * Access: OP 5123 */ 5124 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5125 5126 /* reg_ppcnt_prio_tc 5127 * Priority for counter set that support per priority, valid values: 0-7. 5128 * Traffic class for counter set that support per traffic class, 5129 * valid values: 0- cap_max_tclass-1 . 5130 * For HCA: cap_max_tclass is always 8. 5131 * Otherwise must be 0. 5132 * Access: Index 5133 */ 5134 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5135 5136 /* Ethernet IEEE 802.3 Counter Group */ 5137 5138 /* reg_ppcnt_a_frames_transmitted_ok 5139 * Access: RO 5140 */ 5141 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5142 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5143 5144 /* reg_ppcnt_a_frames_received_ok 5145 * Access: RO 5146 */ 5147 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5148 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5149 5150 /* reg_ppcnt_a_frame_check_sequence_errors 5151 * Access: RO 5152 */ 5153 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5154 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5155 5156 /* reg_ppcnt_a_alignment_errors 5157 * Access: RO 5158 */ 5159 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5160 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5161 5162 /* reg_ppcnt_a_octets_transmitted_ok 5163 * Access: RO 5164 */ 5165 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5166 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5167 5168 /* reg_ppcnt_a_octets_received_ok 5169 * Access: RO 5170 */ 5171 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5172 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5173 5174 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5175 * Access: RO 5176 */ 5177 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5178 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5179 5180 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5181 * Access: RO 5182 */ 5183 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5184 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5185 5186 /* reg_ppcnt_a_multicast_frames_received_ok 5187 * Access: RO 5188 */ 5189 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5190 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5191 5192 /* reg_ppcnt_a_broadcast_frames_received_ok 5193 * Access: RO 5194 */ 5195 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5196 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5197 5198 /* reg_ppcnt_a_in_range_length_errors 5199 * Access: RO 5200 */ 5201 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5202 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5203 5204 /* reg_ppcnt_a_out_of_range_length_field 5205 * Access: RO 5206 */ 5207 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5208 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5209 5210 /* reg_ppcnt_a_frame_too_long_errors 5211 * Access: RO 5212 */ 5213 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5214 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5215 5216 /* reg_ppcnt_a_symbol_error_during_carrier 5217 * Access: RO 5218 */ 5219 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5220 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5221 5222 /* reg_ppcnt_a_mac_control_frames_transmitted 5223 * Access: RO 5224 */ 5225 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5226 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5227 5228 /* reg_ppcnt_a_mac_control_frames_received 5229 * Access: RO 5230 */ 5231 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5232 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5233 5234 /* reg_ppcnt_a_unsupported_opcodes_received 5235 * Access: RO 5236 */ 5237 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5238 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5239 5240 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5241 * Access: RO 5242 */ 5243 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5244 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5245 5246 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5247 * Access: RO 5248 */ 5249 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5251 5252 /* Ethernet RFC 2863 Counter Group */ 5253 5254 /* reg_ppcnt_if_in_discards 5255 * Access: RO 5256 */ 5257 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5258 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5259 5260 /* reg_ppcnt_if_out_discards 5261 * Access: RO 5262 */ 5263 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5264 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5265 5266 /* reg_ppcnt_if_out_errors 5267 * Access: RO 5268 */ 5269 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5270 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5271 5272 /* Ethernet RFC 2819 Counter Group */ 5273 5274 /* reg_ppcnt_ether_stats_undersize_pkts 5275 * Access: RO 5276 */ 5277 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5278 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5279 5280 /* reg_ppcnt_ether_stats_oversize_pkts 5281 * Access: RO 5282 */ 5283 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5284 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5285 5286 /* reg_ppcnt_ether_stats_fragments 5287 * Access: RO 5288 */ 5289 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5290 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5291 5292 /* reg_ppcnt_ether_stats_pkts64octets 5293 * Access: RO 5294 */ 5295 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5296 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5297 5298 /* reg_ppcnt_ether_stats_pkts65to127octets 5299 * Access: RO 5300 */ 5301 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5302 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5303 5304 /* reg_ppcnt_ether_stats_pkts128to255octets 5305 * Access: RO 5306 */ 5307 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5308 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5309 5310 /* reg_ppcnt_ether_stats_pkts256to511octets 5311 * Access: RO 5312 */ 5313 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5314 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5315 5316 /* reg_ppcnt_ether_stats_pkts512to1023octets 5317 * Access: RO 5318 */ 5319 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5320 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5321 5322 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5323 * Access: RO 5324 */ 5325 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5326 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5327 5328 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5329 * Access: RO 5330 */ 5331 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5332 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5333 5334 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5335 * Access: RO 5336 */ 5337 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5338 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5339 5340 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5341 * Access: RO 5342 */ 5343 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5344 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5345 5346 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5347 * Access: RO 5348 */ 5349 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5350 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5351 5352 /* Ethernet RFC 3635 Counter Group */ 5353 5354 /* reg_ppcnt_dot3stats_fcs_errors 5355 * Access: RO 5356 */ 5357 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5358 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5359 5360 /* reg_ppcnt_dot3stats_symbol_errors 5361 * Access: RO 5362 */ 5363 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5364 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5365 5366 /* reg_ppcnt_dot3control_in_unknown_opcodes 5367 * Access: RO 5368 */ 5369 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5370 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5371 5372 /* reg_ppcnt_dot3in_pause_frames 5373 * Access: RO 5374 */ 5375 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5376 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5377 5378 /* Ethernet Extended Counter Group Counters */ 5379 5380 /* reg_ppcnt_ecn_marked 5381 * Access: RO 5382 */ 5383 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5384 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5385 5386 /* Ethernet Discard Counter Group Counters */ 5387 5388 /* reg_ppcnt_ingress_general 5389 * Access: RO 5390 */ 5391 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5393 5394 /* reg_ppcnt_ingress_policy_engine 5395 * Access: RO 5396 */ 5397 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5399 5400 /* reg_ppcnt_ingress_vlan_membership 5401 * Access: RO 5402 */ 5403 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5405 5406 /* reg_ppcnt_ingress_tag_frame_type 5407 * Access: RO 5408 */ 5409 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5410 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5411 5412 /* reg_ppcnt_egress_vlan_membership 5413 * Access: RO 5414 */ 5415 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5417 5418 /* reg_ppcnt_loopback_filter 5419 * Access: RO 5420 */ 5421 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5423 5424 /* reg_ppcnt_egress_general 5425 * Access: RO 5426 */ 5427 MLXSW_ITEM64(reg, ppcnt, egress_general, 5428 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5429 5430 /* reg_ppcnt_egress_hoq 5431 * Access: RO 5432 */ 5433 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5434 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5435 5436 /* reg_ppcnt_egress_policy_engine 5437 * Access: RO 5438 */ 5439 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5440 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5441 5442 /* reg_ppcnt_ingress_tx_link_down 5443 * Access: RO 5444 */ 5445 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5446 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5447 5448 /* reg_ppcnt_egress_stp_filter 5449 * Access: RO 5450 */ 5451 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5452 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5453 5454 /* reg_ppcnt_egress_sll 5455 * Access: RO 5456 */ 5457 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5458 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5459 5460 /* Ethernet Per Priority Group Counters */ 5461 5462 /* reg_ppcnt_rx_octets 5463 * Access: RO 5464 */ 5465 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5466 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5467 5468 /* reg_ppcnt_rx_frames 5469 * Access: RO 5470 */ 5471 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5472 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5473 5474 /* reg_ppcnt_tx_octets 5475 * Access: RO 5476 */ 5477 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5478 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5479 5480 /* reg_ppcnt_tx_frames 5481 * Access: RO 5482 */ 5483 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5484 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5485 5486 /* reg_ppcnt_rx_pause 5487 * Access: RO 5488 */ 5489 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5490 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5491 5492 /* reg_ppcnt_rx_pause_duration 5493 * Access: RO 5494 */ 5495 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5496 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5497 5498 /* reg_ppcnt_tx_pause 5499 * Access: RO 5500 */ 5501 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5502 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5503 5504 /* reg_ppcnt_tx_pause_duration 5505 * Access: RO 5506 */ 5507 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5509 5510 /* reg_ppcnt_rx_pause_transition 5511 * Access: RO 5512 */ 5513 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5514 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5515 5516 /* Ethernet Per Traffic Class Counters */ 5517 5518 /* reg_ppcnt_tc_transmit_queue 5519 * Contains the transmit queue depth in cells of traffic class 5520 * selected by prio_tc and the port selected by local_port. 5521 * The field cannot be cleared. 5522 * Access: RO 5523 */ 5524 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5525 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5526 5527 /* reg_ppcnt_tc_no_buffer_discard_uc 5528 * The number of unicast packets dropped due to lack of shared 5529 * buffer resources. 5530 * Access: RO 5531 */ 5532 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5533 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5534 5535 /* Ethernet Per Traffic Class Congestion Group Counters */ 5536 5537 /* reg_ppcnt_wred_discard 5538 * Access: RO 5539 */ 5540 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5541 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5542 5543 /* reg_ppcnt_ecn_marked_tc 5544 * Access: RO 5545 */ 5546 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5547 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5548 5549 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5550 enum mlxsw_reg_ppcnt_grp grp, 5551 u8 prio_tc) 5552 { 5553 MLXSW_REG_ZERO(ppcnt, payload); 5554 mlxsw_reg_ppcnt_swid_set(payload, 0); 5555 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5556 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5557 mlxsw_reg_ppcnt_grp_set(payload, grp); 5558 mlxsw_reg_ppcnt_clr_set(payload, 0); 5559 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5560 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5561 } 5562 5563 /* PPTB - Port Prio To Buffer Register 5564 * ----------------------------------- 5565 * Configures the switch priority to buffer table. 5566 */ 5567 #define MLXSW_REG_PPTB_ID 0x500B 5568 #define MLXSW_REG_PPTB_LEN 0x10 5569 5570 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5571 5572 enum { 5573 MLXSW_REG_PPTB_MM_UM, 5574 MLXSW_REG_PPTB_MM_UNICAST, 5575 MLXSW_REG_PPTB_MM_MULTICAST, 5576 }; 5577 5578 /* reg_pptb_mm 5579 * Mapping mode. 5580 * 0 - Map both unicast and multicast packets to the same buffer. 5581 * 1 - Map only unicast packets. 5582 * 2 - Map only multicast packets. 5583 * Access: Index 5584 * 5585 * Note: SwitchX-2 only supports the first option. 5586 */ 5587 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5588 5589 /* reg_pptb_local_port 5590 * Local port number. 5591 * Access: Index 5592 */ 5593 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5594 5595 /* reg_pptb_um 5596 * Enables the update of the untagged_buf field. 5597 * Access: RW 5598 */ 5599 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5600 5601 /* reg_pptb_pm 5602 * Enables the update of the prio_to_buff field. 5603 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5604 * Access: RW 5605 */ 5606 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5607 5608 /* reg_pptb_prio_to_buff 5609 * Mapping of switch priority <i> to one of the allocated receive port 5610 * buffers. 5611 * Access: RW 5612 */ 5613 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5614 5615 /* reg_pptb_pm_msb 5616 * Enables the update of the prio_to_buff field. 5617 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5618 * Access: RW 5619 */ 5620 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5621 5622 /* reg_pptb_untagged_buff 5623 * Mapping of untagged frames to one of the allocated receive port buffers. 5624 * Access: RW 5625 * 5626 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5627 * Spectrum, as it maps untagged packets based on the default switch priority. 5628 */ 5629 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5630 5631 /* reg_pptb_prio_to_buff_msb 5632 * Mapping of switch priority <i+8> to one of the allocated receive port 5633 * buffers. 5634 * Access: RW 5635 */ 5636 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5637 5638 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5639 5640 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5641 { 5642 MLXSW_REG_ZERO(pptb, payload); 5643 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5644 mlxsw_reg_pptb_local_port_set(payload, local_port); 5645 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5646 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5647 } 5648 5649 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5650 u8 buff) 5651 { 5652 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5653 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5654 } 5655 5656 /* PBMC - Port Buffer Management Control Register 5657 * ---------------------------------------------- 5658 * The PBMC register configures and retrieves the port packet buffer 5659 * allocation for different Prios, and the Pause threshold management. 5660 */ 5661 #define MLXSW_REG_PBMC_ID 0x500C 5662 #define MLXSW_REG_PBMC_LEN 0x6C 5663 5664 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5665 5666 /* reg_pbmc_local_port 5667 * Local port number. 5668 * Access: Index 5669 */ 5670 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5671 5672 /* reg_pbmc_xoff_timer_value 5673 * When device generates a pause frame, it uses this value as the pause 5674 * timer (time for the peer port to pause in quota-512 bit time). 5675 * Access: RW 5676 */ 5677 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5678 5679 /* reg_pbmc_xoff_refresh 5680 * The time before a new pause frame should be sent to refresh the pause RW 5681 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5682 * time). 5683 * Access: RW 5684 */ 5685 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5686 5687 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5688 5689 /* reg_pbmc_buf_lossy 5690 * The field indicates if the buffer is lossy. 5691 * 0 - Lossless 5692 * 1 - Lossy 5693 * Access: RW 5694 */ 5695 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5696 5697 /* reg_pbmc_buf_epsb 5698 * Eligible for Port Shared buffer. 5699 * If epsb is set, packets assigned to buffer are allowed to insert the port 5700 * shared buffer. 5701 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5702 * Access: RW 5703 */ 5704 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5705 5706 /* reg_pbmc_buf_size 5707 * The part of the packet buffer array is allocated for the specific buffer. 5708 * Units are represented in cells. 5709 * Access: RW 5710 */ 5711 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5712 5713 /* reg_pbmc_buf_xoff_threshold 5714 * Once the amount of data in the buffer goes above this value, device 5715 * starts sending PFC frames for all priorities associated with the 5716 * buffer. Units are represented in cells. Reserved in case of lossy 5717 * buffer. 5718 * Access: RW 5719 * 5720 * Note: In Spectrum, reserved for buffer[9]. 5721 */ 5722 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5723 0x08, 0x04, false); 5724 5725 /* reg_pbmc_buf_xon_threshold 5726 * When the amount of data in the buffer goes below this value, device 5727 * stops sending PFC frames for the priorities associated with the 5728 * buffer. Units are represented in cells. Reserved in case of lossy 5729 * buffer. 5730 * Access: RW 5731 * 5732 * Note: In Spectrum, reserved for buffer[9]. 5733 */ 5734 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5735 0x08, 0x04, false); 5736 5737 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5738 u16 xoff_timer_value, u16 xoff_refresh) 5739 { 5740 MLXSW_REG_ZERO(pbmc, payload); 5741 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5742 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5743 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5744 } 5745 5746 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5747 int buf_index, 5748 u16 size) 5749 { 5750 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5751 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5752 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5753 } 5754 5755 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5756 int buf_index, u16 size, 5757 u16 threshold) 5758 { 5759 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5760 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5761 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5762 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5763 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5764 } 5765 5766 /* PSPA - Port Switch Partition Allocation 5767 * --------------------------------------- 5768 * Controls the association of a port with a switch partition and enables 5769 * configuring ports as stacking ports. 5770 */ 5771 #define MLXSW_REG_PSPA_ID 0x500D 5772 #define MLXSW_REG_PSPA_LEN 0x8 5773 5774 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5775 5776 /* reg_pspa_swid 5777 * Switch partition ID. 5778 * Access: RW 5779 */ 5780 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5781 5782 /* reg_pspa_local_port 5783 * Local port number. 5784 * Access: Index 5785 */ 5786 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5787 5788 /* reg_pspa_sub_port 5789 * Virtual port within the local port. Set to 0 when virtual ports are 5790 * disabled on the local port. 5791 * Access: Index 5792 */ 5793 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5794 5795 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5796 { 5797 MLXSW_REG_ZERO(pspa, payload); 5798 mlxsw_reg_pspa_swid_set(payload, swid); 5799 mlxsw_reg_pspa_local_port_set(payload, local_port); 5800 mlxsw_reg_pspa_sub_port_set(payload, 0); 5801 } 5802 5803 /* PMAOS - Ports Module Administrative and Operational Status 5804 * ---------------------------------------------------------- 5805 * This register configures and retrieves the per module status. 5806 */ 5807 #define MLXSW_REG_PMAOS_ID 0x5012 5808 #define MLXSW_REG_PMAOS_LEN 0x10 5809 5810 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5811 5812 /* reg_pmaos_rst 5813 * Module reset toggle. 5814 * Note: Setting reset while module is plugged-in will result in transition to 5815 * "initializing" operational state. 5816 * Access: OP 5817 */ 5818 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5819 5820 /* reg_pmaos_slot_index 5821 * Slot index. 5822 * Access: Index 5823 */ 5824 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5825 5826 /* reg_pmaos_module 5827 * Module number. 5828 * Access: Index 5829 */ 5830 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5831 5832 enum mlxsw_reg_pmaos_admin_status { 5833 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5834 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5835 /* If the module is active and then unplugged, or experienced an error 5836 * event, the operational status should go to "disabled" and can only 5837 * be enabled upon explicit enable command. 5838 */ 5839 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5840 }; 5841 5842 /* reg_pmaos_admin_status 5843 * Module administrative state (the desired state of the module). 5844 * Note: To disable a module, all ports associated with the port must be 5845 * administatively down first. 5846 * Access: RW 5847 */ 5848 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5849 5850 /* reg_pmaos_ase 5851 * Admin state update enable. 5852 * If this bit is set, admin state will be updated based on admin_state field. 5853 * Only relevant on Set() operations. 5854 * Access: WO 5855 */ 5856 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5857 5858 /* reg_pmaos_ee 5859 * Event update enable. 5860 * If this bit is set, event generation will be updated based on the e field. 5861 * Only relevant on Set operations. 5862 * Access: WO 5863 */ 5864 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5865 5866 enum mlxsw_reg_pmaos_e { 5867 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5868 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5869 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5870 }; 5871 5872 /* reg_pmaos_e 5873 * Event Generation on operational state change. 5874 * Access: RW 5875 */ 5876 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5877 5878 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5879 { 5880 MLXSW_REG_ZERO(pmaos, payload); 5881 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5882 mlxsw_reg_pmaos_module_set(payload, module); 5883 } 5884 5885 /* PPLR - Port Physical Loopback Register 5886 * -------------------------------------- 5887 * This register allows configuration of the port's loopback mode. 5888 */ 5889 #define MLXSW_REG_PPLR_ID 0x5018 5890 #define MLXSW_REG_PPLR_LEN 0x8 5891 5892 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5893 5894 /* reg_pplr_local_port 5895 * Local port number. 5896 * Access: Index 5897 */ 5898 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5899 5900 /* Phy local loopback. When set the port's egress traffic is looped back 5901 * to the receiver and the port transmitter is disabled. 5902 */ 5903 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5904 5905 /* reg_pplr_lb_en 5906 * Loopback enable. 5907 * Access: RW 5908 */ 5909 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5910 5911 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5912 bool phy_local) 5913 { 5914 MLXSW_REG_ZERO(pplr, payload); 5915 mlxsw_reg_pplr_local_port_set(payload, local_port); 5916 mlxsw_reg_pplr_lb_en_set(payload, 5917 phy_local ? 5918 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5919 } 5920 5921 /* PMTDB - Port Module To local DataBase Register 5922 * ---------------------------------------------- 5923 * The PMTDB register allows to query the possible module<->local port 5924 * mapping than can be used in PMLP. It does not represent the actual/current 5925 * mapping of the local to module. Actual mapping is only defined by PMLP. 5926 */ 5927 #define MLXSW_REG_PMTDB_ID 0x501A 5928 #define MLXSW_REG_PMTDB_LEN 0x40 5929 5930 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5931 5932 /* reg_pmtdb_slot_index 5933 * Slot index (0: Main board). 5934 * Access: Index 5935 */ 5936 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 5937 5938 /* reg_pmtdb_module 5939 * Module number. 5940 * Access: Index 5941 */ 5942 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 5943 5944 /* reg_pmtdb_ports_width 5945 * Port's width 5946 * Access: Index 5947 */ 5948 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 5949 5950 /* reg_pmtdb_num_ports 5951 * Number of ports in a single module (split/breakout) 5952 * Access: Index 5953 */ 5954 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 5955 5956 enum mlxsw_reg_pmtdb_status { 5957 MLXSW_REG_PMTDB_STATUS_SUCCESS, 5958 }; 5959 5960 /* reg_pmtdb_status 5961 * Status 5962 * Access: RO 5963 */ 5964 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 5965 5966 /* reg_pmtdb_port_num 5967 * The local_port value which can be assigned to the module. 5968 * In case of more than one port, port<x> represent the /<x> port of 5969 * the module. 5970 * Access: RO 5971 */ 5972 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 5973 5974 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 5975 u8 ports_width, u8 num_ports) 5976 { 5977 MLXSW_REG_ZERO(pmtdb, payload); 5978 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 5979 mlxsw_reg_pmtdb_module_set(payload, module); 5980 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 5981 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 5982 } 5983 5984 /* PMECR - Ports Mapping Event Configuration Register 5985 * -------------------------------------------------- 5986 * The PMECR register is used to enable/disable event triggering 5987 * in case of local port mapping change. 5988 */ 5989 #define MLXSW_REG_PMECR_ID 0x501B 5990 #define MLXSW_REG_PMECR_LEN 0x20 5991 5992 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 5993 5994 /* reg_pmecr_local_port 5995 * Local port number. 5996 * Access: Index 5997 */ 5998 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 5999 6000 /* reg_pmecr_ee 6001 * Event update enable. If this bit is set, event generation will be updated 6002 * based on the e field. Only relevant on Set operations. 6003 * Access: WO 6004 */ 6005 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6006 6007 /* reg_pmecr_eswi 6008 * Software ignore enable bit. If this bit is set, the value of swi is used. 6009 * If this bit is clear, the value of swi is ignored. 6010 * Only relevant on Set operations. 6011 * Access: WO 6012 */ 6013 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6014 6015 /* reg_pmecr_swi 6016 * Software ignore. If this bit is set, the device shouldn't generate events 6017 * in case of PMLP SET operation but only upon self local port mapping change 6018 * (if applicable according to e configuration). This is supplementary 6019 * configuration on top of e value. 6020 * Access: RW 6021 */ 6022 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6023 6024 enum mlxsw_reg_pmecr_e { 6025 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6026 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6027 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6028 }; 6029 6030 /* reg_pmecr_e 6031 * Event generation on local port mapping change. 6032 * Access: RW 6033 */ 6034 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6035 6036 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6037 enum mlxsw_reg_pmecr_e e) 6038 { 6039 MLXSW_REG_ZERO(pmecr, payload); 6040 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6041 mlxsw_reg_pmecr_e_set(payload, e); 6042 mlxsw_reg_pmecr_ee_set(payload, true); 6043 mlxsw_reg_pmecr_swi_set(payload, true); 6044 mlxsw_reg_pmecr_eswi_set(payload, true); 6045 } 6046 6047 /* PMPE - Port Module Plug/Unplug Event Register 6048 * --------------------------------------------- 6049 * This register reports any operational status change of a module. 6050 * A change in the module’s state will generate an event only if the change 6051 * happens after arming the event mechanism. Any changes to the module state 6052 * while the event mechanism is not armed will not be reported. Software can 6053 * query the PMPE register for module status. 6054 */ 6055 #define MLXSW_REG_PMPE_ID 0x5024 6056 #define MLXSW_REG_PMPE_LEN 0x10 6057 6058 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6059 6060 /* reg_pmpe_slot_index 6061 * Slot index. 6062 * Access: Index 6063 */ 6064 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6065 6066 /* reg_pmpe_module 6067 * Module number. 6068 * Access: Index 6069 */ 6070 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6071 6072 enum mlxsw_reg_pmpe_module_status { 6073 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6074 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6075 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6076 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6077 }; 6078 6079 /* reg_pmpe_module_status 6080 * Module status. 6081 * Access: RO 6082 */ 6083 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6084 6085 /* reg_pmpe_error_type 6086 * Module error details. 6087 * Access: RO 6088 */ 6089 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6090 6091 /* PDDR - Port Diagnostics Database Register 6092 * ----------------------------------------- 6093 * The PDDR enables to read the Phy debug database 6094 */ 6095 #define MLXSW_REG_PDDR_ID 0x5031 6096 #define MLXSW_REG_PDDR_LEN 0x100 6097 6098 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6099 6100 /* reg_pddr_local_port 6101 * Local port number. 6102 * Access: Index 6103 */ 6104 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6105 6106 enum mlxsw_reg_pddr_page_select { 6107 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6108 }; 6109 6110 /* reg_pddr_page_select 6111 * Page select index. 6112 * Access: Index 6113 */ 6114 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6115 6116 enum mlxsw_reg_pddr_trblsh_group_opcode { 6117 /* Monitor opcodes */ 6118 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6119 }; 6120 6121 /* reg_pddr_group_opcode 6122 * Group selector. 6123 * Access: Index 6124 */ 6125 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6126 6127 /* reg_pddr_status_opcode 6128 * Group selector. 6129 * Access: RO 6130 */ 6131 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6132 6133 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6134 u8 page_select) 6135 { 6136 MLXSW_REG_ZERO(pddr, payload); 6137 mlxsw_reg_pddr_local_port_set(payload, local_port); 6138 mlxsw_reg_pddr_page_select_set(payload, page_select); 6139 } 6140 6141 /* PMMP - Port Module Memory Map Properties Register 6142 * ------------------------------------------------- 6143 * The PMMP register allows to override the module memory map advertisement. 6144 * The register can only be set when the module is disabled by PMAOS register. 6145 */ 6146 #define MLXSW_REG_PMMP_ID 0x5044 6147 #define MLXSW_REG_PMMP_LEN 0x2C 6148 6149 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6150 6151 /* reg_pmmp_module 6152 * Module number. 6153 * Access: Index 6154 */ 6155 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6156 6157 /* reg_pmmp_slot_index 6158 * Slot index. 6159 * Access: Index 6160 */ 6161 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6162 6163 /* reg_pmmp_sticky 6164 * When set, will keep eeprom_override values after plug-out event. 6165 * Access: OP 6166 */ 6167 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6168 6169 /* reg_pmmp_eeprom_override_mask 6170 * Write mask bit (negative polarity). 6171 * 0 - Allow write 6172 * 1 - Ignore write 6173 * On write, indicates which of the bits from eeprom_override field are 6174 * updated. 6175 * Access: WO 6176 */ 6177 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6178 6179 enum { 6180 /* Set module to low power mode */ 6181 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6182 }; 6183 6184 /* reg_pmmp_eeprom_override 6185 * Override / ignore EEPROM advertisement properties bitmask 6186 * Access: RW 6187 */ 6188 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6189 6190 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6191 { 6192 MLXSW_REG_ZERO(pmmp, payload); 6193 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6194 mlxsw_reg_pmmp_module_set(payload, module); 6195 } 6196 6197 /* PLLP - Port Local port to Label Port mapping Register 6198 * ----------------------------------------------------- 6199 * The PLLP register returns the mapping from Local Port into Label Port. 6200 */ 6201 #define MLXSW_REG_PLLP_ID 0x504A 6202 #define MLXSW_REG_PLLP_LEN 0x10 6203 6204 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6205 6206 /* reg_pllp_local_port 6207 * Local port number. 6208 * Access: Index 6209 */ 6210 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6211 6212 /* reg_pllp_label_port 6213 * Front panel label of the port. 6214 * Access: RO 6215 */ 6216 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6217 6218 /* reg_pllp_split_num 6219 * Label split mapping for local_port. 6220 * Access: RO 6221 */ 6222 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6223 6224 /* reg_pllp_slot_index 6225 * Slot index (0: Main board). 6226 * Access: RO 6227 */ 6228 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6229 6230 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6231 { 6232 MLXSW_REG_ZERO(pllp, payload); 6233 mlxsw_reg_pllp_local_port_set(payload, local_port); 6234 } 6235 6236 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6237 u8 *split_num, u8 *slot_index) 6238 { 6239 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6240 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6241 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6242 } 6243 6244 /* PMTM - Port Module Type Mapping Register 6245 * ---------------------------------------- 6246 * The PMTM register allows query or configuration of module types. 6247 * The register can only be set when the module is disabled by PMAOS register 6248 */ 6249 #define MLXSW_REG_PMTM_ID 0x5067 6250 #define MLXSW_REG_PMTM_LEN 0x10 6251 6252 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6253 6254 /* reg_pmtm_slot_index 6255 * Slot index. 6256 * Access: Index 6257 */ 6258 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6259 6260 /* reg_pmtm_module 6261 * Module number. 6262 * Access: Index 6263 */ 6264 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6265 6266 enum mlxsw_reg_pmtm_module_type { 6267 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6268 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6269 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6270 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6271 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6272 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6273 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6274 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6275 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6276 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6277 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6278 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6279 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6280 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6281 }; 6282 6283 /* reg_pmtm_module_type 6284 * Module type. 6285 * Access: RW 6286 */ 6287 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6288 6289 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6290 { 6291 MLXSW_REG_ZERO(pmtm, payload); 6292 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6293 mlxsw_reg_pmtm_module_set(payload, module); 6294 } 6295 6296 /* HTGT - Host Trap Group Table 6297 * ---------------------------- 6298 * Configures the properties for forwarding to CPU. 6299 */ 6300 #define MLXSW_REG_HTGT_ID 0x7002 6301 #define MLXSW_REG_HTGT_LEN 0x20 6302 6303 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6304 6305 /* reg_htgt_swid 6306 * Switch partition ID. 6307 * Access: Index 6308 */ 6309 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6310 6311 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6312 6313 /* reg_htgt_type 6314 * CPU path type. 6315 * Access: RW 6316 */ 6317 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6318 6319 enum mlxsw_reg_htgt_trap_group { 6320 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6321 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6322 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6323 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6324 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6325 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6326 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6327 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6328 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6329 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6330 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6331 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6332 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6333 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6334 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6335 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6336 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6337 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6338 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6339 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6340 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6341 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6342 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6343 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6344 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6345 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6346 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6347 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6348 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6349 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6350 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6351 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6352 MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL, 6353 6354 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6355 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6356 }; 6357 6358 /* reg_htgt_trap_group 6359 * Trap group number. User defined number specifying which trap groups 6360 * should be forwarded to the CPU. The mapping between trap IDs and trap 6361 * groups is configured using HPKT register. 6362 * Access: Index 6363 */ 6364 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6365 6366 enum { 6367 MLXSW_REG_HTGT_POLICER_DISABLE, 6368 MLXSW_REG_HTGT_POLICER_ENABLE, 6369 }; 6370 6371 /* reg_htgt_pide 6372 * Enable policer ID specified using 'pid' field. 6373 * Access: RW 6374 */ 6375 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6376 6377 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6378 6379 /* reg_htgt_pid 6380 * Policer ID for the trap group. 6381 * Access: RW 6382 */ 6383 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6384 6385 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6386 6387 /* reg_htgt_mirror_action 6388 * Mirror action to use. 6389 * 0 - Trap to CPU. 6390 * 1 - Trap to CPU and mirror to a mirroring agent. 6391 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6392 * Access: RW 6393 * 6394 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6395 */ 6396 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6397 6398 /* reg_htgt_mirroring_agent 6399 * Mirroring agent. 6400 * Access: RW 6401 */ 6402 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6403 6404 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6405 6406 /* reg_htgt_priority 6407 * Trap group priority. 6408 * In case a packet matches multiple classification rules, the packet will 6409 * only be trapped once, based on the trap ID associated with the group (via 6410 * register HPKT) with the highest priority. 6411 * Supported values are 0-7, with 7 represnting the highest priority. 6412 * Access: RW 6413 * 6414 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6415 * by the 'trap_group' field. 6416 */ 6417 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6418 6419 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6420 6421 /* reg_htgt_local_path_cpu_tclass 6422 * CPU ingress traffic class for the trap group. 6423 * Access: RW 6424 */ 6425 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6426 6427 enum mlxsw_reg_htgt_local_path_rdq { 6428 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6429 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6430 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6431 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6432 }; 6433 /* reg_htgt_local_path_rdq 6434 * Receive descriptor queue (RDQ) to use for the trap group. 6435 * Access: RW 6436 */ 6437 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6438 6439 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6440 u8 priority, u8 tc) 6441 { 6442 MLXSW_REG_ZERO(htgt, payload); 6443 6444 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6445 mlxsw_reg_htgt_pide_set(payload, 6446 MLXSW_REG_HTGT_POLICER_DISABLE); 6447 } else { 6448 mlxsw_reg_htgt_pide_set(payload, 6449 MLXSW_REG_HTGT_POLICER_ENABLE); 6450 mlxsw_reg_htgt_pid_set(payload, policer_id); 6451 } 6452 6453 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6454 mlxsw_reg_htgt_trap_group_set(payload, group); 6455 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6456 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6457 mlxsw_reg_htgt_priority_set(payload, priority); 6458 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6459 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6460 } 6461 6462 /* HPKT - Host Packet Trap 6463 * ----------------------- 6464 * Configures trap IDs inside trap groups. 6465 */ 6466 #define MLXSW_REG_HPKT_ID 0x7003 6467 #define MLXSW_REG_HPKT_LEN 0x10 6468 6469 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6470 6471 enum { 6472 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6473 MLXSW_REG_HPKT_ACK_REQUIRED, 6474 }; 6475 6476 /* reg_hpkt_ack 6477 * Require acknowledgements from the host for events. 6478 * If set, then the device will wait for the event it sent to be acknowledged 6479 * by the host. This option is only relevant for event trap IDs. 6480 * Access: RW 6481 * 6482 * Note: Currently not supported by firmware. 6483 */ 6484 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6485 6486 enum mlxsw_reg_hpkt_action { 6487 MLXSW_REG_HPKT_ACTION_FORWARD, 6488 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6489 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6490 MLXSW_REG_HPKT_ACTION_DISCARD, 6491 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6492 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6493 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6494 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6495 }; 6496 6497 /* reg_hpkt_action 6498 * Action to perform on packet when trapped. 6499 * 0 - No action. Forward to CPU based on switching rules. 6500 * 1 - Trap to CPU (CPU receives sole copy). 6501 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6502 * 3 - Discard. 6503 * 4 - Soft discard (allow other traps to act on the packet). 6504 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6505 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6506 * 15 - Restore the firmware's default action. 6507 * Access: RW 6508 * 6509 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6510 * addressed to the CPU. 6511 */ 6512 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6513 6514 /* reg_hpkt_trap_group 6515 * Trap group to associate the trap with. 6516 * Access: RW 6517 */ 6518 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6519 6520 /* reg_hpkt_trap_id 6521 * Trap ID. 6522 * Access: Index 6523 * 6524 * Note: A trap ID can only be associated with a single trap group. The device 6525 * will associate the trap ID with the last trap group configured. 6526 */ 6527 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6528 6529 enum { 6530 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6531 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6532 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6533 }; 6534 6535 /* reg_hpkt_ctrl 6536 * Configure dedicated buffer resources for control packets. 6537 * Ignored by SwitchX-2. 6538 * 0 - Keep factory defaults. 6539 * 1 - Do not use control buffer for this trap ID. 6540 * 2 - Use control buffer for this trap ID. 6541 * Access: RW 6542 */ 6543 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6544 6545 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6546 enum mlxsw_reg_htgt_trap_group trap_group, 6547 bool is_ctrl) 6548 { 6549 MLXSW_REG_ZERO(hpkt, payload); 6550 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6551 mlxsw_reg_hpkt_action_set(payload, action); 6552 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6553 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6554 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6555 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6556 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6557 } 6558 6559 /* RGCR - Router General Configuration Register 6560 * -------------------------------------------- 6561 * The register is used for setting up the router configuration. 6562 */ 6563 #define MLXSW_REG_RGCR_ID 0x8001 6564 #define MLXSW_REG_RGCR_LEN 0x28 6565 6566 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6567 6568 /* reg_rgcr_ipv4_en 6569 * IPv4 router enable. 6570 * Access: RW 6571 */ 6572 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6573 6574 /* reg_rgcr_ipv6_en 6575 * IPv6 router enable. 6576 * Access: RW 6577 */ 6578 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6579 6580 /* reg_rgcr_max_router_interfaces 6581 * Defines the maximum number of active router interfaces for all virtual 6582 * routers. 6583 * Access: RW 6584 */ 6585 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6586 6587 /* reg_rgcr_usp 6588 * Update switch priority and packet color. 6589 * 0 - Preserve the value of Switch Priority and packet color. 6590 * 1 - Recalculate the value of Switch Priority and packet color. 6591 * Access: RW 6592 * 6593 * Note: Not supported by SwitchX and SwitchX-2. 6594 */ 6595 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6596 6597 /* reg_rgcr_pcp_rw 6598 * Indicates how to handle the pcp_rewrite_en value: 6599 * 0 - Preserve the value of pcp_rewrite_en. 6600 * 2 - Disable PCP rewrite. 6601 * 3 - Enable PCP rewrite. 6602 * Access: RW 6603 * 6604 * Note: Not supported by SwitchX and SwitchX-2. 6605 */ 6606 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6607 6608 /* reg_rgcr_activity_dis 6609 * Activity disable: 6610 * 0 - Activity will be set when an entry is hit (default). 6611 * 1 - Activity will not be set when an entry is hit. 6612 * 6613 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6614 * (RALUE). 6615 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6616 * Entry (RAUHT). 6617 * Bits 2:7 are reserved. 6618 * Access: RW 6619 * 6620 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6621 */ 6622 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6623 6624 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6625 bool ipv6_en) 6626 { 6627 MLXSW_REG_ZERO(rgcr, payload); 6628 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6629 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6630 } 6631 6632 /* RITR - Router Interface Table Register 6633 * -------------------------------------- 6634 * The register is used to configure the router interface table. 6635 */ 6636 #define MLXSW_REG_RITR_ID 0x8002 6637 #define MLXSW_REG_RITR_LEN 0x40 6638 6639 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6640 6641 /* reg_ritr_enable 6642 * Enables routing on the router interface. 6643 * Access: RW 6644 */ 6645 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6646 6647 /* reg_ritr_ipv4 6648 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6649 * interface. 6650 * Access: RW 6651 */ 6652 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6653 6654 /* reg_ritr_ipv6 6655 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6656 * interface. 6657 * Access: RW 6658 */ 6659 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6660 6661 /* reg_ritr_ipv4_mc 6662 * IPv4 multicast routing enable. 6663 * Access: RW 6664 */ 6665 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6666 6667 /* reg_ritr_ipv6_mc 6668 * IPv6 multicast routing enable. 6669 * Access: RW 6670 */ 6671 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6672 6673 enum mlxsw_reg_ritr_if_type { 6674 /* VLAN interface. */ 6675 MLXSW_REG_RITR_VLAN_IF, 6676 /* FID interface. */ 6677 MLXSW_REG_RITR_FID_IF, 6678 /* Sub-port interface. */ 6679 MLXSW_REG_RITR_SP_IF, 6680 /* Loopback Interface. */ 6681 MLXSW_REG_RITR_LOOPBACK_IF, 6682 }; 6683 6684 /* reg_ritr_type 6685 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6686 * Access: RW 6687 */ 6688 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6689 6690 enum { 6691 MLXSW_REG_RITR_RIF_CREATE, 6692 MLXSW_REG_RITR_RIF_DEL, 6693 }; 6694 6695 /* reg_ritr_op 6696 * Opcode: 6697 * 0 - Create or edit RIF. 6698 * 1 - Delete RIF. 6699 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6700 * is not supported. An interface must be deleted and re-created in order 6701 * to update properties. 6702 * Access: WO 6703 */ 6704 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6705 6706 /* reg_ritr_rif 6707 * Router interface index. A pointer to the Router Interface Table. 6708 * Access: Index 6709 */ 6710 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6711 6712 /* reg_ritr_ipv4_fe 6713 * IPv4 Forwarding Enable. 6714 * Enables routing of IPv4 traffic on the router interface. When disabled, 6715 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6716 * Not supported in SwitchX-2. 6717 * Access: RW 6718 */ 6719 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6720 6721 /* reg_ritr_ipv6_fe 6722 * IPv6 Forwarding Enable. 6723 * Enables routing of IPv6 traffic on the router interface. When disabled, 6724 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6725 * Not supported in SwitchX-2. 6726 * Access: RW 6727 */ 6728 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6729 6730 /* reg_ritr_ipv4_mc_fe 6731 * IPv4 Multicast Forwarding Enable. 6732 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6733 * will be enabled. 6734 * Access: RW 6735 */ 6736 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6737 6738 /* reg_ritr_ipv6_mc_fe 6739 * IPv6 Multicast Forwarding Enable. 6740 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6741 * will be enabled. 6742 * Access: RW 6743 */ 6744 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6745 6746 /* reg_ritr_lb_en 6747 * Loop-back filter enable for unicast packets. 6748 * If the flag is set then loop-back filter for unicast packets is 6749 * implemented on the RIF. Multicast packets are always subject to 6750 * loop-back filtering. 6751 * Access: RW 6752 */ 6753 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6754 6755 /* reg_ritr_virtual_router 6756 * Virtual router ID associated with the router interface. 6757 * Access: RW 6758 */ 6759 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6760 6761 /* reg_ritr_mtu 6762 * Router interface MTU. 6763 * Access: RW 6764 */ 6765 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6766 6767 /* reg_ritr_if_swid 6768 * Switch partition ID. 6769 * Access: RW 6770 */ 6771 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6772 6773 /* reg_ritr_if_mac_profile_id 6774 * MAC msb profile ID. 6775 * Access: RW 6776 */ 6777 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6778 6779 /* reg_ritr_if_mac 6780 * Router interface MAC address. 6781 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6782 * Access: RW 6783 */ 6784 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6785 6786 /* reg_ritr_if_vrrp_id_ipv6 6787 * VRRP ID for IPv6 6788 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6792 6793 /* reg_ritr_if_vrrp_id_ipv4 6794 * VRRP ID for IPv4 6795 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6796 * Access: RW 6797 */ 6798 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6799 6800 /* VLAN Interface */ 6801 6802 /* reg_ritr_vlan_if_vlan_id 6803 * VLAN ID. 6804 * Access: RW 6805 */ 6806 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6807 6808 /* reg_ritr_vlan_if_efid 6809 * Egress FID. 6810 * Used to connect the RIF to a bridge. 6811 * Access: RW 6812 * 6813 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6814 */ 6815 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6816 6817 /* FID Interface */ 6818 6819 /* reg_ritr_fid_if_fid 6820 * Filtering ID. Used to connect a bridge to the router. 6821 * When legacy bridge model is used, only FIDs from the vFID range are 6822 * supported. When unified bridge model is used, this is the egress FID for 6823 * router to bridge. 6824 * Access: RW 6825 */ 6826 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6827 6828 /* Sub-port Interface */ 6829 6830 /* reg_ritr_sp_if_lag 6831 * LAG indication. When this bit is set the system_port field holds the 6832 * LAG identifier. 6833 * Access: RW 6834 */ 6835 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6836 6837 /* reg_ritr_sp_system_port 6838 * Port unique indentifier. When lag bit is set, this field holds the 6839 * lag_id in bits 0:9. 6840 * Access: RW 6841 */ 6842 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6843 6844 /* reg_ritr_sp_if_efid 6845 * Egress filtering ID. 6846 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6847 * the VID. 6848 * Access: RW 6849 * 6850 * Note: Reserved when legacy bridge model is used. 6851 */ 6852 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6853 6854 /* reg_ritr_sp_if_vid 6855 * VLAN ID. 6856 * Access: RW 6857 */ 6858 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6859 6860 /* Loopback Interface */ 6861 6862 enum mlxsw_reg_ritr_loopback_protocol { 6863 /* IPinIP IPv4 underlay Unicast */ 6864 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6865 /* IPinIP IPv6 underlay Unicast */ 6866 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6867 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6868 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6869 }; 6870 6871 /* reg_ritr_loopback_protocol 6872 * Access: RW 6873 */ 6874 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6875 6876 enum mlxsw_reg_ritr_loopback_ipip_type { 6877 /* Tunnel is IPinIP. */ 6878 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6879 /* Tunnel is GRE, no key. */ 6880 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6881 /* Tunnel is GRE, with a key. */ 6882 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6883 }; 6884 6885 /* reg_ritr_loopback_ipip_type 6886 * Encapsulation type. 6887 * Access: RW 6888 */ 6889 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6890 6891 enum mlxsw_reg_ritr_loopback_ipip_options { 6892 /* The key is defined by gre_key. */ 6893 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6894 }; 6895 6896 /* reg_ritr_loopback_ipip_options 6897 * Access: RW 6898 */ 6899 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6900 6901 /* reg_ritr_loopback_ipip_uvr 6902 * Underlay Virtual Router ID. 6903 * Range is 0..cap_max_virtual_routers-1. 6904 * Reserved for Spectrum-2. 6905 * Access: RW 6906 */ 6907 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6908 6909 /* reg_ritr_loopback_ipip_underlay_rif 6910 * Underlay ingress router interface. 6911 * Reserved for Spectrum. 6912 * Access: RW 6913 */ 6914 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6915 6916 /* reg_ritr_loopback_ipip_usip* 6917 * Encapsulation Underlay source IP. 6918 * Access: RW 6919 */ 6920 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6921 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6922 6923 /* reg_ritr_loopback_ipip_gre_key 6924 * GRE Key. 6925 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6926 * Access: RW 6927 */ 6928 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6929 6930 /* Shared between ingress/egress */ 6931 enum mlxsw_reg_ritr_counter_set_type { 6932 /* No Count. */ 6933 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6934 /* Basic. Used for router interfaces, counting the following: 6935 * - Error and Discard counters. 6936 * - Unicast, Multicast and Broadcast counters. Sharing the 6937 * same set of counters for the different type of traffic 6938 * (IPv4, IPv6 and mpls). 6939 */ 6940 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6941 }; 6942 6943 /* reg_ritr_ingress_counter_index 6944 * Counter Index for flow counter. 6945 * Access: RW 6946 */ 6947 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6948 6949 /* reg_ritr_ingress_counter_set_type 6950 * Igress Counter Set Type for router interface counter. 6951 * Access: RW 6952 */ 6953 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6954 6955 /* reg_ritr_egress_counter_index 6956 * Counter Index for flow counter. 6957 * Access: RW 6958 */ 6959 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6960 6961 /* reg_ritr_egress_counter_set_type 6962 * Egress Counter Set Type for router interface counter. 6963 * Access: RW 6964 */ 6965 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6966 6967 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6968 bool enable, bool egress) 6969 { 6970 enum mlxsw_reg_ritr_counter_set_type set_type; 6971 6972 if (enable) 6973 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6974 else 6975 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6976 6977 if (egress) { 6978 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6979 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6980 } else { 6981 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 6982 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6983 } 6984 } 6985 6986 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6987 { 6988 MLXSW_REG_ZERO(ritr, payload); 6989 mlxsw_reg_ritr_rif_set(payload, rif); 6990 } 6991 6992 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6993 u16 system_port, u16 efid, u16 vid) 6994 { 6995 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6996 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6997 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 6998 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6999 } 7000 7001 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7002 enum mlxsw_reg_ritr_if_type type, 7003 u16 rif, u16 vr_id, u16 mtu) 7004 { 7005 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7006 7007 MLXSW_REG_ZERO(ritr, payload); 7008 mlxsw_reg_ritr_enable_set(payload, enable); 7009 mlxsw_reg_ritr_ipv4_set(payload, 1); 7010 mlxsw_reg_ritr_ipv6_set(payload, 1); 7011 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7012 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7013 mlxsw_reg_ritr_type_set(payload, type); 7014 mlxsw_reg_ritr_op_set(payload, op); 7015 mlxsw_reg_ritr_rif_set(payload, rif); 7016 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7017 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7018 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7019 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7020 mlxsw_reg_ritr_lb_en_set(payload, 1); 7021 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7022 mlxsw_reg_ritr_mtu_set(payload, mtu); 7023 } 7024 7025 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7026 { 7027 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7028 } 7029 7030 static inline void 7031 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7032 u16 mtu, const char *mac, u8 mac_profile_id, 7033 u16 vlan_id, u16 efid) 7034 { 7035 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7036 7037 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7038 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7039 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7040 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7041 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7042 } 7043 7044 static inline void 7045 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7046 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7047 enum mlxsw_reg_ritr_loopback_ipip_options options, 7048 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7049 { 7050 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7051 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7052 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7053 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7054 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7055 } 7056 7057 static inline void 7058 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7059 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7060 enum mlxsw_reg_ritr_loopback_ipip_options options, 7061 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7062 { 7063 mlxsw_reg_ritr_loopback_protocol_set(payload, 7064 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7065 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7066 uvr_id, underlay_rif, gre_key); 7067 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7068 } 7069 7070 static inline void 7071 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7072 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7073 enum mlxsw_reg_ritr_loopback_ipip_options options, 7074 u16 uvr_id, u16 underlay_rif, 7075 const struct in6_addr *usip, u32 gre_key) 7076 { 7077 enum mlxsw_reg_ritr_loopback_protocol protocol = 7078 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7079 7080 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7081 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7082 uvr_id, underlay_rif, gre_key); 7083 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7084 (const char *)usip); 7085 } 7086 7087 /* RTAR - Router TCAM Allocation Register 7088 * -------------------------------------- 7089 * This register is used for allocation of regions in the TCAM table. 7090 */ 7091 #define MLXSW_REG_RTAR_ID 0x8004 7092 #define MLXSW_REG_RTAR_LEN 0x20 7093 7094 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7095 7096 enum mlxsw_reg_rtar_op { 7097 MLXSW_REG_RTAR_OP_ALLOCATE, 7098 MLXSW_REG_RTAR_OP_RESIZE, 7099 MLXSW_REG_RTAR_OP_DEALLOCATE, 7100 }; 7101 7102 /* reg_rtar_op 7103 * Access: WO 7104 */ 7105 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7106 7107 enum mlxsw_reg_rtar_key_type { 7108 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7109 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7110 }; 7111 7112 /* reg_rtar_key_type 7113 * TCAM key type for the region. 7114 * Access: WO 7115 */ 7116 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7117 7118 /* reg_rtar_region_size 7119 * TCAM region size. When allocating/resizing this is the requested 7120 * size, the response is the actual size. 7121 * Note: Actual size may be larger than requested. 7122 * Reserved for op = Deallocate 7123 * Access: WO 7124 */ 7125 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7126 7127 static inline void mlxsw_reg_rtar_pack(char *payload, 7128 enum mlxsw_reg_rtar_op op, 7129 enum mlxsw_reg_rtar_key_type key_type, 7130 u16 region_size) 7131 { 7132 MLXSW_REG_ZERO(rtar, payload); 7133 mlxsw_reg_rtar_op_set(payload, op); 7134 mlxsw_reg_rtar_key_type_set(payload, key_type); 7135 mlxsw_reg_rtar_region_size_set(payload, region_size); 7136 } 7137 7138 /* RATR - Router Adjacency Table Register 7139 * -------------------------------------- 7140 * The RATR register is used to configure the Router Adjacency (next-hop) 7141 * Table. 7142 */ 7143 #define MLXSW_REG_RATR_ID 0x8008 7144 #define MLXSW_REG_RATR_LEN 0x2C 7145 7146 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7147 7148 enum mlxsw_reg_ratr_op { 7149 /* Read */ 7150 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7151 /* Read and clear activity */ 7152 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7153 /* Write Adjacency entry */ 7154 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7155 /* Write Adjacency entry only if the activity is cleared. 7156 * The write may not succeed if the activity is set. There is not 7157 * direct feedback if the write has succeeded or not, however 7158 * the get will reveal the actual entry (SW can compare the get 7159 * response to the set command). 7160 */ 7161 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7162 }; 7163 7164 /* reg_ratr_op 7165 * Note that Write operation may also be used for updating 7166 * counter_set_type and counter_index. In this case all other 7167 * fields must not be updated. 7168 * Access: OP 7169 */ 7170 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7171 7172 /* reg_ratr_v 7173 * Valid bit. Indicates if the adjacency entry is valid. 7174 * Note: the device may need some time before reusing an invalidated 7175 * entry. During this time the entry can not be reused. It is 7176 * recommended to use another entry before reusing an invalidated 7177 * entry (e.g. software can put it at the end of the list for 7178 * reusing). Trying to access an invalidated entry not yet cleared 7179 * by the device results with failure indicating "Try Again" status. 7180 * When valid is '0' then egress_router_interface,trap_action, 7181 * adjacency_parameters and counters are reserved 7182 * Access: RW 7183 */ 7184 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7185 7186 /* reg_ratr_a 7187 * Activity. Set for new entries. Set if a packet lookup has hit on 7188 * the specific entry. To clear the a bit, use "clear activity". 7189 * Access: RO 7190 */ 7191 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7192 7193 enum mlxsw_reg_ratr_type { 7194 /* Ethernet */ 7195 MLXSW_REG_RATR_TYPE_ETHERNET, 7196 /* IPoIB Unicast without GRH. 7197 * Reserved for Spectrum. 7198 */ 7199 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7200 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7201 * adjacency). 7202 * Reserved for Spectrum. 7203 */ 7204 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7205 /* IPoIB Multicast. 7206 * Reserved for Spectrum. 7207 */ 7208 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7209 /* MPLS. 7210 * Reserved for SwitchX/-2. 7211 */ 7212 MLXSW_REG_RATR_TYPE_MPLS, 7213 /* IPinIP Encap. 7214 * Reserved for SwitchX/-2. 7215 */ 7216 MLXSW_REG_RATR_TYPE_IPIP, 7217 }; 7218 7219 /* reg_ratr_type 7220 * Adjacency entry type. 7221 * Access: RW 7222 */ 7223 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7224 7225 /* reg_ratr_adjacency_index_low 7226 * Bits 15:0 of index into the adjacency table. 7227 * For SwitchX and SwitchX-2, the adjacency table is linear and 7228 * used for adjacency entries only. 7229 * For Spectrum, the index is to the KVD linear. 7230 * Access: Index 7231 */ 7232 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7233 7234 /* reg_ratr_egress_router_interface 7235 * Range is 0 .. cap_max_router_interfaces - 1 7236 * Access: RW 7237 */ 7238 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7239 7240 enum mlxsw_reg_ratr_trap_action { 7241 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7242 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7243 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7244 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7245 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7246 }; 7247 7248 /* reg_ratr_trap_action 7249 * see mlxsw_reg_ratr_trap_action 7250 * Access: RW 7251 */ 7252 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7253 7254 /* reg_ratr_adjacency_index_high 7255 * Bits 23:16 of the adjacency_index. 7256 * Access: Index 7257 */ 7258 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7259 7260 enum mlxsw_reg_ratr_trap_id { 7261 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7262 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7263 }; 7264 7265 /* reg_ratr_trap_id 7266 * Trap ID to be reported to CPU. 7267 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7268 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7272 7273 /* reg_ratr_eth_destination_mac 7274 * MAC address of the destination next-hop. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7278 7279 enum mlxsw_reg_ratr_ipip_type { 7280 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7281 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7282 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7283 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7284 }; 7285 7286 /* reg_ratr_ipip_type 7287 * Underlay destination ip type. 7288 * Note: the type field must match the protocol of the router interface. 7289 * Access: RW 7290 */ 7291 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7292 7293 /* reg_ratr_ipip_ipv4_udip 7294 * Underlay ipv4 dip. 7295 * Reserved when ipip_type is IPv6. 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7299 7300 /* reg_ratr_ipip_ipv6_ptr 7301 * Pointer to IPv6 underlay destination ip address. 7302 * For Spectrum: Pointer to KVD linear space. 7303 * Access: RW 7304 */ 7305 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7306 7307 enum mlxsw_reg_flow_counter_set_type { 7308 /* No count */ 7309 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7310 /* Count packets and bytes */ 7311 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7312 /* Count only packets */ 7313 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7314 }; 7315 7316 /* reg_ratr_counter_set_type 7317 * Counter set type for flow counters 7318 * Access: RW 7319 */ 7320 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7321 7322 /* reg_ratr_counter_index 7323 * Counter index for flow counters 7324 * Access: RW 7325 */ 7326 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7327 7328 static inline void 7329 mlxsw_reg_ratr_pack(char *payload, 7330 enum mlxsw_reg_ratr_op op, bool valid, 7331 enum mlxsw_reg_ratr_type type, 7332 u32 adjacency_index, u16 egress_rif) 7333 { 7334 MLXSW_REG_ZERO(ratr, payload); 7335 mlxsw_reg_ratr_op_set(payload, op); 7336 mlxsw_reg_ratr_v_set(payload, valid); 7337 mlxsw_reg_ratr_type_set(payload, type); 7338 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7339 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7340 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7341 } 7342 7343 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7344 const char *dest_mac) 7345 { 7346 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7347 } 7348 7349 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7350 { 7351 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7352 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7353 } 7354 7355 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7356 { 7357 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7358 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7359 } 7360 7361 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7362 bool counter_enable) 7363 { 7364 enum mlxsw_reg_flow_counter_set_type set_type; 7365 7366 if (counter_enable) 7367 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7368 else 7369 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7370 7371 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7372 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7373 } 7374 7375 /* RDPM - Router DSCP to Priority Mapping 7376 * -------------------------------------- 7377 * Controls the mapping from DSCP field to switch priority on routed packets 7378 */ 7379 #define MLXSW_REG_RDPM_ID 0x8009 7380 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7381 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7382 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7383 #define MLXSW_REG_RDPM_LEN 0x40 7384 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7385 MLXSW_REG_RDPM_LEN - \ 7386 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7387 7388 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7389 7390 /* reg_dscp_entry_e 7391 * Enable update of the specific entry 7392 * Access: Index 7393 */ 7394 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7395 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7396 7397 /* reg_dscp_entry_prio 7398 * Switch Priority 7399 * Access: RW 7400 */ 7401 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7402 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7403 7404 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7405 u8 prio) 7406 { 7407 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7408 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7409 } 7410 7411 /* RICNT - Router Interface Counter Register 7412 * ----------------------------------------- 7413 * The RICNT register retrieves per port performance counters 7414 */ 7415 #define MLXSW_REG_RICNT_ID 0x800B 7416 #define MLXSW_REG_RICNT_LEN 0x100 7417 7418 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7419 7420 /* reg_ricnt_counter_index 7421 * Counter index 7422 * Access: RW 7423 */ 7424 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7425 7426 enum mlxsw_reg_ricnt_counter_set_type { 7427 /* No Count. */ 7428 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7429 /* Basic. Used for router interfaces, counting the following: 7430 * - Error and Discard counters. 7431 * - Unicast, Multicast and Broadcast counters. Sharing the 7432 * same set of counters for the different type of traffic 7433 * (IPv4, IPv6 and mpls). 7434 */ 7435 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7436 }; 7437 7438 /* reg_ricnt_counter_set_type 7439 * Counter Set Type for router interface counter 7440 * Access: RW 7441 */ 7442 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7443 7444 enum mlxsw_reg_ricnt_opcode { 7445 /* Nop. Supported only for read access*/ 7446 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7447 /* Clear. Setting the clr bit will reset the counter value for 7448 * all counters of the specified Router Interface. 7449 */ 7450 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7451 }; 7452 7453 /* reg_ricnt_opcode 7454 * Opcode 7455 * Access: RW 7456 */ 7457 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7458 7459 /* reg_ricnt_good_unicast_packets 7460 * good unicast packets. 7461 * Access: RW 7462 */ 7463 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7464 7465 /* reg_ricnt_good_multicast_packets 7466 * good multicast packets. 7467 * Access: RW 7468 */ 7469 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7470 7471 /* reg_ricnt_good_broadcast_packets 7472 * good broadcast packets 7473 * Access: RW 7474 */ 7475 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7476 7477 /* reg_ricnt_good_unicast_bytes 7478 * A count of L3 data and padding octets not including L2 headers 7479 * for good unicast frames. 7480 * Access: RW 7481 */ 7482 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7483 7484 /* reg_ricnt_good_multicast_bytes 7485 * A count of L3 data and padding octets not including L2 headers 7486 * for good multicast frames. 7487 * Access: RW 7488 */ 7489 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7490 7491 /* reg_ritr_good_broadcast_bytes 7492 * A count of L3 data and padding octets not including L2 headers 7493 * for good broadcast frames. 7494 * Access: RW 7495 */ 7496 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7497 7498 /* reg_ricnt_error_packets 7499 * A count of errored frames that do not pass the router checks. 7500 * Access: RW 7501 */ 7502 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7503 7504 /* reg_ricnt_discrad_packets 7505 * A count of non-errored frames that do not pass the router checks. 7506 * Access: RW 7507 */ 7508 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7509 7510 /* reg_ricnt_error_bytes 7511 * A count of L3 data and padding octets not including L2 headers 7512 * for errored frames. 7513 * Access: RW 7514 */ 7515 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7516 7517 /* reg_ricnt_discard_bytes 7518 * A count of L3 data and padding octets not including L2 headers 7519 * for non-errored frames that do not pass the router checks. 7520 * Access: RW 7521 */ 7522 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7523 7524 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7525 enum mlxsw_reg_ricnt_opcode op) 7526 { 7527 MLXSW_REG_ZERO(ricnt, payload); 7528 mlxsw_reg_ricnt_op_set(payload, op); 7529 mlxsw_reg_ricnt_counter_index_set(payload, index); 7530 mlxsw_reg_ricnt_counter_set_type_set(payload, 7531 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7532 } 7533 7534 /* RRCR - Router Rules Copy Register Layout 7535 * ---------------------------------------- 7536 * This register is used for moving and copying route entry rules. 7537 */ 7538 #define MLXSW_REG_RRCR_ID 0x800F 7539 #define MLXSW_REG_RRCR_LEN 0x24 7540 7541 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7542 7543 enum mlxsw_reg_rrcr_op { 7544 /* Move rules */ 7545 MLXSW_REG_RRCR_OP_MOVE, 7546 /* Copy rules */ 7547 MLXSW_REG_RRCR_OP_COPY, 7548 }; 7549 7550 /* reg_rrcr_op 7551 * Access: WO 7552 */ 7553 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7554 7555 /* reg_rrcr_offset 7556 * Offset within the region from which to copy/move. 7557 * Access: Index 7558 */ 7559 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7560 7561 /* reg_rrcr_size 7562 * The number of rules to copy/move. 7563 * Access: WO 7564 */ 7565 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7566 7567 /* reg_rrcr_table_id 7568 * Identifier of the table on which to perform the operation. Encoding is the 7569 * same as in RTAR.key_type 7570 * Access: Index 7571 */ 7572 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7573 7574 /* reg_rrcr_dest_offset 7575 * Offset within the region to which to copy/move 7576 * Access: Index 7577 */ 7578 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7579 7580 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7581 u16 offset, u16 size, 7582 enum mlxsw_reg_rtar_key_type table_id, 7583 u16 dest_offset) 7584 { 7585 MLXSW_REG_ZERO(rrcr, payload); 7586 mlxsw_reg_rrcr_op_set(payload, op); 7587 mlxsw_reg_rrcr_offset_set(payload, offset); 7588 mlxsw_reg_rrcr_size_set(payload, size); 7589 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7590 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7591 } 7592 7593 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7594 * ------------------------------------------------------- 7595 * RALTA is used to allocate the LPM trees of the SHSPM method. 7596 */ 7597 #define MLXSW_REG_RALTA_ID 0x8010 7598 #define MLXSW_REG_RALTA_LEN 0x04 7599 7600 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7601 7602 /* reg_ralta_op 7603 * opcode (valid for Write, must be 0 on Read) 7604 * 0 - allocate a tree 7605 * 1 - deallocate a tree 7606 * Access: OP 7607 */ 7608 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7609 7610 enum mlxsw_reg_ralxx_protocol { 7611 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7612 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7613 }; 7614 7615 /* reg_ralta_protocol 7616 * Protocol. 7617 * Deallocation opcode: Reserved. 7618 * Access: RW 7619 */ 7620 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7621 7622 /* reg_ralta_tree_id 7623 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7624 * the tree identifier (managed by software). 7625 * Note that tree_id 0 is allocated for a default-route tree. 7626 * Access: Index 7627 */ 7628 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7629 7630 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7631 enum mlxsw_reg_ralxx_protocol protocol, 7632 u8 tree_id) 7633 { 7634 MLXSW_REG_ZERO(ralta, payload); 7635 mlxsw_reg_ralta_op_set(payload, !alloc); 7636 mlxsw_reg_ralta_protocol_set(payload, protocol); 7637 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7638 } 7639 7640 /* RALST - Router Algorithmic LPM Structure Tree Register 7641 * ------------------------------------------------------ 7642 * RALST is used to set and query the structure of an LPM tree. 7643 * The structure of the tree must be sorted as a sorted binary tree, while 7644 * each node is a bin that is tagged as the length of the prefixes the lookup 7645 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7646 * of X bits to match with the destination address. The bin 0 indicates 7647 * the default action, when there is no match of any prefix. 7648 */ 7649 #define MLXSW_REG_RALST_ID 0x8011 7650 #define MLXSW_REG_RALST_LEN 0x104 7651 7652 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7653 7654 /* reg_ralst_root_bin 7655 * The bin number of the root bin. 7656 * 0<root_bin=<(length of IP address) 7657 * For a default-route tree configure 0xff 7658 * Access: RW 7659 */ 7660 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7661 7662 /* reg_ralst_tree_id 7663 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7664 * Access: Index 7665 */ 7666 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7667 7668 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7669 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7670 #define MLXSW_REG_RALST_BIN_COUNT 128 7671 7672 /* reg_ralst_left_child_bin 7673 * Holding the children of the bin according to the stored tree's structure. 7674 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7675 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7676 * Access: RW 7677 */ 7678 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7679 7680 /* reg_ralst_right_child_bin 7681 * Holding the children of the bin according to the stored tree's structure. 7682 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7683 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7684 * Access: RW 7685 */ 7686 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7687 false); 7688 7689 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7690 { 7691 MLXSW_REG_ZERO(ralst, payload); 7692 7693 /* Initialize all bins to have no left or right child */ 7694 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7695 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7696 7697 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7698 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7699 } 7700 7701 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7702 u8 left_child_bin, 7703 u8 right_child_bin) 7704 { 7705 int bin_index = bin_number - 1; 7706 7707 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7708 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7709 right_child_bin); 7710 } 7711 7712 /* RALTB - Router Algorithmic LPM Tree Binding Register 7713 * ---------------------------------------------------- 7714 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7715 */ 7716 #define MLXSW_REG_RALTB_ID 0x8012 7717 #define MLXSW_REG_RALTB_LEN 0x04 7718 7719 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7720 7721 /* reg_raltb_virtual_router 7722 * Virtual Router ID 7723 * Range is 0..cap_max_virtual_routers-1 7724 * Access: Index 7725 */ 7726 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7727 7728 /* reg_raltb_protocol 7729 * Protocol. 7730 * Access: Index 7731 */ 7732 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7733 7734 /* reg_raltb_tree_id 7735 * Tree to be used for the {virtual_router, protocol} 7736 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7737 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7738 * Access: RW 7739 */ 7740 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7741 7742 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7743 enum mlxsw_reg_ralxx_protocol protocol, 7744 u8 tree_id) 7745 { 7746 MLXSW_REG_ZERO(raltb, payload); 7747 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7748 mlxsw_reg_raltb_protocol_set(payload, protocol); 7749 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7750 } 7751 7752 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7753 * ----------------------------------------------------- 7754 * RALUE is used to configure and query LPM entries that serve 7755 * the Unicast protocols. 7756 */ 7757 #define MLXSW_REG_RALUE_ID 0x8013 7758 #define MLXSW_REG_RALUE_LEN 0x38 7759 7760 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7761 7762 /* reg_ralue_protocol 7763 * Protocol. 7764 * Access: Index 7765 */ 7766 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7767 7768 enum mlxsw_reg_ralue_op { 7769 /* Read operation. If entry doesn't exist, the operation fails. */ 7770 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7771 /* Clear on read operation. Used to read entry and 7772 * clear Activity bit. 7773 */ 7774 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7775 /* Write operation. Used to write a new entry to the table. All RW 7776 * fields are written for new entry. Activity bit is set 7777 * for new entries. 7778 */ 7779 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7780 /* Update operation. Used to update an existing route entry and 7781 * only update the RW fields that are detailed in the field 7782 * op_u_mask. If entry doesn't exist, the operation fails. 7783 */ 7784 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7785 /* Clear activity. The Activity bit (the field a) is cleared 7786 * for the entry. 7787 */ 7788 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7789 /* Delete operation. Used to delete an existing entry. If entry 7790 * doesn't exist, the operation fails. 7791 */ 7792 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7793 }; 7794 7795 /* reg_ralue_op 7796 * Operation. 7797 * Access: OP 7798 */ 7799 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7800 7801 /* reg_ralue_a 7802 * Activity. Set for new entries. Set if a packet lookup has hit on the 7803 * specific entry, only if the entry is a route. To clear the a bit, use 7804 * "clear activity" op. 7805 * Enabled by activity_dis in RGCR 7806 * Access: RO 7807 */ 7808 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7809 7810 /* reg_ralue_virtual_router 7811 * Virtual Router ID 7812 * Range is 0..cap_max_virtual_routers-1 7813 * Access: Index 7814 */ 7815 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7816 7817 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7818 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7819 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7820 7821 /* reg_ralue_op_u_mask 7822 * opcode update mask. 7823 * On read operation, this field is reserved. 7824 * This field is valid for update opcode, otherwise - reserved. 7825 * This field is a bitmask of the fields that should be updated. 7826 * Access: WO 7827 */ 7828 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7829 7830 /* reg_ralue_prefix_len 7831 * Number of bits in the prefix of the LPM route. 7832 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7833 * two entries in the physical HW table. 7834 * Access: Index 7835 */ 7836 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7837 7838 /* reg_ralue_dip* 7839 * The prefix of the route or of the marker that the object of the LPM 7840 * is compared with. The most significant bits of the dip are the prefix. 7841 * The least significant bits must be '0' if the prefix_len is smaller 7842 * than 128 for IPv6 or smaller than 32 for IPv4. 7843 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7844 * Access: Index 7845 */ 7846 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7847 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7848 7849 enum mlxsw_reg_ralue_entry_type { 7850 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7851 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7852 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7853 }; 7854 7855 /* reg_ralue_entry_type 7856 * Entry type. 7857 * Note - for Marker entries, the action_type and action fields are reserved. 7858 * Access: RW 7859 */ 7860 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7861 7862 /* reg_ralue_bmp_len 7863 * The best match prefix length in the case that there is no match for 7864 * longer prefixes. 7865 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7866 * Note for any update operation with entry_type modification this 7867 * field must be set. 7868 * Access: RW 7869 */ 7870 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7871 7872 enum mlxsw_reg_ralue_action_type { 7873 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7874 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7875 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7876 }; 7877 7878 /* reg_ralue_action_type 7879 * Action Type 7880 * Indicates how the IP address is connected. 7881 * It can be connected to a local subnet through local_erif or can be 7882 * on a remote subnet connected through a next-hop router, 7883 * or transmitted to the CPU. 7884 * Reserved when entry_type = MARKER_ENTRY 7885 * Access: RW 7886 */ 7887 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7888 7889 enum mlxsw_reg_ralue_trap_action { 7890 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7891 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7892 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7893 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7894 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7895 }; 7896 7897 /* reg_ralue_trap_action 7898 * Trap action. 7899 * For IP2ME action, only NOP and MIRROR are possible. 7900 * Access: RW 7901 */ 7902 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7903 7904 /* reg_ralue_trap_id 7905 * Trap ID to be reported to CPU. 7906 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7907 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7908 * Access: RW 7909 */ 7910 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7911 7912 /* reg_ralue_adjacency_index 7913 * Points to the first entry of the group-based ECMP. 7914 * Only relevant in case of REMOTE action. 7915 * Access: RW 7916 */ 7917 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7918 7919 /* reg_ralue_ecmp_size 7920 * Amount of sequential entries starting 7921 * from the adjacency_index (the number of ECMPs). 7922 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7923 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7924 * Only relevant in case of REMOTE action. 7925 * Access: RW 7926 */ 7927 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7928 7929 /* reg_ralue_local_erif 7930 * Egress Router Interface. 7931 * Only relevant in case of LOCAL action. 7932 * Access: RW 7933 */ 7934 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7935 7936 /* reg_ralue_ip2me_v 7937 * Valid bit for the tunnel_ptr field. 7938 * If valid = 0 then trap to CPU as IP2ME trap ID. 7939 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7940 * decapsulation then tunnel decapsulation is done. 7941 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7942 * decapsulation then trap as IP2ME trap ID. 7943 * Only relevant in case of IP2ME action. 7944 * Access: RW 7945 */ 7946 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7947 7948 /* reg_ralue_ip2me_tunnel_ptr 7949 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7950 * For Spectrum, pointer to KVD Linear. 7951 * Only relevant in case of IP2ME action. 7952 * Access: RW 7953 */ 7954 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7955 7956 static inline void mlxsw_reg_ralue_pack(char *payload, 7957 enum mlxsw_reg_ralxx_protocol protocol, 7958 enum mlxsw_reg_ralue_op op, 7959 u16 virtual_router, u8 prefix_len) 7960 { 7961 MLXSW_REG_ZERO(ralue, payload); 7962 mlxsw_reg_ralue_protocol_set(payload, protocol); 7963 mlxsw_reg_ralue_op_set(payload, op); 7964 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7965 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7966 mlxsw_reg_ralue_entry_type_set(payload, 7967 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7968 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7969 } 7970 7971 static inline void mlxsw_reg_ralue_pack4(char *payload, 7972 enum mlxsw_reg_ralxx_protocol protocol, 7973 enum mlxsw_reg_ralue_op op, 7974 u16 virtual_router, u8 prefix_len, 7975 u32 dip) 7976 { 7977 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7978 mlxsw_reg_ralue_dip4_set(payload, dip); 7979 } 7980 7981 static inline void mlxsw_reg_ralue_pack6(char *payload, 7982 enum mlxsw_reg_ralxx_protocol protocol, 7983 enum mlxsw_reg_ralue_op op, 7984 u16 virtual_router, u8 prefix_len, 7985 const void *dip) 7986 { 7987 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7988 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7989 } 7990 7991 static inline void 7992 mlxsw_reg_ralue_act_remote_pack(char *payload, 7993 enum mlxsw_reg_ralue_trap_action trap_action, 7994 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7995 { 7996 mlxsw_reg_ralue_action_type_set(payload, 7997 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7998 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7999 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8000 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8001 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8002 } 8003 8004 static inline void 8005 mlxsw_reg_ralue_act_local_pack(char *payload, 8006 enum mlxsw_reg_ralue_trap_action trap_action, 8007 u16 trap_id, u16 local_erif) 8008 { 8009 mlxsw_reg_ralue_action_type_set(payload, 8010 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8011 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8012 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8013 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8014 } 8015 8016 static inline void 8017 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8018 { 8019 mlxsw_reg_ralue_action_type_set(payload, 8020 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8021 } 8022 8023 static inline void 8024 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8025 { 8026 mlxsw_reg_ralue_action_type_set(payload, 8027 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8028 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8029 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8030 } 8031 8032 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8033 * ---------------------------------------------------------- 8034 * The RAUHT register is used to configure and query the Unicast Host table in 8035 * devices that implement the Algorithmic LPM. 8036 */ 8037 #define MLXSW_REG_RAUHT_ID 0x8014 8038 #define MLXSW_REG_RAUHT_LEN 0x74 8039 8040 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8041 8042 enum mlxsw_reg_rauht_type { 8043 MLXSW_REG_RAUHT_TYPE_IPV4, 8044 MLXSW_REG_RAUHT_TYPE_IPV6, 8045 }; 8046 8047 /* reg_rauht_type 8048 * Access: Index 8049 */ 8050 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8051 8052 enum mlxsw_reg_rauht_op { 8053 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8054 /* Read operation */ 8055 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8056 /* Clear on read operation. Used to read entry and clear 8057 * activity bit. 8058 */ 8059 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8060 /* Add. Used to write a new entry to the table. All R/W fields are 8061 * relevant for new entry. Activity bit is set for new entries. 8062 */ 8063 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8064 /* Update action. Used to update an existing route entry and 8065 * only update the following fields: 8066 * trap_action, trap_id, mac, counter_set_type, counter_index 8067 */ 8068 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8069 /* Clear activity. A bit is cleared for the entry. */ 8070 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8071 /* Delete entry */ 8072 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8073 /* Delete all host entries on a RIF. In this command, dip 8074 * field is reserved. 8075 */ 8076 }; 8077 8078 /* reg_rauht_op 8079 * Access: OP 8080 */ 8081 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8082 8083 /* reg_rauht_a 8084 * Activity. Set for new entries. Set if a packet lookup has hit on 8085 * the specific entry. 8086 * To clear the a bit, use "clear activity" op. 8087 * Enabled by activity_dis in RGCR 8088 * Access: RO 8089 */ 8090 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8091 8092 /* reg_rauht_rif 8093 * Router Interface 8094 * Access: Index 8095 */ 8096 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8097 8098 /* reg_rauht_dip* 8099 * Destination address. 8100 * Access: Index 8101 */ 8102 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8103 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8104 8105 enum mlxsw_reg_rauht_trap_action { 8106 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8107 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8108 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8109 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8110 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8111 }; 8112 8113 /* reg_rauht_trap_action 8114 * Access: RW 8115 */ 8116 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8117 8118 enum mlxsw_reg_rauht_trap_id { 8119 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8120 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8121 }; 8122 8123 /* reg_rauht_trap_id 8124 * Trap ID to be reported to CPU. 8125 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8126 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8127 * trap_id is reserved. 8128 * Access: RW 8129 */ 8130 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8131 8132 /* reg_rauht_counter_set_type 8133 * Counter set type for flow counters 8134 * Access: RW 8135 */ 8136 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8137 8138 /* reg_rauht_counter_index 8139 * Counter index for flow counters 8140 * Access: RW 8141 */ 8142 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8143 8144 /* reg_rauht_mac 8145 * MAC address. 8146 * Access: RW 8147 */ 8148 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8149 8150 static inline void mlxsw_reg_rauht_pack(char *payload, 8151 enum mlxsw_reg_rauht_op op, u16 rif, 8152 const char *mac) 8153 { 8154 MLXSW_REG_ZERO(rauht, payload); 8155 mlxsw_reg_rauht_op_set(payload, op); 8156 mlxsw_reg_rauht_rif_set(payload, rif); 8157 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8158 } 8159 8160 static inline void mlxsw_reg_rauht_pack4(char *payload, 8161 enum mlxsw_reg_rauht_op op, u16 rif, 8162 const char *mac, u32 dip) 8163 { 8164 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8165 mlxsw_reg_rauht_dip4_set(payload, dip); 8166 } 8167 8168 static inline void mlxsw_reg_rauht_pack6(char *payload, 8169 enum mlxsw_reg_rauht_op op, u16 rif, 8170 const char *mac, const char *dip) 8171 { 8172 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8173 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8174 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8175 } 8176 8177 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8178 u64 counter_index) 8179 { 8180 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8181 mlxsw_reg_rauht_counter_set_type_set(payload, 8182 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8183 } 8184 8185 /* RALEU - Router Algorithmic LPM ECMP Update Register 8186 * --------------------------------------------------- 8187 * The register enables updating the ECMP section in the action for multiple 8188 * LPM Unicast entries in a single operation. The update is executed to 8189 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8190 */ 8191 #define MLXSW_REG_RALEU_ID 0x8015 8192 #define MLXSW_REG_RALEU_LEN 0x28 8193 8194 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8195 8196 /* reg_raleu_protocol 8197 * Protocol. 8198 * Access: Index 8199 */ 8200 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8201 8202 /* reg_raleu_virtual_router 8203 * Virtual Router ID 8204 * Range is 0..cap_max_virtual_routers-1 8205 * Access: Index 8206 */ 8207 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8208 8209 /* reg_raleu_adjacency_index 8210 * Adjacency Index used for matching on the existing entries. 8211 * Access: Index 8212 */ 8213 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8214 8215 /* reg_raleu_ecmp_size 8216 * ECMP Size used for matching on the existing entries. 8217 * Access: Index 8218 */ 8219 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8220 8221 /* reg_raleu_new_adjacency_index 8222 * New Adjacency Index. 8223 * Access: WO 8224 */ 8225 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8226 8227 /* reg_raleu_new_ecmp_size 8228 * New ECMP Size. 8229 * Access: WO 8230 */ 8231 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8232 8233 static inline void mlxsw_reg_raleu_pack(char *payload, 8234 enum mlxsw_reg_ralxx_protocol protocol, 8235 u16 virtual_router, 8236 u32 adjacency_index, u16 ecmp_size, 8237 u32 new_adjacency_index, 8238 u16 new_ecmp_size) 8239 { 8240 MLXSW_REG_ZERO(raleu, payload); 8241 mlxsw_reg_raleu_protocol_set(payload, protocol); 8242 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8243 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8244 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8245 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8246 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8247 } 8248 8249 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8250 * ---------------------------------------------------------------- 8251 * The RAUHTD register allows dumping entries from the Router Unicast Host 8252 * Table. For a given session an entry is dumped no more than one time. The 8253 * first RAUHTD access after reset is a new session. A session ends when the 8254 * num_rec response is smaller than num_rec request or for IPv4 when the 8255 * num_entries is smaller than 4. The clear activity affect the current session 8256 * or the last session if a new session has not started. 8257 */ 8258 #define MLXSW_REG_RAUHTD_ID 0x8018 8259 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8260 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8261 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8262 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8263 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8264 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8265 8266 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8267 8268 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8269 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8270 8271 /* reg_rauhtd_filter_fields 8272 * if a bit is '0' then the relevant field is ignored and dump is done 8273 * regardless of the field value 8274 * Bit0 - filter by activity: entry_a 8275 * Bit3 - filter by entry rip: entry_rif 8276 * Access: Index 8277 */ 8278 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8279 8280 enum mlxsw_reg_rauhtd_op { 8281 MLXSW_REG_RAUHTD_OP_DUMP, 8282 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8283 }; 8284 8285 /* reg_rauhtd_op 8286 * Access: OP 8287 */ 8288 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8289 8290 /* reg_rauhtd_num_rec 8291 * At request: number of records requested 8292 * At response: number of records dumped 8293 * For IPv4, each record has 4 entries at request and up to 4 entries 8294 * at response 8295 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8296 * Access: Index 8297 */ 8298 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8299 8300 /* reg_rauhtd_entry_a 8301 * Dump only if activity has value of entry_a 8302 * Reserved if filter_fields bit0 is '0' 8303 * Access: Index 8304 */ 8305 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8306 8307 enum mlxsw_reg_rauhtd_type { 8308 MLXSW_REG_RAUHTD_TYPE_IPV4, 8309 MLXSW_REG_RAUHTD_TYPE_IPV6, 8310 }; 8311 8312 /* reg_rauhtd_type 8313 * Dump only if record type is: 8314 * 0 - IPv4 8315 * 1 - IPv6 8316 * Access: Index 8317 */ 8318 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8319 8320 /* reg_rauhtd_entry_rif 8321 * Dump only if RIF has value of entry_rif 8322 * Reserved if filter_fields bit3 is '0' 8323 * Access: Index 8324 */ 8325 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8326 8327 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8328 enum mlxsw_reg_rauhtd_type type) 8329 { 8330 MLXSW_REG_ZERO(rauhtd, payload); 8331 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8332 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8333 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8334 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8335 mlxsw_reg_rauhtd_type_set(payload, type); 8336 } 8337 8338 /* reg_rauhtd_ipv4_rec_num_entries 8339 * Number of valid entries in this record: 8340 * 0 - 1 valid entry 8341 * 1 - 2 valid entries 8342 * 2 - 3 valid entries 8343 * 3 - 4 valid entries 8344 * Access: RO 8345 */ 8346 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8347 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8348 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8349 8350 /* reg_rauhtd_rec_type 8351 * Record type. 8352 * 0 - IPv4 8353 * 1 - IPv6 8354 * Access: RO 8355 */ 8356 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8357 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8358 8359 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8360 8361 /* reg_rauhtd_ipv4_ent_a 8362 * Activity. Set for new entries. Set if a packet lookup has hit on the 8363 * specific entry. 8364 * Access: RO 8365 */ 8366 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8367 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8368 8369 /* reg_rauhtd_ipv4_ent_rif 8370 * Router interface. 8371 * Access: RO 8372 */ 8373 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8374 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8375 8376 /* reg_rauhtd_ipv4_ent_dip 8377 * Destination IPv4 address. 8378 * Access: RO 8379 */ 8380 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8381 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8382 8383 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8384 8385 /* reg_rauhtd_ipv6_ent_a 8386 * Activity. Set for new entries. Set if a packet lookup has hit on the 8387 * specific entry. 8388 * Access: RO 8389 */ 8390 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8391 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8392 8393 /* reg_rauhtd_ipv6_ent_rif 8394 * Router interface. 8395 * Access: RO 8396 */ 8397 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8398 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8399 8400 /* reg_rauhtd_ipv6_ent_dip 8401 * Destination IPv6 address. 8402 * Access: RO 8403 */ 8404 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8405 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8406 8407 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8408 int ent_index, u16 *p_rif, 8409 u32 *p_dip) 8410 { 8411 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8412 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8413 } 8414 8415 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8416 int rec_index, u16 *p_rif, 8417 char *p_dip) 8418 { 8419 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8420 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8421 } 8422 8423 /* RTDP - Routing Tunnel Decap Properties Register 8424 * ----------------------------------------------- 8425 * The RTDP register is used for configuring the tunnel decap properties of NVE 8426 * and IPinIP. 8427 */ 8428 #define MLXSW_REG_RTDP_ID 0x8020 8429 #define MLXSW_REG_RTDP_LEN 0x44 8430 8431 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8432 8433 enum mlxsw_reg_rtdp_type { 8434 MLXSW_REG_RTDP_TYPE_NVE, 8435 MLXSW_REG_RTDP_TYPE_IPIP, 8436 }; 8437 8438 /* reg_rtdp_type 8439 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8440 * Access: RW 8441 */ 8442 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8443 8444 /* reg_rtdp_tunnel_index 8445 * Index to the Decap entry. 8446 * For Spectrum, Index to KVD Linear. 8447 * Access: Index 8448 */ 8449 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8450 8451 /* reg_rtdp_egress_router_interface 8452 * Underlay egress router interface. 8453 * Valid range is from 0 to cap_max_router_interfaces - 1 8454 * Access: RW 8455 */ 8456 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8457 8458 /* IPinIP */ 8459 8460 /* reg_rtdp_ipip_irif 8461 * Ingress Router Interface for the overlay router 8462 * Access: RW 8463 */ 8464 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8465 8466 enum mlxsw_reg_rtdp_ipip_sip_check { 8467 /* No sip checks. */ 8468 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8469 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8470 * equal ipv4_usip. 8471 */ 8472 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8473 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8474 * equal ipv6_usip. 8475 */ 8476 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8477 }; 8478 8479 /* reg_rtdp_ipip_sip_check 8480 * SIP check to perform. If decapsulation failed due to these configurations 8481 * then trap_id is IPIP_DECAP_ERROR. 8482 * Access: RW 8483 */ 8484 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8485 8486 /* If set, allow decapsulation of IPinIP (without GRE). */ 8487 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8488 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8489 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8490 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8491 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8492 8493 /* reg_rtdp_ipip_type_check 8494 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8495 * these configurations then trap_id is IPIP_DECAP_ERROR. 8496 * Access: RW 8497 */ 8498 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8499 8500 /* reg_rtdp_ipip_gre_key_check 8501 * Whether GRE key should be checked. When check is enabled: 8502 * - A packet received as IPinIP (without GRE) will always pass. 8503 * - A packet received as IPinGREinIP without a key will not pass the check. 8504 * - A packet received as IPinGREinIP with a key will pass the check only if the 8505 * key in the packet is equal to expected_gre_key. 8506 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8507 * Access: RW 8508 */ 8509 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8510 8511 /* reg_rtdp_ipip_ipv4_usip 8512 * Underlay IPv4 address for ipv4 source address check. 8513 * Reserved when sip_check is not '1'. 8514 * Access: RW 8515 */ 8516 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8517 8518 /* reg_rtdp_ipip_ipv6_usip_ptr 8519 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8520 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8521 * is to the KVD linear. 8522 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8523 * Access: RW 8524 */ 8525 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8526 8527 /* reg_rtdp_ipip_expected_gre_key 8528 * GRE key for checking. 8529 * Reserved when gre_key_check is '0'. 8530 * Access: RW 8531 */ 8532 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8533 8534 static inline void mlxsw_reg_rtdp_pack(char *payload, 8535 enum mlxsw_reg_rtdp_type type, 8536 u32 tunnel_index) 8537 { 8538 MLXSW_REG_ZERO(rtdp, payload); 8539 mlxsw_reg_rtdp_type_set(payload, type); 8540 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8541 } 8542 8543 static inline void 8544 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8545 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8546 unsigned int type_check, bool gre_key_check, 8547 u32 expected_gre_key) 8548 { 8549 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8550 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8551 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8552 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8553 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8554 } 8555 8556 static inline void 8557 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8558 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8559 unsigned int type_check, bool gre_key_check, 8560 u32 ipv4_usip, u32 expected_gre_key) 8561 { 8562 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8563 gre_key_check, expected_gre_key); 8564 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8565 } 8566 8567 static inline void 8568 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8569 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8570 unsigned int type_check, bool gre_key_check, 8571 u32 ipv6_usip_ptr, u32 expected_gre_key) 8572 { 8573 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8574 gre_key_check, expected_gre_key); 8575 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8576 } 8577 8578 /* RIPS - Router IP version Six Register 8579 * ------------------------------------- 8580 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8581 * IPinIP 8582 */ 8583 #define MLXSW_REG_RIPS_ID 0x8021 8584 #define MLXSW_REG_RIPS_LEN 0x14 8585 8586 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8587 8588 /* reg_rips_index 8589 * Index to IPv6 address. 8590 * For Spectrum, the index is to the KVD linear. 8591 * Access: Index 8592 */ 8593 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8594 8595 /* reg_rips_ipv6 8596 * IPv6 address 8597 * Access: RW 8598 */ 8599 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8600 8601 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8602 const struct in6_addr *ipv6) 8603 { 8604 MLXSW_REG_ZERO(rips, payload); 8605 mlxsw_reg_rips_index_set(payload, index); 8606 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8607 } 8608 8609 /* RATRAD - Router Adjacency Table Activity Dump Register 8610 * ------------------------------------------------------ 8611 * The RATRAD register is used to dump and optionally clear activity bits of 8612 * router adjacency table entries. 8613 */ 8614 #define MLXSW_REG_RATRAD_ID 0x8022 8615 #define MLXSW_REG_RATRAD_LEN 0x210 8616 8617 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8618 8619 enum { 8620 /* Read activity */ 8621 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8622 /* Read and clear activity */ 8623 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8624 }; 8625 8626 /* reg_ratrad_op 8627 * Access: Operation 8628 */ 8629 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8630 8631 /* reg_ratrad_ecmp_size 8632 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8633 * ranges: 8634 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8635 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8636 * Access: Index 8637 */ 8638 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8639 8640 /* reg_ratrad_adjacency_index 8641 * Index into the adjacency table. 8642 * Access: Index 8643 */ 8644 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8645 8646 /* reg_ratrad_activity_vector 8647 * Activity bit per adjacency index. 8648 * Bits higher than ecmp_size are reserved. 8649 * Access: RO 8650 */ 8651 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8652 8653 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8654 u16 ecmp_size) 8655 { 8656 MLXSW_REG_ZERO(ratrad, payload); 8657 mlxsw_reg_ratrad_op_set(payload, 8658 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8659 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8660 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8661 } 8662 8663 /* RIGR-V2 - Router Interface Group Register Version 2 8664 * --------------------------------------------------- 8665 * The RIGR_V2 register is used to add, remove and query egress interface list 8666 * of a multicast forwarding entry. 8667 */ 8668 #define MLXSW_REG_RIGR2_ID 0x8023 8669 #define MLXSW_REG_RIGR2_LEN 0xB0 8670 8671 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8672 8673 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8674 8675 /* reg_rigr2_rigr_index 8676 * KVD Linear index. 8677 * Access: Index 8678 */ 8679 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8680 8681 /* reg_rigr2_vnext 8682 * Next RIGR Index is valid. 8683 * Access: RW 8684 */ 8685 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8686 8687 /* reg_rigr2_next_rigr_index 8688 * Next RIGR Index. The index is to the KVD linear. 8689 * Reserved when vnxet = '0'. 8690 * Access: RW 8691 */ 8692 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8693 8694 /* reg_rigr2_vrmid 8695 * RMID Index is valid. 8696 * Access: RW 8697 */ 8698 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8699 8700 /* reg_rigr2_rmid_index 8701 * RMID Index. 8702 * Range 0 .. max_mid - 1 8703 * Reserved when vrmid = '0'. 8704 * The index is to the Port Group Table (PGT) 8705 * Access: RW 8706 */ 8707 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8708 8709 /* reg_rigr2_erif_entry_v 8710 * Egress Router Interface is valid. 8711 * Note that low-entries must be set if high-entries are set. For 8712 * example: if erif_entry[2].v is set then erif_entry[1].v and 8713 * erif_entry[0].v must be set. 8714 * Index can be from 0 to cap_mc_erif_list_entries-1 8715 * Access: RW 8716 */ 8717 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8718 8719 /* reg_rigr2_erif_entry_erif 8720 * Egress Router Interface. 8721 * Valid range is from 0 to cap_max_router_interfaces - 1 8722 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8723 * Access: RW 8724 */ 8725 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8726 8727 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8728 bool vnext, u32 next_rigr_index) 8729 { 8730 MLXSW_REG_ZERO(rigr2, payload); 8731 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8732 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8733 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8734 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8735 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8736 } 8737 8738 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8739 bool v, u16 erif) 8740 { 8741 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8742 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8743 } 8744 8745 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8746 * ------------------------------------------------------ 8747 */ 8748 #define MLXSW_REG_RECR2_ID 0x8025 8749 #define MLXSW_REG_RECR2_LEN 0x38 8750 8751 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8752 8753 /* reg_recr2_pp 8754 * Per-port configuration 8755 * Access: Index 8756 */ 8757 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8758 8759 /* reg_recr2_sh 8760 * Symmetric hash 8761 * Access: RW 8762 */ 8763 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8764 8765 /* reg_recr2_seed 8766 * Seed 8767 * Access: RW 8768 */ 8769 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8770 8771 enum { 8772 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8773 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8774 /* Enable IPv4 fields if packet is TCP or UDP */ 8775 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8776 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8777 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8778 /* Enable IPv6 fields if packet is TCP or UDP */ 8779 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8780 /* Enable TCP/UDP header fields if packet is IPv4 */ 8781 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8782 /* Enable TCP/UDP header fields if packet is IPv6 */ 8783 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8784 8785 __MLXSW_REG_RECR2_HEADER_CNT, 8786 }; 8787 8788 /* reg_recr2_outer_header_enables 8789 * Bit mask where each bit enables a specific layer to be included in 8790 * the hash calculation. 8791 * Access: RW 8792 */ 8793 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8794 8795 enum { 8796 /* IPv4 Source IP */ 8797 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8798 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8799 /* IPv4 Destination IP */ 8800 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8801 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8802 /* IP Protocol */ 8803 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8804 /* IPv6 Source IP */ 8805 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8806 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8807 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8808 /* IPv6 Destination IP */ 8809 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8810 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8811 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8812 /* IPv6 Next Header */ 8813 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8814 /* IPv6 Flow Label */ 8815 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8816 /* TCP/UDP Source Port */ 8817 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8818 /* TCP/UDP Destination Port */ 8819 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8820 8821 __MLXSW_REG_RECR2_FIELD_CNT, 8822 }; 8823 8824 /* reg_recr2_outer_header_fields_enable 8825 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8826 * Access: RW 8827 */ 8828 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8829 8830 /* reg_recr2_inner_header_enables 8831 * Bit mask where each bit enables a specific inner layer to be included in the 8832 * hash calculation. Same values as reg_recr2_outer_header_enables. 8833 * Access: RW 8834 */ 8835 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8836 8837 enum { 8838 /* Inner IPv4 Source IP */ 8839 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8840 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8841 /* Inner IPv4 Destination IP */ 8842 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8843 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8844 /* Inner IP Protocol */ 8845 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8846 /* Inner IPv6 Source IP */ 8847 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8848 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8849 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8850 /* Inner IPv6 Destination IP */ 8851 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8852 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8853 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8854 /* Inner IPv6 Next Header */ 8855 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8856 /* Inner IPv6 Flow Label */ 8857 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8858 /* Inner TCP/UDP Source Port */ 8859 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8860 /* Inner TCP/UDP Destination Port */ 8861 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8862 8863 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8864 }; 8865 8866 /* reg_recr2_inner_header_fields_enable 8867 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8868 * Access: RW 8869 */ 8870 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8871 8872 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8873 { 8874 MLXSW_REG_ZERO(recr2, payload); 8875 mlxsw_reg_recr2_pp_set(payload, false); 8876 mlxsw_reg_recr2_sh_set(payload, true); 8877 mlxsw_reg_recr2_seed_set(payload, seed); 8878 } 8879 8880 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8881 * -------------------------------------------------------------- 8882 * The RMFT_V2 register is used to configure and query the multicast table. 8883 */ 8884 #define MLXSW_REG_RMFT2_ID 0x8027 8885 #define MLXSW_REG_RMFT2_LEN 0x174 8886 8887 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8888 8889 /* reg_rmft2_v 8890 * Valid 8891 * Access: RW 8892 */ 8893 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8894 8895 enum mlxsw_reg_rmft2_type { 8896 MLXSW_REG_RMFT2_TYPE_IPV4, 8897 MLXSW_REG_RMFT2_TYPE_IPV6 8898 }; 8899 8900 /* reg_rmft2_type 8901 * Access: Index 8902 */ 8903 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8904 8905 enum mlxsw_sp_reg_rmft2_op { 8906 /* For Write: 8907 * Write operation. Used to write a new entry to the table. All RW 8908 * fields are relevant for new entry. Activity bit is set for new 8909 * entries - Note write with v (Valid) 0 will delete the entry. 8910 * For Query: 8911 * Read operation 8912 */ 8913 MLXSW_REG_RMFT2_OP_READ_WRITE, 8914 }; 8915 8916 /* reg_rmft2_op 8917 * Operation. 8918 * Access: OP 8919 */ 8920 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8921 8922 /* reg_rmft2_a 8923 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8924 * entry. 8925 * Access: RO 8926 */ 8927 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8928 8929 /* reg_rmft2_offset 8930 * Offset within the multicast forwarding table to write to. 8931 * Access: Index 8932 */ 8933 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8934 8935 /* reg_rmft2_virtual_router 8936 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8937 * Access: RW 8938 */ 8939 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8940 8941 enum mlxsw_reg_rmft2_irif_mask { 8942 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8943 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8944 }; 8945 8946 /* reg_rmft2_irif_mask 8947 * Ingress RIF mask. 8948 * Access: RW 8949 */ 8950 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8951 8952 /* reg_rmft2_irif 8953 * Ingress RIF index. 8954 * Access: RW 8955 */ 8956 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8957 8958 /* reg_rmft2_dip{4,6} 8959 * Destination IPv4/6 address 8960 * Access: RW 8961 */ 8962 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8963 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8964 8965 /* reg_rmft2_dip{4,6}_mask 8966 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8967 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8968 * Access: RW 8969 */ 8970 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8971 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8972 8973 /* reg_rmft2_sip{4,6} 8974 * Source IPv4/6 address 8975 * Access: RW 8976 */ 8977 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8978 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8979 8980 /* reg_rmft2_sip{4,6}_mask 8981 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8982 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8983 * Access: RW 8984 */ 8985 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8986 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8987 8988 /* reg_rmft2_flexible_action_set 8989 * ACL action set. The only supported action types in this field and in any 8990 * action-set pointed from here are as follows: 8991 * 00h: ACTION_NULL 8992 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8993 * 03h: ACTION_TRAP 8994 * 06h: ACTION_QOS 8995 * 08h: ACTION_POLICING_MONITORING 8996 * 10h: ACTION_ROUTER_MC 8997 * Access: RW 8998 */ 8999 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9000 MLXSW_REG_FLEX_ACTION_SET_LEN); 9001 9002 static inline void 9003 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9004 u16 virtual_router, 9005 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9006 const char *flex_action_set) 9007 { 9008 MLXSW_REG_ZERO(rmft2, payload); 9009 mlxsw_reg_rmft2_v_set(payload, v); 9010 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9011 mlxsw_reg_rmft2_offset_set(payload, offset); 9012 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9013 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9014 mlxsw_reg_rmft2_irif_set(payload, irif); 9015 if (flex_action_set) 9016 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9017 flex_action_set); 9018 } 9019 9020 static inline void 9021 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9022 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9023 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9024 const char *flexible_action_set) 9025 { 9026 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9027 irif_mask, irif, flexible_action_set); 9028 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9029 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9030 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9031 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9032 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9033 } 9034 9035 static inline void 9036 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9037 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9038 struct in6_addr dip6, struct in6_addr dip6_mask, 9039 struct in6_addr sip6, struct in6_addr sip6_mask, 9040 const char *flexible_action_set) 9041 { 9042 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9043 irif_mask, irif, flexible_action_set); 9044 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9045 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9046 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9047 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9048 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9049 } 9050 9051 /* REIV - Router Egress Interface to VID Register 9052 * ---------------------------------------------- 9053 * The REIV register maps {eRIF, egress_port} -> VID. 9054 * This mapping is done at the egress, after the ACLs. 9055 * This mapping always takes effect after router, regardless of cast 9056 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9057 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9058 * Reserved when the RIF is a loopback RIF. 9059 * 9060 * Note: Reserved when legacy bridge model is used. 9061 */ 9062 #define MLXSW_REG_REIV_ID 0x8034 9063 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9064 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9065 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9066 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9067 MLXSW_REG_REIV_REC_LEN * \ 9068 MLXSW_REG_REIV_REC_MAX_COUNT) 9069 9070 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9071 9072 /* reg_reiv_port_page 9073 * Port page - elport_record[0] is 256*port_page. 9074 * Access: Index 9075 */ 9076 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9077 9078 /* reg_reiv_erif 9079 * Egress RIF. 9080 * Range is 0..cap_max_router_interfaces-1. 9081 * Access: Index 9082 */ 9083 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9084 9085 /* reg_reiv_rec_update 9086 * Update enable (when write): 9087 * 0 - Do not update the entry. 9088 * 1 - Update the entry. 9089 * Access: OP 9090 */ 9091 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9092 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9093 9094 /* reg_reiv_rec_evid 9095 * Egress VID. 9096 * Range is 0..4095. 9097 * Access: RW 9098 */ 9099 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9100 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9101 9102 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9103 { 9104 MLXSW_REG_ZERO(reiv, payload); 9105 mlxsw_reg_reiv_port_page_set(payload, port_page); 9106 mlxsw_reg_reiv_erif_set(payload, erif); 9107 } 9108 9109 /* MFCR - Management Fan Control Register 9110 * -------------------------------------- 9111 * This register controls the settings of the Fan Speed PWM mechanism. 9112 */ 9113 #define MLXSW_REG_MFCR_ID 0x9001 9114 #define MLXSW_REG_MFCR_LEN 0x08 9115 9116 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9117 9118 enum mlxsw_reg_mfcr_pwm_frequency { 9119 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9120 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9121 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9122 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9123 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9124 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9125 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9126 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9127 }; 9128 9129 /* reg_mfcr_pwm_frequency 9130 * Controls the frequency of the PWM signal. 9131 * Access: RW 9132 */ 9133 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9134 9135 #define MLXSW_MFCR_TACHOS_MAX 10 9136 9137 /* reg_mfcr_tacho_active 9138 * Indicates which of the tachometer is active (bit per tachometer). 9139 * Access: RO 9140 */ 9141 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9142 9143 #define MLXSW_MFCR_PWMS_MAX 5 9144 9145 /* reg_mfcr_pwm_active 9146 * Indicates which of the PWM control is active (bit per PWM). 9147 * Access: RO 9148 */ 9149 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9150 9151 static inline void 9152 mlxsw_reg_mfcr_pack(char *payload, 9153 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9154 { 9155 MLXSW_REG_ZERO(mfcr, payload); 9156 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9157 } 9158 9159 static inline void 9160 mlxsw_reg_mfcr_unpack(char *payload, 9161 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9162 u16 *p_tacho_active, u8 *p_pwm_active) 9163 { 9164 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9165 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9166 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9167 } 9168 9169 /* MFSC - Management Fan Speed Control Register 9170 * -------------------------------------------- 9171 * This register controls the settings of the Fan Speed PWM mechanism. 9172 */ 9173 #define MLXSW_REG_MFSC_ID 0x9002 9174 #define MLXSW_REG_MFSC_LEN 0x08 9175 9176 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9177 9178 /* reg_mfsc_pwm 9179 * Fan pwm to control / monitor. 9180 * Access: Index 9181 */ 9182 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9183 9184 /* reg_mfsc_pwm_duty_cycle 9185 * Controls the duty cycle of the PWM. Value range from 0..255 to 9186 * represent duty cycle of 0%...100%. 9187 * Access: RW 9188 */ 9189 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9190 9191 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9192 u8 pwm_duty_cycle) 9193 { 9194 MLXSW_REG_ZERO(mfsc, payload); 9195 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9196 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9197 } 9198 9199 /* MFSM - Management Fan Speed Measurement 9200 * --------------------------------------- 9201 * This register controls the settings of the Tacho measurements and 9202 * enables reading the Tachometer measurements. 9203 */ 9204 #define MLXSW_REG_MFSM_ID 0x9003 9205 #define MLXSW_REG_MFSM_LEN 0x08 9206 9207 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9208 9209 /* reg_mfsm_tacho 9210 * Fan tachometer index. 9211 * Access: Index 9212 */ 9213 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9214 9215 /* reg_mfsm_rpm 9216 * Fan speed (round per minute). 9217 * Access: RO 9218 */ 9219 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9220 9221 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9222 { 9223 MLXSW_REG_ZERO(mfsm, payload); 9224 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9225 } 9226 9227 /* MFSL - Management Fan Speed Limit Register 9228 * ------------------------------------------ 9229 * The Fan Speed Limit register is used to configure the fan speed 9230 * event / interrupt notification mechanism. Fan speed threshold are 9231 * defined for both under-speed and over-speed. 9232 */ 9233 #define MLXSW_REG_MFSL_ID 0x9004 9234 #define MLXSW_REG_MFSL_LEN 0x0C 9235 9236 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9237 9238 /* reg_mfsl_tacho 9239 * Fan tachometer index. 9240 * Access: Index 9241 */ 9242 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9243 9244 /* reg_mfsl_tach_min 9245 * Tachometer minimum value (minimum RPM). 9246 * Access: RW 9247 */ 9248 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9249 9250 /* reg_mfsl_tach_max 9251 * Tachometer maximum value (maximum RPM). 9252 * Access: RW 9253 */ 9254 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9255 9256 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9257 u16 tach_min, u16 tach_max) 9258 { 9259 MLXSW_REG_ZERO(mfsl, payload); 9260 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9261 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9262 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9263 } 9264 9265 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9266 u16 *p_tach_min, u16 *p_tach_max) 9267 { 9268 if (p_tach_min) 9269 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9270 9271 if (p_tach_max) 9272 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9273 } 9274 9275 /* FORE - Fan Out of Range Event Register 9276 * -------------------------------------- 9277 * This register reports the status of the controlled fans compared to the 9278 * range defined by the MFSL register. 9279 */ 9280 #define MLXSW_REG_FORE_ID 0x9007 9281 #define MLXSW_REG_FORE_LEN 0x0C 9282 9283 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9284 9285 /* fan_under_limit 9286 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9287 * to a single tachometer and indicates the specific tachometer reading is 9288 * below the threshold. 9289 * Access: RO 9290 */ 9291 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9292 9293 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9294 bool *fault) 9295 { 9296 u16 limit; 9297 9298 if (fault) { 9299 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9300 *fault = limit & BIT(tacho); 9301 } 9302 } 9303 9304 /* MTCAP - Management Temperature Capabilities 9305 * ------------------------------------------- 9306 * This register exposes the capabilities of the device and 9307 * system temperature sensing. 9308 */ 9309 #define MLXSW_REG_MTCAP_ID 0x9009 9310 #define MLXSW_REG_MTCAP_LEN 0x08 9311 9312 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9313 9314 /* reg_mtcap_sensor_count 9315 * Number of sensors supported by the device. 9316 * This includes the QSFP module sensors (if exists in the QSFP module). 9317 * Access: RO 9318 */ 9319 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9320 9321 /* MTMP - Management Temperature 9322 * ----------------------------- 9323 * This register controls the settings of the temperature measurements 9324 * and enables reading the temperature measurements. Note that temperature 9325 * is in 0.125 degrees Celsius. 9326 */ 9327 #define MLXSW_REG_MTMP_ID 0x900A 9328 #define MLXSW_REG_MTMP_LEN 0x20 9329 9330 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9331 9332 /* reg_mtmp_slot_index 9333 * Slot index (0: Main board). 9334 * Access: Index 9335 */ 9336 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9337 9338 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9339 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9340 /* reg_mtmp_sensor_index 9341 * Sensors index to access. 9342 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9343 * (module 0 is mapped to sensor_index 64). 9344 * Access: Index 9345 */ 9346 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9347 9348 /* Convert to milli degrees Celsius */ 9349 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9350 ((v_) >= 0) ? ((v_) * 125) : \ 9351 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9352 * 125)); }) 9353 9354 /* reg_mtmp_max_operational_temperature 9355 * The highest temperature in the nominal operational range. Reading is in 9356 * 0.125 Celsius degrees units. 9357 * In case of module this is SFF critical temperature threshold. 9358 * Access: RO 9359 */ 9360 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9361 9362 /* reg_mtmp_temperature 9363 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9364 * degrees units. 9365 * Access: RO 9366 */ 9367 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9368 9369 /* reg_mtmp_mte 9370 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9371 * Access: RW 9372 */ 9373 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9374 9375 /* reg_mtmp_mtr 9376 * Max Temperature Reset - clears the value of the max temperature register. 9377 * Access: WO 9378 */ 9379 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9380 9381 /* reg_mtmp_max_temperature 9382 * The highest measured temperature from the sensor. 9383 * When the bit mte is cleared, the field max_temperature is reserved. 9384 * Access: RO 9385 */ 9386 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9387 9388 /* reg_mtmp_tee 9389 * Temperature Event Enable. 9390 * 0 - Do not generate event 9391 * 1 - Generate event 9392 * 2 - Generate single event 9393 * Access: RW 9394 */ 9395 9396 enum mlxsw_reg_mtmp_tee { 9397 MLXSW_REG_MTMP_TEE_NO_EVENT, 9398 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9399 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9400 }; 9401 9402 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9403 9404 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9405 9406 /* reg_mtmp_temperature_threshold_hi 9407 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9408 * Access: RW 9409 */ 9410 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9411 9412 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9413 /* reg_mtmp_temperature_threshold_lo 9414 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9415 * Access: RW 9416 */ 9417 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9418 9419 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9420 9421 /* reg_mtmp_sensor_name 9422 * Sensor Name 9423 * Access: RO 9424 */ 9425 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9426 9427 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9428 u16 sensor_index, bool max_temp_enable, 9429 bool max_temp_reset) 9430 { 9431 MLXSW_REG_ZERO(mtmp, payload); 9432 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9433 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9434 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9435 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9436 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9437 MLXSW_REG_MTMP_THRESH_HI); 9438 } 9439 9440 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9441 int *p_max_temp, int *p_temp_hi, 9442 int *p_max_oper_temp, 9443 char *sensor_name) 9444 { 9445 s16 temp; 9446 9447 if (p_temp) { 9448 temp = mlxsw_reg_mtmp_temperature_get(payload); 9449 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9450 } 9451 if (p_max_temp) { 9452 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9453 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9454 } 9455 if (p_temp_hi) { 9456 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9457 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9458 } 9459 if (p_max_oper_temp) { 9460 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9461 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9462 } 9463 if (sensor_name) 9464 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9465 } 9466 9467 /* MTWE - Management Temperature Warning Event 9468 * ------------------------------------------- 9469 * This register is used for over temperature warning. 9470 */ 9471 #define MLXSW_REG_MTWE_ID 0x900B 9472 #define MLXSW_REG_MTWE_LEN 0x10 9473 9474 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9475 9476 /* reg_mtwe_sensor_warning 9477 * Bit vector indicating which of the sensor reading is above threshold. 9478 * Address 00h bit31 is sensor_warning[127]. 9479 * Address 0Ch bit0 is sensor_warning[0]. 9480 * Access: RO 9481 */ 9482 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9483 9484 /* MTBR - Management Temperature Bulk Register 9485 * ------------------------------------------- 9486 * This register is used for bulk temperature reading. 9487 */ 9488 #define MLXSW_REG_MTBR_ID 0x900F 9489 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9490 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9491 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9492 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9493 MLXSW_REG_MTBR_REC_LEN * \ 9494 MLXSW_REG_MTBR_REC_MAX_COUNT) 9495 9496 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9497 9498 /* reg_mtbr_slot_index 9499 * Slot index (0: Main board). 9500 * Access: Index 9501 */ 9502 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9503 9504 /* reg_mtbr_base_sensor_index 9505 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9506 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9507 * Access: Index 9508 */ 9509 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9510 9511 /* reg_mtbr_num_rec 9512 * Request: Number of records to read 9513 * Response: Number of records read 9514 * See above description for more details. 9515 * Range 1..255 9516 * Access: RW 9517 */ 9518 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9519 9520 /* reg_mtbr_rec_max_temp 9521 * The highest measured temperature from the sensor. 9522 * When the bit mte is cleared, the field max_temperature is reserved. 9523 * Access: RO 9524 */ 9525 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9526 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9527 9528 /* reg_mtbr_rec_temp 9529 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9530 * degrees units. 9531 * Access: RO 9532 */ 9533 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9534 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9535 9536 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9537 u16 base_sensor_index, u8 num_rec) 9538 { 9539 MLXSW_REG_ZERO(mtbr, payload); 9540 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9541 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9542 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9543 } 9544 9545 /* Error codes from temperatute reading */ 9546 enum mlxsw_reg_mtbr_temp_status { 9547 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9548 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9549 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9550 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9551 }; 9552 9553 /* Base index for reading modules temperature */ 9554 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9555 9556 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9557 u16 *p_temp, u16 *p_max_temp) 9558 { 9559 if (p_temp) 9560 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9561 if (p_max_temp) 9562 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9563 } 9564 9565 /* MCIA - Management Cable Info Access 9566 * ----------------------------------- 9567 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9568 */ 9569 9570 #define MLXSW_REG_MCIA_ID 0x9014 9571 #define MLXSW_REG_MCIA_LEN 0x40 9572 9573 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9574 9575 /* reg_mcia_l 9576 * Lock bit. Setting this bit will lock the access to the specific 9577 * cable. Used for updating a full page in a cable EPROM. Any access 9578 * other then subsequence writes will fail while the port is locked. 9579 * Access: RW 9580 */ 9581 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9582 9583 /* reg_mcia_module 9584 * Module number. 9585 * Access: Index 9586 */ 9587 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9588 9589 /* reg_mcia_slot_index 9590 * Slot index (0: Main board) 9591 * Access: Index 9592 */ 9593 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9594 9595 enum { 9596 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9597 /* No response from module's EEPROM. */ 9598 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9599 /* Module type not supported by the device. */ 9600 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9601 /* No module present indication. */ 9602 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9603 /* Error occurred while trying to access module's EEPROM using I2C. */ 9604 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9605 /* Module is disabled. */ 9606 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9607 }; 9608 9609 /* reg_mcia_status 9610 * Module status. 9611 * Access: RO 9612 */ 9613 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9614 9615 /* reg_mcia_i2c_device_address 9616 * I2C device address. 9617 * Access: RW 9618 */ 9619 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9620 9621 /* reg_mcia_page_number 9622 * Page number. 9623 * Access: RW 9624 */ 9625 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9626 9627 /* reg_mcia_device_address 9628 * Device address. 9629 * Access: RW 9630 */ 9631 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9632 9633 /* reg_mcia_bank_number 9634 * Bank number. 9635 * Access: Index 9636 */ 9637 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9638 9639 /* reg_mcia_size 9640 * Number of bytes to read/write (up to 48 bytes). 9641 * Access: RW 9642 */ 9643 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9644 9645 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9646 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9647 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9648 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9649 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9650 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9651 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9652 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9653 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9654 #define MLXSW_REG_MCIA_PAGE0_LO 0 9655 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9656 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9657 9658 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9659 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9660 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9661 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9662 }; 9663 9664 enum mlxsw_reg_mcia_eeprom_module_info_id { 9665 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9666 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9667 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9668 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9669 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9670 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9671 }; 9672 9673 enum mlxsw_reg_mcia_eeprom_module_info { 9674 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9675 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9676 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9677 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9678 }; 9679 9680 /* reg_mcia_eeprom 9681 * Bytes to read/write. 9682 * Access: RW 9683 */ 9684 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9685 9686 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9687 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9688 * on offset 384 through 511, page 3 - on offset 512 through 639. 9689 */ 9690 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9691 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9692 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9693 9694 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9695 u8 lock, u8 page_number, 9696 u16 device_addr, u8 size, 9697 u8 i2c_device_addr) 9698 { 9699 MLXSW_REG_ZERO(mcia, payload); 9700 mlxsw_reg_mcia_slot_set(payload, slot_index); 9701 mlxsw_reg_mcia_module_set(payload, module); 9702 mlxsw_reg_mcia_l_set(payload, lock); 9703 mlxsw_reg_mcia_page_number_set(payload, page_number); 9704 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9705 mlxsw_reg_mcia_size_set(payload, size); 9706 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9707 } 9708 9709 /* MPAT - Monitoring Port Analyzer Table 9710 * ------------------------------------- 9711 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9712 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9713 */ 9714 #define MLXSW_REG_MPAT_ID 0x901A 9715 #define MLXSW_REG_MPAT_LEN 0x78 9716 9717 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9718 9719 /* reg_mpat_pa_id 9720 * Port Analyzer ID. 9721 * Access: Index 9722 */ 9723 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9724 9725 /* reg_mpat_session_id 9726 * Mirror Session ID. 9727 * Used for MIRROR_SESSION<i> trap. 9728 * Access: RW 9729 */ 9730 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9731 9732 /* reg_mpat_system_port 9733 * A unique port identifier for the final destination of the packet. 9734 * Access: RW 9735 */ 9736 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9737 9738 /* reg_mpat_e 9739 * Enable. Indicating the Port Analyzer is enabled. 9740 * Access: RW 9741 */ 9742 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9743 9744 /* reg_mpat_qos 9745 * Quality Of Service Mode. 9746 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9747 * PCP, DEI, DSCP or VL) are configured. 9748 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9749 * same as in the original packet that has triggered the mirroring. For 9750 * SPAN also the pcp,dei are maintained. 9751 * Access: RW 9752 */ 9753 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9754 9755 /* reg_mpat_be 9756 * Best effort mode. Indicates mirroring traffic should not cause packet 9757 * drop or back pressure, but will discard the mirrored packets. Mirrored 9758 * packets will be forwarded on a best effort manner. 9759 * 0: Do not discard mirrored packets 9760 * 1: Discard mirrored packets if causing congestion 9761 * Access: RW 9762 */ 9763 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9764 9765 enum mlxsw_reg_mpat_span_type { 9766 /* Local SPAN Ethernet. 9767 * The original packet is not encapsulated. 9768 */ 9769 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9770 9771 /* Remote SPAN Ethernet VLAN. 9772 * The packet is forwarded to the monitoring port on the monitoring 9773 * VLAN. 9774 */ 9775 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9776 9777 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9778 * The packet is encapsulated with GRE header. 9779 */ 9780 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9781 }; 9782 9783 /* reg_mpat_span_type 9784 * SPAN type. 9785 * Access: RW 9786 */ 9787 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9788 9789 /* reg_mpat_pide 9790 * Policer enable. 9791 * Access: RW 9792 */ 9793 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9794 9795 /* reg_mpat_pid 9796 * Policer ID. 9797 * Access: RW 9798 */ 9799 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9800 9801 /* Remote SPAN - Ethernet VLAN 9802 * - - - - - - - - - - - - - - 9803 */ 9804 9805 /* reg_mpat_eth_rspan_vid 9806 * Encapsulation header VLAN ID. 9807 * Access: RW 9808 */ 9809 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9810 9811 /* Encapsulated Remote SPAN - Ethernet L2 9812 * - - - - - - - - - - - - - - - - - - - 9813 */ 9814 9815 enum mlxsw_reg_mpat_eth_rspan_version { 9816 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9817 }; 9818 9819 /* reg_mpat_eth_rspan_version 9820 * RSPAN mirror header version. 9821 * Access: RW 9822 */ 9823 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9824 9825 /* reg_mpat_eth_rspan_mac 9826 * Destination MAC address. 9827 * Access: RW 9828 */ 9829 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9830 9831 /* reg_mpat_eth_rspan_tp 9832 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9833 * Access: RW 9834 */ 9835 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9836 9837 /* Encapsulated Remote SPAN - Ethernet L3 9838 * - - - - - - - - - - - - - - - - - - - 9839 */ 9840 9841 enum mlxsw_reg_mpat_eth_rspan_protocol { 9842 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9843 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9844 }; 9845 9846 /* reg_mpat_eth_rspan_protocol 9847 * SPAN encapsulation protocol. 9848 * Access: RW 9849 */ 9850 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9851 9852 /* reg_mpat_eth_rspan_ttl 9853 * Encapsulation header Time-to-Live/HopLimit. 9854 * Access: RW 9855 */ 9856 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9857 9858 /* reg_mpat_eth_rspan_smac 9859 * Source MAC address 9860 * Access: RW 9861 */ 9862 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9863 9864 /* reg_mpat_eth_rspan_dip* 9865 * Destination IP address. The IP version is configured by protocol. 9866 * Access: RW 9867 */ 9868 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9869 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9870 9871 /* reg_mpat_eth_rspan_sip* 9872 * Source IP address. The IP version is configured by protocol. 9873 * Access: RW 9874 */ 9875 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9876 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9877 9878 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9879 u16 system_port, bool e, 9880 enum mlxsw_reg_mpat_span_type span_type) 9881 { 9882 MLXSW_REG_ZERO(mpat, payload); 9883 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9884 mlxsw_reg_mpat_system_port_set(payload, system_port); 9885 mlxsw_reg_mpat_e_set(payload, e); 9886 mlxsw_reg_mpat_qos_set(payload, 1); 9887 mlxsw_reg_mpat_be_set(payload, 1); 9888 mlxsw_reg_mpat_span_type_set(payload, span_type); 9889 } 9890 9891 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9892 { 9893 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9894 } 9895 9896 static inline void 9897 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9898 enum mlxsw_reg_mpat_eth_rspan_version version, 9899 const char *mac, 9900 bool tp) 9901 { 9902 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9903 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9904 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9905 } 9906 9907 static inline void 9908 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9909 const char *smac, 9910 u32 sip, u32 dip) 9911 { 9912 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9913 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9914 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9915 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9916 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9917 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9918 } 9919 9920 static inline void 9921 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9922 const char *smac, 9923 struct in6_addr sip, struct in6_addr dip) 9924 { 9925 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9926 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9927 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9928 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9929 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9930 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9931 } 9932 9933 /* MPAR - Monitoring Port Analyzer Register 9934 * ---------------------------------------- 9935 * MPAR register is used to query and configure the port analyzer port mirroring 9936 * properties. 9937 */ 9938 #define MLXSW_REG_MPAR_ID 0x901B 9939 #define MLXSW_REG_MPAR_LEN 0x0C 9940 9941 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9942 9943 /* reg_mpar_local_port 9944 * The local port to mirror the packets from. 9945 * Access: Index 9946 */ 9947 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 9948 9949 enum mlxsw_reg_mpar_i_e { 9950 MLXSW_REG_MPAR_TYPE_EGRESS, 9951 MLXSW_REG_MPAR_TYPE_INGRESS, 9952 }; 9953 9954 /* reg_mpar_i_e 9955 * Ingress/Egress 9956 * Access: Index 9957 */ 9958 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9959 9960 /* reg_mpar_enable 9961 * Enable mirroring 9962 * By default, port mirroring is disabled for all ports. 9963 * Access: RW 9964 */ 9965 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9966 9967 /* reg_mpar_pa_id 9968 * Port Analyzer ID. 9969 * Access: RW 9970 */ 9971 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9972 9973 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 9974 9975 /* reg_mpar_probability_rate 9976 * Sampling rate. 9977 * Valid values are: 1 to 3.5*10^9 9978 * Value of 1 means "sample all". Default is 1. 9979 * Reserved when Spectrum-1. 9980 * Access: RW 9981 */ 9982 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 9983 9984 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 9985 enum mlxsw_reg_mpar_i_e i_e, 9986 bool enable, u8 pa_id, 9987 u32 probability_rate) 9988 { 9989 MLXSW_REG_ZERO(mpar, payload); 9990 mlxsw_reg_mpar_local_port_set(payload, local_port); 9991 mlxsw_reg_mpar_enable_set(payload, enable); 9992 mlxsw_reg_mpar_i_e_set(payload, i_e); 9993 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9994 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 9995 } 9996 9997 /* MGIR - Management General Information Register 9998 * ---------------------------------------------- 9999 * MGIR register allows software to query the hardware and firmware general 10000 * information. 10001 */ 10002 #define MLXSW_REG_MGIR_ID 0x9020 10003 #define MLXSW_REG_MGIR_LEN 0x9C 10004 10005 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10006 10007 /* reg_mgir_hw_info_device_hw_revision 10008 * Access: RO 10009 */ 10010 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10011 10012 /* reg_mgir_fw_info_latency_tlv 10013 * When set, latency-TLV is supported. 10014 * Access: RO 10015 */ 10016 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); 10017 10018 /* reg_mgir_fw_info_string_tlv 10019 * When set, string-TLV is supported. 10020 * Access: RO 10021 */ 10022 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); 10023 10024 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10025 10026 /* reg_mgir_fw_info_psid 10027 * PSID (ASCII string). 10028 * Access: RO 10029 */ 10030 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10031 10032 /* reg_mgir_fw_info_extended_major 10033 * Access: RO 10034 */ 10035 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10036 10037 /* reg_mgir_fw_info_extended_minor 10038 * Access: RO 10039 */ 10040 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10041 10042 /* reg_mgir_fw_info_extended_sub_minor 10043 * Access: RO 10044 */ 10045 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10046 10047 static inline void mlxsw_reg_mgir_pack(char *payload) 10048 { 10049 MLXSW_REG_ZERO(mgir, payload); 10050 } 10051 10052 static inline void 10053 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10054 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10055 { 10056 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10057 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10058 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10059 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10060 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10061 } 10062 10063 /* MRSR - Management Reset and Shutdown Register 10064 * --------------------------------------------- 10065 * MRSR register is used to reset or shutdown the switch or 10066 * the entire system (when applicable). 10067 */ 10068 #define MLXSW_REG_MRSR_ID 0x9023 10069 #define MLXSW_REG_MRSR_LEN 0x08 10070 10071 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10072 10073 /* reg_mrsr_command 10074 * Reset/shutdown command 10075 * 0 - do nothing 10076 * 1 - software reset 10077 * Access: WO 10078 */ 10079 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10080 10081 static inline void mlxsw_reg_mrsr_pack(char *payload) 10082 { 10083 MLXSW_REG_ZERO(mrsr, payload); 10084 mlxsw_reg_mrsr_command_set(payload, 1); 10085 } 10086 10087 /* MLCR - Management LED Control Register 10088 * -------------------------------------- 10089 * Controls the system LEDs. 10090 */ 10091 #define MLXSW_REG_MLCR_ID 0x902B 10092 #define MLXSW_REG_MLCR_LEN 0x0C 10093 10094 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10095 10096 /* reg_mlcr_local_port 10097 * Local port number. 10098 * Access: RW 10099 */ 10100 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10101 10102 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10103 10104 /* reg_mlcr_beacon_duration 10105 * Duration of the beacon to be active, in seconds. 10106 * 0x0 - Will turn off the beacon. 10107 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10108 * Access: RW 10109 */ 10110 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10111 10112 /* reg_mlcr_beacon_remain 10113 * Remaining duration of the beacon, in seconds. 10114 * 0xFFFF indicates an infinite amount of time. 10115 * Access: RO 10116 */ 10117 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10118 10119 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10120 bool active) 10121 { 10122 MLXSW_REG_ZERO(mlcr, payload); 10123 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10124 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10125 MLXSW_REG_MLCR_DURATION_MAX : 0); 10126 } 10127 10128 /* MCION - Management Cable IO and Notifications Register 10129 * ------------------------------------------------------ 10130 * The MCION register is used to query transceiver modules' IO pins and other 10131 * notifications. 10132 */ 10133 #define MLXSW_REG_MCION_ID 0x9052 10134 #define MLXSW_REG_MCION_LEN 0x18 10135 10136 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10137 10138 /* reg_mcion_module 10139 * Module number. 10140 * Access: Index 10141 */ 10142 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10143 10144 /* reg_mcion_slot_index 10145 * Slot index. 10146 * Access: Index 10147 */ 10148 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10149 10150 enum { 10151 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10152 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10153 }; 10154 10155 /* reg_mcion_module_status_bits 10156 * Module IO status as defined by SFF. 10157 * Access: RO 10158 */ 10159 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10160 10161 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10162 { 10163 MLXSW_REG_ZERO(mcion, payload); 10164 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10165 mlxsw_reg_mcion_module_set(payload, module); 10166 } 10167 10168 /* MTPPS - Management Pulse Per Second Register 10169 * -------------------------------------------- 10170 * This register provides the device PPS capabilities, configure the PPS in and 10171 * out modules and holds the PPS in time stamp. 10172 */ 10173 #define MLXSW_REG_MTPPS_ID 0x9053 10174 #define MLXSW_REG_MTPPS_LEN 0x3C 10175 10176 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10177 10178 /* reg_mtpps_enable 10179 * Enables the PPS functionality the specific pin. 10180 * A boolean variable. 10181 * Access: RW 10182 */ 10183 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10184 10185 enum mlxsw_reg_mtpps_pin_mode { 10186 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10187 }; 10188 10189 /* reg_mtpps_pin_mode 10190 * Pin mode to be used. The mode must comply with the supported modes of the 10191 * requested pin. 10192 * Access: RW 10193 */ 10194 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10195 10196 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10197 10198 /* reg_mtpps_pin 10199 * Pin to be configured or queried out of the supported pins. 10200 * Access: Index 10201 */ 10202 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10203 10204 /* reg_mtpps_time_stamp 10205 * When pin_mode = pps_in, the latched device time when it was triggered from 10206 * the external GPIO pin. 10207 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10208 * time to generate next output signal. 10209 * Time is in units of device clock. 10210 * Access: RW 10211 */ 10212 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10213 10214 static inline void 10215 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10216 { 10217 MLXSW_REG_ZERO(mtpps, payload); 10218 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10219 mlxsw_reg_mtpps_pin_mode_set(payload, 10220 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10221 mlxsw_reg_mtpps_enable_set(payload, true); 10222 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10223 } 10224 10225 /* MTUTC - Management UTC Register 10226 * ------------------------------- 10227 * Configures the HW UTC counter. 10228 */ 10229 #define MLXSW_REG_MTUTC_ID 0x9055 10230 #define MLXSW_REG_MTUTC_LEN 0x1C 10231 10232 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10233 10234 enum mlxsw_reg_mtutc_operation { 10235 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10236 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10237 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10238 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10239 }; 10240 10241 /* reg_mtutc_operation 10242 * Operation. 10243 * Access: OP 10244 */ 10245 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10246 10247 /* reg_mtutc_freq_adjustment 10248 * Frequency adjustment: Every PPS the HW frequency will be 10249 * adjusted by this value. Units of HW clock, where HW counts 10250 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10251 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10252 * frequency. 10253 * Access: RW 10254 */ 10255 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10256 10257 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10258 10259 /* reg_mtutc_utc_sec 10260 * UTC seconds. 10261 * Access: WO 10262 */ 10263 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10264 10265 /* reg_mtutc_utc_nsec 10266 * UTC nSecs. 10267 * Range 0..(10^9-1) 10268 * Updated when operation is SET_TIME_IMMEDIATE. 10269 * Reserved on Spectrum-1. 10270 * Access: WO 10271 */ 10272 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10273 10274 /* reg_mtutc_time_adjustment 10275 * Time adjustment. 10276 * Units of nSec. 10277 * Range is from -32768 to +32767. 10278 * Updated when operation is ADJUST_TIME. 10279 * Reserved on Spectrum-1. 10280 * Access: WO 10281 */ 10282 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10283 10284 static inline void 10285 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10286 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10287 { 10288 MLXSW_REG_ZERO(mtutc, payload); 10289 mlxsw_reg_mtutc_operation_set(payload, oper); 10290 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10291 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10292 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10293 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10294 } 10295 10296 /* MCQI - Management Component Query Information 10297 * --------------------------------------------- 10298 * This register allows querying information about firmware components. 10299 */ 10300 #define MLXSW_REG_MCQI_ID 0x9061 10301 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10302 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10303 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10304 10305 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10306 10307 /* reg_mcqi_component_index 10308 * Index of the accessed component. 10309 * Access: Index 10310 */ 10311 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10312 10313 enum mlxfw_reg_mcqi_info_type { 10314 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10315 }; 10316 10317 /* reg_mcqi_info_type 10318 * Component properties set. 10319 * Access: RW 10320 */ 10321 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10322 10323 /* reg_mcqi_offset 10324 * The requested/returned data offset from the section start, given in bytes. 10325 * Must be DWORD aligned. 10326 * Access: RW 10327 */ 10328 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10329 10330 /* reg_mcqi_data_size 10331 * The requested/returned data size, given in bytes. If data_size is not DWORD 10332 * aligned, the last bytes are zero padded. 10333 * Access: RW 10334 */ 10335 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10336 10337 /* reg_mcqi_cap_max_component_size 10338 * Maximum size for this component, given in bytes. 10339 * Access: RO 10340 */ 10341 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10342 10343 /* reg_mcqi_cap_log_mcda_word_size 10344 * Log 2 of the access word size in bytes. Read and write access must be aligned 10345 * to the word size. Write access must be done for an integer number of words. 10346 * Access: RO 10347 */ 10348 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10349 10350 /* reg_mcqi_cap_mcda_max_write_size 10351 * Maximal write size for MCDA register 10352 * Access: RO 10353 */ 10354 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10355 10356 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10357 { 10358 MLXSW_REG_ZERO(mcqi, payload); 10359 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10360 mlxsw_reg_mcqi_info_type_set(payload, 10361 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10362 mlxsw_reg_mcqi_offset_set(payload, 0); 10363 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10364 } 10365 10366 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10367 u32 *p_cap_max_component_size, 10368 u8 *p_cap_log_mcda_word_size, 10369 u16 *p_cap_mcda_max_write_size) 10370 { 10371 *p_cap_max_component_size = 10372 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10373 *p_cap_log_mcda_word_size = 10374 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10375 *p_cap_mcda_max_write_size = 10376 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10377 } 10378 10379 /* MCC - Management Component Control 10380 * ---------------------------------- 10381 * Controls the firmware component and updates the FSM. 10382 */ 10383 #define MLXSW_REG_MCC_ID 0x9062 10384 #define MLXSW_REG_MCC_LEN 0x1C 10385 10386 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10387 10388 enum mlxsw_reg_mcc_instruction { 10389 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10390 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10391 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10392 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10393 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10394 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10395 }; 10396 10397 /* reg_mcc_instruction 10398 * Command to be executed by the FSM. 10399 * Applicable for write operation only. 10400 * Access: RW 10401 */ 10402 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10403 10404 /* reg_mcc_component_index 10405 * Index of the accessed component. Applicable only for commands that 10406 * refer to components. Otherwise, this field is reserved. 10407 * Access: Index 10408 */ 10409 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10410 10411 /* reg_mcc_update_handle 10412 * Token representing the current flow executed by the FSM. 10413 * Access: WO 10414 */ 10415 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10416 10417 /* reg_mcc_error_code 10418 * Indicates the successful completion of the instruction, or the reason it 10419 * failed 10420 * Access: RO 10421 */ 10422 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10423 10424 /* reg_mcc_control_state 10425 * Current FSM state 10426 * Access: RO 10427 */ 10428 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10429 10430 /* reg_mcc_component_size 10431 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10432 * the size may shorten the update time. Value 0x0 means that size is 10433 * unspecified. 10434 * Access: WO 10435 */ 10436 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10437 10438 static inline void mlxsw_reg_mcc_pack(char *payload, 10439 enum mlxsw_reg_mcc_instruction instr, 10440 u16 component_index, u32 update_handle, 10441 u32 component_size) 10442 { 10443 MLXSW_REG_ZERO(mcc, payload); 10444 mlxsw_reg_mcc_instruction_set(payload, instr); 10445 mlxsw_reg_mcc_component_index_set(payload, component_index); 10446 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10447 mlxsw_reg_mcc_component_size_set(payload, component_size); 10448 } 10449 10450 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10451 u8 *p_error_code, u8 *p_control_state) 10452 { 10453 if (p_update_handle) 10454 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10455 if (p_error_code) 10456 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10457 if (p_control_state) 10458 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10459 } 10460 10461 /* MCDA - Management Component Data Access 10462 * --------------------------------------- 10463 * This register allows reading and writing a firmware component. 10464 */ 10465 #define MLXSW_REG_MCDA_ID 0x9063 10466 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10467 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10468 #define MLXSW_REG_MCDA_LEN \ 10469 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10470 10471 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10472 10473 /* reg_mcda_update_handle 10474 * Token representing the current flow executed by the FSM. 10475 * Access: RW 10476 */ 10477 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10478 10479 /* reg_mcda_offset 10480 * Offset of accessed address relative to component start. Accesses must be in 10481 * accordance to log_mcda_word_size in MCQI reg. 10482 * Access: RW 10483 */ 10484 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10485 10486 /* reg_mcda_size 10487 * Size of the data accessed, given in bytes. 10488 * Access: RW 10489 */ 10490 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10491 10492 /* reg_mcda_data 10493 * Data block accessed. 10494 * Access: RW 10495 */ 10496 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10497 10498 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10499 u32 offset, u16 size, u8 *data) 10500 { 10501 int i; 10502 10503 MLXSW_REG_ZERO(mcda, payload); 10504 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10505 mlxsw_reg_mcda_offset_set(payload, offset); 10506 mlxsw_reg_mcda_size_set(payload, size); 10507 10508 for (i = 0; i < size / 4; i++) 10509 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10510 } 10511 10512 /* MPSC - Monitoring Packet Sampling Configuration Register 10513 * -------------------------------------------------------- 10514 * MPSC Register is used to configure the Packet Sampling mechanism. 10515 */ 10516 #define MLXSW_REG_MPSC_ID 0x9080 10517 #define MLXSW_REG_MPSC_LEN 0x1C 10518 10519 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10520 10521 /* reg_mpsc_local_port 10522 * Local port number 10523 * Not supported for CPU port 10524 * Access: Index 10525 */ 10526 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10527 10528 /* reg_mpsc_e 10529 * Enable sampling on port local_port 10530 * Access: RW 10531 */ 10532 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10533 10534 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10535 10536 /* reg_mpsc_rate 10537 * Sampling rate = 1 out of rate packets (with randomization around 10538 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10539 * Access: RW 10540 */ 10541 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10542 10543 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10544 u32 rate) 10545 { 10546 MLXSW_REG_ZERO(mpsc, payload); 10547 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10548 mlxsw_reg_mpsc_e_set(payload, e); 10549 mlxsw_reg_mpsc_rate_set(payload, rate); 10550 } 10551 10552 /* MGPC - Monitoring General Purpose Counter Set Register 10553 * The MGPC register retrieves and sets the General Purpose Counter Set. 10554 */ 10555 #define MLXSW_REG_MGPC_ID 0x9081 10556 #define MLXSW_REG_MGPC_LEN 0x18 10557 10558 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10559 10560 /* reg_mgpc_counter_set_type 10561 * Counter set type. 10562 * Access: OP 10563 */ 10564 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10565 10566 /* reg_mgpc_counter_index 10567 * Counter index. 10568 * Access: Index 10569 */ 10570 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10571 10572 enum mlxsw_reg_mgpc_opcode { 10573 /* Nop */ 10574 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10575 /* Clear counters */ 10576 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10577 }; 10578 10579 /* reg_mgpc_opcode 10580 * Opcode. 10581 * Access: OP 10582 */ 10583 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10584 10585 /* reg_mgpc_byte_counter 10586 * Byte counter value. 10587 * Access: RW 10588 */ 10589 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10590 10591 /* reg_mgpc_packet_counter 10592 * Packet counter value. 10593 * Access: RW 10594 */ 10595 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10596 10597 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10598 enum mlxsw_reg_mgpc_opcode opcode, 10599 enum mlxsw_reg_flow_counter_set_type set_type) 10600 { 10601 MLXSW_REG_ZERO(mgpc, payload); 10602 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10603 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10604 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10605 } 10606 10607 /* MPRS - Monitoring Parsing State Register 10608 * ---------------------------------------- 10609 * The MPRS register is used for setting up the parsing for hash, 10610 * policy-engine and routing. 10611 */ 10612 #define MLXSW_REG_MPRS_ID 0x9083 10613 #define MLXSW_REG_MPRS_LEN 0x14 10614 10615 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10616 10617 /* reg_mprs_parsing_depth 10618 * Minimum parsing depth. 10619 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10620 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10621 * Access: RW 10622 */ 10623 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10624 10625 /* reg_mprs_parsing_en 10626 * Parsing enable. 10627 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10628 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10629 * Access: RW 10630 */ 10631 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10632 10633 /* reg_mprs_vxlan_udp_dport 10634 * VxLAN UDP destination port. 10635 * Used for identifying VxLAN packets and for dport field in 10636 * encapsulation. Default is 4789. 10637 * Access: RW 10638 */ 10639 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10640 10641 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10642 u16 vxlan_udp_dport) 10643 { 10644 MLXSW_REG_ZERO(mprs, payload); 10645 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10646 mlxsw_reg_mprs_parsing_en_set(payload, true); 10647 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10648 } 10649 10650 /* MOGCR - Monitoring Global Configuration Register 10651 * ------------------------------------------------ 10652 */ 10653 #define MLXSW_REG_MOGCR_ID 0x9086 10654 #define MLXSW_REG_MOGCR_LEN 0x20 10655 10656 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10657 10658 /* reg_mogcr_ptp_iftc 10659 * PTP Ingress FIFO Trap Clear 10660 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10661 * to this value. Default 0. 10662 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10663 * Access: RW 10664 */ 10665 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10666 10667 /* reg_mogcr_ptp_eftc 10668 * PTP Egress FIFO Trap Clear 10669 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10670 * to this value. Default 0. 10671 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10672 * Access: RW 10673 */ 10674 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10675 10676 /* reg_mogcr_mirroring_pid_base 10677 * Base policer id for mirroring policers. 10678 * Must have an even value (e.g. 1000, not 1001). 10679 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10680 * Access: RW 10681 */ 10682 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10683 10684 /* MPAGR - Monitoring Port Analyzer Global Register 10685 * ------------------------------------------------ 10686 * This register is used for global port analyzer configurations. 10687 * Note: This register is not supported by current FW versions for Spectrum-1. 10688 */ 10689 #define MLXSW_REG_MPAGR_ID 0x9089 10690 #define MLXSW_REG_MPAGR_LEN 0x0C 10691 10692 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10693 10694 enum mlxsw_reg_mpagr_trigger { 10695 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10696 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10697 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10698 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10699 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10700 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10701 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10702 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10703 }; 10704 10705 /* reg_mpagr_trigger 10706 * Mirror trigger. 10707 * Access: Index 10708 */ 10709 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10710 10711 /* reg_mpagr_pa_id 10712 * Port analyzer ID. 10713 * Access: RW 10714 */ 10715 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10716 10717 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10718 10719 /* reg_mpagr_probability_rate 10720 * Sampling rate. 10721 * Valid values are: 1 to 3.5*10^9 10722 * Value of 1 means "sample all". Default is 1. 10723 * Access: RW 10724 */ 10725 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10726 10727 static inline void mlxsw_reg_mpagr_pack(char *payload, 10728 enum mlxsw_reg_mpagr_trigger trigger, 10729 u8 pa_id, u32 probability_rate) 10730 { 10731 MLXSW_REG_ZERO(mpagr, payload); 10732 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10733 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10734 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10735 } 10736 10737 /* MOMTE - Monitoring Mirror Trigger Enable Register 10738 * ------------------------------------------------- 10739 * This register is used to configure the mirror enable for different mirror 10740 * reasons. 10741 */ 10742 #define MLXSW_REG_MOMTE_ID 0x908D 10743 #define MLXSW_REG_MOMTE_LEN 0x10 10744 10745 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10746 10747 /* reg_momte_local_port 10748 * Local port number. 10749 * Access: Index 10750 */ 10751 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10752 10753 enum mlxsw_reg_momte_type { 10754 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10755 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10756 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10757 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10758 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10759 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10760 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10761 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10762 }; 10763 10764 /* reg_momte_type 10765 * Type of mirroring. 10766 * Access: Index 10767 */ 10768 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10769 10770 /* reg_momte_tclass_en 10771 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10772 * 0: disable (default) 10773 * 1: enable 10774 * Access: RW 10775 */ 10776 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10777 10778 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10779 enum mlxsw_reg_momte_type type) 10780 { 10781 MLXSW_REG_ZERO(momte, payload); 10782 mlxsw_reg_momte_local_port_set(payload, local_port); 10783 mlxsw_reg_momte_type_set(payload, type); 10784 } 10785 10786 /* MTPPPC - Time Precision Packet Port Configuration 10787 * ------------------------------------------------- 10788 * This register serves for configuration of which PTP messages should be 10789 * timestamped. This is a global configuration, despite the register name. 10790 * 10791 * Reserved when Spectrum-2. 10792 */ 10793 #define MLXSW_REG_MTPPPC_ID 0x9090 10794 #define MLXSW_REG_MTPPPC_LEN 0x28 10795 10796 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10797 10798 /* reg_mtpppc_ing_timestamp_message_type 10799 * Bitwise vector of PTP message types to timestamp at ingress. 10800 * MessageType field as defined by IEEE 1588 10801 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10802 * Default all 0 10803 * Access: RW 10804 */ 10805 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10806 10807 /* reg_mtpppc_egr_timestamp_message_type 10808 * Bitwise vector of PTP message types to timestamp at egress. 10809 * MessageType field as defined by IEEE 1588 10810 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10811 * Default all 0 10812 * Access: RW 10813 */ 10814 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10815 10816 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10817 { 10818 MLXSW_REG_ZERO(mtpppc, payload); 10819 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10820 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10821 } 10822 10823 /* MTPPTR - Time Precision Packet Timestamping Reading 10824 * --------------------------------------------------- 10825 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10826 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10827 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10828 * trapped. The sequence number is used to synchronize the timestamp FIFO 10829 * entries and the trapped packets. 10830 * Reserved when Spectrum-2. 10831 */ 10832 10833 #define MLXSW_REG_MTPPTR_ID 0x9091 10834 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10835 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10836 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10837 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10838 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10839 10840 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10841 10842 /* reg_mtpptr_local_port 10843 * Not supported for CPU port. 10844 * Access: Index 10845 */ 10846 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10847 10848 enum mlxsw_reg_mtpptr_dir { 10849 MLXSW_REG_MTPPTR_DIR_INGRESS, 10850 MLXSW_REG_MTPPTR_DIR_EGRESS, 10851 }; 10852 10853 /* reg_mtpptr_dir 10854 * Direction. 10855 * Access: Index 10856 */ 10857 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10858 10859 /* reg_mtpptr_clr 10860 * Clear the records. 10861 * Access: OP 10862 */ 10863 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10864 10865 /* reg_mtpptr_num_rec 10866 * Number of valid records in the response 10867 * Range 0.. cap_ptp_timestamp_fifo 10868 * Access: RO 10869 */ 10870 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10871 10872 /* reg_mtpptr_rec_message_type 10873 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10874 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10875 * Access: RO 10876 */ 10877 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10878 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10879 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10880 10881 /* reg_mtpptr_rec_domain_number 10882 * DomainNumber field as defined by IEEE 1588 10883 * Access: RO 10884 */ 10885 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10886 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10887 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10888 10889 /* reg_mtpptr_rec_sequence_id 10890 * SequenceId field as defined by IEEE 1588 10891 * Access: RO 10892 */ 10893 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10894 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10895 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10896 10897 /* reg_mtpptr_rec_timestamp_high 10898 * Timestamp of when the PTP packet has passed through the port Units of PLL 10899 * clock time. 10900 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10901 * Access: RO 10902 */ 10903 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10904 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10905 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10906 10907 /* reg_mtpptr_rec_timestamp_low 10908 * See rec_timestamp_high. 10909 * Access: RO 10910 */ 10911 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10912 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10913 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10914 10915 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10916 unsigned int rec, 10917 u8 *p_message_type, 10918 u8 *p_domain_number, 10919 u16 *p_sequence_id, 10920 u64 *p_timestamp) 10921 { 10922 u32 timestamp_high, timestamp_low; 10923 10924 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10925 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10926 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10927 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10928 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10929 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10930 } 10931 10932 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10933 * --------------------------------------------------------- 10934 * This register is used for configuring under which trap to deliver PTP 10935 * packets depending on type of the packet. 10936 */ 10937 #define MLXSW_REG_MTPTPT_ID 0x9092 10938 #define MLXSW_REG_MTPTPT_LEN 0x08 10939 10940 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10941 10942 enum mlxsw_reg_mtptpt_trap_id { 10943 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10944 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10945 }; 10946 10947 /* reg_mtptpt_trap_id 10948 * Trap id. 10949 * Access: Index 10950 */ 10951 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10952 10953 /* reg_mtptpt_message_type 10954 * Bitwise vector of PTP message types to trap. This is a necessary but 10955 * non-sufficient condition since need to enable also per port. See MTPPPC. 10956 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10957 * Bit0: Sync, Bit1: Delay_Req) 10958 */ 10959 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10960 10961 static inline void mlxsw_reg_mtptpt_pack(char *payload, 10962 enum mlxsw_reg_mtptpt_trap_id trap_id, 10963 u16 message_type) 10964 { 10965 MLXSW_REG_ZERO(mtptpt, payload); 10966 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10967 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10968 } 10969 10970 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 10971 * ------------------------------------------------------------------------- 10972 */ 10973 #define MLXSW_REG_MTPCPC_ID 0x9093 10974 #define MLXSW_REG_MTPCPC_LEN 0x2C 10975 10976 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 10977 10978 /* reg_mtpcpc_pport 10979 * Per port: 10980 * 0: config is global. When reading - the local_port is 1. 10981 * 1: config is per port. 10982 * Access: Index 10983 */ 10984 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 10985 10986 /* reg_mtpcpc_local_port 10987 * Local port number. 10988 * Supported to/from CPU port. 10989 * Reserved when pport = 0. 10990 * Access: Index 10991 */ 10992 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 10993 10994 /* reg_mtpcpc_ptp_trap_en 10995 * Enable PTP traps. 10996 * The trap_id is configured by MTPTPT. 10997 * Access: RW 10998 */ 10999 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 11000 11001 /* reg_mtpcpc_ing_correction_message_type 11002 * Bitwise vector of PTP message types to update correction-field at ingress. 11003 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11004 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11005 * Default all 0 11006 * Access: RW 11007 */ 11008 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 11009 11010 /* reg_mtpcpc_egr_correction_message_type 11011 * Bitwise vector of PTP message types to update correction-field at egress. 11012 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11013 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11014 * Default all 0 11015 * Access: RW 11016 */ 11017 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 11018 11019 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 11020 u16 local_port, bool ptp_trap_en, 11021 u16 ing, u16 egr) 11022 { 11023 MLXSW_REG_ZERO(mtpcpc, payload); 11024 mlxsw_reg_mtpcpc_pport_set(payload, pport); 11025 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 11026 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 11027 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 11028 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 11029 } 11030 11031 /* MFGD - Monitoring FW General Debug Register 11032 * ------------------------------------------- 11033 */ 11034 #define MLXSW_REG_MFGD_ID 0x90F0 11035 #define MLXSW_REG_MFGD_LEN 0x0C 11036 11037 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11038 11039 /* reg_mfgd_fw_fatal_event_mode 11040 * 0 - don't check FW fatal (default) 11041 * 1 - check FW fatal - enable MFDE trap 11042 * Access: RW 11043 */ 11044 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11045 11046 /* reg_mfgd_trigger_test 11047 * Access: WO 11048 */ 11049 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11050 11051 /* MGPIR - Management General Peripheral Information Register 11052 * ---------------------------------------------------------- 11053 * MGPIR register allows software to query the hardware and 11054 * firmware general information of peripheral entities. 11055 */ 11056 #define MLXSW_REG_MGPIR_ID 0x9100 11057 #define MLXSW_REG_MGPIR_LEN 0xA0 11058 11059 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11060 11061 enum mlxsw_reg_mgpir_device_type { 11062 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11063 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11064 }; 11065 11066 /* mgpir_slot_index 11067 * Slot index (0: Main board). 11068 * Access: Index 11069 */ 11070 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11071 11072 /* mgpir_device_type 11073 * Access: RO 11074 */ 11075 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11076 11077 /* mgpir_devices_per_flash 11078 * Number of devices of device_type per flash (can be shared by few devices). 11079 * Access: RO 11080 */ 11081 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11082 11083 /* mgpir_num_of_devices 11084 * Number of devices of device_type. 11085 * Access: RO 11086 */ 11087 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11088 11089 /* max_modules_per_slot 11090 * Maximum number of modules that can be connected per slot. 11091 * Access: RO 11092 */ 11093 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11094 11095 /* mgpir_num_of_slots 11096 * Number of slots in the system. 11097 * Access: RO 11098 */ 11099 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11100 11101 /* mgpir_num_of_modules 11102 * Number of modules. 11103 * Access: RO 11104 */ 11105 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11106 11107 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11108 { 11109 MLXSW_REG_ZERO(mgpir, payload); 11110 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11111 } 11112 11113 static inline void 11114 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11115 enum mlxsw_reg_mgpir_device_type *device_type, 11116 u8 *devices_per_flash, u8 *num_of_modules, 11117 u8 *num_of_slots) 11118 { 11119 if (num_of_devices) 11120 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11121 if (device_type) 11122 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11123 if (devices_per_flash) 11124 *devices_per_flash = 11125 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11126 if (num_of_modules) 11127 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11128 if (num_of_slots) 11129 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11130 } 11131 11132 /* MBCT - Management Binary Code Transfer Register 11133 * ----------------------------------------------- 11134 * This register allows to transfer binary codes from the host to 11135 * the management FW by transferring it by chunks of maximum 1KB. 11136 */ 11137 #define MLXSW_REG_MBCT_ID 0x9120 11138 #define MLXSW_REG_MBCT_LEN 0x420 11139 11140 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11141 11142 /* reg_mbct_slot_index 11143 * Slot index. 0 is reserved. 11144 * Access: Index 11145 */ 11146 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11147 11148 /* reg_mbct_data_size 11149 * Actual data field size in bytes for the current data transfer. 11150 * Access: WO 11151 */ 11152 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11153 11154 enum mlxsw_reg_mbct_op { 11155 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11156 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11157 MLXSW_REG_MBCT_OP_ACTIVATE, 11158 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11159 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11160 }; 11161 11162 /* reg_mbct_op 11163 * Access: WO 11164 */ 11165 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11166 11167 /* reg_mbct_last 11168 * Indicates that the current data field is the last chunk of the INI. 11169 * Access: WO 11170 */ 11171 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11172 11173 /* reg_mbct_oee 11174 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11175 * was executed and the fsm_state has changed. 11176 * Access: WO 11177 */ 11178 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11179 11180 enum mlxsw_reg_mbct_status { 11181 /* Partial data transfer completed successfully and ready for next 11182 * data transfer. 11183 */ 11184 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11185 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11186 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11187 /* Error - trying to erase INI while it being used. */ 11188 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11189 /* Last data transfer completed, applying magic pattern. */ 11190 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11191 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11192 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11193 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11194 }; 11195 11196 /* reg_mbct_status 11197 * Status. 11198 * Access: RO 11199 */ 11200 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11201 11202 enum mlxsw_reg_mbct_fsm_state { 11203 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11204 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11205 }; 11206 11207 /* reg_mbct_fsm_state 11208 * FSM state. 11209 * Access: RO 11210 */ 11211 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11212 11213 #define MLXSW_REG_MBCT_DATA_LEN 1024 11214 11215 /* reg_mbct_data 11216 * Up to 1KB of data. 11217 * Access: WO 11218 */ 11219 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11220 11221 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11222 enum mlxsw_reg_mbct_op op, bool oee) 11223 { 11224 MLXSW_REG_ZERO(mbct, payload); 11225 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11226 mlxsw_reg_mbct_op_set(payload, op); 11227 mlxsw_reg_mbct_oee_set(payload, oee); 11228 } 11229 11230 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11231 u16 data_size, bool last, 11232 const char *data) 11233 { 11234 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11235 return; 11236 mlxsw_reg_mbct_data_size_set(payload, data_size); 11237 mlxsw_reg_mbct_last_set(payload, last); 11238 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11239 } 11240 11241 static inline void 11242 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11243 enum mlxsw_reg_mbct_status *p_status, 11244 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11245 { 11246 if (p_slot_index) 11247 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11248 *p_status = mlxsw_reg_mbct_status_get(payload); 11249 if (p_fsm_state) 11250 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11251 } 11252 11253 /* MDDT - Management DownStream Device Tunneling Register 11254 * ------------------------------------------------------ 11255 * This register allows to deliver query and request messages (PRM registers, 11256 * commands) to a DownStream device. 11257 */ 11258 #define MLXSW_REG_MDDT_ID 0x9160 11259 #define MLXSW_REG_MDDT_LEN 0x110 11260 11261 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11262 11263 /* reg_mddt_slot_index 11264 * Slot index. 11265 * Access: Index 11266 */ 11267 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11268 11269 /* reg_mddt_device_index 11270 * Device index. 11271 * Access: Index 11272 */ 11273 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11274 11275 /* reg_mddt_read_size 11276 * Read size in D-Words. 11277 * Access: OP 11278 */ 11279 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11280 11281 /* reg_mddt_write_size 11282 * Write size in D-Words. 11283 * Access: OP 11284 */ 11285 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11286 11287 enum mlxsw_reg_mddt_status { 11288 MLXSW_REG_MDDT_STATUS_OK, 11289 }; 11290 11291 /* reg_mddt_status 11292 * Return code of the Downstream Device to the register that was sent. 11293 * Access: RO 11294 */ 11295 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11296 11297 enum mlxsw_reg_mddt_method { 11298 MLXSW_REG_MDDT_METHOD_QUERY, 11299 MLXSW_REG_MDDT_METHOD_WRITE, 11300 }; 11301 11302 /* reg_mddt_method 11303 * Access: OP 11304 */ 11305 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11306 11307 /* reg_mddt_register_id 11308 * Access: Index 11309 */ 11310 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11311 11312 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11313 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11314 11315 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11316 { 11317 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11318 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11319 } 11320 11321 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11322 u8 device_index, 11323 enum mlxsw_reg_mddt_method method, 11324 const struct mlxsw_reg_info *reg, 11325 char **inner_payload) 11326 { 11327 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11328 11329 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11330 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11331 11332 MLXSW_REG_ZERO(mddt, payload); 11333 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11334 mlxsw_reg_mddt_device_index_set(payload, device_index); 11335 mlxsw_reg_mddt_method_set(payload, method); 11336 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11337 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11338 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11339 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11340 } 11341 11342 /* MDDQ - Management DownStream Device Query Register 11343 * -------------------------------------------------- 11344 * This register allows to query the DownStream device properties. The desired 11345 * information is chosen upon the query_type field and is delivered by 32B 11346 * of data blocks. 11347 */ 11348 #define MLXSW_REG_MDDQ_ID 0x9161 11349 #define MLXSW_REG_MDDQ_LEN 0x30 11350 11351 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11352 11353 /* reg_mddq_sie 11354 * Slot info event enable. 11355 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11356 * active / ready will generate a DSDSC event. 11357 * Access: RW 11358 */ 11359 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11360 11361 enum mlxsw_reg_mddq_query_type { 11362 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11363 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11364 * on the slot, data_valid 11365 * will be '0'. 11366 */ 11367 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11368 }; 11369 11370 /* reg_mddq_query_type 11371 * Access: Index 11372 */ 11373 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11374 11375 /* reg_mddq_slot_index 11376 * Slot index. 0 is reserved. 11377 * Access: Index 11378 */ 11379 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11380 11381 /* reg_mddq_response_msg_seq 11382 * Response message sequential number. For a specific request, the response 11383 * message sequential number is the following one. In addition, the last 11384 * message should be 0. 11385 * Access: RO 11386 */ 11387 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11388 11389 /* reg_mddq_request_msg_seq 11390 * Request message sequential number. 11391 * The first message number should be 0. 11392 * Access: Index 11393 */ 11394 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11395 11396 /* reg_mddq_data_valid 11397 * If set, the data in the data field is valid and contain the information 11398 * for the queried index. 11399 * Access: RO 11400 */ 11401 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11402 11403 /* reg_mddq_slot_info_provisioned 11404 * If set, the INI file is applied and the card is provisioned. 11405 * Access: RO 11406 */ 11407 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11408 11409 /* reg_mddq_slot_info_sr_valid 11410 * If set, Shift Register is valid (after being provisioned) and data 11411 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11412 * Access: RO 11413 */ 11414 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11415 11416 enum mlxsw_reg_mddq_slot_info_ready { 11417 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11418 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11419 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11420 }; 11421 11422 /* reg_mddq_slot_info_lc_ready 11423 * If set, the LC is powered on, matching the INI version and a new FW 11424 * version can be burnt (if necessary). 11425 * Access: RO 11426 */ 11427 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11428 11429 /* reg_mddq_slot_info_active 11430 * If set, the FW has completed the MDDC.device_enable command. 11431 * Access: RO 11432 */ 11433 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11434 11435 /* reg_mddq_slot_info_hw_revision 11436 * Major user-configured version number of the current INI file. 11437 * Valid only when active or ready are '1'. 11438 * Access: RO 11439 */ 11440 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11441 11442 /* reg_mddq_slot_info_ini_file_version 11443 * User-configured version number of the current INI file. 11444 * Valid only when active or lc_ready are '1'. 11445 * Access: RO 11446 */ 11447 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11448 11449 /* reg_mddq_slot_info_card_type 11450 * Access: RO 11451 */ 11452 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11453 11454 static inline void 11455 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11456 enum mlxsw_reg_mddq_query_type query_type) 11457 { 11458 MLXSW_REG_ZERO(mddq, payload); 11459 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11460 mlxsw_reg_mddq_query_type_set(payload, query_type); 11461 } 11462 11463 static inline void 11464 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11465 { 11466 __mlxsw_reg_mddq_pack(payload, slot_index, 11467 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11468 mlxsw_reg_mddq_sie_set(payload, sie); 11469 } 11470 11471 static inline void 11472 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11473 bool *p_provisioned, bool *p_sr_valid, 11474 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11475 bool *p_active, u16 *p_hw_revision, 11476 u16 *p_ini_file_version, 11477 u8 *p_card_type) 11478 { 11479 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11480 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11481 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11482 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11483 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11484 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11485 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11486 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11487 } 11488 11489 /* reg_mddq_device_info_flash_owner 11490 * If set, the device is the flash owner. Otherwise, a shared flash 11491 * is used by this device (another device is the flash owner). 11492 * Access: RO 11493 */ 11494 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11495 11496 /* reg_mddq_device_info_device_index 11497 * Device index. The first device should number 0. 11498 * Access: RO 11499 */ 11500 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11501 11502 /* reg_mddq_device_info_fw_major 11503 * Major FW version number. 11504 * Access: RO 11505 */ 11506 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11507 11508 /* reg_mddq_device_info_fw_minor 11509 * Minor FW version number. 11510 * Access: RO 11511 */ 11512 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11513 11514 /* reg_mddq_device_info_fw_sub_minor 11515 * Sub-minor FW version number. 11516 * Access: RO 11517 */ 11518 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11519 11520 static inline void 11521 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11522 u8 request_msg_seq) 11523 { 11524 __mlxsw_reg_mddq_pack(payload, slot_index, 11525 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11526 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11527 } 11528 11529 static inline void 11530 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11531 bool *p_data_valid, bool *p_flash_owner, 11532 u8 *p_device_index, u16 *p_fw_major, 11533 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11534 { 11535 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11536 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11537 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11538 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11539 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11540 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11541 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11542 } 11543 11544 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11545 11546 /* reg_mddq_slot_ascii_name 11547 * Slot's ASCII name. 11548 * Access: RO 11549 */ 11550 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11551 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11552 11553 static inline void 11554 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11555 { 11556 __mlxsw_reg_mddq_pack(payload, slot_index, 11557 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11558 } 11559 11560 static inline void 11561 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11562 { 11563 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11564 } 11565 11566 /* MDDC - Management DownStream Device Control Register 11567 * ---------------------------------------------------- 11568 * This register allows to control downstream devices and line cards. 11569 */ 11570 #define MLXSW_REG_MDDC_ID 0x9163 11571 #define MLXSW_REG_MDDC_LEN 0x30 11572 11573 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11574 11575 /* reg_mddc_slot_index 11576 * Slot index. 0 is reserved. 11577 * Access: Index 11578 */ 11579 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11580 11581 /* reg_mddc_rst 11582 * Reset request. 11583 * Access: OP 11584 */ 11585 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11586 11587 /* reg_mddc_device_enable 11588 * When set, FW is the manager and allowed to program the downstream device. 11589 * Access: RW 11590 */ 11591 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11592 11593 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11594 bool device_enable) 11595 { 11596 MLXSW_REG_ZERO(mddc, payload); 11597 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11598 mlxsw_reg_mddc_rst_set(payload, rst); 11599 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11600 } 11601 11602 /* MFDE - Monitoring FW Debug Register 11603 * ----------------------------------- 11604 */ 11605 #define MLXSW_REG_MFDE_ID 0x9200 11606 #define MLXSW_REG_MFDE_LEN 0x30 11607 11608 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11609 11610 /* reg_mfde_irisc_id 11611 * Which irisc triggered the event 11612 * Access: RO 11613 */ 11614 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11615 11616 enum mlxsw_reg_mfde_severity { 11617 /* Unrecoverable switch behavior */ 11618 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11619 /* Unexpected state with possible systemic failure */ 11620 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11621 /* Unexpected state without systemic failure */ 11622 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11623 }; 11624 11625 /* reg_mfde_severity 11626 * The severity of the event. 11627 * Access: RO 11628 */ 11629 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11630 11631 enum mlxsw_reg_mfde_event_id { 11632 /* CRspace timeout */ 11633 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11634 /* KVD insertion machine stopped */ 11635 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11636 /* Triggered by MFGD.trigger_test */ 11637 MLXSW_REG_MFDE_EVENT_ID_TEST, 11638 /* Triggered when firmware hits an assert */ 11639 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11640 /* Fatal error interrupt from hardware */ 11641 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11642 }; 11643 11644 /* reg_mfde_event_id 11645 * Access: RO 11646 */ 11647 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11648 11649 enum mlxsw_reg_mfde_method { 11650 MLXSW_REG_MFDE_METHOD_QUERY, 11651 MLXSW_REG_MFDE_METHOD_WRITE, 11652 }; 11653 11654 /* reg_mfde_method 11655 * Access: RO 11656 */ 11657 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11658 11659 /* reg_mfde_long_process 11660 * Indicates if the command is in long_process mode. 11661 * Access: RO 11662 */ 11663 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11664 11665 enum mlxsw_reg_mfde_command_type { 11666 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11667 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11668 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11669 }; 11670 11671 /* reg_mfde_command_type 11672 * Access: RO 11673 */ 11674 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11675 11676 /* reg_mfde_reg_attr_id 11677 * EMAD - register id, MAD - attibute id 11678 * Access: RO 11679 */ 11680 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11681 11682 /* reg_mfde_crspace_to_log_address 11683 * crspace address accessed, which resulted in timeout. 11684 * Access: RO 11685 */ 11686 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11687 11688 /* reg_mfde_crspace_to_oe 11689 * 0 - New event 11690 * 1 - Old event, occurred before MFGD activation. 11691 * Access: RO 11692 */ 11693 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11694 11695 /* reg_mfde_crspace_to_log_id 11696 * Which irisc triggered the timeout. 11697 * Access: RO 11698 */ 11699 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11700 11701 /* reg_mfde_crspace_to_log_ip 11702 * IP (instruction pointer) that triggered the timeout. 11703 * Access: RO 11704 */ 11705 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11706 11707 /* reg_mfde_kvd_im_stop_oe 11708 * 0 - New event 11709 * 1 - Old event, occurred before MFGD activation. 11710 * Access: RO 11711 */ 11712 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11713 11714 /* reg_mfde_kvd_im_stop_pipes_mask 11715 * Bit per kvh pipe. 11716 * Access: RO 11717 */ 11718 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11719 11720 /* reg_mfde_fw_assert_var0-4 11721 * Variables passed to assert. 11722 * Access: RO 11723 */ 11724 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11725 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11726 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11727 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11728 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11729 11730 /* reg_mfde_fw_assert_existptr 11731 * The instruction pointer when assert was triggered. 11732 * Access: RO 11733 */ 11734 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11735 11736 /* reg_mfde_fw_assert_callra 11737 * The return address after triggering assert. 11738 * Access: RO 11739 */ 11740 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11741 11742 /* reg_mfde_fw_assert_oe 11743 * 0 - New event 11744 * 1 - Old event, occurred before MFGD activation. 11745 * Access: RO 11746 */ 11747 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11748 11749 /* reg_mfde_fw_assert_tile_v 11750 * 0: The assert was from main 11751 * 1: The assert was from a tile 11752 * Access: RO 11753 */ 11754 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11755 11756 /* reg_mfde_fw_assert_tile_index 11757 * When tile_v=1, the tile_index that caused the assert. 11758 * Access: RO 11759 */ 11760 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11761 11762 /* reg_mfde_fw_assert_ext_synd 11763 * A generated one-to-one identifier which is specific per-assert. 11764 * Access: RO 11765 */ 11766 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11767 11768 /* reg_mfde_fatal_cause_id 11769 * HW interrupt cause id. 11770 * Access: RO 11771 */ 11772 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11773 11774 /* reg_mfde_fatal_cause_tile_v 11775 * 0: The assert was from main 11776 * 1: The assert was from a tile 11777 * Access: RO 11778 */ 11779 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11780 11781 /* reg_mfde_fatal_cause_tile_index 11782 * When tile_v=1, the tile_index that caused the assert. 11783 * Access: RO 11784 */ 11785 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11786 11787 /* TNGCR - Tunneling NVE General Configuration Register 11788 * ---------------------------------------------------- 11789 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11790 */ 11791 #define MLXSW_REG_TNGCR_ID 0xA001 11792 #define MLXSW_REG_TNGCR_LEN 0x44 11793 11794 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11795 11796 enum mlxsw_reg_tngcr_type { 11797 MLXSW_REG_TNGCR_TYPE_VXLAN, 11798 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11799 MLXSW_REG_TNGCR_TYPE_GENEVE, 11800 MLXSW_REG_TNGCR_TYPE_NVGRE, 11801 }; 11802 11803 /* reg_tngcr_type 11804 * Tunnel type for encapsulation and decapsulation. The types are mutually 11805 * exclusive. 11806 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11807 * Access: RW 11808 */ 11809 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11810 11811 /* reg_tngcr_nve_valid 11812 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11813 * Access: RW 11814 */ 11815 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11816 11817 /* reg_tngcr_nve_ttl_uc 11818 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11819 * Access: RW 11820 */ 11821 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11822 11823 /* reg_tngcr_nve_ttl_mc 11824 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11825 * Access: RW 11826 */ 11827 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11828 11829 enum { 11830 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11831 MLXSW_REG_TNGCR_FL_NO_COPY, 11832 /* Copy flow label from inner packet if packet is IPv6 and 11833 * encapsulation is by IPv6. Otherwise, calculate flow label using 11834 * nve_flh. 11835 */ 11836 MLXSW_REG_TNGCR_FL_COPY, 11837 }; 11838 11839 /* reg_tngcr_nve_flc 11840 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11841 * Access: RW 11842 */ 11843 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11844 11845 enum { 11846 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11847 * uses {nve_fl_prefix, nve_fl_suffix}. 11848 */ 11849 MLXSW_REG_TNGCR_FL_NO_HASH, 11850 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11851 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11852 */ 11853 MLXSW_REG_TNGCR_FL_HASH, 11854 }; 11855 11856 /* reg_tngcr_nve_flh 11857 * NVE flow label hash. 11858 * Access: RW 11859 */ 11860 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11861 11862 /* reg_tngcr_nve_fl_prefix 11863 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11864 * Access: RW 11865 */ 11866 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11867 11868 /* reg_tngcr_nve_fl_suffix 11869 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11870 * Reserved when nve_flh=1 and for Spectrum. 11871 * Access: RW 11872 */ 11873 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11874 11875 enum { 11876 /* Source UDP port is fixed (default '0') */ 11877 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11878 /* Source UDP port is calculated based on hash */ 11879 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11880 }; 11881 11882 /* reg_tngcr_nve_udp_sport_type 11883 * NVE UDP source port type. 11884 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11885 * When the source UDP port is calculated based on hash, then the 8 LSBs 11886 * are calculated from hash the 8 MSBs are configured by 11887 * nve_udp_sport_prefix. 11888 * Access: RW 11889 */ 11890 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11891 11892 /* reg_tngcr_nve_udp_sport_prefix 11893 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11894 * Reserved when NVE type is NVGRE. 11895 * Access: RW 11896 */ 11897 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11898 11899 /* reg_tngcr_nve_group_size_mc 11900 * The amount of sequential linked lists of MC entries. The first linked 11901 * list is configured by SFD.underlay_mc_ptr. 11902 * Valid values: 1, 2, 4, 8, 16, 32, 64 11903 * The linked list are configured by TNUMT. 11904 * The hash is set by LAG hash. 11905 * Access: RW 11906 */ 11907 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11908 11909 /* reg_tngcr_nve_group_size_flood 11910 * The amount of sequential linked lists of flooding entries. The first 11911 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11912 * Valid values: 1, 2, 4, 8, 16, 32, 64 11913 * The linked list are configured by TNUMT. 11914 * The hash is set by LAG hash. 11915 * Access: RW 11916 */ 11917 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11918 11919 /* reg_tngcr_learn_enable 11920 * During decapsulation, whether to learn from NVE port. 11921 * Reserved when Spectrum-2. See TNPC. 11922 * Access: RW 11923 */ 11924 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11925 11926 /* reg_tngcr_underlay_virtual_router 11927 * Underlay virtual router. 11928 * Reserved when Spectrum-2. 11929 * Access: RW 11930 */ 11931 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11932 11933 /* reg_tngcr_underlay_rif 11934 * Underlay ingress router interface. RIF type should be loopback generic. 11935 * Reserved when Spectrum. 11936 * Access: RW 11937 */ 11938 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11939 11940 /* reg_tngcr_usipv4 11941 * Underlay source IPv4 address of the NVE. 11942 * Access: RW 11943 */ 11944 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11945 11946 /* reg_tngcr_usipv6 11947 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11948 * modified under traffic of NVE tunneling encapsulation. 11949 * Access: RW 11950 */ 11951 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11952 11953 static inline void mlxsw_reg_tngcr_pack(char *payload, 11954 enum mlxsw_reg_tngcr_type type, 11955 bool valid, u8 ttl) 11956 { 11957 MLXSW_REG_ZERO(tngcr, payload); 11958 mlxsw_reg_tngcr_type_set(payload, type); 11959 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11960 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11961 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11962 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11963 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11964 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11965 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11966 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11967 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11968 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11969 } 11970 11971 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11972 * ------------------------------------------------------- 11973 * The TNUMT register is for building the underlay MC table. It is used 11974 * for MC, flooding and BC traffic into the NVE tunnel. 11975 */ 11976 #define MLXSW_REG_TNUMT_ID 0xA003 11977 #define MLXSW_REG_TNUMT_LEN 0x20 11978 11979 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11980 11981 enum mlxsw_reg_tnumt_record_type { 11982 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11983 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11984 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11985 }; 11986 11987 /* reg_tnumt_record_type 11988 * Record type. 11989 * Access: RW 11990 */ 11991 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11992 11993 /* reg_tnumt_tunnel_port 11994 * Tunnel port. 11995 * Access: RW 11996 */ 11997 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11998 11999 /* reg_tnumt_underlay_mc_ptr 12000 * Index to the underlay multicast table. 12001 * For Spectrum the index is to the KVD linear. 12002 * Access: Index 12003 */ 12004 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 12005 12006 /* reg_tnumt_vnext 12007 * The next_underlay_mc_ptr is valid. 12008 * Access: RW 12009 */ 12010 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 12011 12012 /* reg_tnumt_next_underlay_mc_ptr 12013 * The next index to the underlay multicast table. 12014 * Access: RW 12015 */ 12016 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 12017 12018 /* reg_tnumt_record_size 12019 * Number of IP addresses in the record. 12020 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 12021 * Access: RW 12022 */ 12023 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 12024 12025 /* reg_tnumt_udip 12026 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 12027 * Access: RW 12028 */ 12029 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 12030 12031 /* reg_tnumt_udip_ptr 12032 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 12033 * i >= size. The IPv6 addresses are configured by RIPS. 12034 * Access: RW 12035 */ 12036 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 12037 12038 static inline void mlxsw_reg_tnumt_pack(char *payload, 12039 enum mlxsw_reg_tnumt_record_type type, 12040 enum mlxsw_reg_tunnel_port tport, 12041 u32 underlay_mc_ptr, bool vnext, 12042 u32 next_underlay_mc_ptr, 12043 u8 record_size) 12044 { 12045 MLXSW_REG_ZERO(tnumt, payload); 12046 mlxsw_reg_tnumt_record_type_set(payload, type); 12047 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12048 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12049 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12050 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12051 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12052 } 12053 12054 /* TNQCR - Tunneling NVE QoS Configuration Register 12055 * ------------------------------------------------ 12056 * The TNQCR register configures how QoS is set in encapsulation into the 12057 * underlay network. 12058 */ 12059 #define MLXSW_REG_TNQCR_ID 0xA010 12060 #define MLXSW_REG_TNQCR_LEN 0x0C 12061 12062 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12063 12064 /* reg_tnqcr_enc_set_dscp 12065 * For encapsulation: How to set DSCP field: 12066 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12067 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12068 * 1 - Set the DSCP field as TNQDR.dscp 12069 * Access: RW 12070 */ 12071 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12072 12073 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12074 { 12075 MLXSW_REG_ZERO(tnqcr, payload); 12076 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12077 } 12078 12079 /* TNQDR - Tunneling NVE QoS Default Register 12080 * ------------------------------------------ 12081 * The TNQDR register configures the default QoS settings for NVE 12082 * encapsulation. 12083 */ 12084 #define MLXSW_REG_TNQDR_ID 0xA011 12085 #define MLXSW_REG_TNQDR_LEN 0x08 12086 12087 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12088 12089 /* reg_tnqdr_local_port 12090 * Local port number (receive port). CPU port is supported. 12091 * Access: Index 12092 */ 12093 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12094 12095 /* reg_tnqdr_dscp 12096 * For encapsulation, the default DSCP. 12097 * Access: RW 12098 */ 12099 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12100 12101 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12102 { 12103 MLXSW_REG_ZERO(tnqdr, payload); 12104 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12105 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12106 } 12107 12108 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12109 * -------------------------------------------------------- 12110 * The TNEEM register maps ECN of the IP header at the ingress to the 12111 * encapsulation to the ECN of the underlay network. 12112 */ 12113 #define MLXSW_REG_TNEEM_ID 0xA012 12114 #define MLXSW_REG_TNEEM_LEN 0x0C 12115 12116 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12117 12118 /* reg_tneem_overlay_ecn 12119 * ECN of the IP header in the overlay network. 12120 * Access: Index 12121 */ 12122 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12123 12124 /* reg_tneem_underlay_ecn 12125 * ECN of the IP header in the underlay network. 12126 * Access: RW 12127 */ 12128 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12129 12130 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12131 u8 underlay_ecn) 12132 { 12133 MLXSW_REG_ZERO(tneem, payload); 12134 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12135 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12136 } 12137 12138 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12139 * -------------------------------------------------------- 12140 * The TNDEM register configures the actions that are done in the 12141 * decapsulation. 12142 */ 12143 #define MLXSW_REG_TNDEM_ID 0xA013 12144 #define MLXSW_REG_TNDEM_LEN 0x0C 12145 12146 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12147 12148 /* reg_tndem_underlay_ecn 12149 * ECN field of the IP header in the underlay network. 12150 * Access: Index 12151 */ 12152 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12153 12154 /* reg_tndem_overlay_ecn 12155 * ECN field of the IP header in the overlay network. 12156 * Access: Index 12157 */ 12158 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12159 12160 /* reg_tndem_eip_ecn 12161 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12162 * from the decapsulation. 12163 * Access: RW 12164 */ 12165 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12166 12167 /* reg_tndem_trap_en 12168 * Trap enable: 12169 * 0 - No trap due to decap ECN 12170 * 1 - Trap enable with trap_id 12171 * Access: RW 12172 */ 12173 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12174 12175 /* reg_tndem_trap_id 12176 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12177 * Reserved when trap_en is '0'. 12178 * Access: RW 12179 */ 12180 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12181 12182 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12183 u8 overlay_ecn, u8 ecn, bool trap_en, 12184 u16 trap_id) 12185 { 12186 MLXSW_REG_ZERO(tndem, payload); 12187 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12188 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12189 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12190 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12191 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12192 } 12193 12194 /* TNPC - Tunnel Port Configuration Register 12195 * ----------------------------------------- 12196 * The TNPC register is used for tunnel port configuration. 12197 * Reserved when Spectrum. 12198 */ 12199 #define MLXSW_REG_TNPC_ID 0xA020 12200 #define MLXSW_REG_TNPC_LEN 0x18 12201 12202 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12203 12204 /* reg_tnpc_tunnel_port 12205 * Tunnel port. 12206 * Access: Index 12207 */ 12208 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12209 12210 /* reg_tnpc_learn_enable_v6 12211 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12212 * Access: RW 12213 */ 12214 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12215 12216 /* reg_tnpc_learn_enable_v4 12217 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12218 * Access: RW 12219 */ 12220 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12221 12222 static inline void mlxsw_reg_tnpc_pack(char *payload, 12223 enum mlxsw_reg_tunnel_port tport, 12224 bool learn_enable) 12225 { 12226 MLXSW_REG_ZERO(tnpc, payload); 12227 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12228 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12229 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12230 } 12231 12232 /* TIGCR - Tunneling IPinIP General Configuration Register 12233 * ------------------------------------------------------- 12234 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12235 */ 12236 #define MLXSW_REG_TIGCR_ID 0xA801 12237 #define MLXSW_REG_TIGCR_LEN 0x10 12238 12239 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12240 12241 /* reg_tigcr_ipip_ttlc 12242 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12243 * header. 12244 * Access: RW 12245 */ 12246 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12247 12248 /* reg_tigcr_ipip_ttl_uc 12249 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12250 * reg_tigcr_ipip_ttlc is unset. 12251 * Access: RW 12252 */ 12253 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12254 12255 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12256 { 12257 MLXSW_REG_ZERO(tigcr, payload); 12258 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12259 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12260 } 12261 12262 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12263 * ----------------------------------------------------------- 12264 * The TIEEM register maps ECN of the IP header at the ingress to the 12265 * encapsulation to the ECN of the underlay network. 12266 */ 12267 #define MLXSW_REG_TIEEM_ID 0xA812 12268 #define MLXSW_REG_TIEEM_LEN 0x0C 12269 12270 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12271 12272 /* reg_tieem_overlay_ecn 12273 * ECN of the IP header in the overlay network. 12274 * Access: Index 12275 */ 12276 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12277 12278 /* reg_tineem_underlay_ecn 12279 * ECN of the IP header in the underlay network. 12280 * Access: RW 12281 */ 12282 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12283 12284 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12285 u8 underlay_ecn) 12286 { 12287 MLXSW_REG_ZERO(tieem, payload); 12288 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12289 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12290 } 12291 12292 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12293 * ----------------------------------------------------------- 12294 * The TIDEM register configures the actions that are done in the 12295 * decapsulation. 12296 */ 12297 #define MLXSW_REG_TIDEM_ID 0xA813 12298 #define MLXSW_REG_TIDEM_LEN 0x0C 12299 12300 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12301 12302 /* reg_tidem_underlay_ecn 12303 * ECN field of the IP header in the underlay network. 12304 * Access: Index 12305 */ 12306 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12307 12308 /* reg_tidem_overlay_ecn 12309 * ECN field of the IP header in the overlay network. 12310 * Access: Index 12311 */ 12312 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12313 12314 /* reg_tidem_eip_ecn 12315 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12316 * from the decapsulation. 12317 * Access: RW 12318 */ 12319 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12320 12321 /* reg_tidem_trap_en 12322 * Trap enable: 12323 * 0 - No trap due to decap ECN 12324 * 1 - Trap enable with trap_id 12325 * Access: RW 12326 */ 12327 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12328 12329 /* reg_tidem_trap_id 12330 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12331 * Reserved when trap_en is '0'. 12332 * Access: RW 12333 */ 12334 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12335 12336 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12337 u8 overlay_ecn, u8 eip_ecn, 12338 bool trap_en, u16 trap_id) 12339 { 12340 MLXSW_REG_ZERO(tidem, payload); 12341 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12342 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12343 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12344 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12345 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12346 } 12347 12348 /* SBPR - Shared Buffer Pools Register 12349 * ----------------------------------- 12350 * The SBPR configures and retrieves the shared buffer pools and configuration. 12351 */ 12352 #define MLXSW_REG_SBPR_ID 0xB001 12353 #define MLXSW_REG_SBPR_LEN 0x14 12354 12355 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12356 12357 /* reg_sbpr_desc 12358 * When set, configures descriptor buffer. 12359 * Access: Index 12360 */ 12361 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12362 12363 /* shared direstion enum for SBPR, SBCM, SBPM */ 12364 enum mlxsw_reg_sbxx_dir { 12365 MLXSW_REG_SBXX_DIR_INGRESS, 12366 MLXSW_REG_SBXX_DIR_EGRESS, 12367 }; 12368 12369 /* reg_sbpr_dir 12370 * Direction. 12371 * Access: Index 12372 */ 12373 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12374 12375 /* reg_sbpr_pool 12376 * Pool index. 12377 * Access: Index 12378 */ 12379 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12380 12381 /* reg_sbpr_infi_size 12382 * Size is infinite. 12383 * Access: RW 12384 */ 12385 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12386 12387 /* reg_sbpr_size 12388 * Pool size in buffer cells. 12389 * Reserved when infi_size = 1. 12390 * Access: RW 12391 */ 12392 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12393 12394 enum mlxsw_reg_sbpr_mode { 12395 MLXSW_REG_SBPR_MODE_STATIC, 12396 MLXSW_REG_SBPR_MODE_DYNAMIC, 12397 }; 12398 12399 /* reg_sbpr_mode 12400 * Pool quota calculation mode. 12401 * Access: RW 12402 */ 12403 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12404 12405 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12406 enum mlxsw_reg_sbxx_dir dir, 12407 enum mlxsw_reg_sbpr_mode mode, u32 size, 12408 bool infi_size) 12409 { 12410 MLXSW_REG_ZERO(sbpr, payload); 12411 mlxsw_reg_sbpr_pool_set(payload, pool); 12412 mlxsw_reg_sbpr_dir_set(payload, dir); 12413 mlxsw_reg_sbpr_mode_set(payload, mode); 12414 mlxsw_reg_sbpr_size_set(payload, size); 12415 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12416 } 12417 12418 /* SBCM - Shared Buffer Class Management Register 12419 * ---------------------------------------------- 12420 * The SBCM register configures and retrieves the shared buffer allocation 12421 * and configuration according to Port-PG, including the binding to pool 12422 * and definition of the associated quota. 12423 */ 12424 #define MLXSW_REG_SBCM_ID 0xB002 12425 #define MLXSW_REG_SBCM_LEN 0x28 12426 12427 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12428 12429 /* reg_sbcm_local_port 12430 * Local port number. 12431 * For Ingress: excludes CPU port and Router port 12432 * For Egress: excludes IP Router 12433 * Access: Index 12434 */ 12435 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12436 12437 /* reg_sbcm_pg_buff 12438 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12439 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12440 * For traffic class: range is 0..cap_max_tclass - 1 12441 * Note that when traffic class is in MC aware mode then the traffic 12442 * classes which are MC aware cannot be configured. 12443 * Access: Index 12444 */ 12445 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12446 12447 /* reg_sbcm_dir 12448 * Direction. 12449 * Access: Index 12450 */ 12451 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12452 12453 /* reg_sbcm_min_buff 12454 * Minimum buffer size for the limiter, in cells. 12455 * Access: RW 12456 */ 12457 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12458 12459 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12460 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12461 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12462 12463 /* reg_sbcm_infi_max 12464 * Max buffer is infinite. 12465 * Access: RW 12466 */ 12467 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12468 12469 /* reg_sbcm_max_buff 12470 * When the pool associated to the port-pg/tclass is configured to 12471 * static, Maximum buffer size for the limiter configured in cells. 12472 * When the pool associated to the port-pg/tclass is configured to 12473 * dynamic, the max_buff holds the "alpha" parameter, supporting 12474 * the following values: 12475 * 0: 0 12476 * i: (1/128)*2^(i-1), for i=1..14 12477 * 0xFF: Infinity 12478 * Reserved when infi_max = 1. 12479 * Access: RW 12480 */ 12481 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12482 12483 /* reg_sbcm_pool 12484 * Association of the port-priority to a pool. 12485 * Access: RW 12486 */ 12487 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12488 12489 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12490 enum mlxsw_reg_sbxx_dir dir, 12491 u32 min_buff, u32 max_buff, 12492 bool infi_max, u8 pool) 12493 { 12494 MLXSW_REG_ZERO(sbcm, payload); 12495 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12496 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12497 mlxsw_reg_sbcm_dir_set(payload, dir); 12498 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12499 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12500 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12501 mlxsw_reg_sbcm_pool_set(payload, pool); 12502 } 12503 12504 /* SBPM - Shared Buffer Port Management Register 12505 * --------------------------------------------- 12506 * The SBPM register configures and retrieves the shared buffer allocation 12507 * and configuration according to Port-Pool, including the definition 12508 * of the associated quota. 12509 */ 12510 #define MLXSW_REG_SBPM_ID 0xB003 12511 #define MLXSW_REG_SBPM_LEN 0x28 12512 12513 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12514 12515 /* reg_sbpm_local_port 12516 * Local port number. 12517 * For Ingress: excludes CPU port and Router port 12518 * For Egress: excludes IP Router 12519 * Access: Index 12520 */ 12521 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12522 12523 /* reg_sbpm_pool 12524 * The pool associated to quota counting on the local_port. 12525 * Access: Index 12526 */ 12527 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12528 12529 /* reg_sbpm_dir 12530 * Direction. 12531 * Access: Index 12532 */ 12533 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12534 12535 /* reg_sbpm_buff_occupancy 12536 * Current buffer occupancy in cells. 12537 * Access: RO 12538 */ 12539 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12540 12541 /* reg_sbpm_clr 12542 * Clear Max Buffer Occupancy 12543 * When this bit is set, max_buff_occupancy field is cleared (and a 12544 * new max value is tracked from the time the clear was performed). 12545 * Access: OP 12546 */ 12547 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12548 12549 /* reg_sbpm_max_buff_occupancy 12550 * Maximum value of buffer occupancy in cells monitored. Cleared by 12551 * writing to the clr field. 12552 * Access: RO 12553 */ 12554 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12555 12556 /* reg_sbpm_min_buff 12557 * Minimum buffer size for the limiter, in cells. 12558 * Access: RW 12559 */ 12560 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12561 12562 /* reg_sbpm_max_buff 12563 * When the pool associated to the port-pg/tclass is configured to 12564 * static, Maximum buffer size for the limiter configured in cells. 12565 * When the pool associated to the port-pg/tclass is configured to 12566 * dynamic, the max_buff holds the "alpha" parameter, supporting 12567 * the following values: 12568 * 0: 0 12569 * i: (1/128)*2^(i-1), for i=1..14 12570 * 0xFF: Infinity 12571 * Access: RW 12572 */ 12573 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12574 12575 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12576 enum mlxsw_reg_sbxx_dir dir, bool clr, 12577 u32 min_buff, u32 max_buff) 12578 { 12579 MLXSW_REG_ZERO(sbpm, payload); 12580 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12581 mlxsw_reg_sbpm_pool_set(payload, pool); 12582 mlxsw_reg_sbpm_dir_set(payload, dir); 12583 mlxsw_reg_sbpm_clr_set(payload, clr); 12584 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12585 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12586 } 12587 12588 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12589 u32 *p_max_buff_occupancy) 12590 { 12591 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12592 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12593 } 12594 12595 /* SBMM - Shared Buffer Multicast Management Register 12596 * -------------------------------------------------- 12597 * The SBMM register configures and retrieves the shared buffer allocation 12598 * and configuration for MC packets according to Switch-Priority, including 12599 * the binding to pool and definition of the associated quota. 12600 */ 12601 #define MLXSW_REG_SBMM_ID 0xB004 12602 #define MLXSW_REG_SBMM_LEN 0x28 12603 12604 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12605 12606 /* reg_sbmm_prio 12607 * Switch Priority. 12608 * Access: Index 12609 */ 12610 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12611 12612 /* reg_sbmm_min_buff 12613 * Minimum buffer size for the limiter, in cells. 12614 * Access: RW 12615 */ 12616 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12617 12618 /* reg_sbmm_max_buff 12619 * When the pool associated to the port-pg/tclass is configured to 12620 * static, Maximum buffer size for the limiter configured in cells. 12621 * When the pool associated to the port-pg/tclass is configured to 12622 * dynamic, the max_buff holds the "alpha" parameter, supporting 12623 * the following values: 12624 * 0: 0 12625 * i: (1/128)*2^(i-1), for i=1..14 12626 * 0xFF: Infinity 12627 * Access: RW 12628 */ 12629 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12630 12631 /* reg_sbmm_pool 12632 * Association of the port-priority to a pool. 12633 * Access: RW 12634 */ 12635 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12636 12637 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12638 u32 max_buff, u8 pool) 12639 { 12640 MLXSW_REG_ZERO(sbmm, payload); 12641 mlxsw_reg_sbmm_prio_set(payload, prio); 12642 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12643 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12644 mlxsw_reg_sbmm_pool_set(payload, pool); 12645 } 12646 12647 /* SBSR - Shared Buffer Status Register 12648 * ------------------------------------ 12649 * The SBSR register retrieves the shared buffer occupancy according to 12650 * Port-Pool. Note that this register enables reading a large amount of data. 12651 * It is the user's responsibility to limit the amount of data to ensure the 12652 * response can match the maximum transfer unit. In case the response exceeds 12653 * the maximum transport unit, it will be truncated with no special notice. 12654 */ 12655 #define MLXSW_REG_SBSR_ID 0xB005 12656 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12657 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12658 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12659 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12660 MLXSW_REG_SBSR_REC_LEN * \ 12661 MLXSW_REG_SBSR_REC_MAX_COUNT) 12662 12663 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12664 12665 /* reg_sbsr_clr 12666 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12667 * field is cleared (and a new max value is tracked from the time the clear 12668 * was performed). 12669 * Access: OP 12670 */ 12671 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12672 12673 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12674 12675 /* reg_sbsr_port_page 12676 * Determines the range of the ports specified in the 'ingress_port_mask' 12677 * and 'egress_port_mask' bit masks. 12678 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12679 * Access: Index 12680 */ 12681 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12682 12683 /* reg_sbsr_ingress_port_mask 12684 * Bit vector for all ingress network ports. 12685 * Indicates which of the ports (for which the relevant bit is set) 12686 * are affected by the set operation. Configuration of any other port 12687 * does not change. 12688 * Access: Index 12689 */ 12690 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12691 12692 /* reg_sbsr_pg_buff_mask 12693 * Bit vector for all switch priority groups. 12694 * Indicates which of the priorities (for which the relevant bit is set) 12695 * are affected by the set operation. Configuration of any other priority 12696 * does not change. 12697 * Range is 0..cap_max_pg_buffers - 1 12698 * Access: Index 12699 */ 12700 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12701 12702 /* reg_sbsr_egress_port_mask 12703 * Bit vector for all egress network ports. 12704 * Indicates which of the ports (for which the relevant bit is set) 12705 * are affected by the set operation. Configuration of any other port 12706 * does not change. 12707 * Access: Index 12708 */ 12709 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12710 12711 /* reg_sbsr_tclass_mask 12712 * Bit vector for all traffic classes. 12713 * Indicates which of the traffic classes (for which the relevant bit is 12714 * set) are affected by the set operation. Configuration of any other 12715 * traffic class does not change. 12716 * Range is 0..cap_max_tclass - 1 12717 * Access: Index 12718 */ 12719 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12720 12721 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12722 { 12723 MLXSW_REG_ZERO(sbsr, payload); 12724 mlxsw_reg_sbsr_clr_set(payload, clr); 12725 } 12726 12727 /* reg_sbsr_rec_buff_occupancy 12728 * Current buffer occupancy in cells. 12729 * Access: RO 12730 */ 12731 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12732 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12733 12734 /* reg_sbsr_rec_max_buff_occupancy 12735 * Maximum value of buffer occupancy in cells monitored. Cleared by 12736 * writing to the clr field. 12737 * Access: RO 12738 */ 12739 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12740 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12741 12742 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12743 u32 *p_buff_occupancy, 12744 u32 *p_max_buff_occupancy) 12745 { 12746 *p_buff_occupancy = 12747 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12748 *p_max_buff_occupancy = 12749 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12750 } 12751 12752 /* SBIB - Shared Buffer Internal Buffer Register 12753 * --------------------------------------------- 12754 * The SBIB register configures per port buffers for internal use. The internal 12755 * buffers consume memory on the port buffers (note that the port buffers are 12756 * used also by PBMC). 12757 * 12758 * For Spectrum this is used for egress mirroring. 12759 */ 12760 #define MLXSW_REG_SBIB_ID 0xB006 12761 #define MLXSW_REG_SBIB_LEN 0x10 12762 12763 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12764 12765 /* reg_sbib_local_port 12766 * Local port number 12767 * Not supported for CPU port and router port 12768 * Access: Index 12769 */ 12770 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12771 12772 /* reg_sbib_buff_size 12773 * Units represented in cells 12774 * Allowed range is 0 to (cap_max_headroom_size - 1) 12775 * Default is 0 12776 * Access: RW 12777 */ 12778 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12779 12780 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12781 u32 buff_size) 12782 { 12783 MLXSW_REG_ZERO(sbib, payload); 12784 mlxsw_reg_sbib_local_port_set(payload, local_port); 12785 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12786 } 12787 12788 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12789 MLXSW_REG(sgcr), 12790 MLXSW_REG(spad), 12791 MLXSW_REG(sspr), 12792 MLXSW_REG(sfdat), 12793 MLXSW_REG(sfd), 12794 MLXSW_REG(sfn), 12795 MLXSW_REG(spms), 12796 MLXSW_REG(spvid), 12797 MLXSW_REG(spvm), 12798 MLXSW_REG(spaft), 12799 MLXSW_REG(sfgc), 12800 MLXSW_REG(sfdf), 12801 MLXSW_REG(sldr), 12802 MLXSW_REG(slcr), 12803 MLXSW_REG(slcor), 12804 MLXSW_REG(spmlr), 12805 MLXSW_REG(svfa), 12806 MLXSW_REG(spvtr), 12807 MLXSW_REG(svpe), 12808 MLXSW_REG(sfmr), 12809 MLXSW_REG(spvmlr), 12810 MLXSW_REG(spfsr), 12811 MLXSW_REG(spvc), 12812 MLXSW_REG(spevet), 12813 MLXSW_REG(smpe), 12814 MLXSW_REG(smid2), 12815 MLXSW_REG(cwtp), 12816 MLXSW_REG(cwtpm), 12817 MLXSW_REG(pgcr), 12818 MLXSW_REG(ppbt), 12819 MLXSW_REG(pacl), 12820 MLXSW_REG(pagt), 12821 MLXSW_REG(ptar), 12822 MLXSW_REG(ppbs), 12823 MLXSW_REG(prcr), 12824 MLXSW_REG(pefa), 12825 MLXSW_REG(pemrbt), 12826 MLXSW_REG(ptce2), 12827 MLXSW_REG(perpt), 12828 MLXSW_REG(peabfe), 12829 MLXSW_REG(perar), 12830 MLXSW_REG(ptce3), 12831 MLXSW_REG(percr), 12832 MLXSW_REG(pererp), 12833 MLXSW_REG(iedr), 12834 MLXSW_REG(qpts), 12835 MLXSW_REG(qpcr), 12836 MLXSW_REG(qtct), 12837 MLXSW_REG(qeec), 12838 MLXSW_REG(qrwe), 12839 MLXSW_REG(qpdsm), 12840 MLXSW_REG(qpdp), 12841 MLXSW_REG(qpdpm), 12842 MLXSW_REG(qtctm), 12843 MLXSW_REG(qpsc), 12844 MLXSW_REG(pmlp), 12845 MLXSW_REG(pmtu), 12846 MLXSW_REG(ptys), 12847 MLXSW_REG(ppad), 12848 MLXSW_REG(paos), 12849 MLXSW_REG(pfcc), 12850 MLXSW_REG(ppcnt), 12851 MLXSW_REG(pptb), 12852 MLXSW_REG(pbmc), 12853 MLXSW_REG(pspa), 12854 MLXSW_REG(pmaos), 12855 MLXSW_REG(pplr), 12856 MLXSW_REG(pmtdb), 12857 MLXSW_REG(pmecr), 12858 MLXSW_REG(pmpe), 12859 MLXSW_REG(pddr), 12860 MLXSW_REG(pmmp), 12861 MLXSW_REG(pllp), 12862 MLXSW_REG(pmtm), 12863 MLXSW_REG(htgt), 12864 MLXSW_REG(hpkt), 12865 MLXSW_REG(rgcr), 12866 MLXSW_REG(ritr), 12867 MLXSW_REG(rtar), 12868 MLXSW_REG(ratr), 12869 MLXSW_REG(rtdp), 12870 MLXSW_REG(rips), 12871 MLXSW_REG(ratrad), 12872 MLXSW_REG(rdpm), 12873 MLXSW_REG(ricnt), 12874 MLXSW_REG(rrcr), 12875 MLXSW_REG(ralta), 12876 MLXSW_REG(ralst), 12877 MLXSW_REG(raltb), 12878 MLXSW_REG(ralue), 12879 MLXSW_REG(rauht), 12880 MLXSW_REG(raleu), 12881 MLXSW_REG(rauhtd), 12882 MLXSW_REG(rigr2), 12883 MLXSW_REG(recr2), 12884 MLXSW_REG(rmft2), 12885 MLXSW_REG(reiv), 12886 MLXSW_REG(mfcr), 12887 MLXSW_REG(mfsc), 12888 MLXSW_REG(mfsm), 12889 MLXSW_REG(mfsl), 12890 MLXSW_REG(fore), 12891 MLXSW_REG(mtcap), 12892 MLXSW_REG(mtmp), 12893 MLXSW_REG(mtwe), 12894 MLXSW_REG(mtbr), 12895 MLXSW_REG(mcia), 12896 MLXSW_REG(mpat), 12897 MLXSW_REG(mpar), 12898 MLXSW_REG(mgir), 12899 MLXSW_REG(mrsr), 12900 MLXSW_REG(mlcr), 12901 MLXSW_REG(mcion), 12902 MLXSW_REG(mtpps), 12903 MLXSW_REG(mtutc), 12904 MLXSW_REG(mpsc), 12905 MLXSW_REG(mcqi), 12906 MLXSW_REG(mcc), 12907 MLXSW_REG(mcda), 12908 MLXSW_REG(mgpc), 12909 MLXSW_REG(mprs), 12910 MLXSW_REG(mogcr), 12911 MLXSW_REG(mpagr), 12912 MLXSW_REG(momte), 12913 MLXSW_REG(mtpppc), 12914 MLXSW_REG(mtpptr), 12915 MLXSW_REG(mtptpt), 12916 MLXSW_REG(mtpcpc), 12917 MLXSW_REG(mfgd), 12918 MLXSW_REG(mgpir), 12919 MLXSW_REG(mbct), 12920 MLXSW_REG(mddt), 12921 MLXSW_REG(mddq), 12922 MLXSW_REG(mddc), 12923 MLXSW_REG(mfde), 12924 MLXSW_REG(tngcr), 12925 MLXSW_REG(tnumt), 12926 MLXSW_REG(tnqcr), 12927 MLXSW_REG(tnqdr), 12928 MLXSW_REG(tneem), 12929 MLXSW_REG(tndem), 12930 MLXSW_REG(tnpc), 12931 MLXSW_REG(tigcr), 12932 MLXSW_REG(tieem), 12933 MLXSW_REG(tidem), 12934 MLXSW_REG(sbpr), 12935 MLXSW_REG(sbcm), 12936 MLXSW_REG(sbpm), 12937 MLXSW_REG(sbmm), 12938 MLXSW_REG(sbsr), 12939 MLXSW_REG(sbib), 12940 }; 12941 12942 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12943 { 12944 const struct mlxsw_reg_info *reg_info; 12945 int i; 12946 12947 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12948 reg_info = mlxsw_reg_infos[i]; 12949 if (reg_info->id == reg_id) 12950 return reg_info->name; 12951 } 12952 return "*UNKNOWN*"; 12953 } 12954 12955 /* PUDE - Port Up / Down Event 12956 * --------------------------- 12957 * Reports the operational state change of a port. 12958 */ 12959 #define MLXSW_REG_PUDE_LEN 0x10 12960 12961 /* reg_pude_swid 12962 * Switch partition ID with which to associate the port. 12963 * Access: Index 12964 */ 12965 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12966 12967 /* reg_pude_local_port 12968 * Local port number. 12969 * Access: Index 12970 */ 12971 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12972 12973 /* reg_pude_admin_status 12974 * Port administrative state (the desired state). 12975 * 1 - Up. 12976 * 2 - Down. 12977 * 3 - Up once. This means that in case of link failure, the port won't go 12978 * into polling mode, but will wait to be re-enabled by software. 12979 * 4 - Disabled by system. Can only be set by hardware. 12980 * Access: RO 12981 */ 12982 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12983 12984 /* reg_pude_oper_status 12985 * Port operatioanl state. 12986 * 1 - Up. 12987 * 2 - Down. 12988 * 3 - Down by port failure. This means that the device will not let the 12989 * port up again until explicitly specified by software. 12990 * Access: RO 12991 */ 12992 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12993 12994 #endif 12995