1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9 #include <linux/module.h> 10 #include <linux/device.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <net/switchdev.h> 18 #include <linux/etherdevice.h> 19 #include <linux/io.h> 20 #include <linux/printk.h> 21 #include <linux/iopoll.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/reset.h> 26 27 #include "sparx5_main_regs.h" 28 #include "sparx5_main.h" 29 #include "sparx5_port.h" 30 #include "sparx5_qos.h" 31 32 #define QLIM_WM(fraction) \ 33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) 34 #define IO_RANGES 3 35 36 struct initial_port_config { 37 u32 portno; 38 struct device_node *node; 39 struct sparx5_port_config conf; 40 struct phy *serdes; 41 }; 42 43 struct sparx5_ram_config { 44 void __iomem *init_reg; 45 u32 init_val; 46 }; 47 48 struct sparx5_main_io_resource { 49 enum sparx5_target id; 50 phys_addr_t offset; 51 int range; 52 }; 53 54 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 65 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 66 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 67 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 68 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 69 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 70 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 71 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 72 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 73 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 74 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 75 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 76 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 77 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 78 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 79 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 80 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 81 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 82 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 83 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 84 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 85 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 86 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 87 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 88 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 89 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 90 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 91 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 92 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 93 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 94 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 95 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 96 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 97 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 98 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 99 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 100 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 101 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 102 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 103 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 104 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 105 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 106 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 107 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 108 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 109 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 110 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 111 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 112 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 113 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 114 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 115 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 116 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 117 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 118 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 119 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 120 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 121 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 122 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 123 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 124 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 125 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 126 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 127 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 128 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 129 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 130 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 131 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 132 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 133 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 134 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 135 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 136 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 137 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 138 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 139 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 140 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 141 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 142 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 143 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 144 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 145 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 146 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 147 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 148 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 149 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 150 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 151 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 152 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 153 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 154 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 155 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 156 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 157 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 158 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 159 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 160 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 161 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 162 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 163 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 164 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 165 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 166 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 167 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 168 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 169 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 170 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 171 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 172 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 173 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 174 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 175 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 176 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 177 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 178 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 179 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 180 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 181 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 182 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 183 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 184 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 185 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 186 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 187 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 188 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 189 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 190 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 191 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 192 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 193 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 194 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */ 195 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 196 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 197 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 198 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 199 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 200 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 201 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 202 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 203 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 204 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 205 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 206 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 207 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 208 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 209 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 210 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 211 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 212 }; 213 214 static int sparx5_create_targets(struct sparx5 *sparx5) 215 { 216 struct resource *iores[IO_RANGES]; 217 void __iomem *iomem[IO_RANGES]; 218 void __iomem *begin[IO_RANGES]; 219 int range_id[IO_RANGES]; 220 int idx, jdx; 221 222 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 223 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 224 225 if (idx == iomap->range) { 226 range_id[idx] = jdx; 227 idx++; 228 } 229 } 230 for (idx = 0; idx < IO_RANGES; idx++) { 231 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 232 idx); 233 if (!iores[idx]) { 234 dev_err(sparx5->dev, "Invalid resource\n"); 235 return -EINVAL; 236 } 237 iomem[idx] = devm_ioremap(sparx5->dev, 238 iores[idx]->start, 239 resource_size(iores[idx])); 240 if (!iomem[idx]) { 241 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 242 iores[idx]->name); 243 return -ENOMEM; 244 } 245 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; 246 } 247 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 248 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 249 250 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; 251 } 252 return 0; 253 } 254 255 static int sparx5_create_port(struct sparx5 *sparx5, 256 struct initial_port_config *config) 257 { 258 struct sparx5_port *spx5_port; 259 struct net_device *ndev; 260 struct phylink *phylink; 261 int err; 262 263 ndev = sparx5_create_netdev(sparx5, config->portno); 264 if (IS_ERR(ndev)) { 265 dev_err(sparx5->dev, "Could not create net device: %02u\n", 266 config->portno); 267 return PTR_ERR(ndev); 268 } 269 spx5_port = netdev_priv(ndev); 270 spx5_port->of_node = config->node; 271 spx5_port->serdes = config->serdes; 272 spx5_port->pvid = NULL_VID; 273 spx5_port->signd_internal = true; 274 spx5_port->signd_active_high = true; 275 spx5_port->signd_enable = true; 276 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 277 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 278 spx5_port->custom_etype = 0x8880; /* Vitesse */ 279 spx5_port->phylink_pcs.poll = true; 280 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 281 spx5_port->is_mrouter = false; 282 sparx5->ports[config->portno] = spx5_port; 283 284 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 285 if (err) { 286 dev_err(sparx5->dev, "port init failed\n"); 287 return err; 288 } 289 spx5_port->conf = config->conf; 290 291 /* Setup VLAN */ 292 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 293 294 /* Create a phylink for PHY management. Also handles SFPs */ 295 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 296 spx5_port->phylink_config.type = PHYLINK_NETDEV; 297 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 298 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | 299 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; 300 301 __set_bit(PHY_INTERFACE_MODE_SGMII, 302 spx5_port->phylink_config.supported_interfaces); 303 __set_bit(PHY_INTERFACE_MODE_QSGMII, 304 spx5_port->phylink_config.supported_interfaces); 305 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 306 spx5_port->phylink_config.supported_interfaces); 307 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 308 spx5_port->phylink_config.supported_interfaces); 309 310 if (spx5_port->conf.bandwidth == SPEED_5000 || 311 spx5_port->conf.bandwidth == SPEED_10000 || 312 spx5_port->conf.bandwidth == SPEED_25000) 313 __set_bit(PHY_INTERFACE_MODE_5GBASER, 314 spx5_port->phylink_config.supported_interfaces); 315 316 if (spx5_port->conf.bandwidth == SPEED_10000 || 317 spx5_port->conf.bandwidth == SPEED_25000) 318 __set_bit(PHY_INTERFACE_MODE_10GBASER, 319 spx5_port->phylink_config.supported_interfaces); 320 321 if (spx5_port->conf.bandwidth == SPEED_25000) 322 __set_bit(PHY_INTERFACE_MODE_25GBASER, 323 spx5_port->phylink_config.supported_interfaces); 324 325 phylink = phylink_create(&spx5_port->phylink_config, 326 of_fwnode_handle(config->node), 327 config->conf.phy_mode, 328 &sparx5_phylink_mac_ops); 329 if (IS_ERR(phylink)) 330 return PTR_ERR(phylink); 331 332 spx5_port->phylink = phylink; 333 334 return 0; 335 } 336 337 static int sparx5_init_ram(struct sparx5 *s5) 338 { 339 const struct sparx5_ram_config spx5_ram_cfg[] = { 340 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 341 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 342 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 343 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 344 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 345 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 346 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 347 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 348 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 349 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 350 }; 351 const struct sparx5_ram_config *cfg; 352 u32 value, pending, jdx, idx; 353 354 for (jdx = 0; jdx < 10; jdx++) { 355 pending = ARRAY_SIZE(spx5_ram_cfg); 356 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 357 cfg = &spx5_ram_cfg[idx]; 358 if (jdx == 0) { 359 writel(cfg->init_val, cfg->init_reg); 360 } else { 361 value = readl(cfg->init_reg); 362 if ((value & cfg->init_val) != cfg->init_val) 363 pending--; 364 } 365 } 366 if (!pending) 367 break; 368 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 369 } 370 371 if (pending > 0) { 372 /* Still initializing, should be complete in 373 * less than 1ms 374 */ 375 dev_err(s5->dev, "Memory initialization error\n"); 376 return -EINVAL; 377 } 378 return 0; 379 } 380 381 static int sparx5_init_switchcore(struct sparx5 *sparx5) 382 { 383 u32 value; 384 int err = 0; 385 386 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 387 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 388 sparx5, 389 EACL_POL_EACL_CFG); 390 391 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 392 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 393 sparx5, 394 EACL_POL_EACL_CFG); 395 396 /* Initialize memories, if not done already */ 397 value = spx5_rd(sparx5, HSCH_RESET_CFG); 398 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 399 err = sparx5_init_ram(sparx5); 400 if (err) 401 return err; 402 } 403 404 /* Reset counters */ 405 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 406 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 407 408 /* Enable switch-core and queue system */ 409 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 410 411 return 0; 412 } 413 414 static int sparx5_init_coreclock(struct sparx5 *sparx5) 415 { 416 enum sparx5_core_clockfreq freq = sparx5->coreclock; 417 u32 clk_div, clk_period, pol_upd_int, idx; 418 419 /* Verify if core clock frequency is supported on target. 420 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 421 * freq. is used 422 */ 423 switch (sparx5->target_ct) { 424 case SPX5_TARGET_CT_7546: 425 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 426 freq = SPX5_CORE_CLOCK_250MHZ; 427 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 428 freq = 0; /* Not supported */ 429 break; 430 case SPX5_TARGET_CT_7549: 431 case SPX5_TARGET_CT_7552: 432 case SPX5_TARGET_CT_7556: 433 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 434 freq = SPX5_CORE_CLOCK_500MHZ; 435 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 436 freq = 0; /* Not supported */ 437 break; 438 case SPX5_TARGET_CT_7558: 439 case SPX5_TARGET_CT_7558TSN: 440 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 441 freq = SPX5_CORE_CLOCK_625MHZ; 442 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 443 freq = 0; /* Not supported */ 444 break; 445 case SPX5_TARGET_CT_7546TSN: 446 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 447 freq = SPX5_CORE_CLOCK_625MHZ; 448 break; 449 case SPX5_TARGET_CT_7549TSN: 450 case SPX5_TARGET_CT_7552TSN: 451 case SPX5_TARGET_CT_7556TSN: 452 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 453 freq = SPX5_CORE_CLOCK_625MHZ; 454 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 455 freq = 0; /* Not supported */ 456 break; 457 default: 458 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 459 sparx5->target_ct); 460 return -ENODEV; 461 } 462 463 switch (freq) { 464 case SPX5_CORE_CLOCK_250MHZ: 465 clk_div = 10; 466 pol_upd_int = 312; 467 break; 468 case SPX5_CORE_CLOCK_500MHZ: 469 clk_div = 5; 470 pol_upd_int = 624; 471 break; 472 case SPX5_CORE_CLOCK_625MHZ: 473 clk_div = 4; 474 pol_upd_int = 780; 475 break; 476 default: 477 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", 478 sparx5->coreclock, sparx5->target_ct); 479 return -EINVAL; 480 } 481 482 /* Update state with chosen frequency */ 483 sparx5->coreclock = freq; 484 485 /* Configure the LCPLL */ 486 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 487 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 488 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 489 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 490 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 491 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 492 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 493 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 494 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 495 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 496 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 497 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 498 sparx5, 499 CLKGEN_LCPLL1_CORE_CLK_CFG); 500 501 clk_period = sparx5_clk_period(freq); 502 503 spx5_rmw(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(clk_period / 100), 504 HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, 505 sparx5, 506 HSCH_SYS_CLK_PER); 507 508 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 509 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 510 sparx5, 511 ANA_AC_POL_BDLB_DLB_CTRL); 512 513 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 514 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 515 sparx5, 516 ANA_AC_POL_SLB_DLB_CTRL); 517 518 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 519 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 520 sparx5, 521 LRN_AUTOAGE_CFG_1); 522 523 for (idx = 0; idx < 3; idx++) 524 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 525 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 526 sparx5, 527 GCB_SIO_CLOCK(idx)); 528 529 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 530 ((256 * 1000) / clk_period), 531 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 532 sparx5, 533 HSCH_TAS_STATEMACHINE_CFG); 534 535 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 536 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 537 sparx5, 538 ANA_AC_POL_POL_UPD_INT_CFG); 539 540 return 0; 541 } 542 543 static int sparx5_qlim_set(struct sparx5 *sparx5) 544 { 545 u32 res, dp, prio; 546 547 for (res = 0; res < 2; res++) { 548 for (prio = 0; prio < 8; prio++) 549 spx5_wr(0xFFF, sparx5, 550 QRES_RES_CFG(prio + 630 + res * 1024)); 551 552 for (dp = 0; dp < 4; dp++) 553 spx5_wr(0xFFF, sparx5, 554 QRES_RES_CFG(dp + 638 + res * 1024)); 555 } 556 557 /* Set 80,90,95,100% of memory size for top watermarks */ 558 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 559 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 560 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 561 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 562 563 return 0; 564 } 565 566 /* Some boards needs to map the SGPIO for signal detect explicitly to the 567 * port module 568 */ 569 static void sparx5_board_init(struct sparx5 *sparx5) 570 { 571 int idx; 572 573 if (!sparx5->sd_sgpio_remapping) 574 return; 575 576 /* Enable SGPIO Signal Detect remapping */ 577 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 578 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 579 sparx5, 580 GCB_HW_SGPIO_SD_CFG); 581 582 /* Refer to LOS SGPIO */ 583 for (idx = 0; idx < SPX5_PORTS; idx++) 584 if (sparx5->ports[idx]) 585 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 586 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 587 sparx5, 588 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 589 } 590 591 static int sparx5_start(struct sparx5 *sparx5) 592 { 593 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 594 char queue_name[32]; 595 u32 idx; 596 int err; 597 598 /* Setup own UPSIDs */ 599 for (idx = 0; idx < 3; idx++) { 600 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 601 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 602 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 603 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 604 } 605 606 /* Enable CPU ports */ 607 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) 608 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 609 QFWD_SWITCH_PORT_MODE_PORT_ENA, 610 sparx5, 611 QFWD_SWITCH_PORT_MODE(idx)); 612 613 /* Init masks */ 614 sparx5_update_fwd(sparx5); 615 616 /* CPU copy CPU pgids */ 617 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 618 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); 619 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 620 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); 621 622 /* Recalc injected frame FCS */ 623 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) 624 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 625 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 626 sparx5, ANA_CL_FILTER_CTRL(idx)); 627 628 /* Init MAC table, ageing */ 629 sparx5_mact_init(sparx5); 630 631 /* Init PGID table arbitrator */ 632 sparx5_pgid_init(sparx5); 633 634 /* Setup VLANs */ 635 sparx5_vlan_init(sparx5); 636 637 /* Add host mode BC address (points only to CPU) */ 638 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); 639 640 /* Enable queue limitation watermarks */ 641 sparx5_qlim_set(sparx5); 642 643 err = sparx5_config_auto_calendar(sparx5); 644 if (err) 645 return err; 646 647 err = sparx5_config_dsm_calendar(sparx5); 648 if (err) 649 return err; 650 651 /* Init stats */ 652 err = sparx_stats_init(sparx5); 653 if (err) 654 return err; 655 656 /* Init mact_sw struct */ 657 mutex_init(&sparx5->mact_lock); 658 INIT_LIST_HEAD(&sparx5->mact_entries); 659 snprintf(queue_name, sizeof(queue_name), "%s-mact", 660 dev_name(sparx5->dev)); 661 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 662 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 663 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 664 SPX5_MACT_PULL_DELAY); 665 666 mutex_init(&sparx5->mdb_lock); 667 INIT_LIST_HEAD(&sparx5->mdb_entries); 668 669 err = sparx5_register_netdevs(sparx5); 670 if (err) 671 return err; 672 673 sparx5_board_init(sparx5); 674 err = sparx5_register_notifier_blocks(sparx5); 675 676 /* Start Frame DMA with fallback to register based INJ/XTR */ 677 err = -ENXIO; 678 if (sparx5->fdma_irq >= 0) { 679 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) 680 err = devm_request_threaded_irq(sparx5->dev, 681 sparx5->fdma_irq, 682 NULL, 683 sparx5_fdma_handler, 684 IRQF_ONESHOT, 685 "sparx5-fdma", sparx5); 686 if (!err) 687 err = sparx5_fdma_start(sparx5); 688 if (err) 689 sparx5->fdma_irq = -ENXIO; 690 } else { 691 sparx5->fdma_irq = -ENXIO; 692 } 693 if (err && sparx5->xtr_irq >= 0) { 694 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 695 sparx5_xtr_handler, IRQF_SHARED, 696 "sparx5-xtr", sparx5); 697 if (!err) 698 err = sparx5_manual_injection_mode(sparx5); 699 if (err) 700 sparx5->xtr_irq = -ENXIO; 701 } else { 702 sparx5->xtr_irq = -ENXIO; 703 } 704 705 if (sparx5->ptp_irq >= 0) { 706 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 707 NULL, sparx5_ptp_irq_handler, 708 IRQF_ONESHOT, "sparx5-ptp", 709 sparx5); 710 if (err) 711 sparx5->ptp_irq = -ENXIO; 712 713 sparx5->ptp = 1; 714 } 715 716 return err; 717 } 718 719 static void sparx5_cleanup_ports(struct sparx5 *sparx5) 720 { 721 sparx5_unregister_netdevs(sparx5); 722 sparx5_destroy_netdevs(sparx5); 723 } 724 725 static int mchp_sparx5_probe(struct platform_device *pdev) 726 { 727 struct initial_port_config *configs, *config; 728 struct device_node *np = pdev->dev.of_node; 729 struct device_node *ports, *portnp; 730 struct reset_control *reset; 731 struct sparx5 *sparx5; 732 int idx = 0, err = 0; 733 734 if (!np && !pdev->dev.platform_data) 735 return -ENODEV; 736 737 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 738 if (!sparx5) 739 return -ENOMEM; 740 741 platform_set_drvdata(pdev, sparx5); 742 sparx5->pdev = pdev; 743 sparx5->dev = &pdev->dev; 744 745 /* Do switch core reset if available */ 746 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 747 if (IS_ERR(reset)) 748 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 749 "Failed to get switch reset controller.\n"); 750 reset_control_reset(reset); 751 752 /* Default values, some from DT */ 753 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 754 755 ports = of_get_child_by_name(np, "ethernet-ports"); 756 if (!ports) { 757 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 758 return -ENODEV; 759 } 760 sparx5->port_count = of_get_child_count(ports); 761 762 configs = kcalloc(sparx5->port_count, 763 sizeof(struct initial_port_config), GFP_KERNEL); 764 if (!configs) { 765 err = -ENOMEM; 766 goto cleanup_pnode; 767 } 768 769 for_each_available_child_of_node(ports, portnp) { 770 struct sparx5_port_config *conf; 771 struct phy *serdes; 772 u32 portno; 773 774 err = of_property_read_u32(portnp, "reg", &portno); 775 if (err) { 776 dev_err(sparx5->dev, "port reg property error\n"); 777 continue; 778 } 779 config = &configs[idx]; 780 conf = &config->conf; 781 conf->speed = SPEED_UNKNOWN; 782 conf->bandwidth = SPEED_UNKNOWN; 783 err = of_get_phy_mode(portnp, &conf->phy_mode); 784 if (err) { 785 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 786 portno); 787 continue; 788 } 789 err = of_property_read_u32(portnp, "microchip,bandwidth", 790 &conf->bandwidth); 791 if (err) { 792 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 793 portno); 794 continue; 795 } 796 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 797 if (err) 798 conf->sd_sgpio = ~0; 799 else 800 sparx5->sd_sgpio_remapping = true; 801 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 802 if (IS_ERR(serdes)) { 803 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), 804 "port %u: missing serdes\n", 805 portno); 806 of_node_put(portnp); 807 goto cleanup_config; 808 } 809 config->portno = portno; 810 config->node = portnp; 811 config->serdes = serdes; 812 813 conf->media = PHY_MEDIA_DAC; 814 conf->serdes_reset = true; 815 conf->portmode = conf->phy_mode; 816 conf->power_down = true; 817 idx++; 818 } 819 820 err = sparx5_create_targets(sparx5); 821 if (err) 822 goto cleanup_config; 823 824 if (!of_get_mac_address(np, sparx5->base_mac)) { 825 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 826 eth_random_addr(sparx5->base_mac); 827 sparx5->base_mac[5] = 0; 828 } 829 830 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 831 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 832 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); 833 834 /* Read chip ID to check CPU interface */ 835 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 836 837 sparx5->target_ct = (enum spx5_target_chiptype) 838 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 839 840 /* Initialize Switchcore and internal RAMs */ 841 err = sparx5_init_switchcore(sparx5); 842 if (err) { 843 dev_err(sparx5->dev, "Switchcore initialization error\n"); 844 goto cleanup_config; 845 } 846 847 /* Initialize the LC-PLL (core clock) and set affected registers */ 848 err = sparx5_init_coreclock(sparx5); 849 if (err) { 850 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 851 goto cleanup_config; 852 } 853 854 for (idx = 0; idx < sparx5->port_count; ++idx) { 855 config = &configs[idx]; 856 if (!config->node) 857 continue; 858 859 err = sparx5_create_port(sparx5, config); 860 if (err) { 861 dev_err(sparx5->dev, "port create error\n"); 862 goto cleanup_ports; 863 } 864 } 865 866 err = sparx5_start(sparx5); 867 if (err) { 868 dev_err(sparx5->dev, "Start failed\n"); 869 goto cleanup_ports; 870 } 871 872 err = sparx5_qos_init(sparx5); 873 if (err) { 874 dev_err(sparx5->dev, "Failed to initialize QoS\n"); 875 goto cleanup_ports; 876 } 877 878 err = sparx5_ptp_init(sparx5); 879 if (err) { 880 dev_err(sparx5->dev, "PTP failed\n"); 881 goto cleanup_ports; 882 } 883 goto cleanup_config; 884 885 cleanup_ports: 886 sparx5_cleanup_ports(sparx5); 887 cleanup_config: 888 kfree(configs); 889 cleanup_pnode: 890 of_node_put(ports); 891 return err; 892 } 893 894 static int mchp_sparx5_remove(struct platform_device *pdev) 895 { 896 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 897 898 if (sparx5->xtr_irq) { 899 disable_irq(sparx5->xtr_irq); 900 sparx5->xtr_irq = -ENXIO; 901 } 902 if (sparx5->fdma_irq) { 903 disable_irq(sparx5->fdma_irq); 904 sparx5->fdma_irq = -ENXIO; 905 } 906 sparx5_ptp_deinit(sparx5); 907 sparx5_fdma_stop(sparx5); 908 sparx5_cleanup_ports(sparx5); 909 /* Unregister netdevs */ 910 sparx5_unregister_notifier_blocks(sparx5); 911 912 return 0; 913 } 914 915 static const struct of_device_id mchp_sparx5_match[] = { 916 { .compatible = "microchip,sparx5-switch" }, 917 { } 918 }; 919 MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 920 921 static struct platform_driver mchp_sparx5_driver = { 922 .probe = mchp_sparx5_probe, 923 .remove = mchp_sparx5_remove, 924 .driver = { 925 .name = "sparx5-switch", 926 .of_match_table = mchp_sparx5_match, 927 }, 928 }; 929 930 module_platform_driver(mchp_sparx5_driver); 931 932 MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 933 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 934 MODULE_LICENSE("Dual MIT/GPL"); 935