1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/skbuff.h> 19 #include <linux/iopoll.h> 20 #include <net/arp.h> 21 #include <net/netevent.h> 22 #include <net/rtnetlink.h> 23 #include <net/switchdev.h> 24 25 #include "ocelot.h" 26 #include "ocelot_ace.h" 27 28 #define TABLE_UPDATE_SLEEP_US 10 29 #define TABLE_UPDATE_TIMEOUT_US 100000 30 31 /* MAC table entry types. 32 * ENTRYTYPE_NORMAL is subject to aging. 33 * ENTRYTYPE_LOCKED is not subject to aging. 34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 36 */ 37 enum macaccess_entry_type { 38 ENTRYTYPE_NORMAL = 0, 39 ENTRYTYPE_LOCKED, 40 ENTRYTYPE_MACv4, 41 ENTRYTYPE_MACv6, 42 }; 43 44 struct ocelot_mact_entry { 45 u8 mac[ETH_ALEN]; 46 u16 vid; 47 enum macaccess_entry_type type; 48 }; 49 50 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 51 { 52 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 53 } 54 55 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 56 { 57 u32 val; 58 59 return readx_poll_timeout(ocelot_mact_read_macaccess, 60 ocelot, val, 61 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 62 MACACCESS_CMD_IDLE, 63 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 64 } 65 66 static void ocelot_mact_select(struct ocelot *ocelot, 67 const unsigned char mac[ETH_ALEN], 68 unsigned int vid) 69 { 70 u32 macl = 0, mach = 0; 71 72 /* Set the MAC address to handle and the vlan associated in a format 73 * understood by the hardware. 74 */ 75 mach |= vid << 16; 76 mach |= mac[0] << 8; 77 mach |= mac[1] << 0; 78 macl |= mac[2] << 24; 79 macl |= mac[3] << 16; 80 macl |= mac[4] << 8; 81 macl |= mac[5] << 0; 82 83 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 84 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 85 86 } 87 88 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 89 const unsigned char mac[ETH_ALEN], 90 unsigned int vid, 91 enum macaccess_entry_type type) 92 { 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 97 ANA_TABLES_MACACCESS_DEST_IDX(port) | 98 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 100 ANA_TABLES_MACACCESS); 101 102 return ocelot_mact_wait_for_completion(ocelot); 103 } 104 105 static int ocelot_mact_forget(struct ocelot *ocelot, 106 const unsigned char mac[ETH_ALEN], 107 unsigned int vid) 108 { 109 ocelot_mact_select(ocelot, mac, vid); 110 111 /* Issue a forget command */ 112 ocelot_write(ocelot, 113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 114 ANA_TABLES_MACACCESS); 115 116 return ocelot_mact_wait_for_completion(ocelot); 117 } 118 119 static void ocelot_mact_init(struct ocelot *ocelot) 120 { 121 /* Configure the learning mode entries attributes: 122 * - Do not copy the frame to the CPU extraction queues. 123 * - Use the vlan and mac_cpoy for dmac lookup. 124 */ 125 ocelot_rmw(ocelot, 0, 126 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 127 | ANA_AGENCTRL_LEARN_FWD_KILL 128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 129 ANA_AGENCTRL); 130 131 /* Clear the MAC table */ 132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 133 } 134 135 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 136 { 137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 139 ANA_PORT_VCAP_S2_CFG, port); 140 } 141 142 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 143 { 144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 145 } 146 147 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 148 { 149 u32 val; 150 151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 152 ocelot, 153 val, 154 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 155 ANA_TABLES_VLANACCESS_CMD_IDLE, 156 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 157 } 158 159 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 160 { 161 /* Select the VID to configure */ 162 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 163 ANA_TABLES_VLANTIDX); 164 /* Set the vlan port members mask and issue a write command */ 165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 166 ANA_TABLES_VLANACCESS_CMD_WRITE, 167 ANA_TABLES_VLANACCESS); 168 169 return ocelot_vlant_wait_for_completion(ocelot); 170 } 171 172 static void ocelot_vlan_mode(struct ocelot *ocelot, int port, 173 netdev_features_t features) 174 { 175 u32 val; 176 177 /* Filtering */ 178 val = ocelot_read(ocelot, ANA_VLANMASK); 179 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 180 val |= BIT(port); 181 else 182 val &= ~BIT(port); 183 ocelot_write(ocelot, val, ANA_VLANMASK); 184 } 185 186 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 187 bool vlan_aware) 188 { 189 struct ocelot_port *ocelot_port = ocelot->ports[port]; 190 u32 val; 191 192 if (vlan_aware) 193 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 194 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 195 else 196 val = 0; 197 ocelot_rmw_gix(ocelot, val, 198 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 199 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 200 ANA_PORT_VLAN_CFG, port); 201 202 if (vlan_aware && !ocelot_port->vid) 203 /* If port is vlan-aware and tagged, drop untagged and priority 204 * tagged frames. 205 */ 206 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 207 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 208 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 209 else 210 val = 0; 211 ocelot_rmw_gix(ocelot, val, 212 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 215 ANA_PORT_DROP_CFG, port); 216 217 if (vlan_aware) { 218 if (ocelot_port->vid) 219 /* Tag all frames except when VID == DEFAULT_VLAN */ 220 val |= REW_TAG_CFG_TAG_CFG(1); 221 else 222 /* Tag all frames */ 223 val |= REW_TAG_CFG_TAG_CFG(3); 224 } else { 225 /* Port tagging disabled. */ 226 val = REW_TAG_CFG_TAG_CFG(0); 227 } 228 ocelot_rmw_gix(ocelot, val, 229 REW_TAG_CFG_TAG_CFG_M, 230 REW_TAG_CFG, port); 231 } 232 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 233 234 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 235 u16 vid) 236 { 237 struct ocelot_port *ocelot_port = ocelot->ports[port]; 238 239 if (ocelot_port->vid != vid) { 240 /* Always permit deleting the native VLAN (vid = 0) */ 241 if (ocelot_port->vid && vid) { 242 dev_err(ocelot->dev, 243 "Port already has a native VLAN: %d\n", 244 ocelot_port->vid); 245 return -EBUSY; 246 } 247 ocelot_port->vid = vid; 248 } 249 250 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 251 REW_PORT_VLAN_CFG_PORT_VID_M, 252 REW_PORT_VLAN_CFG, port); 253 254 return 0; 255 } 256 257 /* Default vlan to clasify for untagged frames (may be zero) */ 258 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 259 { 260 struct ocelot_port *ocelot_port = ocelot->ports[port]; 261 262 ocelot_rmw_gix(ocelot, 263 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 264 ANA_PORT_VLAN_CFG_VLAN_VID_M, 265 ANA_PORT_VLAN_CFG, port); 266 267 ocelot_port->pvid = pvid; 268 } 269 270 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 271 bool untagged) 272 { 273 int ret; 274 275 /* Make the port a member of the VLAN */ 276 ocelot->vlan_mask[vid] |= BIT(port); 277 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 278 if (ret) 279 return ret; 280 281 /* Default ingress vlan classification */ 282 if (pvid) 283 ocelot_port_set_pvid(ocelot, port, vid); 284 285 /* Untagged egress vlan clasification */ 286 if (untagged) { 287 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 288 if (ret) 289 return ret; 290 } 291 292 return 0; 293 } 294 EXPORT_SYMBOL(ocelot_vlan_add); 295 296 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 297 bool untagged) 298 { 299 struct ocelot_port_private *priv = netdev_priv(dev); 300 struct ocelot_port *ocelot_port = &priv->port; 301 struct ocelot *ocelot = ocelot_port->ocelot; 302 int port = priv->chip_port; 303 int ret; 304 305 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged); 306 if (ret) 307 return ret; 308 309 /* Add the port MAC address to with the right VLAN information */ 310 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 311 ENTRYTYPE_LOCKED); 312 313 return 0; 314 } 315 316 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 317 { 318 struct ocelot_port *ocelot_port = ocelot->ports[port]; 319 int ret; 320 321 /* Stop the port from being a member of the vlan */ 322 ocelot->vlan_mask[vid] &= ~BIT(port); 323 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 324 if (ret) 325 return ret; 326 327 /* Ingress */ 328 if (ocelot_port->pvid == vid) 329 ocelot_port_set_pvid(ocelot, port, 0); 330 331 /* Egress */ 332 if (ocelot_port->vid == vid) 333 ocelot_port_set_native_vlan(ocelot, port, 0); 334 335 return 0; 336 } 337 EXPORT_SYMBOL(ocelot_vlan_del); 338 339 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 340 { 341 struct ocelot_port_private *priv = netdev_priv(dev); 342 struct ocelot *ocelot = priv->port.ocelot; 343 int port = priv->chip_port; 344 int ret; 345 346 /* 8021q removes VID 0 on module unload for all interfaces 347 * with VLAN filtering feature. We need to keep it to receive 348 * untagged traffic. 349 */ 350 if (vid == 0) 351 return 0; 352 353 ret = ocelot_vlan_del(ocelot, port, vid); 354 if (ret) 355 return ret; 356 357 /* Del the port MAC address to with the right VLAN information */ 358 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 359 360 return 0; 361 } 362 363 static void ocelot_vlan_init(struct ocelot *ocelot) 364 { 365 u16 port, vid; 366 367 /* Clear VLAN table, by default all ports are members of all VLANs */ 368 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 369 ANA_TABLES_VLANACCESS); 370 ocelot_vlant_wait_for_completion(ocelot); 371 372 /* Configure the port VLAN memberships */ 373 for (vid = 1; vid < VLAN_N_VID; vid++) { 374 ocelot->vlan_mask[vid] = 0; 375 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 376 } 377 378 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 379 * traffic. It is added automatically if 8021q module is loaded, but 380 * we can't rely on it since module may be not loaded. 381 */ 382 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 383 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 384 385 /* Set vlan ingress filter mask to all ports but the CPU port by 386 * default. 387 */ 388 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 389 ANA_VLANMASK); 390 391 for (port = 0; port < ocelot->num_phys_ports; port++) { 392 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 393 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 394 } 395 } 396 397 /* Watermark encode 398 * Bit 8: Unit; 0:1, 1:16 399 * Bit 7-0: Value to be multiplied with unit 400 */ 401 static u16 ocelot_wm_enc(u16 value) 402 { 403 if (value >= BIT(8)) 404 return BIT(8) | (value / 16); 405 406 return value; 407 } 408 409 void ocelot_adjust_link(struct ocelot *ocelot, int port, 410 struct phy_device *phydev) 411 { 412 struct ocelot_port *ocelot_port = ocelot->ports[port]; 413 int speed, mode = 0; 414 415 switch (phydev->speed) { 416 case SPEED_10: 417 speed = OCELOT_SPEED_10; 418 break; 419 case SPEED_100: 420 speed = OCELOT_SPEED_100; 421 break; 422 case SPEED_1000: 423 speed = OCELOT_SPEED_1000; 424 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 425 break; 426 case SPEED_2500: 427 speed = OCELOT_SPEED_2500; 428 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 429 break; 430 default: 431 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 432 port, phydev->speed); 433 return; 434 } 435 436 phy_print_status(phydev); 437 438 if (!phydev->link) 439 return; 440 441 /* Only full duplex supported for now */ 442 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 443 mode, DEV_MAC_MODE_CFG); 444 445 if (ocelot->ops->pcs_init) 446 ocelot->ops->pcs_init(ocelot, port); 447 448 /* Enable MAC module */ 449 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 450 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 451 452 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 453 * reset */ 454 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 455 DEV_CLOCK_CFG); 456 457 /* No PFC */ 458 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 459 ANA_PFC_PFC_CFG, port); 460 461 /* Core: Enable port for frame transfer */ 462 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 463 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 464 QSYS_SWITCH_PORT_MODE_PORT_ENA, 465 QSYS_SWITCH_PORT_MODE, port); 466 467 /* Flow control */ 468 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 469 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 470 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 471 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 472 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 473 SYS_MAC_FC_CFG, port); 474 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 475 } 476 EXPORT_SYMBOL(ocelot_adjust_link); 477 478 static void ocelot_port_adjust_link(struct net_device *dev) 479 { 480 struct ocelot_port_private *priv = netdev_priv(dev); 481 struct ocelot *ocelot = priv->port.ocelot; 482 int port = priv->chip_port; 483 484 ocelot_adjust_link(ocelot, port, dev->phydev); 485 } 486 487 void ocelot_port_enable(struct ocelot *ocelot, int port, 488 struct phy_device *phy) 489 { 490 /* Enable receiving frames on the port, and activate auto-learning of 491 * MAC addresses. 492 */ 493 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 494 ANA_PORT_PORT_CFG_RECV_ENA | 495 ANA_PORT_PORT_CFG_PORTID_VAL(port), 496 ANA_PORT_PORT_CFG, port); 497 } 498 EXPORT_SYMBOL(ocelot_port_enable); 499 500 static int ocelot_port_open(struct net_device *dev) 501 { 502 struct ocelot_port_private *priv = netdev_priv(dev); 503 struct ocelot *ocelot = priv->port.ocelot; 504 int port = priv->chip_port; 505 int err; 506 507 if (priv->serdes) { 508 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET, 509 priv->phy_mode); 510 if (err) { 511 netdev_err(dev, "Could not set mode of SerDes\n"); 512 return err; 513 } 514 } 515 516 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link, 517 priv->phy_mode); 518 if (err) { 519 netdev_err(dev, "Could not attach to PHY\n"); 520 return err; 521 } 522 523 dev->phydev = priv->phy; 524 525 phy_attached_info(priv->phy); 526 phy_start(priv->phy); 527 528 ocelot_port_enable(ocelot, port, priv->phy); 529 530 return 0; 531 } 532 533 void ocelot_port_disable(struct ocelot *ocelot, int port) 534 { 535 struct ocelot_port *ocelot_port = ocelot->ports[port]; 536 537 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 538 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 539 QSYS_SWITCH_PORT_MODE, port); 540 } 541 EXPORT_SYMBOL(ocelot_port_disable); 542 543 static int ocelot_port_stop(struct net_device *dev) 544 { 545 struct ocelot_port_private *priv = netdev_priv(dev); 546 struct ocelot *ocelot = priv->port.ocelot; 547 int port = priv->chip_port; 548 549 phy_disconnect(priv->phy); 550 551 dev->phydev = NULL; 552 553 ocelot_port_disable(ocelot, port); 554 555 return 0; 556 } 557 558 /* Generate the IFH for frame injection 559 * 560 * The IFH is a 128bit-value 561 * bit 127: bypass the analyzer processing 562 * bit 56-67: destination mask 563 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 564 * bit 20-27: cpu extraction queue mask 565 * bit 16: tag type 0: C-tag, 1: S-tag 566 * bit 0-11: VID 567 */ 568 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 569 { 570 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 571 ifh[1] = (0xf00 & info->port) >> 8; 572 ifh[2] = (0xff & info->port) << 24; 573 ifh[3] = (info->tag_type << 16) | info->vid; 574 575 return 0; 576 } 577 578 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 579 struct sk_buff *skb) 580 { 581 struct skb_shared_info *shinfo = skb_shinfo(skb); 582 struct ocelot *ocelot = ocelot_port->ocelot; 583 584 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 585 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 586 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 587 /* Store timestamp ID in cb[0] of sk_buff */ 588 skb->cb[0] = ocelot_port->ts_id % 4; 589 skb_queue_tail(&ocelot_port->tx_skbs, skb); 590 return 0; 591 } 592 return -ENODATA; 593 } 594 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 595 596 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 597 { 598 struct ocelot_port_private *priv = netdev_priv(dev); 599 struct skb_shared_info *shinfo = skb_shinfo(skb); 600 struct ocelot_port *ocelot_port = &priv->port; 601 struct ocelot *ocelot = ocelot_port->ocelot; 602 u32 val, ifh[OCELOT_TAG_LEN / 4]; 603 struct frame_info info = {}; 604 u8 grp = 0; /* Send everything on CPU group 0 */ 605 unsigned int i, count, last; 606 int port = priv->chip_port; 607 608 val = ocelot_read(ocelot, QS_INJ_STATUS); 609 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 610 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 611 return NETDEV_TX_BUSY; 612 613 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 614 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 615 616 info.port = BIT(port); 617 info.tag_type = IFH_TAG_TYPE_C; 618 info.vid = skb_vlan_tag_get(skb); 619 620 /* Check if timestamping is needed */ 621 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 622 info.rew_op = ocelot_port->ptp_cmd; 623 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 624 info.rew_op |= (ocelot_port->ts_id % 4) << 3; 625 } 626 627 ocelot_gen_ifh(ifh, &info); 628 629 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 630 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 631 QS_INJ_WR, grp); 632 633 count = (skb->len + 3) / 4; 634 last = skb->len % 4; 635 for (i = 0; i < count; i++) { 636 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 637 } 638 639 /* Add padding */ 640 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 641 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 642 i++; 643 } 644 645 /* Indicate EOF and valid bytes in last word */ 646 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 647 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 648 QS_INJ_CTRL_EOF, 649 QS_INJ_CTRL, grp); 650 651 /* Add dummy CRC */ 652 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 653 skb_tx_timestamp(skb); 654 655 dev->stats.tx_packets++; 656 dev->stats.tx_bytes += skb->len; 657 658 if (!ocelot_port_add_txtstamp_skb(ocelot_port, skb)) { 659 ocelot_port->ts_id++; 660 return NETDEV_TX_OK; 661 } 662 663 dev_kfree_skb_any(skb); 664 return NETDEV_TX_OK; 665 } 666 667 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 668 struct timespec64 *ts) 669 { 670 unsigned long flags; 671 u32 val; 672 673 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 674 675 /* Read current PTP time to get seconds */ 676 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 677 678 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 679 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 680 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 681 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 682 683 /* Read packet HW timestamp from FIFO */ 684 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 685 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 686 687 /* Sec has incremented since the ts was registered */ 688 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 689 ts->tv_sec--; 690 691 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 692 } 693 694 void ocelot_get_txtstamp(struct ocelot *ocelot) 695 { 696 int budget = OCELOT_PTP_QUEUE_SZ; 697 698 while (budget--) { 699 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 700 struct skb_shared_hwtstamps shhwtstamps; 701 struct ocelot_port *port; 702 struct timespec64 ts; 703 unsigned long flags; 704 u32 val, id, txport; 705 706 val = ocelot_read(ocelot, SYS_PTP_STATUS); 707 708 /* Check if a timestamp can be retrieved */ 709 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 710 break; 711 712 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 713 714 /* Retrieve the ts ID and Tx port */ 715 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 716 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 717 718 /* Retrieve its associated skb */ 719 port = ocelot->ports[txport]; 720 721 spin_lock_irqsave(&port->tx_skbs.lock, flags); 722 723 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 724 if (skb->cb[0] != id) 725 continue; 726 __skb_unlink(skb, &port->tx_skbs); 727 skb_match = skb; 728 break; 729 } 730 731 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 732 733 /* Next ts */ 734 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 735 736 if (unlikely(!skb_match)) 737 continue; 738 739 /* Get the h/w timestamp */ 740 ocelot_get_hwtimestamp(ocelot, &ts); 741 742 /* Set the timestamp into the skb */ 743 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 744 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 745 skb_tstamp_tx(skb_match, &shhwtstamps); 746 747 dev_kfree_skb_any(skb_match); 748 } 749 } 750 EXPORT_SYMBOL(ocelot_get_txtstamp); 751 752 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 753 { 754 struct ocelot_port_private *priv = netdev_priv(dev); 755 struct ocelot_port *ocelot_port = &priv->port; 756 struct ocelot *ocelot = ocelot_port->ocelot; 757 758 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid); 759 } 760 761 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 762 { 763 struct ocelot_port_private *priv = netdev_priv(dev); 764 struct ocelot_port *ocelot_port = &priv->port; 765 struct ocelot *ocelot = ocelot_port->ocelot; 766 767 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid, 768 ENTRYTYPE_LOCKED); 769 } 770 771 static void ocelot_set_rx_mode(struct net_device *dev) 772 { 773 struct ocelot_port_private *priv = netdev_priv(dev); 774 struct ocelot *ocelot = priv->port.ocelot; 775 u32 val; 776 int i; 777 778 /* This doesn't handle promiscuous mode because the bridge core is 779 * setting IFF_PROMISC on all slave interfaces and all frames would be 780 * forwarded to the CPU port. 781 */ 782 val = GENMASK(ocelot->num_phys_ports - 1, 0); 783 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 784 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 785 786 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 787 } 788 789 static int ocelot_port_get_phys_port_name(struct net_device *dev, 790 char *buf, size_t len) 791 { 792 struct ocelot_port_private *priv = netdev_priv(dev); 793 int port = priv->chip_port; 794 int ret; 795 796 ret = snprintf(buf, len, "p%d", port); 797 if (ret >= len) 798 return -EINVAL; 799 800 return 0; 801 } 802 803 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 804 { 805 struct ocelot_port_private *priv = netdev_priv(dev); 806 struct ocelot_port *ocelot_port = &priv->port; 807 struct ocelot *ocelot = ocelot_port->ocelot; 808 const struct sockaddr *addr = p; 809 810 /* Learn the new net device MAC address in the mac table. */ 811 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid, 812 ENTRYTYPE_LOCKED); 813 /* Then forget the previous one. */ 814 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid); 815 816 ether_addr_copy(dev->dev_addr, addr->sa_data); 817 return 0; 818 } 819 820 static void ocelot_get_stats64(struct net_device *dev, 821 struct rtnl_link_stats64 *stats) 822 { 823 struct ocelot_port_private *priv = netdev_priv(dev); 824 struct ocelot *ocelot = priv->port.ocelot; 825 int port = priv->chip_port; 826 827 /* Configure the port to read the stats from */ 828 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), 829 SYS_STAT_CFG); 830 831 /* Get Rx stats */ 832 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 833 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 834 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 835 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 836 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 837 ocelot_read(ocelot, SYS_COUNT_RX_64) + 838 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 839 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 840 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 841 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 842 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 843 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 844 stats->rx_dropped = dev->stats.rx_dropped; 845 846 /* Get Tx stats */ 847 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 848 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 849 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 850 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 851 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 852 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 853 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 854 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 855 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 856 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 857 } 858 859 int ocelot_fdb_add(struct ocelot *ocelot, int port, 860 const unsigned char *addr, u16 vid, bool vlan_aware) 861 { 862 struct ocelot_port *ocelot_port = ocelot->ports[port]; 863 864 if (!vid) { 865 if (!vlan_aware) 866 /* If the bridge is not VLAN aware and no VID was 867 * provided, set it to pvid to ensure the MAC entry 868 * matches incoming untagged packets 869 */ 870 vid = ocelot_port->pvid; 871 else 872 /* If the bridge is VLAN aware a VID must be provided as 873 * otherwise the learnt entry wouldn't match any frame. 874 */ 875 return -EINVAL; 876 } 877 878 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 879 } 880 EXPORT_SYMBOL(ocelot_fdb_add); 881 882 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 883 struct net_device *dev, 884 const unsigned char *addr, 885 u16 vid, u16 flags, 886 struct netlink_ext_ack *extack) 887 { 888 struct ocelot_port_private *priv = netdev_priv(dev); 889 struct ocelot *ocelot = priv->port.ocelot; 890 int port = priv->chip_port; 891 892 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware); 893 } 894 895 int ocelot_fdb_del(struct ocelot *ocelot, int port, 896 const unsigned char *addr, u16 vid) 897 { 898 return ocelot_mact_forget(ocelot, addr, vid); 899 } 900 EXPORT_SYMBOL(ocelot_fdb_del); 901 902 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 903 struct net_device *dev, 904 const unsigned char *addr, u16 vid) 905 { 906 struct ocelot_port_private *priv = netdev_priv(dev); 907 struct ocelot *ocelot = priv->port.ocelot; 908 int port = priv->chip_port; 909 910 return ocelot_fdb_del(ocelot, port, addr, vid); 911 } 912 913 struct ocelot_dump_ctx { 914 struct net_device *dev; 915 struct sk_buff *skb; 916 struct netlink_callback *cb; 917 int idx; 918 }; 919 920 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 921 bool is_static, void *data) 922 { 923 struct ocelot_dump_ctx *dump = data; 924 u32 portid = NETLINK_CB(dump->cb->skb).portid; 925 u32 seq = dump->cb->nlh->nlmsg_seq; 926 struct nlmsghdr *nlh; 927 struct ndmsg *ndm; 928 929 if (dump->idx < dump->cb->args[2]) 930 goto skip; 931 932 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 933 sizeof(*ndm), NLM_F_MULTI); 934 if (!nlh) 935 return -EMSGSIZE; 936 937 ndm = nlmsg_data(nlh); 938 ndm->ndm_family = AF_BRIDGE; 939 ndm->ndm_pad1 = 0; 940 ndm->ndm_pad2 = 0; 941 ndm->ndm_flags = NTF_SELF; 942 ndm->ndm_type = 0; 943 ndm->ndm_ifindex = dump->dev->ifindex; 944 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 945 946 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 947 goto nla_put_failure; 948 949 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 950 goto nla_put_failure; 951 952 nlmsg_end(dump->skb, nlh); 953 954 skip: 955 dump->idx++; 956 return 0; 957 958 nla_put_failure: 959 nlmsg_cancel(dump->skb, nlh); 960 return -EMSGSIZE; 961 } 962 963 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 964 struct ocelot_mact_entry *entry) 965 { 966 u32 val, dst, macl, mach; 967 char mac[ETH_ALEN]; 968 969 /* Set row and column to read from */ 970 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 971 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 972 973 /* Issue a read command */ 974 ocelot_write(ocelot, 975 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 976 ANA_TABLES_MACACCESS); 977 978 if (ocelot_mact_wait_for_completion(ocelot)) 979 return -ETIMEDOUT; 980 981 /* Read the entry flags */ 982 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 983 if (!(val & ANA_TABLES_MACACCESS_VALID)) 984 return -EINVAL; 985 986 /* If the entry read has another port configured as its destination, 987 * do not report it. 988 */ 989 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 990 if (dst != port) 991 return -EINVAL; 992 993 /* Get the entry's MAC address and VLAN id */ 994 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 995 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 996 997 mac[0] = (mach >> 8) & 0xff; 998 mac[1] = (mach >> 0) & 0xff; 999 mac[2] = (macl >> 24) & 0xff; 1000 mac[3] = (macl >> 16) & 0xff; 1001 mac[4] = (macl >> 8) & 0xff; 1002 mac[5] = (macl >> 0) & 0xff; 1003 1004 entry->vid = (mach >> 16) & 0xfff; 1005 ether_addr_copy(entry->mac, mac); 1006 1007 return 0; 1008 } 1009 1010 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1011 dsa_fdb_dump_cb_t *cb, void *data) 1012 { 1013 int i, j; 1014 1015 /* Loop through all the mac tables entries. There are 1024 rows of 4 1016 * entries. 1017 */ 1018 for (i = 0; i < 1024; i++) { 1019 for (j = 0; j < 4; j++) { 1020 struct ocelot_mact_entry entry; 1021 bool is_static; 1022 int ret; 1023 1024 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1025 /* If the entry is invalid (wrong port, invalid...), 1026 * skip it. 1027 */ 1028 if (ret == -EINVAL) 1029 continue; 1030 else if (ret) 1031 return ret; 1032 1033 is_static = (entry.type == ENTRYTYPE_LOCKED); 1034 1035 ret = cb(entry.mac, entry.vid, is_static, data); 1036 if (ret) 1037 return ret; 1038 } 1039 } 1040 1041 return 0; 1042 } 1043 EXPORT_SYMBOL(ocelot_fdb_dump); 1044 1045 static int ocelot_port_fdb_dump(struct sk_buff *skb, 1046 struct netlink_callback *cb, 1047 struct net_device *dev, 1048 struct net_device *filter_dev, int *idx) 1049 { 1050 struct ocelot_port_private *priv = netdev_priv(dev); 1051 struct ocelot *ocelot = priv->port.ocelot; 1052 struct ocelot_dump_ctx dump = { 1053 .dev = dev, 1054 .skb = skb, 1055 .cb = cb, 1056 .idx = *idx, 1057 }; 1058 int port = priv->chip_port; 1059 int ret; 1060 1061 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump); 1062 1063 *idx = dump.idx; 1064 1065 return ret; 1066 } 1067 1068 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 1069 u16 vid) 1070 { 1071 return ocelot_vlan_vid_add(dev, vid, false, false); 1072 } 1073 1074 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 1075 u16 vid) 1076 { 1077 return ocelot_vlan_vid_del(dev, vid); 1078 } 1079 1080 static int ocelot_set_features(struct net_device *dev, 1081 netdev_features_t features) 1082 { 1083 netdev_features_t changed = dev->features ^ features; 1084 struct ocelot_port_private *priv = netdev_priv(dev); 1085 struct ocelot *ocelot = priv->port.ocelot; 1086 int port = priv->chip_port; 1087 1088 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1089 priv->tc.offload_cnt) { 1090 netdev_err(dev, 1091 "Cannot disable HW TC offload while offloads active\n"); 1092 return -EBUSY; 1093 } 1094 1095 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 1096 ocelot_vlan_mode(ocelot, port, features); 1097 1098 return 0; 1099 } 1100 1101 static int ocelot_get_port_parent_id(struct net_device *dev, 1102 struct netdev_phys_item_id *ppid) 1103 { 1104 struct ocelot_port_private *priv = netdev_priv(dev); 1105 struct ocelot *ocelot = priv->port.ocelot; 1106 1107 ppid->id_len = sizeof(ocelot->base_mac); 1108 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 1109 1110 return 0; 1111 } 1112 1113 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1114 { 1115 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1116 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1117 } 1118 EXPORT_SYMBOL(ocelot_hwstamp_get); 1119 1120 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1121 { 1122 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1123 struct hwtstamp_config cfg; 1124 1125 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1126 return -EFAULT; 1127 1128 /* reserved for future extensions */ 1129 if (cfg.flags) 1130 return -EINVAL; 1131 1132 /* Tx type sanity check */ 1133 switch (cfg.tx_type) { 1134 case HWTSTAMP_TX_ON: 1135 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1136 break; 1137 case HWTSTAMP_TX_ONESTEP_SYNC: 1138 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1139 * need to update the origin time. 1140 */ 1141 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1142 break; 1143 case HWTSTAMP_TX_OFF: 1144 ocelot_port->ptp_cmd = 0; 1145 break; 1146 default: 1147 return -ERANGE; 1148 } 1149 1150 mutex_lock(&ocelot->ptp_lock); 1151 1152 switch (cfg.rx_filter) { 1153 case HWTSTAMP_FILTER_NONE: 1154 break; 1155 case HWTSTAMP_FILTER_ALL: 1156 case HWTSTAMP_FILTER_SOME: 1157 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1158 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1159 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1160 case HWTSTAMP_FILTER_NTP_ALL: 1161 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1162 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1163 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1164 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1165 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1166 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1167 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1168 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1169 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1170 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1171 break; 1172 default: 1173 mutex_unlock(&ocelot->ptp_lock); 1174 return -ERANGE; 1175 } 1176 1177 /* Commit back the result & save it */ 1178 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1179 mutex_unlock(&ocelot->ptp_lock); 1180 1181 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1182 } 1183 EXPORT_SYMBOL(ocelot_hwstamp_set); 1184 1185 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1186 { 1187 struct ocelot_port_private *priv = netdev_priv(dev); 1188 struct ocelot *ocelot = priv->port.ocelot; 1189 int port = priv->chip_port; 1190 1191 /* The function is only used for PTP operations for now */ 1192 if (!ocelot->ptp) 1193 return -EOPNOTSUPP; 1194 1195 switch (cmd) { 1196 case SIOCSHWTSTAMP: 1197 return ocelot_hwstamp_set(ocelot, port, ifr); 1198 case SIOCGHWTSTAMP: 1199 return ocelot_hwstamp_get(ocelot, port, ifr); 1200 default: 1201 return -EOPNOTSUPP; 1202 } 1203 } 1204 1205 static const struct net_device_ops ocelot_port_netdev_ops = { 1206 .ndo_open = ocelot_port_open, 1207 .ndo_stop = ocelot_port_stop, 1208 .ndo_start_xmit = ocelot_port_xmit, 1209 .ndo_set_rx_mode = ocelot_set_rx_mode, 1210 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1211 .ndo_set_mac_address = ocelot_port_set_mac_address, 1212 .ndo_get_stats64 = ocelot_get_stats64, 1213 .ndo_fdb_add = ocelot_port_fdb_add, 1214 .ndo_fdb_del = ocelot_port_fdb_del, 1215 .ndo_fdb_dump = ocelot_port_fdb_dump, 1216 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1217 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1218 .ndo_set_features = ocelot_set_features, 1219 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1220 .ndo_setup_tc = ocelot_setup_tc, 1221 .ndo_do_ioctl = ocelot_ioctl, 1222 }; 1223 1224 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1225 { 1226 int i; 1227 1228 if (sset != ETH_SS_STATS) 1229 return; 1230 1231 for (i = 0; i < ocelot->num_stats; i++) 1232 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1233 ETH_GSTRING_LEN); 1234 } 1235 EXPORT_SYMBOL(ocelot_get_strings); 1236 1237 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset, 1238 u8 *data) 1239 { 1240 struct ocelot_port_private *priv = netdev_priv(netdev); 1241 struct ocelot *ocelot = priv->port.ocelot; 1242 int port = priv->chip_port; 1243 1244 ocelot_get_strings(ocelot, port, sset, data); 1245 } 1246 1247 static void ocelot_update_stats(struct ocelot *ocelot) 1248 { 1249 int i, j; 1250 1251 mutex_lock(&ocelot->stats_lock); 1252 1253 for (i = 0; i < ocelot->num_phys_ports; i++) { 1254 /* Configure the port to read the stats from */ 1255 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1256 1257 for (j = 0; j < ocelot->num_stats; j++) { 1258 u32 val; 1259 unsigned int idx = i * ocelot->num_stats + j; 1260 1261 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1262 ocelot->stats_layout[j].offset); 1263 1264 if (val < (ocelot->stats[idx] & U32_MAX)) 1265 ocelot->stats[idx] += (u64)1 << 32; 1266 1267 ocelot->stats[idx] = (ocelot->stats[idx] & 1268 ~(u64)U32_MAX) + val; 1269 } 1270 } 1271 1272 mutex_unlock(&ocelot->stats_lock); 1273 } 1274 1275 static void ocelot_check_stats_work(struct work_struct *work) 1276 { 1277 struct delayed_work *del_work = to_delayed_work(work); 1278 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1279 stats_work); 1280 1281 ocelot_update_stats(ocelot); 1282 1283 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1284 OCELOT_STATS_CHECK_DELAY); 1285 } 1286 1287 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1288 { 1289 int i; 1290 1291 /* check and update now */ 1292 ocelot_update_stats(ocelot); 1293 1294 /* Copy all counters */ 1295 for (i = 0; i < ocelot->num_stats; i++) 1296 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1297 } 1298 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1299 1300 static void ocelot_port_get_ethtool_stats(struct net_device *dev, 1301 struct ethtool_stats *stats, 1302 u64 *data) 1303 { 1304 struct ocelot_port_private *priv = netdev_priv(dev); 1305 struct ocelot *ocelot = priv->port.ocelot; 1306 int port = priv->chip_port; 1307 1308 ocelot_get_ethtool_stats(ocelot, port, data); 1309 } 1310 1311 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1312 { 1313 if (sset != ETH_SS_STATS) 1314 return -EOPNOTSUPP; 1315 1316 return ocelot->num_stats; 1317 } 1318 EXPORT_SYMBOL(ocelot_get_sset_count); 1319 1320 static int ocelot_port_get_sset_count(struct net_device *dev, int sset) 1321 { 1322 struct ocelot_port_private *priv = netdev_priv(dev); 1323 struct ocelot *ocelot = priv->port.ocelot; 1324 int port = priv->chip_port; 1325 1326 return ocelot_get_sset_count(ocelot, port, sset); 1327 } 1328 1329 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1330 struct ethtool_ts_info *info) 1331 { 1332 info->phc_index = ocelot->ptp_clock ? 1333 ptp_clock_index(ocelot->ptp_clock) : -1; 1334 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1335 SOF_TIMESTAMPING_RX_SOFTWARE | 1336 SOF_TIMESTAMPING_SOFTWARE | 1337 SOF_TIMESTAMPING_TX_HARDWARE | 1338 SOF_TIMESTAMPING_RX_HARDWARE | 1339 SOF_TIMESTAMPING_RAW_HARDWARE; 1340 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1341 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1342 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1343 1344 return 0; 1345 } 1346 EXPORT_SYMBOL(ocelot_get_ts_info); 1347 1348 static int ocelot_port_get_ts_info(struct net_device *dev, 1349 struct ethtool_ts_info *info) 1350 { 1351 struct ocelot_port_private *priv = netdev_priv(dev); 1352 struct ocelot *ocelot = priv->port.ocelot; 1353 int port = priv->chip_port; 1354 1355 if (!ocelot->ptp) 1356 return ethtool_op_get_ts_info(dev, info); 1357 1358 return ocelot_get_ts_info(ocelot, port, info); 1359 } 1360 1361 static const struct ethtool_ops ocelot_ethtool_ops = { 1362 .get_strings = ocelot_port_get_strings, 1363 .get_ethtool_stats = ocelot_port_get_ethtool_stats, 1364 .get_sset_count = ocelot_port_get_sset_count, 1365 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1366 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1367 .get_ts_info = ocelot_port_get_ts_info, 1368 }; 1369 1370 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1371 { 1372 u32 port_cfg; 1373 int p, i; 1374 1375 if (!(BIT(port) & ocelot->bridge_mask)) 1376 return; 1377 1378 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1379 1380 switch (state) { 1381 case BR_STATE_FORWARDING: 1382 ocelot->bridge_fwd_mask |= BIT(port); 1383 /* Fallthrough */ 1384 case BR_STATE_LEARNING: 1385 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1386 break; 1387 1388 default: 1389 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1390 ocelot->bridge_fwd_mask &= ~BIT(port); 1391 break; 1392 } 1393 1394 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 1395 1396 /* Apply FWD mask. The loop is needed to add/remove the current port as 1397 * a source for the other ports. 1398 */ 1399 for (p = 0; p < ocelot->num_phys_ports; p++) { 1400 if (p == ocelot->cpu || (ocelot->bridge_fwd_mask & BIT(p))) { 1401 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 1402 1403 for (i = 0; i < ocelot->num_phys_ports; i++) { 1404 unsigned long bond_mask = ocelot->lags[i]; 1405 1406 if (!bond_mask) 1407 continue; 1408 1409 if (bond_mask & BIT(p)) { 1410 mask &= ~bond_mask; 1411 break; 1412 } 1413 } 1414 1415 /* Avoid the NPI port from looping back to itself */ 1416 if (p != ocelot->cpu) 1417 mask |= BIT(ocelot->cpu); 1418 1419 ocelot_write_rix(ocelot, mask, 1420 ANA_PGID_PGID, PGID_SRC + p); 1421 } else { 1422 /* Only the CPU port, this is compatible with link 1423 * aggregation. 1424 */ 1425 ocelot_write_rix(ocelot, 1426 BIT(ocelot->cpu), 1427 ANA_PGID_PGID, PGID_SRC + p); 1428 } 1429 } 1430 } 1431 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1432 1433 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port, 1434 struct switchdev_trans *trans, 1435 u8 state) 1436 { 1437 if (switchdev_trans_ph_prepare(trans)) 1438 return; 1439 1440 ocelot_bridge_stp_state_set(ocelot, port, state); 1441 } 1442 1443 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1444 { 1445 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2), 1446 ANA_AUTOAGE); 1447 } 1448 EXPORT_SYMBOL(ocelot_set_ageing_time); 1449 1450 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port, 1451 unsigned long ageing_clock_t) 1452 { 1453 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1454 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1455 1456 ocelot_set_ageing_time(ocelot, ageing_time); 1457 } 1458 1459 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc) 1460 { 1461 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1462 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1463 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1464 u32 val = 0; 1465 1466 if (mc) 1467 val = cpu_fwd_mcast; 1468 1469 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast, 1470 ANA_PORT_CPU_FWD_CFG, port); 1471 } 1472 1473 static int ocelot_port_attr_set(struct net_device *dev, 1474 const struct switchdev_attr *attr, 1475 struct switchdev_trans *trans) 1476 { 1477 struct ocelot_port_private *priv = netdev_priv(dev); 1478 struct ocelot *ocelot = priv->port.ocelot; 1479 int port = priv->chip_port; 1480 int err = 0; 1481 1482 switch (attr->id) { 1483 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1484 ocelot_port_attr_stp_state_set(ocelot, port, trans, 1485 attr->u.stp_state); 1486 break; 1487 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1488 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time); 1489 break; 1490 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1491 priv->vlan_aware = attr->u.vlan_filtering; 1492 ocelot_port_vlan_filtering(ocelot, port, priv->vlan_aware); 1493 break; 1494 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1495 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled); 1496 break; 1497 default: 1498 err = -EOPNOTSUPP; 1499 break; 1500 } 1501 1502 return err; 1503 } 1504 1505 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1506 const struct switchdev_obj_port_vlan *vlan, 1507 struct switchdev_trans *trans) 1508 { 1509 int ret; 1510 u16 vid; 1511 1512 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1513 ret = ocelot_vlan_vid_add(dev, vid, 1514 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1515 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1516 if (ret) 1517 return ret; 1518 } 1519 1520 return 0; 1521 } 1522 1523 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1524 const struct switchdev_obj_port_vlan *vlan) 1525 { 1526 int ret; 1527 u16 vid; 1528 1529 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1530 ret = ocelot_vlan_vid_del(dev, vid); 1531 1532 if (ret) 1533 return ret; 1534 } 1535 1536 return 0; 1537 } 1538 1539 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1540 const unsigned char *addr, 1541 u16 vid) 1542 { 1543 struct ocelot_multicast *mc; 1544 1545 list_for_each_entry(mc, &ocelot->multicast, list) { 1546 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1547 return mc; 1548 } 1549 1550 return NULL; 1551 } 1552 1553 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1554 const struct switchdev_obj_port_mdb *mdb, 1555 struct switchdev_trans *trans) 1556 { 1557 struct ocelot_port_private *priv = netdev_priv(dev); 1558 struct ocelot_port *ocelot_port = &priv->port; 1559 struct ocelot *ocelot = ocelot_port->ocelot; 1560 unsigned char addr[ETH_ALEN]; 1561 struct ocelot_multicast *mc; 1562 int port = priv->chip_port; 1563 u16 vid = mdb->vid; 1564 bool new = false; 1565 1566 if (!vid) 1567 vid = ocelot_port->pvid; 1568 1569 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1570 if (!mc) { 1571 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1572 if (!mc) 1573 return -ENOMEM; 1574 1575 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1576 mc->vid = vid; 1577 1578 list_add_tail(&mc->list, &ocelot->multicast); 1579 new = true; 1580 } 1581 1582 memcpy(addr, mc->addr, ETH_ALEN); 1583 addr[0] = 0; 1584 1585 if (!new) { 1586 addr[2] = mc->ports << 0; 1587 addr[1] = mc->ports << 8; 1588 ocelot_mact_forget(ocelot, addr, vid); 1589 } 1590 1591 mc->ports |= BIT(port); 1592 addr[2] = mc->ports << 0; 1593 addr[1] = mc->ports << 8; 1594 1595 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1596 } 1597 1598 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1599 const struct switchdev_obj_port_mdb *mdb) 1600 { 1601 struct ocelot_port_private *priv = netdev_priv(dev); 1602 struct ocelot_port *ocelot_port = &priv->port; 1603 struct ocelot *ocelot = ocelot_port->ocelot; 1604 unsigned char addr[ETH_ALEN]; 1605 struct ocelot_multicast *mc; 1606 int port = priv->chip_port; 1607 u16 vid = mdb->vid; 1608 1609 if (!vid) 1610 vid = ocelot_port->pvid; 1611 1612 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1613 if (!mc) 1614 return -ENOENT; 1615 1616 memcpy(addr, mc->addr, ETH_ALEN); 1617 addr[2] = mc->ports << 0; 1618 addr[1] = mc->ports << 8; 1619 addr[0] = 0; 1620 ocelot_mact_forget(ocelot, addr, vid); 1621 1622 mc->ports &= ~BIT(port); 1623 if (!mc->ports) { 1624 list_del(&mc->list); 1625 devm_kfree(ocelot->dev, mc); 1626 return 0; 1627 } 1628 1629 addr[2] = mc->ports << 0; 1630 addr[1] = mc->ports << 8; 1631 1632 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1633 } 1634 1635 static int ocelot_port_obj_add(struct net_device *dev, 1636 const struct switchdev_obj *obj, 1637 struct switchdev_trans *trans, 1638 struct netlink_ext_ack *extack) 1639 { 1640 int ret = 0; 1641 1642 switch (obj->id) { 1643 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1644 ret = ocelot_port_obj_add_vlan(dev, 1645 SWITCHDEV_OBJ_PORT_VLAN(obj), 1646 trans); 1647 break; 1648 case SWITCHDEV_OBJ_ID_PORT_MDB: 1649 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1650 trans); 1651 break; 1652 default: 1653 return -EOPNOTSUPP; 1654 } 1655 1656 return ret; 1657 } 1658 1659 static int ocelot_port_obj_del(struct net_device *dev, 1660 const struct switchdev_obj *obj) 1661 { 1662 int ret = 0; 1663 1664 switch (obj->id) { 1665 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1666 ret = ocelot_port_vlan_del_vlan(dev, 1667 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1668 break; 1669 case SWITCHDEV_OBJ_ID_PORT_MDB: 1670 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1671 break; 1672 default: 1673 return -EOPNOTSUPP; 1674 } 1675 1676 return ret; 1677 } 1678 1679 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1680 struct net_device *bridge) 1681 { 1682 if (!ocelot->bridge_mask) { 1683 ocelot->hw_bridge_dev = bridge; 1684 } else { 1685 if (ocelot->hw_bridge_dev != bridge) 1686 /* This is adding the port to a second bridge, this is 1687 * unsupported */ 1688 return -ENODEV; 1689 } 1690 1691 ocelot->bridge_mask |= BIT(port); 1692 1693 return 0; 1694 } 1695 EXPORT_SYMBOL(ocelot_port_bridge_join); 1696 1697 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1698 struct net_device *bridge) 1699 { 1700 ocelot->bridge_mask &= ~BIT(port); 1701 1702 if (!ocelot->bridge_mask) 1703 ocelot->hw_bridge_dev = NULL; 1704 1705 ocelot_port_vlan_filtering(ocelot, port, 0); 1706 ocelot_port_set_pvid(ocelot, port, 0); 1707 return ocelot_port_set_native_vlan(ocelot, port, 0); 1708 } 1709 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1710 1711 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1712 { 1713 int i, port, lag; 1714 1715 /* Reset destination and aggregation PGIDS */ 1716 for (port = 0; port < ocelot->num_phys_ports; port++) 1717 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1718 1719 for (i = PGID_AGGR; i < PGID_SRC; i++) 1720 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1721 ANA_PGID_PGID, i); 1722 1723 /* Now, set PGIDs for each LAG */ 1724 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1725 unsigned long bond_mask; 1726 int aggr_count = 0; 1727 u8 aggr_idx[16]; 1728 1729 bond_mask = ocelot->lags[lag]; 1730 if (!bond_mask) 1731 continue; 1732 1733 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1734 // Destination mask 1735 ocelot_write_rix(ocelot, bond_mask, 1736 ANA_PGID_PGID, port); 1737 aggr_idx[aggr_count] = port; 1738 aggr_count++; 1739 } 1740 1741 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1742 u32 ac; 1743 1744 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1745 ac &= ~bond_mask; 1746 ac |= BIT(aggr_idx[i % aggr_count]); 1747 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1748 } 1749 } 1750 } 1751 1752 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1753 { 1754 unsigned long bond_mask = ocelot->lags[lag]; 1755 unsigned int p; 1756 1757 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1758 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1759 1760 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1761 1762 /* Use lag port as logical port for port i */ 1763 ocelot_write_gix(ocelot, port_cfg | 1764 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1765 ANA_PORT_PORT_CFG, p); 1766 } 1767 } 1768 1769 static int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1770 struct net_device *bond) 1771 { 1772 struct net_device *ndev; 1773 u32 bond_mask = 0; 1774 int lag, lp; 1775 1776 rcu_read_lock(); 1777 for_each_netdev_in_bond_rcu(bond, ndev) { 1778 struct ocelot_port_private *priv = netdev_priv(ndev); 1779 1780 bond_mask |= BIT(priv->chip_port); 1781 } 1782 rcu_read_unlock(); 1783 1784 lp = __ffs(bond_mask); 1785 1786 /* If the new port is the lowest one, use it as the logical port from 1787 * now on 1788 */ 1789 if (port == lp) { 1790 lag = port; 1791 ocelot->lags[port] = bond_mask; 1792 bond_mask &= ~BIT(port); 1793 if (bond_mask) { 1794 lp = __ffs(bond_mask); 1795 ocelot->lags[lp] = 0; 1796 } 1797 } else { 1798 lag = lp; 1799 ocelot->lags[lp] |= BIT(port); 1800 } 1801 1802 ocelot_setup_lag(ocelot, lag); 1803 ocelot_set_aggr_pgids(ocelot); 1804 1805 return 0; 1806 } 1807 1808 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1809 struct net_device *bond) 1810 { 1811 u32 port_cfg; 1812 int i; 1813 1814 /* Remove port from any lag */ 1815 for (i = 0; i < ocelot->num_phys_ports; i++) 1816 ocelot->lags[i] &= ~BIT(port); 1817 1818 /* if it was the logical port of the lag, move the lag config to the 1819 * next port 1820 */ 1821 if (ocelot->lags[port]) { 1822 int n = __ffs(ocelot->lags[port]); 1823 1824 ocelot->lags[n] = ocelot->lags[port]; 1825 ocelot->lags[port] = 0; 1826 1827 ocelot_setup_lag(ocelot, n); 1828 } 1829 1830 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1831 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1832 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1833 ANA_PORT_PORT_CFG, port); 1834 1835 ocelot_set_aggr_pgids(ocelot); 1836 } 1837 1838 /* Checks if the net_device instance given to us originate from our driver. */ 1839 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1840 { 1841 return dev->netdev_ops == &ocelot_port_netdev_ops; 1842 } 1843 1844 static int ocelot_netdevice_port_event(struct net_device *dev, 1845 unsigned long event, 1846 struct netdev_notifier_changeupper_info *info) 1847 { 1848 struct ocelot_port_private *priv = netdev_priv(dev); 1849 struct ocelot_port *ocelot_port = &priv->port; 1850 struct ocelot *ocelot = ocelot_port->ocelot; 1851 int port = priv->chip_port; 1852 int err = 0; 1853 1854 switch (event) { 1855 case NETDEV_CHANGEUPPER: 1856 if (netif_is_bridge_master(info->upper_dev)) { 1857 if (info->linking) { 1858 err = ocelot_port_bridge_join(ocelot, port, 1859 info->upper_dev); 1860 } else { 1861 err = ocelot_port_bridge_leave(ocelot, port, 1862 info->upper_dev); 1863 priv->vlan_aware = false; 1864 } 1865 } 1866 if (netif_is_lag_master(info->upper_dev)) { 1867 if (info->linking) 1868 err = ocelot_port_lag_join(ocelot, port, 1869 info->upper_dev); 1870 else 1871 ocelot_port_lag_leave(ocelot, port, 1872 info->upper_dev); 1873 } 1874 break; 1875 default: 1876 break; 1877 } 1878 1879 return err; 1880 } 1881 1882 static int ocelot_netdevice_event(struct notifier_block *unused, 1883 unsigned long event, void *ptr) 1884 { 1885 struct netdev_notifier_changeupper_info *info = ptr; 1886 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1887 int ret = 0; 1888 1889 if (!ocelot_netdevice_dev_check(dev)) 1890 return 0; 1891 1892 if (event == NETDEV_PRECHANGEUPPER && 1893 netif_is_lag_master(info->upper_dev)) { 1894 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1895 struct netlink_ext_ack *extack; 1896 1897 if (lag_upper_info && 1898 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1899 extack = netdev_notifier_info_to_extack(&info->info); 1900 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1901 1902 ret = -EINVAL; 1903 goto notify; 1904 } 1905 } 1906 1907 if (netif_is_lag_master(dev)) { 1908 struct net_device *slave; 1909 struct list_head *iter; 1910 1911 netdev_for_each_lower_dev(dev, slave, iter) { 1912 ret = ocelot_netdevice_port_event(slave, event, info); 1913 if (ret) 1914 goto notify; 1915 } 1916 } else { 1917 ret = ocelot_netdevice_port_event(dev, event, info); 1918 } 1919 1920 notify: 1921 return notifier_from_errno(ret); 1922 } 1923 1924 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1925 .notifier_call = ocelot_netdevice_event, 1926 }; 1927 EXPORT_SYMBOL(ocelot_netdevice_nb); 1928 1929 static int ocelot_switchdev_event(struct notifier_block *unused, 1930 unsigned long event, void *ptr) 1931 { 1932 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1933 int err; 1934 1935 switch (event) { 1936 case SWITCHDEV_PORT_ATTR_SET: 1937 err = switchdev_handle_port_attr_set(dev, ptr, 1938 ocelot_netdevice_dev_check, 1939 ocelot_port_attr_set); 1940 return notifier_from_errno(err); 1941 } 1942 1943 return NOTIFY_DONE; 1944 } 1945 1946 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1947 .notifier_call = ocelot_switchdev_event, 1948 }; 1949 EXPORT_SYMBOL(ocelot_switchdev_nb); 1950 1951 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1952 unsigned long event, void *ptr) 1953 { 1954 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1955 int err; 1956 1957 switch (event) { 1958 /* Blocking events. */ 1959 case SWITCHDEV_PORT_OBJ_ADD: 1960 err = switchdev_handle_port_obj_add(dev, ptr, 1961 ocelot_netdevice_dev_check, 1962 ocelot_port_obj_add); 1963 return notifier_from_errno(err); 1964 case SWITCHDEV_PORT_OBJ_DEL: 1965 err = switchdev_handle_port_obj_del(dev, ptr, 1966 ocelot_netdevice_dev_check, 1967 ocelot_port_obj_del); 1968 return notifier_from_errno(err); 1969 case SWITCHDEV_PORT_ATTR_SET: 1970 err = switchdev_handle_port_attr_set(dev, ptr, 1971 ocelot_netdevice_dev_check, 1972 ocelot_port_attr_set); 1973 return notifier_from_errno(err); 1974 } 1975 1976 return NOTIFY_DONE; 1977 } 1978 1979 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1980 .notifier_call = ocelot_switchdev_blocking_event, 1981 }; 1982 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1983 1984 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts) 1985 { 1986 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1987 unsigned long flags; 1988 time64_t s; 1989 u32 val; 1990 s64 ns; 1991 1992 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1993 1994 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1995 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1996 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 1997 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1998 1999 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; 2000 s <<= 32; 2001 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 2002 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2003 2004 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2005 2006 /* Deal with negative values */ 2007 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) { 2008 s--; 2009 ns &= 0xf; 2010 ns += 999999984; 2011 } 2012 2013 set_normalized_timespec64(ts, s, ns); 2014 return 0; 2015 } 2016 EXPORT_SYMBOL(ocelot_ptp_gettime64); 2017 2018 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp, 2019 const struct timespec64 *ts) 2020 { 2021 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2022 unsigned long flags; 2023 u32 val; 2024 2025 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2026 2027 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2028 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2029 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 2030 2031 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2032 2033 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB, 2034 TOD_ACC_PIN); 2035 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, 2036 TOD_ACC_PIN); 2037 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2038 2039 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2040 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2041 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); 2042 2043 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2044 2045 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2046 return 0; 2047 } 2048 2049 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 2050 { 2051 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 2052 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2053 unsigned long flags; 2054 u32 val; 2055 2056 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2057 2058 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2059 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2060 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 2061 2062 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2063 2064 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 2065 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN); 2066 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2067 2068 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2069 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2070 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); 2071 2072 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2073 2074 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2075 } else { 2076 /* Fall back using ocelot_ptp_settime64 which is not exact. */ 2077 struct timespec64 ts; 2078 u64 now; 2079 2080 ocelot_ptp_gettime64(ptp, &ts); 2081 2082 now = ktime_to_ns(timespec64_to_ktime(ts)); 2083 ts = ns_to_timespec64(now + delta); 2084 2085 ocelot_ptp_settime64(ptp, &ts); 2086 } 2087 return 0; 2088 } 2089 2090 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 2091 { 2092 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2093 u32 unit = 0, direction = 0; 2094 unsigned long flags; 2095 u64 adj = 0; 2096 2097 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2098 2099 if (!scaled_ppm) 2100 goto disable_adj; 2101 2102 if (scaled_ppm < 0) { 2103 direction = PTP_CFG_CLK_ADJ_CFG_DIR; 2104 scaled_ppm = -scaled_ppm; 2105 } 2106 2107 adj = PSEC_PER_SEC << 16; 2108 do_div(adj, scaled_ppm); 2109 do_div(adj, 1000); 2110 2111 /* If the adjustment value is too large, use ns instead */ 2112 if (adj >= (1L << 30)) { 2113 unit = PTP_CFG_CLK_ADJ_FREQ_NS; 2114 do_div(adj, 1000); 2115 } 2116 2117 /* Still too big */ 2118 if (adj >= (1L << 30)) 2119 goto disable_adj; 2120 2121 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ); 2122 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction, 2123 PTP_CLK_CFG_ADJ_CFG); 2124 2125 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2126 return 0; 2127 2128 disable_adj: 2129 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG); 2130 2131 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2132 return 0; 2133 } 2134 2135 static struct ptp_clock_info ocelot_ptp_clock_info = { 2136 .owner = THIS_MODULE, 2137 .name = "ocelot ptp", 2138 .max_adj = 0x7fffffff, 2139 .n_alarm = 0, 2140 .n_ext_ts = 0, 2141 .n_per_out = 0, 2142 .n_pins = 0, 2143 .pps = 0, 2144 .gettime64 = ocelot_ptp_gettime64, 2145 .settime64 = ocelot_ptp_settime64, 2146 .adjtime = ocelot_ptp_adjtime, 2147 .adjfine = ocelot_ptp_adjfine, 2148 }; 2149 2150 static int ocelot_init_timestamp(struct ocelot *ocelot) 2151 { 2152 struct ptp_clock *ptp_clock; 2153 2154 ocelot->ptp_info = ocelot_ptp_clock_info; 2155 ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev); 2156 if (IS_ERR(ptp_clock)) 2157 return PTR_ERR(ptp_clock); 2158 /* Check if PHC support is missing at the configuration level */ 2159 if (!ptp_clock) 2160 return 0; 2161 2162 ocelot->ptp_clock = ptp_clock; 2163 2164 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG); 2165 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW); 2166 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH); 2167 2168 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); 2169 2170 /* There is no device reconfiguration, PTP Rx stamping is always 2171 * enabled. 2172 */ 2173 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 2174 2175 return 0; 2176 } 2177 2178 static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu) 2179 { 2180 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2181 int atop_wm; 2182 2183 ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG); 2184 2185 /* Set Pause WM hysteresis 2186 * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ 2187 * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ 2188 */ 2189 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 2190 SYS_PAUSE_CFG_PAUSE_STOP(101) | 2191 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); 2192 2193 /* Tail dropping watermark */ 2194 atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ; 2195 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu), 2196 SYS_ATOP, port); 2197 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 2198 } 2199 2200 void ocelot_init_port(struct ocelot *ocelot, int port) 2201 { 2202 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2203 2204 skb_queue_head_init(&ocelot_port->tx_skbs); 2205 2206 /* Basic L2 initialization */ 2207 2208 /* Set MAC IFG Gaps 2209 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2210 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2211 */ 2212 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2213 DEV_MAC_IFG_CFG); 2214 2215 /* Load seed (0) and set MAC HDX late collision */ 2216 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2217 DEV_MAC_HDX_CFG_SEED_LOAD, 2218 DEV_MAC_HDX_CFG); 2219 mdelay(1); 2220 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2221 DEV_MAC_HDX_CFG); 2222 2223 /* Set Max Length and maximum tags allowed */ 2224 ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN); 2225 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2226 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2227 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2228 DEV_MAC_TAGS_CFG); 2229 2230 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2231 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2232 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2233 2234 /* Drop frames with multicast source address */ 2235 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2236 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2237 ANA_PORT_DROP_CFG, port); 2238 2239 /* Set default VLAN and tag type to 8021Q. */ 2240 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2241 REW_PORT_VLAN_CFG_PORT_TPID_M, 2242 REW_PORT_VLAN_CFG, port); 2243 2244 /* Enable vcap lookups */ 2245 ocelot_vcap_enable(ocelot, port); 2246 } 2247 EXPORT_SYMBOL(ocelot_init_port); 2248 2249 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 2250 void __iomem *regs, 2251 struct phy_device *phy) 2252 { 2253 struct ocelot_port_private *priv; 2254 struct ocelot_port *ocelot_port; 2255 struct net_device *dev; 2256 int err; 2257 2258 dev = alloc_etherdev(sizeof(struct ocelot_port_private)); 2259 if (!dev) 2260 return -ENOMEM; 2261 SET_NETDEV_DEV(dev, ocelot->dev); 2262 priv = netdev_priv(dev); 2263 priv->dev = dev; 2264 priv->phy = phy; 2265 priv->chip_port = port; 2266 ocelot_port = &priv->port; 2267 ocelot_port->ocelot = ocelot; 2268 ocelot_port->regs = regs; 2269 ocelot->ports[port] = ocelot_port; 2270 2271 dev->netdev_ops = &ocelot_port_netdev_ops; 2272 dev->ethtool_ops = &ocelot_ethtool_ops; 2273 2274 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2275 NETIF_F_HW_TC; 2276 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2277 2278 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2279 dev->dev_addr[ETH_ALEN - 1] += port; 2280 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2281 ENTRYTYPE_LOCKED); 2282 2283 ocelot_init_port(ocelot, port); 2284 2285 err = register_netdev(dev); 2286 if (err) { 2287 dev_err(ocelot->dev, "register_netdev failed\n"); 2288 free_netdev(dev); 2289 } 2290 2291 return err; 2292 } 2293 EXPORT_SYMBOL(ocelot_probe_port); 2294 2295 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu, 2296 enum ocelot_tag_prefix injection, 2297 enum ocelot_tag_prefix extraction) 2298 { 2299 /* Configure and enable the CPU port. */ 2300 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2301 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2302 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2303 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2304 ANA_PORT_PORT_CFG, cpu); 2305 2306 /* If the CPU port is a physical port, set up the port in Node 2307 * Processor Interface (NPI) mode. This is the mode through which 2308 * frames can be injected from and extracted to an external CPU. 2309 * Only one port can be an NPI at the same time. 2310 */ 2311 if (cpu < ocelot->num_phys_ports) { 2312 int mtu = VLAN_ETH_FRAME_LEN + OCELOT_TAG_LEN; 2313 2314 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 2315 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu), 2316 QSYS_EXT_CPU_CFG); 2317 2318 if (injection == OCELOT_TAG_PREFIX_SHORT) 2319 mtu += OCELOT_SHORT_PREFIX_LEN; 2320 else if (injection == OCELOT_TAG_PREFIX_LONG) 2321 mtu += OCELOT_LONG_PREFIX_LEN; 2322 2323 ocelot_port_set_mtu(ocelot, cpu, mtu); 2324 } 2325 2326 /* CPU port Injection/Extraction configuration */ 2327 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2328 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2329 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2330 QSYS_SWITCH_PORT_MODE, cpu); 2331 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2332 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2333 SYS_PORT_MODE, cpu); 2334 2335 /* Configure the CPU port to be VLAN aware */ 2336 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2337 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2338 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2339 ANA_PORT_VLAN_CFG, cpu); 2340 2341 ocelot->cpu = cpu; 2342 } 2343 EXPORT_SYMBOL(ocelot_set_cpu_port); 2344 2345 int ocelot_init(struct ocelot *ocelot) 2346 { 2347 char queue_name[32]; 2348 int i, ret; 2349 u32 port; 2350 2351 if (ocelot->ops->reset) { 2352 ret = ocelot->ops->reset(ocelot); 2353 if (ret) { 2354 dev_err(ocelot->dev, "Switch reset failed\n"); 2355 return ret; 2356 } 2357 } 2358 2359 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2360 sizeof(u32), GFP_KERNEL); 2361 if (!ocelot->lags) 2362 return -ENOMEM; 2363 2364 ocelot->stats = devm_kcalloc(ocelot->dev, 2365 ocelot->num_phys_ports * ocelot->num_stats, 2366 sizeof(u64), GFP_KERNEL); 2367 if (!ocelot->stats) 2368 return -ENOMEM; 2369 2370 mutex_init(&ocelot->stats_lock); 2371 mutex_init(&ocelot->ptp_lock); 2372 spin_lock_init(&ocelot->ptp_clock_lock); 2373 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2374 dev_name(ocelot->dev)); 2375 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2376 if (!ocelot->stats_queue) 2377 return -ENOMEM; 2378 2379 INIT_LIST_HEAD(&ocelot->multicast); 2380 ocelot_mact_init(ocelot); 2381 ocelot_vlan_init(ocelot); 2382 ocelot_ace_init(ocelot); 2383 2384 for (port = 0; port < ocelot->num_phys_ports; port++) { 2385 /* Clear all counters (5 groups) */ 2386 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2387 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2388 SYS_STAT_CFG); 2389 } 2390 2391 /* Only use S-Tag */ 2392 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2393 2394 /* Aggregation mode */ 2395 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2396 ANA_AGGR_CFG_AC_DMAC_ENA | 2397 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2398 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2399 2400 /* Set MAC age time to default value. The entry is aged after 2401 * 2*AGE_PERIOD 2402 */ 2403 ocelot_write(ocelot, 2404 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2405 ANA_AUTOAGE); 2406 2407 /* Disable learning for frames discarded by VLAN ingress filtering */ 2408 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2409 2410 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2411 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2412 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2413 2414 /* Setup flooding PGIDs */ 2415 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2416 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2417 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2418 ANA_FLOODING, 0); 2419 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2420 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2421 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2422 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2423 ANA_FLOODING_IPMC); 2424 2425 for (port = 0; port < ocelot->num_phys_ports; port++) { 2426 /* Transmit the frame to the local port. */ 2427 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2428 /* Do not forward BPDU frames to the front ports. */ 2429 ocelot_write_gix(ocelot, 2430 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2431 ANA_PORT_CPU_FWD_BPDU_CFG, 2432 port); 2433 /* Ensure bridging is disabled */ 2434 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2435 } 2436 2437 /* Allow broadcast MAC frames. */ 2438 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2439 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2440 2441 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2442 } 2443 ocelot_write_rix(ocelot, 2444 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2445 ANA_PGID_PGID, PGID_MC); 2446 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2447 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2448 2449 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2450 * registers endianness. 2451 */ 2452 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2453 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2454 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2455 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2456 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2457 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2458 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2459 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2460 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2461 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2462 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2463 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2464 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2465 for (i = 0; i < 16; i++) 2466 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2467 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2468 ANA_CPUQ_8021_CFG, i); 2469 2470 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2471 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2472 OCELOT_STATS_CHECK_DELAY); 2473 2474 if (ocelot->ptp) { 2475 ret = ocelot_init_timestamp(ocelot); 2476 if (ret) { 2477 dev_err(ocelot->dev, 2478 "Timestamp initialization failed\n"); 2479 return ret; 2480 } 2481 } 2482 2483 return 0; 2484 } 2485 EXPORT_SYMBOL(ocelot_init); 2486 2487 void ocelot_deinit(struct ocelot *ocelot) 2488 { 2489 struct ocelot_port *port; 2490 int i; 2491 2492 cancel_delayed_work(&ocelot->stats_work); 2493 destroy_workqueue(ocelot->stats_queue); 2494 mutex_destroy(&ocelot->stats_lock); 2495 ocelot_ace_deinit(); 2496 if (ocelot->ptp_clock) 2497 ptp_clock_unregister(ocelot->ptp_clock); 2498 2499 for (i = 0; i < ocelot->num_phys_ports; i++) { 2500 port = ocelot->ports[i]; 2501 skb_queue_purge(&port->tx_skbs); 2502 } 2503 } 2504 EXPORT_SYMBOL(ocelot_deinit); 2505 2506 MODULE_LICENSE("Dual MIT/GPL"); 2507