1*a556c76aSAlexandre Belloni /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*a556c76aSAlexandre Belloni /* 3*a556c76aSAlexandre Belloni * Microsemi Ocelot Switch driver 4*a556c76aSAlexandre Belloni * 5*a556c76aSAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 6*a556c76aSAlexandre Belloni */ 7*a556c76aSAlexandre Belloni 8*a556c76aSAlexandre Belloni #ifndef _MSCC_OCELOT_QS_H_ 9*a556c76aSAlexandre Belloni #define _MSCC_OCELOT_QS_H_ 10*a556c76aSAlexandre Belloni 11*a556c76aSAlexandre Belloni /* TODO handle BE */ 12*a556c76aSAlexandre Belloni #define XTR_EOF_0 0x00000080U 13*a556c76aSAlexandre Belloni #define XTR_EOF_1 0x01000080U 14*a556c76aSAlexandre Belloni #define XTR_EOF_2 0x02000080U 15*a556c76aSAlexandre Belloni #define XTR_EOF_3 0x03000080U 16*a556c76aSAlexandre Belloni #define XTR_PRUNED 0x04000080U 17*a556c76aSAlexandre Belloni #define XTR_ABORT 0x05000080U 18*a556c76aSAlexandre Belloni #define XTR_ESCAPE 0x06000080U 19*a556c76aSAlexandre Belloni #define XTR_NOT_READY 0x07000080U 20*a556c76aSAlexandre Belloni #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) 21*a556c76aSAlexandre Belloni 22*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_RSZ 0x4 23*a556c76aSAlexandre Belloni 24*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 25*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2) 26*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 27*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 28*a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 29*a556c76aSAlexandre Belloni 30*a556c76aSAlexandre Belloni #define QS_XTR_RD_RSZ 0x4 31*a556c76aSAlexandre Belloni 32*a556c76aSAlexandre Belloni #define QS_XTR_FRM_PRUNING_RSZ 0x4 33*a556c76aSAlexandre Belloni 34*a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) 35*a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5) 36*a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) 37*a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) 38*a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2) 39*a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) 40*a556c76aSAlexandre Belloni #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) 41*a556c76aSAlexandre Belloni #define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0) 42*a556c76aSAlexandre Belloni 43*a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_RSZ 0x4 44*a556c76aSAlexandre Belloni 45*a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 46*a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2) 47*a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 48*a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 49*a556c76aSAlexandre Belloni 50*a556c76aSAlexandre Belloni #define QS_INJ_WR_RSZ 0x4 51*a556c76aSAlexandre Belloni 52*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_RSZ 0x4 53*a556c76aSAlexandre Belloni 54*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21)) 55*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21) 56*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21) 57*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_ABORT BIT(20) 58*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_EOF BIT(19) 59*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_SOF BIT(18) 60*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16)) 61*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16) 62*a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16) 63*a556c76aSAlexandre Belloni 64*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4)) 65*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4) 66*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4) 67*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2)) 68*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2) 69*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2) 70*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0)) 71*a556c76aSAlexandre Belloni #define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0) 72*a556c76aSAlexandre Belloni 73*a556c76aSAlexandre Belloni #define QS_INJ_ERR_RSZ 0x4 74*a556c76aSAlexandre Belloni 75*a556c76aSAlexandre Belloni #define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1) 76*a556c76aSAlexandre Belloni #define QS_INJ_ERR_WR_ERR_STICKY BIT(0) 77*a556c76aSAlexandre Belloni 78*a556c76aSAlexandre Belloni #endif 79