1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /** 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 IONIC_CMD_LIF_SETPHC = 25, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 58 /* QoS commands */ 59 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 60 IONIC_CMD_QOS_CLASS_INIT = 241, 61 IONIC_CMD_QOS_CLASS_RESET = 242, 62 IONIC_CMD_QOS_CLASS_UPDATE = 243, 63 IONIC_CMD_QOS_CLEAR_STATS = 244, 64 IONIC_CMD_QOS_RESET = 245, 65 66 /* Firmware commands */ 67 IONIC_CMD_FW_DOWNLOAD = 252, 68 IONIC_CMD_FW_CONTROL = 253, 69 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 70 IONIC_CMD_FW_CONTROL_V1 = 255, 71 }; 72 73 /** 74 * enum ionic_status_code - Device command return codes 75 */ 76 enum ionic_status_code { 77 IONIC_RC_SUCCESS = 0, /* Success */ 78 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 79 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 80 IONIC_RC_EIO = 3, /* I/O error */ 81 IONIC_RC_EPERM = 4, /* Permission denied */ 82 IONIC_RC_EQID = 5, /* Bad qid */ 83 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 84 IONIC_RC_ENOENT = 7, /* No such element */ 85 IONIC_RC_EINTR = 8, /* operation interrupted */ 86 IONIC_RC_EAGAIN = 9, /* Try again */ 87 IONIC_RC_ENOMEM = 10, /* Out of memory */ 88 IONIC_RC_EFAULT = 11, /* Bad address */ 89 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 90 IONIC_RC_EEXIST = 13, /* object already exists */ 91 IONIC_RC_EINVAL = 14, /* Invalid argument */ 92 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 93 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 94 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 95 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 96 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 97 IONIC_RC_ERROR = 29, /* Generic error */ 98 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 99 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 100 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 101 }; 102 103 enum ionic_notifyq_opcode { 104 IONIC_EVENT_LINK_CHANGE = 1, 105 IONIC_EVENT_RESET = 2, 106 IONIC_EVENT_HEARTBEAT = 3, 107 IONIC_EVENT_LOG = 4, 108 IONIC_EVENT_XCVR = 5, 109 }; 110 111 /** 112 * struct ionic_admin_cmd - General admin command format 113 * @opcode: Opcode for the command 114 * @lif_index: LIF index 115 * @cmd_data: Opcode-specific command bytes 116 */ 117 struct ionic_admin_cmd { 118 u8 opcode; 119 u8 rsvd; 120 __le16 lif_index; 121 u8 cmd_data[60]; 122 }; 123 124 /** 125 * struct ionic_admin_comp - General admin command completion format 126 * @status: Status of the command (enum ionic_status_code) 127 * @comp_index: Index in the descriptor ring for which this is the completion 128 * @cmd_data: Command-specific bytes 129 * @color: Color bit (Always 0 for commands issued to the 130 * Device Cmd Registers) 131 */ 132 struct ionic_admin_comp { 133 u8 status; 134 u8 rsvd; 135 __le16 comp_index; 136 u8 cmd_data[11]; 137 u8 color; 138 #define IONIC_COMP_COLOR_MASK 0x80 139 }; 140 141 static inline u8 color_match(u8 color, u8 done_color) 142 { 143 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 144 } 145 146 /** 147 * struct ionic_nop_cmd - NOP command 148 * @opcode: opcode 149 */ 150 struct ionic_nop_cmd { 151 u8 opcode; 152 u8 rsvd[63]; 153 }; 154 155 /** 156 * struct ionic_nop_comp - NOP command completion 157 * @status: Status of the command (enum ionic_status_code) 158 */ 159 struct ionic_nop_comp { 160 u8 status; 161 u8 rsvd[15]; 162 }; 163 164 /** 165 * struct ionic_dev_init_cmd - Device init command 166 * @opcode: opcode 167 * @type: Device type 168 */ 169 struct ionic_dev_init_cmd { 170 u8 opcode; 171 u8 type; 172 u8 rsvd[62]; 173 }; 174 175 /** 176 * struct ionic_dev_init_comp - Device init command completion 177 * @status: Status of the command (enum ionic_status_code) 178 */ 179 struct ionic_dev_init_comp { 180 u8 status; 181 u8 rsvd[15]; 182 }; 183 184 /** 185 * struct ionic_dev_reset_cmd - Device reset command 186 * @opcode: opcode 187 */ 188 struct ionic_dev_reset_cmd { 189 u8 opcode; 190 u8 rsvd[63]; 191 }; 192 193 /** 194 * struct ionic_dev_reset_comp - Reset command completion 195 * @status: Status of the command (enum ionic_status_code) 196 */ 197 struct ionic_dev_reset_comp { 198 u8 status; 199 u8 rsvd[15]; 200 }; 201 202 #define IONIC_IDENTITY_VERSION_1 1 203 204 /** 205 * struct ionic_dev_identify_cmd - Driver/device identify command 206 * @opcode: opcode 207 * @ver: Highest version of identify supported by driver 208 */ 209 struct ionic_dev_identify_cmd { 210 u8 opcode; 211 u8 ver; 212 u8 rsvd[62]; 213 }; 214 215 /** 216 * struct ionic_dev_identify_comp - Driver/device identify command completion 217 * @status: Status of the command (enum ionic_status_code) 218 * @ver: Version of identify returned by device 219 */ 220 struct ionic_dev_identify_comp { 221 u8 status; 222 u8 ver; 223 u8 rsvd[14]; 224 }; 225 226 enum ionic_os_type { 227 IONIC_OS_TYPE_LINUX = 1, 228 IONIC_OS_TYPE_WIN = 2, 229 IONIC_OS_TYPE_DPDK = 3, 230 IONIC_OS_TYPE_FREEBSD = 4, 231 IONIC_OS_TYPE_IPXE = 5, 232 IONIC_OS_TYPE_ESXI = 6, 233 }; 234 235 /** 236 * union ionic_drv_identity - driver identity information 237 * @os_type: OS type (see enum ionic_os_type) 238 * @os_dist: OS distribution, numeric format 239 * @os_dist_str: OS distribution, string format 240 * @kernel_ver: Kernel version, numeric format 241 * @kernel_ver_str: Kernel version, string format 242 * @driver_ver_str: Driver version, string format 243 */ 244 union ionic_drv_identity { 245 struct { 246 __le32 os_type; 247 __le32 os_dist; 248 char os_dist_str[128]; 249 __le32 kernel_ver; 250 char kernel_ver_str[32]; 251 char driver_ver_str[32]; 252 }; 253 __le32 words[478]; 254 }; 255 256 /** 257 * union ionic_dev_identity - device identity information 258 * @version: Version of device identify 259 * @type: Identify type (0 for now) 260 * @nports: Number of ports provisioned 261 * @nlifs: Number of LIFs provisioned 262 * @nintrs: Number of interrupts provisioned 263 * @ndbpgs_per_lif: Number of doorbell pages per LIF 264 * @intr_coal_mult: Interrupt coalescing multiplication factor 265 * Scale user-supplied interrupt coalescing 266 * value in usecs to device units using: 267 * device units = usecs * mult / div 268 * @intr_coal_div: Interrupt coalescing division factor 269 * Scale user-supplied interrupt coalescing 270 * value in usecs to device units using: 271 * device units = usecs * mult / div 272 * @eq_count: Number of shared event queues 273 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 274 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 275 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 276 */ 277 union ionic_dev_identity { 278 struct { 279 u8 version; 280 u8 type; 281 u8 rsvd[2]; 282 u8 nports; 283 u8 rsvd2[3]; 284 __le32 nlifs; 285 __le32 nintrs; 286 __le32 ndbpgs_per_lif; 287 __le32 intr_coal_mult; 288 __le32 intr_coal_div; 289 __le32 eq_count; 290 __le64 hwstamp_mask; 291 __le32 hwstamp_mult; 292 __le32 hwstamp_shift; 293 }; 294 __le32 words[478]; 295 }; 296 297 enum ionic_lif_type { 298 IONIC_LIF_TYPE_CLASSIC = 0, 299 IONIC_LIF_TYPE_MACVLAN = 1, 300 IONIC_LIF_TYPE_NETQUEUE = 2, 301 }; 302 303 /** 304 * struct ionic_lif_identify_cmd - LIF identify command 305 * @opcode: opcode 306 * @type: LIF type (enum ionic_lif_type) 307 * @ver: Version of identify returned by device 308 */ 309 struct ionic_lif_identify_cmd { 310 u8 opcode; 311 u8 type; 312 u8 ver; 313 u8 rsvd[61]; 314 }; 315 316 /** 317 * struct ionic_lif_identify_comp - LIF identify command completion 318 * @status: Status of the command (enum ionic_status_code) 319 * @ver: Version of identify returned by device 320 */ 321 struct ionic_lif_identify_comp { 322 u8 status; 323 u8 ver; 324 u8 rsvd2[14]; 325 }; 326 327 /** 328 * enum ionic_lif_capability - LIF capabilities 329 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 330 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 331 */ 332 enum ionic_lif_capability { 333 IONIC_LIF_CAP_ETH = BIT(0), 334 IONIC_LIF_CAP_RDMA = BIT(1), 335 }; 336 337 /** 338 * enum ionic_logical_qtype - Logical Queue Types 339 * @IONIC_QTYPE_ADMINQ: Administrative Queue 340 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 341 * @IONIC_QTYPE_RXQ: Receive Queue 342 * @IONIC_QTYPE_TXQ: Transmit Queue 343 * @IONIC_QTYPE_EQ: Event Queue 344 * @IONIC_QTYPE_MAX: Max queue type supported 345 */ 346 enum ionic_logical_qtype { 347 IONIC_QTYPE_ADMINQ = 0, 348 IONIC_QTYPE_NOTIFYQ = 1, 349 IONIC_QTYPE_RXQ = 2, 350 IONIC_QTYPE_TXQ = 3, 351 IONIC_QTYPE_EQ = 4, 352 IONIC_QTYPE_MAX = 16, 353 }; 354 355 /** 356 * enum ionic_q_feature - Common Features for most queue types 357 * 358 * Common features use bits 0-15. Per-queue-type features use higher bits. 359 * 360 * @IONIC_QIDENT_F_CQ: Queue has completion ring 361 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 362 * @IONIC_QIDENT_F_EQ: Queue can use event queue 363 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 364 * @IONIC_Q_F_2X_DESC: Double main descriptor size 365 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 366 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 367 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 368 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 369 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 370 */ 371 enum ionic_q_feature { 372 IONIC_QIDENT_F_CQ = BIT_ULL(0), 373 IONIC_QIDENT_F_SG = BIT_ULL(1), 374 IONIC_QIDENT_F_EQ = BIT_ULL(2), 375 IONIC_QIDENT_F_CMB = BIT_ULL(3), 376 IONIC_Q_F_2X_DESC = BIT_ULL(4), 377 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 378 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 379 IONIC_Q_F_4X_DESC = BIT_ULL(7), 380 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 381 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 382 }; 383 384 /** 385 * enum ionic_rxq_feature - RXQ-specific Features 386 * 387 * Per-queue-type features use bits 16 and higher. 388 * 389 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 390 */ 391 enum ionic_rxq_feature { 392 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 393 }; 394 395 /** 396 * enum ionic_txq_feature - TXQ-specific Features 397 * 398 * Per-queue-type features use bits 16 and higher. 399 * 400 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 401 */ 402 enum ionic_txq_feature { 403 IONIC_TXQ_F_HWSTAMP = BIT(16), 404 }; 405 406 /** 407 * struct ionic_hwstamp_bits - Hardware timestamp decoding bits 408 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 409 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 410 * from the base cq descriptor. 411 */ 412 enum ionic_hwstamp_bits { 413 IONIC_HWSTAMP_INVALID = ~0ull, 414 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 415 }; 416 417 /** 418 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 419 * @qtype: Hardware Queue Type 420 * @qid_count: Number of Queue IDs of the logical type 421 * @qid_base: Minimum Queue ID of the logical type 422 */ 423 struct ionic_lif_logical_qtype { 424 u8 qtype; 425 u8 rsvd[3]; 426 __le32 qid_count; 427 __le32 qid_base; 428 }; 429 430 /** 431 * enum ionic_lif_state - LIF state 432 * @IONIC_LIF_DISABLE: LIF disabled 433 * @IONIC_LIF_ENABLE: LIF enabled 434 * @IONIC_LIF_QUIESCE: LIF Quiesced 435 */ 436 enum ionic_lif_state { 437 IONIC_LIF_QUIESCE = 0, 438 IONIC_LIF_ENABLE = 1, 439 IONIC_LIF_DISABLE = 2, 440 }; 441 442 /** 443 * union ionic_lif_config - LIF configuration 444 * @state: LIF state (enum ionic_lif_state) 445 * @name: LIF name 446 * @mtu: MTU 447 * @mac: Station MAC address 448 * @vlan: Default Vlan ID 449 * @features: Features (enum ionic_eth_hw_features) 450 * @queue_count: Queue counts per queue-type 451 */ 452 union ionic_lif_config { 453 struct { 454 u8 state; 455 u8 rsvd[3]; 456 char name[IONIC_IFNAMSIZ]; 457 __le32 mtu; 458 u8 mac[6]; 459 __le16 vlan; 460 __le64 features; 461 __le32 queue_count[IONIC_QTYPE_MAX]; 462 } __packed; 463 __le32 words[64]; 464 }; 465 466 /** 467 * struct ionic_lif_identity - LIF identity information (type-specific) 468 * 469 * @capabilities: LIF capabilities 470 * 471 * @eth: Ethernet identify structure 472 * @version: Ethernet identify structure version 473 * @max_ucast_filters: Number of perfect unicast addresses supported 474 * @max_mcast_filters: Number of perfect multicast addresses supported 475 * @min_frame_size: Minimum size of frames to be sent 476 * @max_frame_size: Maximum size of frames to be sent 477 * @hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 478 * @hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 479 * @config: LIF config struct with features, mtu, mac, q counts 480 * 481 * @rdma: RDMA identify structure 482 * @version: RDMA version of opcodes and queue descriptors 483 * @qp_opcodes: Number of RDMA queue pair opcodes supported 484 * @admin_opcodes: Number of RDMA admin opcodes supported 485 * @npts_per_lif: Page table size per LIF 486 * @nmrs_per_lif: Number of memory regions per LIF 487 * @nahs_per_lif: Number of address handles per LIF 488 * @max_stride: Max work request stride 489 * @cl_stride: Cache line stride 490 * @pte_stride: Page table entry stride 491 * @rrq_stride: Remote RQ work request stride 492 * @rsq_stride: Remote SQ work request stride 493 * @dcqcn_profiles: Number of DCQCN profiles 494 * @aq_qtype: RDMA Admin Qtype 495 * @sq_qtype: RDMA Send Qtype 496 * @rq_qtype: RDMA Receive Qtype 497 * @cq_qtype: RDMA Completion Qtype 498 * @eq_qtype: RDMA Event Qtype 499 */ 500 union ionic_lif_identity { 501 struct { 502 __le64 capabilities; 503 504 struct { 505 u8 version; 506 u8 rsvd[3]; 507 __le32 max_ucast_filters; 508 __le32 max_mcast_filters; 509 __le16 rss_ind_tbl_sz; 510 __le32 min_frame_size; 511 __le32 max_frame_size; 512 u8 rsvd2[2]; 513 __le64 hwstamp_tx_modes; 514 __le64 hwstamp_rx_filters; 515 u8 rsvd3[88]; 516 union ionic_lif_config config; 517 } __packed eth; 518 519 struct { 520 u8 version; 521 u8 qp_opcodes; 522 u8 admin_opcodes; 523 u8 rsvd; 524 __le32 npts_per_lif; 525 __le32 nmrs_per_lif; 526 __le32 nahs_per_lif; 527 u8 max_stride; 528 u8 cl_stride; 529 u8 pte_stride; 530 u8 rrq_stride; 531 u8 rsq_stride; 532 u8 dcqcn_profiles; 533 u8 rsvd_dimensions[10]; 534 struct ionic_lif_logical_qtype aq_qtype; 535 struct ionic_lif_logical_qtype sq_qtype; 536 struct ionic_lif_logical_qtype rq_qtype; 537 struct ionic_lif_logical_qtype cq_qtype; 538 struct ionic_lif_logical_qtype eq_qtype; 539 } __packed rdma; 540 } __packed; 541 __le32 words[478]; 542 }; 543 544 /** 545 * struct ionic_lif_init_cmd - LIF init command 546 * @opcode: Opcode 547 * @type: LIF type (enum ionic_lif_type) 548 * @index: LIF index 549 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 550 */ 551 struct ionic_lif_init_cmd { 552 u8 opcode; 553 u8 type; 554 __le16 index; 555 __le32 rsvd; 556 __le64 info_pa; 557 u8 rsvd2[48]; 558 }; 559 560 /** 561 * struct ionic_lif_init_comp - LIF init command completion 562 * @status: Status of the command (enum ionic_status_code) 563 * @hw_index: Hardware index of the initialized LIF 564 */ 565 struct ionic_lif_init_comp { 566 u8 status; 567 u8 rsvd; 568 __le16 hw_index; 569 u8 rsvd2[12]; 570 }; 571 572 /** 573 * struct ionic_q_identify_cmd - queue identify command 574 * @opcode: opcode 575 * @lif_type: LIF type (enum ionic_lif_type) 576 * @type: Logical queue type (enum ionic_logical_qtype) 577 * @ver: Highest queue type version that the driver supports 578 */ 579 struct ionic_q_identify_cmd { 580 u8 opcode; 581 u8 rsvd; 582 __le16 lif_type; 583 u8 type; 584 u8 ver; 585 u8 rsvd2[58]; 586 }; 587 588 /** 589 * struct ionic_q_identify_comp - queue identify command completion 590 * @status: Status of the command (enum ionic_status_code) 591 * @comp_index: Index in the descriptor ring for which this is the completion 592 * @ver: Queue type version that can be used with FW 593 */ 594 struct ionic_q_identify_comp { 595 u8 status; 596 u8 rsvd; 597 __le16 comp_index; 598 u8 ver; 599 u8 rsvd2[11]; 600 }; 601 602 /** 603 * union ionic_q_identity - queue identity information 604 * @version: Queue type version that can be used with FW 605 * @supported: Bitfield of queue versions, first bit = ver 0 606 * @features: Queue features (enum ionic_q_feature, etc) 607 * @desc_sz: Descriptor size 608 * @comp_sz: Completion descriptor size 609 * @sg_desc_sz: Scatter/Gather descriptor size 610 * @max_sg_elems: Maximum number of Scatter/Gather elements 611 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 612 */ 613 union ionic_q_identity { 614 struct { 615 u8 version; 616 u8 supported; 617 u8 rsvd[6]; 618 __le64 features; 619 __le16 desc_sz; 620 __le16 comp_sz; 621 __le16 sg_desc_sz; 622 __le16 max_sg_elems; 623 __le16 sg_desc_stride; 624 }; 625 __le32 words[478]; 626 }; 627 628 /** 629 * struct ionic_q_init_cmd - Queue init command 630 * @opcode: opcode 631 * @type: Logical queue type 632 * @ver: Queue type version 633 * @lif_index: LIF index 634 * @index: (LIF, qtype) relative admin queue index 635 * @intr_index: Interrupt control register index, or Event queue index 636 * @pid: Process ID 637 * @flags: 638 * IRQ: Interrupt requested on completion 639 * ENA: Enable the queue. If ENA=0 the queue is initialized 640 * but remains disabled, to be later enabled with the 641 * Queue Enable command. If ENA=1, then queue is 642 * initialized and then enabled. 643 * SG: Enable Scatter-Gather on the queue. 644 * in number of descs. The actual ring size is 645 * (1 << ring_size). For example, to 646 * select a ring size of 64 descriptors write 647 * ring_size = 6. The minimum ring_size value is 2 648 * for a ring size of 4 descriptors. The maximum 649 * ring_size value is 16 for a ring size of 64k 650 * descriptors. Values of ring_size <2 and >16 are 651 * reserved. 652 * EQ: Enable the Event Queue 653 * @cos: Class of service for this queue 654 * @ring_size: Queue ring size, encoded as a log2(size) 655 * @ring_base: Queue ring base address 656 * @cq_ring_base: Completion queue ring base address 657 * @sg_ring_base: Scatter/Gather ring base address 658 * @features: Mask of queue features to enable, if not in the flags above. 659 */ 660 struct ionic_q_init_cmd { 661 u8 opcode; 662 u8 rsvd; 663 __le16 lif_index; 664 u8 type; 665 u8 ver; 666 u8 rsvd1[2]; 667 __le32 index; 668 __le16 pid; 669 __le16 intr_index; 670 __le16 flags; 671 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 672 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 673 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 674 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 675 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 676 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 677 u8 cos; 678 u8 ring_size; 679 __le64 ring_base; 680 __le64 cq_ring_base; 681 __le64 sg_ring_base; 682 u8 rsvd2[12]; 683 __le64 features; 684 } __packed; 685 686 /** 687 * struct ionic_q_init_comp - Queue init command completion 688 * @status: Status of the command (enum ionic_status_code) 689 * @comp_index: Index in the descriptor ring for which this is the completion 690 * @hw_index: Hardware Queue ID 691 * @hw_type: Hardware Queue type 692 * @color: Color 693 */ 694 struct ionic_q_init_comp { 695 u8 status; 696 u8 rsvd; 697 __le16 comp_index; 698 __le32 hw_index; 699 u8 hw_type; 700 u8 rsvd2[6]; 701 u8 color; 702 }; 703 704 /* the device's internal addressing uses up to 52 bits */ 705 #define IONIC_ADDR_LEN 52 706 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 707 708 enum ionic_txq_desc_opcode { 709 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 710 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 711 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 712 IONIC_TXQ_DESC_OPCODE_TSO = 3, 713 }; 714 715 /** 716 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 717 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 718 * 719 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 720 * Non-offload send. No segmentation, 721 * fragmentation or checksum calc/insertion is 722 * performed by device; packet is prepared 723 * to send by software stack and requires 724 * no further manipulation from device. 725 * 726 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 727 * Offload 16-bit L4 checksum 728 * calculation/insertion. The device will 729 * calculate the L4 checksum value and 730 * insert the result in the packet's L4 731 * header checksum field. The L4 checksum 732 * is calculated starting at @csum_start bytes 733 * into the packet to the end of the packet. 734 * The checksum insertion position is given 735 * in @csum_offset, which is the offset from 736 * @csum_start to the checksum field in the L4 737 * header. This feature is only applicable to 738 * protocols such as TCP, UDP and ICMP where a 739 * standard (i.e. the 'IP-style' checksum) 740 * one's complement 16-bit checksum is used, 741 * using an IP pseudo-header to seed the 742 * calculation. Software will preload the L4 743 * checksum field with the IP pseudo-header 744 * checksum. 745 * 746 * For tunnel encapsulation, @csum_start and 747 * @csum_offset refer to the inner L4 748 * header. Supported tunnels encapsulations 749 * are: IPIP, GRE, and UDP. If the @encap 750 * is clear, no further processing by the 751 * device is required; software will 752 * calculate the outer header checksums. If 753 * the @encap is set, the device will 754 * offload the outer header checksums using 755 * LCO (local checksum offload) (see 756 * Documentation/networking/checksum-offloads.rst 757 * for more info). 758 * 759 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 760 * Offload 16-bit checksum computation to hardware. 761 * If @csum_l3 is set then the packet's L3 checksum is 762 * updated. Similarly, if @csum_l4 is set the L4 763 * checksum is updated. If @encap is set then encap header 764 * checksums are also updated. 765 * 766 * IONIC_TXQ_DESC_OPCODE_TSO: 767 * Device performs TCP segmentation offload 768 * (TSO). @hdr_len is the number of bytes 769 * to the end of TCP header (the offset to 770 * the TCP payload). @mss is the desired 771 * MSS, the TCP payload length for each 772 * segment. The device will calculate/ 773 * insert IP (IPv4 only) and TCP checksums 774 * for each segment. In the first data 775 * buffer containing the header template, 776 * the driver will set IPv4 checksum to 0 777 * and preload TCP checksum with the IP 778 * pseudo header calculated with IP length = 0. 779 * 780 * Supported tunnel encapsulations are IPIP, 781 * layer-3 GRE, and UDP. @hdr_len includes 782 * both outer and inner headers. The driver 783 * will set IPv4 checksum to zero and 784 * preload TCP checksum with IP pseudo 785 * header on the inner header. 786 * 787 * TCP ECN offload is supported. The device 788 * will set CWR flag in the first segment if 789 * CWR is set in the template header, and 790 * clear CWR in remaining segments. 791 * @flags: 792 * vlan: 793 * Insert an L2 VLAN header using @vlan_tci 794 * encap: 795 * Calculate encap header checksum 796 * csum_l3: 797 * Compute L3 header checksum 798 * csum_l4: 799 * Compute L4 header checksum 800 * tso_sot: 801 * TSO start 802 * tso_eot: 803 * TSO end 804 * @num_sg_elems: Number of scatter-gather elements in SG 805 * descriptor 806 * @addr: First data buffer's DMA address 807 * (Subsequent data buffers are on txq_sg_desc) 808 * @len: First data buffer's length, in bytes 809 * @vlan_tci: VLAN tag to insert in the packet (if requested 810 * by @V-bit). Includes .1p and .1q tags 811 * @hdr_len: Length of packet headers, including 812 * encapsulating outer header, if applicable 813 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 814 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 815 * all other modes. For 816 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 817 * of headers up to inner-most L4 header. For 818 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 819 * inner-most L4 payload, so inclusive of 820 * inner-most L4 header. 821 * @mss: Desired MSS value for TSO; only applicable for 822 * IONIC_TXQ_DESC_OPCODE_TSO 823 * @csum_start: Offset from packet to first byte checked in L4 checksum 824 * @csum_offset: Offset from csum_start to L4 checksum field 825 */ 826 struct ionic_txq_desc { 827 __le64 cmd; 828 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 829 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 830 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 831 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 832 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 833 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 834 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 835 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 836 837 /* common flags */ 838 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 839 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 840 841 /* flags for csum_hw opcode */ 842 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 843 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 844 845 /* flags for tso opcode */ 846 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 847 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 848 849 __le16 len; 850 union { 851 __le16 vlan_tci; 852 __le16 hword0; 853 }; 854 union { 855 __le16 csum_start; 856 __le16 hdr_len; 857 __le16 hword1; 858 }; 859 union { 860 __le16 csum_offset; 861 __le16 mss; 862 __le16 hword2; 863 }; 864 }; 865 866 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 867 u8 nsge, u64 addr) 868 { 869 u64 cmd; 870 871 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 872 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 873 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 874 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 875 876 return cmd; 877 }; 878 879 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 880 u8 *nsge, u64 *addr) 881 { 882 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 883 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 884 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 885 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 886 }; 887 888 /** 889 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 890 * @addr: DMA address of SG element data buffer 891 * @len: Length of SG element data buffer, in bytes 892 */ 893 struct ionic_txq_sg_elem { 894 __le64 addr; 895 __le16 len; 896 __le16 rsvd[3]; 897 }; 898 899 /** 900 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 901 * @elems: Scatter-gather elements 902 */ 903 struct ionic_txq_sg_desc { 904 #define IONIC_TX_MAX_SG_ELEMS 8 905 #define IONIC_TX_SG_DESC_STRIDE 8 906 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 907 }; 908 909 struct ionic_txq_sg_desc_v1 { 910 #define IONIC_TX_MAX_SG_ELEMS_V1 15 911 #define IONIC_TX_SG_DESC_STRIDE_V1 16 912 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 913 }; 914 915 /** 916 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 917 * @status: Status of the command (enum ionic_status_code) 918 * @comp_index: Index in the descriptor ring for which this is the completion 919 * @color: Color bit 920 */ 921 struct ionic_txq_comp { 922 u8 status; 923 u8 rsvd; 924 __le16 comp_index; 925 u8 rsvd2[11]; 926 u8 color; 927 }; 928 929 enum ionic_rxq_desc_opcode { 930 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 931 IONIC_RXQ_DESC_OPCODE_SG = 1, 932 }; 933 934 /** 935 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 936 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 937 * 938 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 939 * Receive full packet into data buffer 940 * starting at @addr. Results of 941 * receive, including actual bytes received, 942 * are recorded in Rx completion descriptor. 943 * 944 * @len: Data buffer's length, in bytes 945 * @addr: Data buffer's DMA address 946 */ 947 struct ionic_rxq_desc { 948 u8 opcode; 949 u8 rsvd[5]; 950 __le16 len; 951 __le64 addr; 952 }; 953 954 /** 955 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 956 * @addr: DMA address of SG element data buffer 957 * @len: Length of SG element data buffer, in bytes 958 */ 959 struct ionic_rxq_sg_elem { 960 __le64 addr; 961 __le16 len; 962 __le16 rsvd[3]; 963 }; 964 965 /** 966 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 967 * @elems: Scatter-gather elements 968 */ 969 struct ionic_rxq_sg_desc { 970 #define IONIC_RX_MAX_SG_ELEMS 8 971 #define IONIC_RX_SG_DESC_STRIDE 8 972 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 973 }; 974 975 /** 976 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 977 * @status: Status of the command (enum ionic_status_code) 978 * @num_sg_elems: Number of SG elements used by this descriptor 979 * @comp_index: Index in the descriptor ring for which this is the completion 980 * @rss_hash: 32-bit RSS hash 981 * @csum: 16-bit sum of the packet's L2 payload 982 * If the packet's L2 payload is odd length, an extra 983 * zero-value byte is included in the @csum calculation but 984 * not included in @len. 985 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 986 * set. Includes .1p and .1q tags. 987 * @len: Received packet length, in bytes. Excludes FCS. 988 * @csum_calc L2 payload checksum is computed or not 989 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 990 * 991 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 992 * The TCP checksum calculated by the device 993 * matched the checksum in the receive packet's 994 * TCP header. 995 * 996 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 997 * The TCP checksum calculated by the device did 998 * not match the checksum in the receive packet's 999 * TCP header. 1000 * 1001 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1002 * The UDP checksum calculated by the device 1003 * matched the checksum in the receive packet's 1004 * UDP header 1005 * 1006 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1007 * The UDP checksum calculated by the device did 1008 * not match the checksum in the receive packet's 1009 * UDP header. 1010 * 1011 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1012 * The IPv4 checksum calculated by the device 1013 * matched the checksum in the receive packet's 1014 * first IPv4 header. If the receive packet 1015 * contains both a tunnel IPv4 header and a 1016 * transport IPv4 header, the device validates the 1017 * checksum for the both IPv4 headers. 1018 * 1019 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1020 * The IPv4 checksum calculated by the device did 1021 * not match the checksum in the receive packet's 1022 * first IPv4 header. If the receive packet 1023 * contains both a tunnel IPv4 header and a 1024 * transport IPv4 header, the device validates the 1025 * checksum for both IP headers. 1026 * 1027 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1028 * The VLAN header was stripped and placed in @vlan_tci. 1029 * 1030 * IONIC_RXQ_COMP_CSUM_F_CALC: 1031 * The checksum was calculated by the device. 1032 * 1033 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1034 */ 1035 struct ionic_rxq_comp { 1036 u8 status; 1037 u8 num_sg_elems; 1038 __le16 comp_index; 1039 __le32 rss_hash; 1040 __le16 csum; 1041 __le16 vlan_tci; 1042 __le16 len; 1043 u8 csum_flags; 1044 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1045 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1046 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1047 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1048 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1049 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1050 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1051 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1052 u8 pkt_type_color; 1053 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1054 }; 1055 1056 enum ionic_pkt_type { 1057 IONIC_PKT_TYPE_NON_IP = 0x00, 1058 IONIC_PKT_TYPE_IPV4 = 0x01, 1059 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1060 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1061 IONIC_PKT_TYPE_IPV6 = 0x08, 1062 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1063 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1064 /* below types are only used if encap offloads are enabled on lif */ 1065 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1066 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1067 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1068 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1069 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1070 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1071 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1072 }; 1073 1074 enum ionic_eth_hw_features { 1075 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1076 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1077 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1078 IONIC_ETH_HW_RX_HASH = BIT(3), 1079 IONIC_ETH_HW_RX_CSUM = BIT(4), 1080 IONIC_ETH_HW_TX_SG = BIT(5), 1081 IONIC_ETH_HW_RX_SG = BIT(6), 1082 IONIC_ETH_HW_TX_CSUM = BIT(7), 1083 IONIC_ETH_HW_TSO = BIT(8), 1084 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1085 IONIC_ETH_HW_TSO_ECN = BIT(10), 1086 IONIC_ETH_HW_TSO_GRE = BIT(11), 1087 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1088 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1089 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1090 IONIC_ETH_HW_TSO_UDP = BIT(15), 1091 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1092 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1093 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1094 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1095 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1096 }; 1097 1098 /** 1099 * enum ionic_pkt_class - Packet classification mask. 1100 * 1101 * Used with rx steering filter, packets indicated by the mask can be steered 1102 * toward a specific receive queue. 1103 * 1104 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1105 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1106 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1107 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1108 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1109 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1110 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1111 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1112 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1113 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1114 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1115 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1116 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1117 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1118 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1119 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1120 */ 1121 enum ionic_pkt_class { 1122 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1123 1124 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1125 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1126 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1127 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1128 1129 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1130 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1131 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1132 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1133 1134 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1135 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1136 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1137 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1138 1139 IONIC_PKT_CLS_PTP2_SYNC = 1140 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1141 IONIC_PKT_CLS_PTP2_DREQ = 1142 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1143 IONIC_PKT_CLS_PTP2_ALL = 1144 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1145 1146 IONIC_PKT_CLS_PTP_SYNC = 1147 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1148 IONIC_PKT_CLS_PTP_DREQ = 1149 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1150 IONIC_PKT_CLS_PTP_ALL = 1151 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1152 }; 1153 1154 /** 1155 * struct ionic_q_control_cmd - Queue control command 1156 * @opcode: opcode 1157 * @type: Queue type 1158 * @lif_index: LIF index 1159 * @index: Queue index 1160 * @oper: Operation (enum ionic_q_control_oper) 1161 */ 1162 struct ionic_q_control_cmd { 1163 u8 opcode; 1164 u8 type; 1165 __le16 lif_index; 1166 __le32 index; 1167 u8 oper; 1168 u8 rsvd[55]; 1169 }; 1170 1171 typedef struct ionic_admin_comp ionic_q_control_comp; 1172 1173 enum q_control_oper { 1174 IONIC_Q_DISABLE = 0, 1175 IONIC_Q_ENABLE = 1, 1176 IONIC_Q_HANG_RESET = 2, 1177 }; 1178 1179 /** 1180 * enum ionic_phy_type - Physical connection type 1181 * @IONIC_PHY_TYPE_NONE: No PHY installed 1182 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1183 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1184 */ 1185 enum ionic_phy_type { 1186 IONIC_PHY_TYPE_NONE = 0, 1187 IONIC_PHY_TYPE_COPPER = 1, 1188 IONIC_PHY_TYPE_FIBER = 2, 1189 }; 1190 1191 /** 1192 * enum ionic_xcvr_state - Transceiver status 1193 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1194 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1195 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1196 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1197 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1198 */ 1199 enum ionic_xcvr_state { 1200 IONIC_XCVR_STATE_REMOVED = 0, 1201 IONIC_XCVR_STATE_INSERTED = 1, 1202 IONIC_XCVR_STATE_PENDING = 2, 1203 IONIC_XCVR_STATE_SPROM_READ = 3, 1204 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1205 }; 1206 1207 /** 1208 * enum ionic_xcvr_pid - Supported link modes 1209 */ 1210 enum ionic_xcvr_pid { 1211 IONIC_XCVR_PID_UNKNOWN = 0, 1212 1213 /* CU */ 1214 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1215 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1216 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1217 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1218 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1219 1220 /* Fiber */ 1221 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1222 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1223 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1224 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1225 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1226 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1227 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1228 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1229 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1230 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1231 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1232 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1233 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1234 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1235 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1236 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1237 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1238 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1239 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1240 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1241 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1242 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1243 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1244 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1245 }; 1246 1247 /** 1248 * enum ionic_port_type - Port types 1249 * @IONIC_PORT_TYPE_NONE: Port type not configured 1250 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1251 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1252 */ 1253 enum ionic_port_type { 1254 IONIC_PORT_TYPE_NONE = 0, 1255 IONIC_PORT_TYPE_ETH = 1, 1256 IONIC_PORT_TYPE_MGMT = 2, 1257 }; 1258 1259 /** 1260 * enum ionic_port_admin_state - Port config state 1261 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1262 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1263 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1264 */ 1265 enum ionic_port_admin_state { 1266 IONIC_PORT_ADMIN_STATE_NONE = 0, 1267 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1268 IONIC_PORT_ADMIN_STATE_UP = 2, 1269 }; 1270 1271 /** 1272 * enum ionic_port_oper_status - Port operational status 1273 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1274 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1275 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1276 */ 1277 enum ionic_port_oper_status { 1278 IONIC_PORT_OPER_STATUS_NONE = 0, 1279 IONIC_PORT_OPER_STATUS_UP = 1, 1280 IONIC_PORT_OPER_STATUS_DOWN = 2, 1281 }; 1282 1283 /** 1284 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1285 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1286 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1287 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1288 */ 1289 enum ionic_port_fec_type { 1290 IONIC_PORT_FEC_TYPE_NONE = 0, 1291 IONIC_PORT_FEC_TYPE_FC = 1, 1292 IONIC_PORT_FEC_TYPE_RS = 2, 1293 }; 1294 1295 /** 1296 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1297 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1298 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1299 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1300 */ 1301 enum ionic_port_pause_type { 1302 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1303 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1304 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1305 }; 1306 1307 /** 1308 * enum ionic_port_loopback_mode - Loopback modes 1309 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1310 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1311 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1312 */ 1313 enum ionic_port_loopback_mode { 1314 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1315 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1316 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1317 }; 1318 1319 /** 1320 * struct ionic_xcvr_status - Transceiver Status information 1321 * @state: Transceiver status (enum ionic_xcvr_state) 1322 * @phy: Physical connection type (enum ionic_phy_type) 1323 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1324 * @sprom: Transceiver sprom contents 1325 */ 1326 struct ionic_xcvr_status { 1327 u8 state; 1328 u8 phy; 1329 __le16 pid; 1330 u8 sprom[256]; 1331 }; 1332 1333 /** 1334 * union ionic_port_config - Port configuration 1335 * @speed: port speed (in Mbps) 1336 * @mtu: mtu 1337 * @state: port admin state (enum ionic_port_admin_state) 1338 * @an_enable: autoneg enable 1339 * @fec_type: fec type (enum ionic_port_fec_type) 1340 * @pause_type: pause type (enum ionic_port_pause_type) 1341 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1342 */ 1343 union ionic_port_config { 1344 struct { 1345 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1346 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1347 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1348 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1349 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1350 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1351 __le32 speed; 1352 __le32 mtu; 1353 u8 state; 1354 u8 an_enable; 1355 u8 fec_type; 1356 #define IONIC_PAUSE_TYPE_MASK 0x0f 1357 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1358 #define IONIC_PAUSE_F_TX 0x10 1359 #define IONIC_PAUSE_F_RX 0x20 1360 u8 pause_type; 1361 u8 loopback_mode; 1362 }; 1363 __le32 words[64]; 1364 }; 1365 1366 /** 1367 * struct ionic_port_status - Port Status information 1368 * @status: link status (enum ionic_port_oper_status) 1369 * @id: port id 1370 * @speed: link speed (in Mbps) 1371 * @link_down_count: number of times link went from up to down 1372 * @fec_type: fec type (enum ionic_port_fec_type) 1373 * @xcvr: transceiver status 1374 */ 1375 struct ionic_port_status { 1376 __le32 id; 1377 __le32 speed; 1378 u8 status; 1379 __le16 link_down_count; 1380 u8 fec_type; 1381 u8 rsvd[48]; 1382 struct ionic_xcvr_status xcvr; 1383 } __packed; 1384 1385 /** 1386 * struct ionic_port_identify_cmd - Port identify command 1387 * @opcode: opcode 1388 * @index: port index 1389 * @ver: Highest version of identify supported by driver 1390 */ 1391 struct ionic_port_identify_cmd { 1392 u8 opcode; 1393 u8 index; 1394 u8 ver; 1395 u8 rsvd[61]; 1396 }; 1397 1398 /** 1399 * struct ionic_port_identify_comp - Port identify command completion 1400 * @status: Status of the command (enum ionic_status_code) 1401 * @ver: Version of identify returned by device 1402 */ 1403 struct ionic_port_identify_comp { 1404 u8 status; 1405 u8 ver; 1406 u8 rsvd[14]; 1407 }; 1408 1409 /** 1410 * struct ionic_port_init_cmd - Port initialization command 1411 * @opcode: opcode 1412 * @index: port index 1413 * @info_pa: destination address for port info (struct ionic_port_info) 1414 */ 1415 struct ionic_port_init_cmd { 1416 u8 opcode; 1417 u8 index; 1418 u8 rsvd[6]; 1419 __le64 info_pa; 1420 u8 rsvd2[48]; 1421 }; 1422 1423 /** 1424 * struct ionic_port_init_comp - Port initialization command completion 1425 * @status: Status of the command (enum ionic_status_code) 1426 */ 1427 struct ionic_port_init_comp { 1428 u8 status; 1429 u8 rsvd[15]; 1430 }; 1431 1432 /** 1433 * struct ionic_port_reset_cmd - Port reset command 1434 * @opcode: opcode 1435 * @index: port index 1436 */ 1437 struct ionic_port_reset_cmd { 1438 u8 opcode; 1439 u8 index; 1440 u8 rsvd[62]; 1441 }; 1442 1443 /** 1444 * struct ionic_port_reset_comp - Port reset command completion 1445 * @status: Status of the command (enum ionic_status_code) 1446 */ 1447 struct ionic_port_reset_comp { 1448 u8 status; 1449 u8 rsvd[15]; 1450 }; 1451 1452 /** 1453 * enum ionic_stats_ctl_cmd - List of commands for stats control 1454 * @IONIC_STATS_CTL_RESET: Reset statistics 1455 */ 1456 enum ionic_stats_ctl_cmd { 1457 IONIC_STATS_CTL_RESET = 0, 1458 }; 1459 1460 /** 1461 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1462 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1463 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1464 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1465 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1466 */ 1467 enum ionic_txstamp_mode { 1468 IONIC_TXSTAMP_OFF = 0, 1469 IONIC_TXSTAMP_ON = 1, 1470 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1471 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1472 }; 1473 1474 /** 1475 * enum ionic_port_attr - List of device attributes 1476 * @IONIC_PORT_ATTR_STATE: Port state attribute 1477 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1478 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1479 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1480 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1481 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1482 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1483 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1484 */ 1485 enum ionic_port_attr { 1486 IONIC_PORT_ATTR_STATE = 0, 1487 IONIC_PORT_ATTR_SPEED = 1, 1488 IONIC_PORT_ATTR_MTU = 2, 1489 IONIC_PORT_ATTR_AUTONEG = 3, 1490 IONIC_PORT_ATTR_FEC = 4, 1491 IONIC_PORT_ATTR_PAUSE = 5, 1492 IONIC_PORT_ATTR_LOOPBACK = 6, 1493 IONIC_PORT_ATTR_STATS_CTRL = 7, 1494 }; 1495 1496 /** 1497 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1498 * @opcode: Opcode 1499 * @index: Port index 1500 * @attr: Attribute type (enum ionic_port_attr) 1501 * @state: Port state 1502 * @speed: Port speed 1503 * @mtu: Port MTU 1504 * @an_enable: Port autonegotiation setting 1505 * @fec_type: Port FEC type setting 1506 * @pause_type: Port pause type setting 1507 * @loopback_mode: Port loopback mode 1508 * @stats_ctl: Port stats setting 1509 */ 1510 struct ionic_port_setattr_cmd { 1511 u8 opcode; 1512 u8 index; 1513 u8 attr; 1514 u8 rsvd; 1515 union { 1516 u8 state; 1517 __le32 speed; 1518 __le32 mtu; 1519 u8 an_enable; 1520 u8 fec_type; 1521 u8 pause_type; 1522 u8 loopback_mode; 1523 u8 stats_ctl; 1524 u8 rsvd2[60]; 1525 }; 1526 }; 1527 1528 /** 1529 * struct ionic_port_setattr_comp - Port set attr command completion 1530 * @status: Status of the command (enum ionic_status_code) 1531 * @color: Color bit 1532 */ 1533 struct ionic_port_setattr_comp { 1534 u8 status; 1535 u8 rsvd[14]; 1536 u8 color; 1537 }; 1538 1539 /** 1540 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1541 * @opcode: Opcode 1542 * @index: port index 1543 * @attr: Attribute type (enum ionic_port_attr) 1544 */ 1545 struct ionic_port_getattr_cmd { 1546 u8 opcode; 1547 u8 index; 1548 u8 attr; 1549 u8 rsvd[61]; 1550 }; 1551 1552 /** 1553 * struct ionic_port_getattr_comp - Port get attr command completion 1554 * @status: Status of the command (enum ionic_status_code) 1555 * @state: Port state 1556 * @speed: Port speed 1557 * @mtu: Port MTU 1558 * @an_enable: Port autonegotiation setting 1559 * @fec_type: Port FEC type setting 1560 * @pause_type: Port pause type setting 1561 * @loopback_mode: Port loopback mode 1562 * @color: Color bit 1563 */ 1564 struct ionic_port_getattr_comp { 1565 u8 status; 1566 u8 rsvd[3]; 1567 union { 1568 u8 state; 1569 __le32 speed; 1570 __le32 mtu; 1571 u8 an_enable; 1572 u8 fec_type; 1573 u8 pause_type; 1574 u8 loopback_mode; 1575 u8 rsvd2[11]; 1576 } __packed; 1577 u8 color; 1578 }; 1579 1580 /** 1581 * struct ionic_lif_status - LIF status register 1582 * @eid: most recent NotifyQ event id 1583 * @port_num: port the LIF is connected to 1584 * @link_status: port status (enum ionic_port_oper_status) 1585 * @link_speed: speed of link in Mbps 1586 * @link_down_count: number of times link went from up to down 1587 */ 1588 struct ionic_lif_status { 1589 __le64 eid; 1590 u8 port_num; 1591 u8 rsvd; 1592 __le16 link_status; 1593 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1594 __le16 link_down_count; 1595 u8 rsvd2[46]; 1596 }; 1597 1598 /** 1599 * struct ionic_lif_reset_cmd - LIF reset command 1600 * @opcode: opcode 1601 * @index: LIF index 1602 */ 1603 struct ionic_lif_reset_cmd { 1604 u8 opcode; 1605 u8 rsvd; 1606 __le16 index; 1607 __le32 rsvd2[15]; 1608 }; 1609 1610 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1611 1612 enum ionic_dev_state { 1613 IONIC_DEV_DISABLE = 0, 1614 IONIC_DEV_ENABLE = 1, 1615 IONIC_DEV_HANG_RESET = 2, 1616 }; 1617 1618 /** 1619 * enum ionic_dev_attr - List of device attributes 1620 * @IONIC_DEV_ATTR_STATE: Device state attribute 1621 * @IONIC_DEV_ATTR_NAME: Device name attribute 1622 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1623 */ 1624 enum ionic_dev_attr { 1625 IONIC_DEV_ATTR_STATE = 0, 1626 IONIC_DEV_ATTR_NAME = 1, 1627 IONIC_DEV_ATTR_FEATURES = 2, 1628 }; 1629 1630 /** 1631 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1632 * @opcode: Opcode 1633 * @attr: Attribute type (enum ionic_dev_attr) 1634 * @state: Device state (enum ionic_dev_state) 1635 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1636 * @features: Device features 1637 */ 1638 struct ionic_dev_setattr_cmd { 1639 u8 opcode; 1640 u8 attr; 1641 __le16 rsvd; 1642 union { 1643 u8 state; 1644 char name[IONIC_IFNAMSIZ]; 1645 __le64 features; 1646 u8 rsvd2[60]; 1647 } __packed; 1648 }; 1649 1650 /** 1651 * struct ionic_dev_setattr_comp - Device set attr command completion 1652 * @status: Status of the command (enum ionic_status_code) 1653 * @features: Device features 1654 * @color: Color bit 1655 */ 1656 struct ionic_dev_setattr_comp { 1657 u8 status; 1658 u8 rsvd[3]; 1659 union { 1660 __le64 features; 1661 u8 rsvd2[11]; 1662 } __packed; 1663 u8 color; 1664 }; 1665 1666 /** 1667 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1668 * @opcode: opcode 1669 * @attr: Attribute type (enum ionic_dev_attr) 1670 */ 1671 struct ionic_dev_getattr_cmd { 1672 u8 opcode; 1673 u8 attr; 1674 u8 rsvd[62]; 1675 }; 1676 1677 /** 1678 * struct ionic_dev_setattr_comp - Device set attr command completion 1679 * @status: Status of the command (enum ionic_status_code) 1680 * @features: Device features 1681 * @color: Color bit 1682 */ 1683 struct ionic_dev_getattr_comp { 1684 u8 status; 1685 u8 rsvd[3]; 1686 union { 1687 __le64 features; 1688 u8 rsvd2[11]; 1689 } __packed; 1690 u8 color; 1691 }; 1692 1693 /** 1694 * RSS parameters 1695 */ 1696 #define IONIC_RSS_HASH_KEY_SIZE 40 1697 1698 enum ionic_rss_hash_types { 1699 IONIC_RSS_TYPE_IPV4 = BIT(0), 1700 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1701 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1702 IONIC_RSS_TYPE_IPV6 = BIT(3), 1703 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1704 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1705 }; 1706 1707 /** 1708 * enum ionic_lif_attr - List of LIF attributes 1709 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1710 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1711 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1712 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1713 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1714 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1715 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1716 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1717 */ 1718 enum ionic_lif_attr { 1719 IONIC_LIF_ATTR_STATE = 0, 1720 IONIC_LIF_ATTR_NAME = 1, 1721 IONIC_LIF_ATTR_MTU = 2, 1722 IONIC_LIF_ATTR_MAC = 3, 1723 IONIC_LIF_ATTR_FEATURES = 4, 1724 IONIC_LIF_ATTR_RSS = 5, 1725 IONIC_LIF_ATTR_STATS_CTRL = 6, 1726 IONIC_LIF_ATTR_TXSTAMP = 7, 1727 }; 1728 1729 /** 1730 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1731 * @opcode: Opcode 1732 * @attr: Attribute type (enum ionic_lif_attr) 1733 * @index: LIF index 1734 * @state: LIF state (enum ionic_lif_state) 1735 * @name: The netdev name string, 0 terminated 1736 * @mtu: Mtu 1737 * @mac: Station mac 1738 * @features: Features (enum ionic_eth_hw_features) 1739 * @rss: RSS properties 1740 * @types: The hash types to enable (see rss_hash_types) 1741 * @key: The hash secret key 1742 * @addr: Address for the indirection table shared memory 1743 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1744 * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1745 */ 1746 struct ionic_lif_setattr_cmd { 1747 u8 opcode; 1748 u8 attr; 1749 __le16 index; 1750 union { 1751 u8 state; 1752 char name[IONIC_IFNAMSIZ]; 1753 __le32 mtu; 1754 u8 mac[6]; 1755 __le64 features; 1756 struct { 1757 __le16 types; 1758 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1759 u8 rsvd[6]; 1760 __le64 addr; 1761 } rss; 1762 u8 stats_ctl; 1763 __le16 txstamp_mode; 1764 u8 rsvd[60]; 1765 } __packed; 1766 }; 1767 1768 /** 1769 * struct ionic_lif_setattr_comp - LIF set attr command completion 1770 * @status: Status of the command (enum ionic_status_code) 1771 * @comp_index: Index in the descriptor ring for which this is the completion 1772 * @features: features (enum ionic_eth_hw_features) 1773 * @color: Color bit 1774 */ 1775 struct ionic_lif_setattr_comp { 1776 u8 status; 1777 u8 rsvd; 1778 __le16 comp_index; 1779 union { 1780 __le64 features; 1781 u8 rsvd2[11]; 1782 } __packed; 1783 u8 color; 1784 }; 1785 1786 /** 1787 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1788 * @opcode: Opcode 1789 * @attr: Attribute type (enum ionic_lif_attr) 1790 * @index: LIF index 1791 */ 1792 struct ionic_lif_getattr_cmd { 1793 u8 opcode; 1794 u8 attr; 1795 __le16 index; 1796 u8 rsvd[60]; 1797 }; 1798 1799 /** 1800 * struct ionic_lif_getattr_comp - LIF get attr command completion 1801 * @status: Status of the command (enum ionic_status_code) 1802 * @comp_index: Index in the descriptor ring for which this is the completion 1803 * @state: LIF state (enum ionic_lif_state) 1804 * @name: The netdev name string, 0 terminated 1805 * @mtu: Mtu 1806 * @mac: Station mac 1807 * @features: Features (enum ionic_eth_hw_features) 1808 * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1809 * @color: Color bit 1810 */ 1811 struct ionic_lif_getattr_comp { 1812 u8 status; 1813 u8 rsvd; 1814 __le16 comp_index; 1815 union { 1816 u8 state; 1817 __le32 mtu; 1818 u8 mac[6]; 1819 __le64 features; 1820 __le16 txstamp_mode; 1821 u8 rsvd2[11]; 1822 } __packed; 1823 u8 color; 1824 }; 1825 1826 /** 1827 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1828 * @opcode: Opcode 1829 * @lif_index: LIF index 1830 * @tick: Hardware stamp tick of an instant in time. 1831 * @nsec: Nanosecond stamp of the same instant. 1832 * @frac: Fractional nanoseconds at the same instant. 1833 * @mult: Cycle to nanosecond multiplier. 1834 * @shift: Cycle to nanosecond divisor (power of two). 1835 */ 1836 struct ionic_lif_setphc_cmd { 1837 u8 opcode; 1838 u8 rsvd1; 1839 __le16 lif_index; 1840 u8 rsvd2[4]; 1841 __le64 tick; 1842 __le64 nsec; 1843 __le64 frac; 1844 __le32 mult; 1845 __le32 shift; 1846 u8 rsvd3[24]; 1847 }; 1848 1849 enum ionic_rx_mode { 1850 IONIC_RX_MODE_F_UNICAST = BIT(0), 1851 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1852 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1853 IONIC_RX_MODE_F_PROMISC = BIT(3), 1854 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1855 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1856 }; 1857 1858 /** 1859 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1860 * @opcode: opcode 1861 * @lif_index: LIF index 1862 * @rx_mode: Rx mode flags: 1863 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1864 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1865 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1866 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1867 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1868 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1869 */ 1870 struct ionic_rx_mode_set_cmd { 1871 u8 opcode; 1872 u8 rsvd; 1873 __le16 lif_index; 1874 __le16 rx_mode; 1875 __le16 rsvd2[29]; 1876 }; 1877 1878 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1879 1880 enum ionic_rx_filter_match_type { 1881 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 1882 IONIC_RX_FILTER_MATCH_MAC = 0x1, 1883 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 1884 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 1885 }; 1886 1887 /** 1888 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1889 * @opcode: opcode 1890 * @qtype: Queue type 1891 * @lif_index: LIF index 1892 * @qid: Queue ID 1893 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1894 * @vlan: VLAN filter 1895 * @vlan: VLAN ID 1896 * @mac: MAC filter 1897 * @addr: MAC address (network-byte order) 1898 * @mac_vlan: MACVLAN filter 1899 * @vlan: VLAN ID 1900 * @addr: MAC address (network-byte order) 1901 * @pkt_class: Packet classification filter 1902 */ 1903 struct ionic_rx_filter_add_cmd { 1904 u8 opcode; 1905 u8 qtype; 1906 __le16 lif_index; 1907 __le32 qid; 1908 __le16 match; 1909 union { 1910 struct { 1911 __le16 vlan; 1912 } vlan; 1913 struct { 1914 u8 addr[6]; 1915 } mac; 1916 struct { 1917 __le16 vlan; 1918 u8 addr[6]; 1919 } mac_vlan; 1920 __le64 pkt_class; 1921 u8 rsvd[54]; 1922 } __packed; 1923 }; 1924 1925 /** 1926 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1927 * @status: Status of the command (enum ionic_status_code) 1928 * @comp_index: Index in the descriptor ring for which this is the completion 1929 * @filter_id: Filter ID 1930 * @color: Color bit 1931 */ 1932 struct ionic_rx_filter_add_comp { 1933 u8 status; 1934 u8 rsvd; 1935 __le16 comp_index; 1936 __le32 filter_id; 1937 u8 rsvd2[7]; 1938 u8 color; 1939 }; 1940 1941 /** 1942 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1943 * @opcode: opcode 1944 * @lif_index: LIF index 1945 * @filter_id: Filter ID 1946 */ 1947 struct ionic_rx_filter_del_cmd { 1948 u8 opcode; 1949 u8 rsvd; 1950 __le16 lif_index; 1951 __le32 filter_id; 1952 u8 rsvd2[56]; 1953 }; 1954 1955 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1956 1957 enum ionic_vf_attr { 1958 IONIC_VF_ATTR_SPOOFCHK = 1, 1959 IONIC_VF_ATTR_TRUST = 2, 1960 IONIC_VF_ATTR_MAC = 3, 1961 IONIC_VF_ATTR_LINKSTATE = 4, 1962 IONIC_VF_ATTR_VLAN = 5, 1963 IONIC_VF_ATTR_RATE = 6, 1964 IONIC_VF_ATTR_STATSADDR = 7, 1965 }; 1966 1967 /** 1968 * enum ionic_vf_link_status - Virtual Function link status 1969 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1970 * @IONIC_VF_LINK_STATUS_UP: Link always up 1971 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 1972 */ 1973 enum ionic_vf_link_status { 1974 IONIC_VF_LINK_STATUS_AUTO = 0, 1975 IONIC_VF_LINK_STATUS_UP = 1, 1976 IONIC_VF_LINK_STATUS_DOWN = 2, 1977 }; 1978 1979 /** 1980 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1981 * @opcode: Opcode 1982 * @attr: Attribute type (enum ionic_vf_attr) 1983 * @vf_index: VF index 1984 * @macaddr: mac address 1985 * @vlanid: vlan ID 1986 * @maxrate: max Tx rate in Mbps 1987 * @spoofchk: enable address spoof checking 1988 * @trust: enable VF trust 1989 * @linkstate: set link up or down 1990 * @stats_pa: set DMA address for VF stats 1991 */ 1992 struct ionic_vf_setattr_cmd { 1993 u8 opcode; 1994 u8 attr; 1995 __le16 vf_index; 1996 union { 1997 u8 macaddr[6]; 1998 __le16 vlanid; 1999 __le32 maxrate; 2000 u8 spoofchk; 2001 u8 trust; 2002 u8 linkstate; 2003 __le64 stats_pa; 2004 u8 pad[60]; 2005 } __packed; 2006 }; 2007 2008 struct ionic_vf_setattr_comp { 2009 u8 status; 2010 u8 attr; 2011 __le16 vf_index; 2012 __le16 comp_index; 2013 u8 rsvd[9]; 2014 u8 color; 2015 }; 2016 2017 /** 2018 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2019 * @opcode: Opcode 2020 * @attr: Attribute type (enum ionic_vf_attr) 2021 * @vf_index: VF index 2022 */ 2023 struct ionic_vf_getattr_cmd { 2024 u8 opcode; 2025 u8 attr; 2026 __le16 vf_index; 2027 u8 rsvd[60]; 2028 }; 2029 2030 struct ionic_vf_getattr_comp { 2031 u8 status; 2032 u8 attr; 2033 __le16 vf_index; 2034 union { 2035 u8 macaddr[6]; 2036 __le16 vlanid; 2037 __le32 maxrate; 2038 u8 spoofchk; 2039 u8 trust; 2040 u8 linkstate; 2041 __le64 stats_pa; 2042 u8 pad[11]; 2043 } __packed; 2044 u8 color; 2045 }; 2046 2047 /** 2048 * struct ionic_qos_identify_cmd - QoS identify command 2049 * @opcode: opcode 2050 * @ver: Highest version of identify supported by driver 2051 * 2052 */ 2053 struct ionic_qos_identify_cmd { 2054 u8 opcode; 2055 u8 ver; 2056 u8 rsvd[62]; 2057 }; 2058 2059 /** 2060 * struct ionic_qos_identify_comp - QoS identify command completion 2061 * @status: Status of the command (enum ionic_status_code) 2062 * @ver: Version of identify returned by device 2063 */ 2064 struct ionic_qos_identify_comp { 2065 u8 status; 2066 u8 ver; 2067 u8 rsvd[14]; 2068 }; 2069 2070 #define IONIC_QOS_TC_MAX 8 2071 #define IONIC_QOS_ALL_TC 0xFF 2072 /* Capri max supported, should be renamed. */ 2073 #define IONIC_QOS_CLASS_MAX 7 2074 #define IONIC_QOS_PCP_MAX 8 2075 #define IONIC_QOS_CLASS_NAME_SZ 32 2076 #define IONIC_QOS_DSCP_MAX 64 2077 #define IONIC_QOS_ALL_PCP 0xFF 2078 #define IONIC_DSCP_BLOCK_SIZE 8 2079 2080 /** 2081 * enum ionic_qos_class 2082 */ 2083 enum ionic_qos_class { 2084 IONIC_QOS_CLASS_DEFAULT = 0, 2085 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2086 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2087 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2088 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2089 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2090 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2091 }; 2092 2093 /** 2094 * enum ionic_qos_class_type - Traffic classification criteria 2095 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2096 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2097 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2098 */ 2099 enum ionic_qos_class_type { 2100 IONIC_QOS_CLASS_TYPE_NONE = 0, 2101 IONIC_QOS_CLASS_TYPE_PCP = 1, 2102 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2103 }; 2104 2105 /** 2106 * enum ionic_qos_sched_type - QoS class scheduling type 2107 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2108 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2109 */ 2110 enum ionic_qos_sched_type { 2111 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2112 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2113 }; 2114 2115 /** 2116 * union ionic_qos_config - QoS configuration structure 2117 * @flags: Configuration flags 2118 * IONIC_QOS_CONFIG_F_ENABLE enable 2119 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2120 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2121 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2122 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2123 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2124 * @class_type: QoS class type (enum ionic_qos_class_type) 2125 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2126 * @name: QoS class name 2127 * @mtu: MTU of the class 2128 * @pfc_cos: Priority-Flow Control class of service 2129 * @dwrr_weight: QoS class scheduling weight 2130 * @strict_rlmt: Rate limit for strict priority scheduling 2131 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2132 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2133 * @dot1q_pcp: Dot1q pcp value 2134 * @ndscp: Number of valid dscp values in the ip_dscp field 2135 * @ip_dscp: IP dscp values 2136 */ 2137 union ionic_qos_config { 2138 struct { 2139 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2140 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2141 /* Used to rewrite PCP or DSCP value. */ 2142 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2143 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2144 /* Non-disruptive TC update */ 2145 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2146 u8 flags; 2147 u8 sched_type; 2148 u8 class_type; 2149 u8 pause_type; 2150 char name[IONIC_QOS_CLASS_NAME_SZ]; 2151 __le32 mtu; 2152 /* flow control */ 2153 u8 pfc_cos; 2154 /* scheduler */ 2155 union { 2156 u8 dwrr_weight; 2157 __le64 strict_rlmt; 2158 }; 2159 /* marking */ 2160 /* Used to rewrite PCP or DSCP value. */ 2161 union { 2162 u8 rw_dot1q_pcp; 2163 u8 rw_ip_dscp; 2164 }; 2165 /* classification */ 2166 union { 2167 u8 dot1q_pcp; 2168 struct { 2169 u8 ndscp; 2170 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2171 }; 2172 }; 2173 }; 2174 __le32 words[64]; 2175 }; 2176 2177 /** 2178 * union ionic_qos_identity - QoS identity structure 2179 * @version: Version of the identify structure 2180 * @type: QoS system type 2181 * @nclasses: Number of usable QoS classes 2182 * @config: Current configuration of classes 2183 */ 2184 union ionic_qos_identity { 2185 struct { 2186 u8 version; 2187 u8 type; 2188 u8 rsvd[62]; 2189 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2190 }; 2191 __le32 words[478]; 2192 }; 2193 2194 /** 2195 * struct ionic_qos_init_cmd - QoS config init command 2196 * @opcode: Opcode 2197 * @group: QoS class id 2198 * @info_pa: destination address for qos info 2199 */ 2200 struct ionic_qos_init_cmd { 2201 u8 opcode; 2202 u8 group; 2203 u8 rsvd[6]; 2204 __le64 info_pa; 2205 u8 rsvd1[48]; 2206 }; 2207 2208 typedef struct ionic_admin_comp ionic_qos_init_comp; 2209 2210 /** 2211 * struct ionic_qos_reset_cmd - QoS config reset command 2212 * @opcode: Opcode 2213 * @group: QoS class id 2214 */ 2215 struct ionic_qos_reset_cmd { 2216 u8 opcode; 2217 u8 group; 2218 u8 rsvd[62]; 2219 }; 2220 2221 /** 2222 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 2223 * @opcode: Opcode 2224 */ 2225 struct ionic_qos_clear_stats_cmd { 2226 u8 opcode; 2227 u8 group_bitmap; 2228 u8 rsvd[62]; 2229 }; 2230 2231 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2232 2233 /** 2234 * struct ionic_fw_download_cmd - Firmware download command 2235 * @opcode: opcode 2236 * @addr: dma address of the firmware buffer 2237 * @offset: offset of the firmware buffer within the full image 2238 * @length: number of valid bytes in the firmware buffer 2239 */ 2240 struct ionic_fw_download_cmd { 2241 u8 opcode; 2242 u8 rsvd[3]; 2243 __le32 offset; 2244 __le64 addr; 2245 __le32 length; 2246 }; 2247 2248 typedef struct ionic_admin_comp ionic_fw_download_comp; 2249 2250 /** 2251 * enum ionic_fw_control_oper - FW control operations 2252 * @IONIC_FW_RESET: Reset firmware 2253 * @IONIC_FW_INSTALL: Install firmware 2254 * @IONIC_FW_ACTIVATE: Activate firmware 2255 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2256 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2257 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2258 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2259 */ 2260 enum ionic_fw_control_oper { 2261 IONIC_FW_RESET = 0, 2262 IONIC_FW_INSTALL = 1, 2263 IONIC_FW_ACTIVATE = 2, 2264 IONIC_FW_INSTALL_ASYNC = 3, 2265 IONIC_FW_INSTALL_STATUS = 4, 2266 IONIC_FW_ACTIVATE_ASYNC = 5, 2267 IONIC_FW_ACTIVATE_STATUS = 6, 2268 IONIC_FW_UPDATE_CLEANUP = 7, 2269 }; 2270 2271 /** 2272 * struct ionic_fw_control_cmd - Firmware control command 2273 * @opcode: opcode 2274 * @oper: firmware control operation (enum ionic_fw_control_oper) 2275 * @slot: slot to activate 2276 */ 2277 struct ionic_fw_control_cmd { 2278 u8 opcode; 2279 u8 rsvd[3]; 2280 u8 oper; 2281 u8 slot; 2282 u8 rsvd1[58]; 2283 }; 2284 2285 /** 2286 * struct ionic_fw_control_comp - Firmware control copletion 2287 * @status: Status of the command (enum ionic_status_code) 2288 * @comp_index: Index in the descriptor ring for which this is the completion 2289 * @slot: Slot where the firmware was installed 2290 * @color: Color bit 2291 */ 2292 struct ionic_fw_control_comp { 2293 u8 status; 2294 u8 rsvd; 2295 __le16 comp_index; 2296 u8 slot; 2297 u8 rsvd1[10]; 2298 u8 color; 2299 }; 2300 2301 /****************************************************************** 2302 ******************* RDMA Commands ******************************** 2303 ******************************************************************/ 2304 2305 /** 2306 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2307 * @opcode: opcode 2308 * @lif_index: LIF index 2309 * 2310 * There is no RDMA specific dev command completion struct. Completion uses 2311 * the common struct ionic_admin_comp. Only the status is indicated. 2312 * Nonzero status means the LIF does not support RDMA. 2313 **/ 2314 struct ionic_rdma_reset_cmd { 2315 u8 opcode; 2316 u8 rsvd; 2317 __le16 lif_index; 2318 u8 rsvd2[60]; 2319 }; 2320 2321 /** 2322 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2323 * @opcode: opcode, 52, 53 2324 * @lif_index: LIF index 2325 * @qid_ver: (qid | (RDMA version << 24)) 2326 * @cid: intr, eq_id, or cq_id 2327 * @dbid: doorbell page id 2328 * @depth_log2: log base two of queue depth 2329 * @stride_log2: log base two of queue stride 2330 * @dma_addr: address of the queue memory 2331 * 2332 * The same command struct is used to create an RDMA event queue, completion 2333 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2334 * queue, an event queue id for a completion queue, or a completion queue id 2335 * for an RDMA admin queue. 2336 * 2337 * The queue created via a dev command must be contiguous in dma space. 2338 * 2339 * The dev commands are intended only to be used during driver initialization, 2340 * to create queues supporting the RDMA admin queue. Other queues, and other 2341 * types of RDMA resources like memory regions, will be created and registered 2342 * via the RDMA admin queue, and will support a more complete interface 2343 * providing scatter gather lists for larger, scattered queue buffers and 2344 * memory registration. 2345 * 2346 * There is no RDMA specific dev command completion struct. Completion uses 2347 * the common struct ionic_admin_comp. Only the status is indicated. 2348 **/ 2349 struct ionic_rdma_queue_cmd { 2350 u8 opcode; 2351 u8 rsvd; 2352 __le16 lif_index; 2353 __le32 qid_ver; 2354 __le32 cid; 2355 __le16 dbid; 2356 u8 depth_log2; 2357 u8 stride_log2; 2358 __le64 dma_addr; 2359 u8 rsvd2[40]; 2360 }; 2361 2362 /****************************************************************** 2363 ******************* Notify Events ******************************** 2364 ******************************************************************/ 2365 2366 /** 2367 * struct ionic_notifyq_event - Generic event reporting structure 2368 * @eid: event number 2369 * @ecode: event code 2370 * @data: unspecified data about the event 2371 * 2372 * This is the generic event report struct from which the other 2373 * actual events will be formed. 2374 */ 2375 struct ionic_notifyq_event { 2376 __le64 eid; 2377 __le16 ecode; 2378 u8 data[54]; 2379 }; 2380 2381 /** 2382 * struct ionic_link_change_event - Link change event notification 2383 * @eid: event number 2384 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2385 * @link_status: link up/down, with error bits (enum ionic_port_status) 2386 * @link_speed: speed of the network link 2387 * 2388 * Sent when the network link state changes between UP and DOWN 2389 */ 2390 struct ionic_link_change_event { 2391 __le64 eid; 2392 __le16 ecode; 2393 __le16 link_status; 2394 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2395 u8 rsvd[48]; 2396 }; 2397 2398 /** 2399 * struct ionic_reset_event - Reset event notification 2400 * @eid: event number 2401 * @ecode: event code = IONIC_EVENT_RESET 2402 * @reset_code: reset type 2403 * @state: 0=pending, 1=complete, 2=error 2404 * 2405 * Sent when the NIC or some subsystem is going to be or 2406 * has been reset. 2407 */ 2408 struct ionic_reset_event { 2409 __le64 eid; 2410 __le16 ecode; 2411 u8 reset_code; 2412 u8 state; 2413 u8 rsvd[52]; 2414 }; 2415 2416 /** 2417 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2418 * @eid: event number 2419 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2420 */ 2421 struct ionic_heartbeat_event { 2422 __le64 eid; 2423 __le16 ecode; 2424 u8 rsvd[54]; 2425 }; 2426 2427 /** 2428 * struct ionic_log_event - Sent to notify the driver of an internal error 2429 * @eid: event number 2430 * @ecode: event code = IONIC_EVENT_LOG 2431 * @data: log data 2432 */ 2433 struct ionic_log_event { 2434 __le64 eid; 2435 __le16 ecode; 2436 u8 data[54]; 2437 }; 2438 2439 /** 2440 * struct ionic_xcvr_event - Transceiver change event 2441 * @eid: event number 2442 * @ecode: event code = IONIC_EVENT_XCVR 2443 */ 2444 struct ionic_xcvr_event { 2445 __le64 eid; 2446 __le16 ecode; 2447 u8 rsvd[54]; 2448 }; 2449 2450 /** 2451 * struct ionic_port_stats - Port statistics structure 2452 */ 2453 struct ionic_port_stats { 2454 __le64 frames_rx_ok; 2455 __le64 frames_rx_all; 2456 __le64 frames_rx_bad_fcs; 2457 __le64 frames_rx_bad_all; 2458 __le64 octets_rx_ok; 2459 __le64 octets_rx_all; 2460 __le64 frames_rx_unicast; 2461 __le64 frames_rx_multicast; 2462 __le64 frames_rx_broadcast; 2463 __le64 frames_rx_pause; 2464 __le64 frames_rx_bad_length; 2465 __le64 frames_rx_undersized; 2466 __le64 frames_rx_oversized; 2467 __le64 frames_rx_fragments; 2468 __le64 frames_rx_jabber; 2469 __le64 frames_rx_pripause; 2470 __le64 frames_rx_stomped_crc; 2471 __le64 frames_rx_too_long; 2472 __le64 frames_rx_vlan_good; 2473 __le64 frames_rx_dropped; 2474 __le64 frames_rx_less_than_64b; 2475 __le64 frames_rx_64b; 2476 __le64 frames_rx_65b_127b; 2477 __le64 frames_rx_128b_255b; 2478 __le64 frames_rx_256b_511b; 2479 __le64 frames_rx_512b_1023b; 2480 __le64 frames_rx_1024b_1518b; 2481 __le64 frames_rx_1519b_2047b; 2482 __le64 frames_rx_2048b_4095b; 2483 __le64 frames_rx_4096b_8191b; 2484 __le64 frames_rx_8192b_9215b; 2485 __le64 frames_rx_other; 2486 __le64 frames_tx_ok; 2487 __le64 frames_tx_all; 2488 __le64 frames_tx_bad; 2489 __le64 octets_tx_ok; 2490 __le64 octets_tx_total; 2491 __le64 frames_tx_unicast; 2492 __le64 frames_tx_multicast; 2493 __le64 frames_tx_broadcast; 2494 __le64 frames_tx_pause; 2495 __le64 frames_tx_pripause; 2496 __le64 frames_tx_vlan; 2497 __le64 frames_tx_less_than_64b; 2498 __le64 frames_tx_64b; 2499 __le64 frames_tx_65b_127b; 2500 __le64 frames_tx_128b_255b; 2501 __le64 frames_tx_256b_511b; 2502 __le64 frames_tx_512b_1023b; 2503 __le64 frames_tx_1024b_1518b; 2504 __le64 frames_tx_1519b_2047b; 2505 __le64 frames_tx_2048b_4095b; 2506 __le64 frames_tx_4096b_8191b; 2507 __le64 frames_tx_8192b_9215b; 2508 __le64 frames_tx_other; 2509 __le64 frames_tx_pri_0; 2510 __le64 frames_tx_pri_1; 2511 __le64 frames_tx_pri_2; 2512 __le64 frames_tx_pri_3; 2513 __le64 frames_tx_pri_4; 2514 __le64 frames_tx_pri_5; 2515 __le64 frames_tx_pri_6; 2516 __le64 frames_tx_pri_7; 2517 __le64 frames_rx_pri_0; 2518 __le64 frames_rx_pri_1; 2519 __le64 frames_rx_pri_2; 2520 __le64 frames_rx_pri_3; 2521 __le64 frames_rx_pri_4; 2522 __le64 frames_rx_pri_5; 2523 __le64 frames_rx_pri_6; 2524 __le64 frames_rx_pri_7; 2525 __le64 tx_pripause_0_1us_count; 2526 __le64 tx_pripause_1_1us_count; 2527 __le64 tx_pripause_2_1us_count; 2528 __le64 tx_pripause_3_1us_count; 2529 __le64 tx_pripause_4_1us_count; 2530 __le64 tx_pripause_5_1us_count; 2531 __le64 tx_pripause_6_1us_count; 2532 __le64 tx_pripause_7_1us_count; 2533 __le64 rx_pripause_0_1us_count; 2534 __le64 rx_pripause_1_1us_count; 2535 __le64 rx_pripause_2_1us_count; 2536 __le64 rx_pripause_3_1us_count; 2537 __le64 rx_pripause_4_1us_count; 2538 __le64 rx_pripause_5_1us_count; 2539 __le64 rx_pripause_6_1us_count; 2540 __le64 rx_pripause_7_1us_count; 2541 __le64 rx_pause_1us_count; 2542 __le64 frames_tx_truncated; 2543 }; 2544 2545 struct ionic_mgmt_port_stats { 2546 __le64 frames_rx_ok; 2547 __le64 frames_rx_all; 2548 __le64 frames_rx_bad_fcs; 2549 __le64 frames_rx_bad_all; 2550 __le64 octets_rx_ok; 2551 __le64 octets_rx_all; 2552 __le64 frames_rx_unicast; 2553 __le64 frames_rx_multicast; 2554 __le64 frames_rx_broadcast; 2555 __le64 frames_rx_pause; 2556 __le64 frames_rx_bad_length; 2557 __le64 frames_rx_undersized; 2558 __le64 frames_rx_oversized; 2559 __le64 frames_rx_fragments; 2560 __le64 frames_rx_jabber; 2561 __le64 frames_rx_64b; 2562 __le64 frames_rx_65b_127b; 2563 __le64 frames_rx_128b_255b; 2564 __le64 frames_rx_256b_511b; 2565 __le64 frames_rx_512b_1023b; 2566 __le64 frames_rx_1024b_1518b; 2567 __le64 frames_rx_gt_1518b; 2568 __le64 frames_rx_fifo_full; 2569 __le64 frames_tx_ok; 2570 __le64 frames_tx_all; 2571 __le64 frames_tx_bad; 2572 __le64 octets_tx_ok; 2573 __le64 octets_tx_total; 2574 __le64 frames_tx_unicast; 2575 __le64 frames_tx_multicast; 2576 __le64 frames_tx_broadcast; 2577 __le64 frames_tx_pause; 2578 }; 2579 2580 enum ionic_pb_buffer_drop_stats { 2581 IONIC_BUFFER_INTRINSIC_DROP = 0, 2582 IONIC_BUFFER_DISCARDED, 2583 IONIC_BUFFER_ADMITTED, 2584 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2585 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2586 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2587 IONIC_BUFFER_TRUNCATION_DROP, 2588 IONIC_BUFFER_PORT_DISABLED_DROP, 2589 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2590 IONIC_BUFFER_SPAN_TAIL_DROP, 2591 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2592 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2593 IONIC_BUFFER_INVALID_PORT_DROP, 2594 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2595 IONIC_BUFFER_DROP_MAX, 2596 }; 2597 2598 enum ionic_oflow_drop_stats { 2599 IONIC_OFLOW_OCCUPANCY_DROP, 2600 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2601 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2602 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2603 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2604 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2605 IONIC_OFLOW_DROP_MAX, 2606 }; 2607 2608 /** 2609 * struct port_pb_stats - packet buffers system stats 2610 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2611 */ 2612 struct ionic_port_pb_stats { 2613 __le64 sop_count_in; 2614 __le64 eop_count_in; 2615 __le64 sop_count_out; 2616 __le64 eop_count_out; 2617 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2618 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2619 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2620 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2621 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2622 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2623 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2624 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2625 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2626 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2627 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2628 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2629 }; 2630 2631 /** 2632 * struct ionic_port_identity - port identity structure 2633 * @version: identity structure version 2634 * @type: type of port (enum ionic_port_type) 2635 * @num_lanes: number of lanes for the port 2636 * @autoneg: autoneg supported 2637 * @min_frame_size: minimum frame size supported 2638 * @max_frame_size: maximum frame size supported 2639 * @fec_type: supported fec types 2640 * @pause_type: supported pause types 2641 * @loopback_mode: supported loopback mode 2642 * @speeds: supported speeds 2643 * @config: current port configuration 2644 */ 2645 union ionic_port_identity { 2646 struct { 2647 u8 version; 2648 u8 type; 2649 u8 num_lanes; 2650 u8 autoneg; 2651 __le32 min_frame_size; 2652 __le32 max_frame_size; 2653 u8 fec_type[4]; 2654 u8 pause_type[2]; 2655 u8 loopback_mode[2]; 2656 __le32 speeds[16]; 2657 u8 rsvd2[44]; 2658 union ionic_port_config config; 2659 }; 2660 __le32 words[478]; 2661 }; 2662 2663 /** 2664 * struct ionic_port_info - port info structure 2665 * @config: Port configuration data 2666 * @status: Port status data 2667 * @stats: Port statistics data 2668 * @mgmt_stats: Port management statistics data 2669 * @port_pb_drop_stats: uplink pb drop stats 2670 */ 2671 struct ionic_port_info { 2672 union ionic_port_config config; 2673 struct ionic_port_status status; 2674 union { 2675 struct ionic_port_stats stats; 2676 struct ionic_mgmt_port_stats mgmt_stats; 2677 }; 2678 /* room for pb_stats to start at 2k offset */ 2679 u8 rsvd[760]; 2680 struct ionic_port_pb_stats pb_stats; 2681 }; 2682 2683 /** 2684 * struct ionic_lif_stats - LIF statistics structure 2685 */ 2686 struct ionic_lif_stats { 2687 /* RX */ 2688 __le64 rx_ucast_bytes; 2689 __le64 rx_ucast_packets; 2690 __le64 rx_mcast_bytes; 2691 __le64 rx_mcast_packets; 2692 __le64 rx_bcast_bytes; 2693 __le64 rx_bcast_packets; 2694 __le64 rsvd0; 2695 __le64 rsvd1; 2696 /* RX drops */ 2697 __le64 rx_ucast_drop_bytes; 2698 __le64 rx_ucast_drop_packets; 2699 __le64 rx_mcast_drop_bytes; 2700 __le64 rx_mcast_drop_packets; 2701 __le64 rx_bcast_drop_bytes; 2702 __le64 rx_bcast_drop_packets; 2703 __le64 rx_dma_error; 2704 __le64 rsvd2; 2705 /* TX */ 2706 __le64 tx_ucast_bytes; 2707 __le64 tx_ucast_packets; 2708 __le64 tx_mcast_bytes; 2709 __le64 tx_mcast_packets; 2710 __le64 tx_bcast_bytes; 2711 __le64 tx_bcast_packets; 2712 __le64 rsvd3; 2713 __le64 rsvd4; 2714 /* TX drops */ 2715 __le64 tx_ucast_drop_bytes; 2716 __le64 tx_ucast_drop_packets; 2717 __le64 tx_mcast_drop_bytes; 2718 __le64 tx_mcast_drop_packets; 2719 __le64 tx_bcast_drop_bytes; 2720 __le64 tx_bcast_drop_packets; 2721 __le64 tx_dma_error; 2722 __le64 rsvd5; 2723 /* Rx Queue/Ring drops */ 2724 __le64 rx_queue_disabled; 2725 __le64 rx_queue_empty; 2726 __le64 rx_queue_error; 2727 __le64 rx_desc_fetch_error; 2728 __le64 rx_desc_data_error; 2729 __le64 rsvd6; 2730 __le64 rsvd7; 2731 __le64 rsvd8; 2732 /* Tx Queue/Ring drops */ 2733 __le64 tx_queue_disabled; 2734 __le64 tx_queue_error; 2735 __le64 tx_desc_fetch_error; 2736 __le64 tx_desc_data_error; 2737 __le64 tx_queue_empty; 2738 __le64 rsvd10; 2739 __le64 rsvd11; 2740 __le64 rsvd12; 2741 2742 /* RDMA/ROCE TX */ 2743 __le64 tx_rdma_ucast_bytes; 2744 __le64 tx_rdma_ucast_packets; 2745 __le64 tx_rdma_mcast_bytes; 2746 __le64 tx_rdma_mcast_packets; 2747 __le64 tx_rdma_cnp_packets; 2748 __le64 rsvd13; 2749 __le64 rsvd14; 2750 __le64 rsvd15; 2751 2752 /* RDMA/ROCE RX */ 2753 __le64 rx_rdma_ucast_bytes; 2754 __le64 rx_rdma_ucast_packets; 2755 __le64 rx_rdma_mcast_bytes; 2756 __le64 rx_rdma_mcast_packets; 2757 __le64 rx_rdma_cnp_packets; 2758 __le64 rx_rdma_ecn_packets; 2759 __le64 rsvd16; 2760 __le64 rsvd17; 2761 2762 __le64 rsvd18; 2763 __le64 rsvd19; 2764 __le64 rsvd20; 2765 __le64 rsvd21; 2766 __le64 rsvd22; 2767 __le64 rsvd23; 2768 __le64 rsvd24; 2769 __le64 rsvd25; 2770 2771 __le64 rsvd26; 2772 __le64 rsvd27; 2773 __le64 rsvd28; 2774 __le64 rsvd29; 2775 __le64 rsvd30; 2776 __le64 rsvd31; 2777 __le64 rsvd32; 2778 __le64 rsvd33; 2779 2780 __le64 rsvd34; 2781 __le64 rsvd35; 2782 __le64 rsvd36; 2783 __le64 rsvd37; 2784 __le64 rsvd38; 2785 __le64 rsvd39; 2786 __le64 rsvd40; 2787 __le64 rsvd41; 2788 2789 __le64 rsvd42; 2790 __le64 rsvd43; 2791 __le64 rsvd44; 2792 __le64 rsvd45; 2793 __le64 rsvd46; 2794 __le64 rsvd47; 2795 __le64 rsvd48; 2796 __le64 rsvd49; 2797 2798 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2799 __le64 rdma_req_rx_pkt_seq_err; 2800 __le64 rdma_req_rx_rnr_retry_err; 2801 __le64 rdma_req_rx_remote_access_err; 2802 __le64 rdma_req_rx_remote_inv_req_err; 2803 __le64 rdma_req_rx_remote_oper_err; 2804 __le64 rdma_req_rx_implied_nak_seq_err; 2805 __le64 rdma_req_rx_cqe_err; 2806 __le64 rdma_req_rx_cqe_flush_err; 2807 2808 __le64 rdma_req_rx_dup_responses; 2809 __le64 rdma_req_rx_invalid_packets; 2810 __le64 rdma_req_tx_local_access_err; 2811 __le64 rdma_req_tx_local_oper_err; 2812 __le64 rdma_req_tx_memory_mgmt_err; 2813 __le64 rsvd52; 2814 __le64 rsvd53; 2815 __le64 rsvd54; 2816 2817 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2818 __le64 rdma_resp_rx_dup_requests; 2819 __le64 rdma_resp_rx_out_of_buffer; 2820 __le64 rdma_resp_rx_out_of_seq_pkts; 2821 __le64 rdma_resp_rx_cqe_err; 2822 __le64 rdma_resp_rx_cqe_flush_err; 2823 __le64 rdma_resp_rx_local_len_err; 2824 __le64 rdma_resp_rx_inv_request_err; 2825 __le64 rdma_resp_rx_local_qp_oper_err; 2826 2827 __le64 rdma_resp_rx_out_of_atomic_resource; 2828 __le64 rdma_resp_tx_pkt_seq_err; 2829 __le64 rdma_resp_tx_remote_inv_req_err; 2830 __le64 rdma_resp_tx_remote_access_err; 2831 __le64 rdma_resp_tx_remote_oper_err; 2832 __le64 rdma_resp_tx_rnr_retry_err; 2833 __le64 rsvd57; 2834 __le64 rsvd58; 2835 }; 2836 2837 /** 2838 * struct ionic_lif_info - LIF info structure 2839 * @config: LIF configuration structure 2840 * @status: LIF status structure 2841 * @stats: LIF statistics structure 2842 */ 2843 struct ionic_lif_info { 2844 union ionic_lif_config config; 2845 struct ionic_lif_status status; 2846 struct ionic_lif_stats stats; 2847 }; 2848 2849 union ionic_dev_cmd { 2850 u32 words[16]; 2851 struct ionic_admin_cmd cmd; 2852 struct ionic_nop_cmd nop; 2853 2854 struct ionic_dev_identify_cmd identify; 2855 struct ionic_dev_init_cmd init; 2856 struct ionic_dev_reset_cmd reset; 2857 struct ionic_dev_getattr_cmd getattr; 2858 struct ionic_dev_setattr_cmd setattr; 2859 2860 struct ionic_port_identify_cmd port_identify; 2861 struct ionic_port_init_cmd port_init; 2862 struct ionic_port_reset_cmd port_reset; 2863 struct ionic_port_getattr_cmd port_getattr; 2864 struct ionic_port_setattr_cmd port_setattr; 2865 2866 struct ionic_vf_setattr_cmd vf_setattr; 2867 struct ionic_vf_getattr_cmd vf_getattr; 2868 2869 struct ionic_lif_identify_cmd lif_identify; 2870 struct ionic_lif_init_cmd lif_init; 2871 struct ionic_lif_reset_cmd lif_reset; 2872 2873 struct ionic_qos_identify_cmd qos_identify; 2874 struct ionic_qos_init_cmd qos_init; 2875 struct ionic_qos_reset_cmd qos_reset; 2876 struct ionic_qos_clear_stats_cmd qos_clear_stats; 2877 2878 struct ionic_q_identify_cmd q_identify; 2879 struct ionic_q_init_cmd q_init; 2880 struct ionic_q_control_cmd q_control; 2881 2882 struct ionic_fw_download_cmd fw_download; 2883 struct ionic_fw_control_cmd fw_control; 2884 }; 2885 2886 union ionic_dev_cmd_comp { 2887 u32 words[4]; 2888 u8 status; 2889 struct ionic_admin_comp comp; 2890 struct ionic_nop_comp nop; 2891 2892 struct ionic_dev_identify_comp identify; 2893 struct ionic_dev_init_comp init; 2894 struct ionic_dev_reset_comp reset; 2895 struct ionic_dev_getattr_comp getattr; 2896 struct ionic_dev_setattr_comp setattr; 2897 2898 struct ionic_port_identify_comp port_identify; 2899 struct ionic_port_init_comp port_init; 2900 struct ionic_port_reset_comp port_reset; 2901 struct ionic_port_getattr_comp port_getattr; 2902 struct ionic_port_setattr_comp port_setattr; 2903 2904 struct ionic_vf_setattr_comp vf_setattr; 2905 struct ionic_vf_getattr_comp vf_getattr; 2906 2907 struct ionic_lif_identify_comp lif_identify; 2908 struct ionic_lif_init_comp lif_init; 2909 ionic_lif_reset_comp lif_reset; 2910 2911 struct ionic_qos_identify_comp qos_identify; 2912 ionic_qos_init_comp qos_init; 2913 ionic_qos_reset_comp qos_reset; 2914 2915 struct ionic_q_identify_comp q_identify; 2916 struct ionic_q_init_comp q_init; 2917 2918 ionic_fw_download_comp fw_download; 2919 struct ionic_fw_control_comp fw_control; 2920 }; 2921 2922 /** 2923 * struct ionic_hwstamp_regs - Hardware current timestamp registers 2924 * @tick_low: Low 32 bits of hardware timestamp 2925 * @tick_high: High 32 bits of hardware timestamp 2926 */ 2927 struct ionic_hwstamp_regs { 2928 u32 tick_low; 2929 u32 tick_high; 2930 }; 2931 2932 /** 2933 * union ionic_dev_info_regs - Device info register format (read-only) 2934 * @signature: Signature value of 0x44455649 ('DEVI') 2935 * @version: Current version of info 2936 * @asic_type: Asic type 2937 * @asic_rev: Asic revision 2938 * @fw_status: Firmware status 2939 * bit 0 - 1 = fw running 2940 * bit 4-7 - 4 bit generation number, changes on fw restart 2941 * @fw_heartbeat: Firmware heartbeat counter 2942 * @serial_num: Serial number 2943 * @fw_version: Firmware version 2944 * @hwstamp_regs: Hardware current timestamp registers 2945 */ 2946 union ionic_dev_info_regs { 2947 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2948 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2949 struct { 2950 u32 signature; 2951 u8 version; 2952 u8 asic_type; 2953 u8 asic_rev; 2954 #define IONIC_FW_STS_F_RUNNING 0x01 2955 #define IONIC_FW_STS_F_GENERATION 0xF0 2956 u8 fw_status; 2957 u32 fw_heartbeat; 2958 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2959 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2960 u8 rsvd_pad1024[948]; 2961 struct ionic_hwstamp_regs hwstamp; 2962 }; 2963 u32 words[512]; 2964 }; 2965 2966 /** 2967 * union ionic_dev_cmd_regs - Device command register format (read-write) 2968 * @doorbell: Device Cmd Doorbell, write-only 2969 * Write a 1 to signal device to process cmd, 2970 * poll done for completion. 2971 * @done: Done indicator, bit 0 == 1 when command is complete 2972 * @cmd: Opcode-specific command bytes 2973 * @comp: Opcode-specific response bytes 2974 * @data: Opcode-specific side-data 2975 */ 2976 union ionic_dev_cmd_regs { 2977 struct { 2978 u32 doorbell; 2979 u32 done; 2980 union ionic_dev_cmd cmd; 2981 union ionic_dev_cmd_comp comp; 2982 u8 rsvd[48]; 2983 u32 data[478]; 2984 } __packed; 2985 u32 words[512]; 2986 }; 2987 2988 /** 2989 * union ionic_dev_regs - Device register format for bar 0 page 0 2990 * @info: Device info registers 2991 * @devcmd: Device command registers 2992 */ 2993 union ionic_dev_regs { 2994 struct { 2995 union ionic_dev_info_regs info; 2996 union ionic_dev_cmd_regs devcmd; 2997 } __packed; 2998 __le32 words[1024]; 2999 }; 3000 3001 union ionic_adminq_cmd { 3002 struct ionic_admin_cmd cmd; 3003 struct ionic_nop_cmd nop; 3004 struct ionic_q_identify_cmd q_identify; 3005 struct ionic_q_init_cmd q_init; 3006 struct ionic_q_control_cmd q_control; 3007 struct ionic_lif_setattr_cmd lif_setattr; 3008 struct ionic_lif_getattr_cmd lif_getattr; 3009 struct ionic_lif_setphc_cmd lif_setphc; 3010 struct ionic_rx_mode_set_cmd rx_mode_set; 3011 struct ionic_rx_filter_add_cmd rx_filter_add; 3012 struct ionic_rx_filter_del_cmd rx_filter_del; 3013 struct ionic_rdma_reset_cmd rdma_reset; 3014 struct ionic_rdma_queue_cmd rdma_queue; 3015 struct ionic_fw_download_cmd fw_download; 3016 struct ionic_fw_control_cmd fw_control; 3017 }; 3018 3019 union ionic_adminq_comp { 3020 struct ionic_admin_comp comp; 3021 struct ionic_nop_comp nop; 3022 struct ionic_q_identify_comp q_identify; 3023 struct ionic_q_init_comp q_init; 3024 struct ionic_lif_setattr_comp lif_setattr; 3025 struct ionic_lif_getattr_comp lif_getattr; 3026 struct ionic_admin_comp lif_setphc; 3027 struct ionic_rx_filter_add_comp rx_filter_add; 3028 struct ionic_fw_control_comp fw_control; 3029 }; 3030 3031 #define IONIC_BARS_MAX 6 3032 #define IONIC_PCI_BAR_DBELL 1 3033 3034 /* BAR0 */ 3035 #define IONIC_BAR0_SIZE 0x8000 3036 3037 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3038 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3039 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3040 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3041 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3042 #define IONIC_DEV_CMD_DONE 0x00000001 3043 3044 #define IONIC_ASIC_TYPE_CAPRI 0 3045 3046 /** 3047 * struct ionic_doorbell - Doorbell register layout 3048 * @p_index: Producer index 3049 * @ring: Selects the specific ring of the queue to update 3050 * Type-specific meaning: 3051 * ring=0: Default producer/consumer queue 3052 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3053 * send events to EQs when armed. EQs send 3054 * interrupts when armed. 3055 * @qid_lo: Queue destination for the producer index and flags (low bits) 3056 * @qid_hi: Queue destination for the producer index and flags (high bits) 3057 */ 3058 struct ionic_doorbell { 3059 __le16 p_index; 3060 u8 ring; 3061 u8 qid_lo; 3062 __le16 qid_hi; 3063 u16 rsvd2; 3064 }; 3065 3066 struct ionic_intr_status { 3067 u32 status[2]; 3068 }; 3069 3070 struct ionic_notifyq_cmd { 3071 __le32 data; /* Not used but needed for qcq structure */ 3072 }; 3073 3074 union ionic_notifyq_comp { 3075 struct ionic_notifyq_event event; 3076 struct ionic_link_change_event link_change; 3077 struct ionic_reset_event reset; 3078 struct ionic_heartbeat_event heartbeat; 3079 struct ionic_log_event log; 3080 }; 3081 3082 /* Deprecate */ 3083 struct ionic_identity { 3084 union ionic_drv_identity drv; 3085 union ionic_dev_identity dev; 3086 union ionic_lif_identity lif; 3087 union ionic_port_identity port; 3088 union ionic_qos_identity qos; 3089 union ionic_q_identity txq; 3090 }; 3091 3092 #endif /* _IONIC_IF_H_ */ 3093