1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_LIF_H_ 5 #define _IONIC_LIF_H_ 6 7 #include <linux/pci.h> 8 #include "ionic_rx_filter.h" 9 10 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 11 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 12 13 #define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) 14 #define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) 15 #define IONIC_RX_COPYBREAK_DEFAULT 256 16 17 struct ionic_tx_stats { 18 u64 dma_map_err; 19 u64 pkts; 20 u64 bytes; 21 u64 clean; 22 u64 linearize; 23 u64 no_csum; 24 u64 csum; 25 u64 crc32_csum; 26 u64 tso; 27 u64 frags; 28 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; 29 }; 30 31 struct ionic_rx_stats { 32 u64 dma_map_err; 33 u64 alloc_err; 34 u64 pkts; 35 u64 bytes; 36 u64 csum_none; 37 u64 csum_complete; 38 u64 csum_error; 39 u64 buffers_posted; 40 }; 41 42 #define IONIC_QCQ_F_INITED BIT(0) 43 #define IONIC_QCQ_F_SG BIT(1) 44 #define IONIC_QCQ_F_INTR BIT(2) 45 #define IONIC_QCQ_F_TX_STATS BIT(3) 46 #define IONIC_QCQ_F_RX_STATS BIT(4) 47 #define IONIC_QCQ_F_NOTIFYQ BIT(5) 48 49 struct ionic_napi_stats { 50 u64 poll_count; 51 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; 52 }; 53 54 struct ionic_q_stats { 55 union { 56 struct ionic_tx_stats tx; 57 struct ionic_rx_stats rx; 58 }; 59 }; 60 61 struct ionic_qcq { 62 void *base; 63 dma_addr_t base_pa; 64 unsigned int total_size; 65 struct ionic_queue q; 66 struct ionic_cq cq; 67 struct ionic_intr_info intr; 68 struct napi_struct napi; 69 struct ionic_napi_stats napi_stats; 70 struct ionic_q_stats *stats; 71 unsigned int flags; 72 struct dentry *dentry; 73 }; 74 75 struct ionic_qcqst { 76 struct ionic_qcq *qcq; 77 struct ionic_q_stats *stats; 78 }; 79 80 #define q_to_qcq(q) container_of(q, struct ionic_qcq, q) 81 #define q_to_tx_stats(q) (&q_to_qcq(q)->stats->tx) 82 #define q_to_rx_stats(q) (&q_to_qcq(q)->stats->rx) 83 #define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) 84 #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) 85 86 enum ionic_deferred_work_type { 87 IONIC_DW_TYPE_RX_MODE, 88 IONIC_DW_TYPE_RX_ADDR_ADD, 89 IONIC_DW_TYPE_RX_ADDR_DEL, 90 IONIC_DW_TYPE_LINK_STATUS, 91 IONIC_DW_TYPE_LIF_RESET, 92 }; 93 94 struct ionic_deferred_work { 95 struct list_head list; 96 enum ionic_deferred_work_type type; 97 union { 98 unsigned int rx_mode; 99 u8 addr[ETH_ALEN]; 100 }; 101 }; 102 103 struct ionic_deferred { 104 spinlock_t lock; /* lock for deferred work list */ 105 struct list_head list; 106 struct work_struct work; 107 }; 108 109 struct ionic_lif_sw_stats { 110 u64 tx_packets; 111 u64 tx_bytes; 112 u64 rx_packets; 113 u64 rx_bytes; 114 u64 tx_tso; 115 u64 tx_no_csum; 116 u64 tx_csum; 117 u64 rx_csum_none; 118 u64 rx_csum_complete; 119 u64 rx_csum_error; 120 }; 121 122 enum ionic_lif_state_flags { 123 IONIC_LIF_INITED, 124 IONIC_LIF_SW_DEBUG_STATS, 125 IONIC_LIF_UP, 126 IONIC_LIF_LINK_CHECK_REQUESTED, 127 IONIC_LIF_QUEUE_RESET, 128 129 /* leave this as last */ 130 IONIC_LIF_STATE_SIZE 131 }; 132 133 #define IONIC_LIF_NAME_MAX_SZ 32 134 struct ionic_lif { 135 char name[IONIC_LIF_NAME_MAX_SZ]; 136 struct list_head list; 137 struct net_device *netdev; 138 DECLARE_BITMAP(state, IONIC_LIF_STATE_SIZE); 139 struct ionic *ionic; 140 bool registered; 141 unsigned int index; 142 unsigned int hw_index; 143 unsigned int kern_pid; 144 u64 __iomem *kern_dbpage; 145 spinlock_t adminq_lock; /* lock for AdminQ operations */ 146 struct ionic_qcq *adminqcq; 147 struct ionic_qcq *notifyqcq; 148 struct ionic_qcqst *txqcqs; 149 struct ionic_qcqst *rxqcqs; 150 u64 last_eid; 151 unsigned int neqs; 152 unsigned int nxqs; 153 unsigned int ntxq_descs; 154 unsigned int nrxq_descs; 155 u32 rx_copybreak; 156 unsigned int rx_mode; 157 u64 hw_features; 158 bool mc_overflow; 159 unsigned int nmcast; 160 bool uc_overflow; 161 unsigned int nucast; 162 163 struct ionic_lif_info *info; 164 dma_addr_t info_pa; 165 u32 info_sz; 166 167 u16 rss_types; 168 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 169 u8 *rss_ind_tbl; 170 dma_addr_t rss_ind_tbl_pa; 171 u32 rss_ind_tbl_sz; 172 173 struct ionic_rx_filters rx_filters; 174 struct ionic_deferred deferred; 175 unsigned long *dbid_inuse; 176 unsigned int dbid_count; 177 struct dentry *dentry; 178 u32 rx_coalesce_usecs; 179 u32 flags; 180 struct work_struct tx_timeout_work; 181 }; 182 183 #define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq) 184 #define lif_to_rxqcq(lif, i) ((lif)->rxqcqs[i].qcq) 185 #define lif_to_txstats(lif, i) ((lif)->txqcqs[i].stats->tx) 186 #define lif_to_rxstats(lif, i) ((lif)->rxqcqs[i].stats->rx) 187 #define lif_to_txq(lif, i) (&lif_to_txqcq((lif), i)->q) 188 #define lif_to_rxq(lif, i) (&lif_to_txqcq((lif), i)->q) 189 190 static inline int ionic_wait_for_bit(struct ionic_lif *lif, int bitname) 191 { 192 unsigned long tlimit = jiffies + HZ; 193 194 while (test_and_set_bit(bitname, lif->state) && 195 time_before(jiffies, tlimit)) 196 usleep_range(100, 200); 197 198 return test_bit(bitname, lif->state); 199 } 200 201 static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) 202 { 203 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 204 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 205 206 /* Div-by-zero should never be an issue, but check anyway */ 207 if (!div || !mult) 208 return 0; 209 210 /* Round up in case usecs is close to the next hw unit */ 211 usecs += (div / mult) >> 1; 212 213 /* Convert from usecs to device units */ 214 return (usecs * mult) / div; 215 } 216 217 static inline u32 ionic_coal_hw_to_usec(struct ionic *ionic, u32 units) 218 { 219 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 220 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 221 222 /* Div-by-zero should never be an issue, but check anyway */ 223 if (!div || !mult) 224 return 0; 225 226 /* Convert from device units to usec */ 227 return (units * div) / mult; 228 } 229 230 int ionic_lifs_alloc(struct ionic *ionic); 231 void ionic_lifs_free(struct ionic *ionic); 232 void ionic_lifs_deinit(struct ionic *ionic); 233 int ionic_lifs_init(struct ionic *ionic); 234 int ionic_lifs_register(struct ionic *ionic); 235 void ionic_lifs_unregister(struct ionic *ionic); 236 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 237 union ionic_lif_identity *lif_ident); 238 int ionic_lifs_size(struct ionic *ionic); 239 int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, 240 const u8 *key, const u32 *indir); 241 242 int ionic_open(struct net_device *netdev); 243 int ionic_stop(struct net_device *netdev); 244 int ionic_reset_queues(struct ionic_lif *lif); 245 246 static inline void debug_stats_txq_post(struct ionic_qcq *qcq, 247 struct ionic_txq_desc *desc, bool dbell) 248 { 249 u8 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) 250 & IONIC_TXQ_DESC_NSGE_MASK); 251 252 qcq->q.dbell_count += dbell; 253 254 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) 255 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; 256 257 qcq->stats->tx.sg_cntr[num_sg_elems]++; 258 } 259 260 static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, 261 unsigned int work_done) 262 { 263 qcq->napi_stats.poll_count++; 264 265 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) 266 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; 267 268 qcq->napi_stats.work_done_cntr[work_done]++; 269 } 270 271 #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) 272 #define DEBUG_STATS_RX_BUFF_CNT(qcq) ((qcq)->stats->rx.buffers_posted++) 273 #define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++) 274 #define DEBUG_STATS_TXQ_POST(qcq, txdesc, dbell) \ 275 debug_stats_txq_post(qcq, txdesc, dbell) 276 #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ 277 debug_stats_napi_poll(qcq, work_done) 278 279 #endif /* _IONIC_LIF_H_ */ 280