1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 113 { 114 if (!IS_ERR(mac)) { 115 ether_addr_copy(ndev->dev_addr, mac); 116 } else { 117 u32 mahr = ravb_read(ndev, MAHR); 118 u32 malr = ravb_read(ndev, MALR); 119 120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 124 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 125 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 126 } 127 } 128 129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 130 { 131 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 132 mdiobb); 133 134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 135 } 136 137 /* MDC pin control */ 138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 139 { 140 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 141 } 142 143 /* Data I/O pin control */ 144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 145 { 146 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 147 } 148 149 /* Set data bit */ 150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 151 { 152 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 153 } 154 155 /* Get data bit */ 156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 157 { 158 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 159 mdiobb); 160 161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 162 } 163 164 /* MDIO bus control struct */ 165 static struct mdiobb_ops bb_ops = { 166 .owner = THIS_MODULE, 167 .set_mdc = ravb_set_mdc, 168 .set_mdio_dir = ravb_set_mdio_dir, 169 .set_mdio_data = ravb_set_mdio_data, 170 .get_mdio_data = ravb_get_mdio_data, 171 }; 172 173 /* Free TX skb function for AVB-IP */ 174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 175 { 176 struct ravb_private *priv = netdev_priv(ndev); 177 struct net_device_stats *stats = &priv->stats[q]; 178 int num_tx_desc = priv->num_tx_desc; 179 struct ravb_tx_desc *desc; 180 int free_num = 0; 181 int entry; 182 u32 size; 183 184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 185 bool txed; 186 187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 188 num_tx_desc); 189 desc = &priv->tx_ring[q][entry]; 190 txed = desc->die_dt == DT_FEMPTY; 191 if (free_txed_only && !txed) 192 break; 193 /* Descriptor type must be checked before all other reads */ 194 dma_rmb(); 195 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 196 /* Free the original skb. */ 197 if (priv->tx_skb[q][entry / num_tx_desc]) { 198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 199 size, DMA_TO_DEVICE); 200 /* Last packet descriptor? */ 201 if (entry % num_tx_desc == num_tx_desc - 1) { 202 entry /= num_tx_desc; 203 dev_kfree_skb_any(priv->tx_skb[q][entry]); 204 priv->tx_skb[q][entry] = NULL; 205 if (txed) 206 stats->tx_packets++; 207 } 208 free_num++; 209 } 210 if (txed) 211 stats->tx_bytes += size; 212 desc->die_dt = DT_EEMPTY; 213 } 214 return free_num; 215 } 216 217 /* Free skb's and DMA buffers for Ethernet AVB */ 218 static void ravb_ring_free(struct net_device *ndev, int q) 219 { 220 struct ravb_private *priv = netdev_priv(ndev); 221 int num_tx_desc = priv->num_tx_desc; 222 int ring_size; 223 int i; 224 225 if (priv->rx_ring[q]) { 226 for (i = 0; i < priv->num_rx_ring[q]; i++) { 227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 228 229 if (!dma_mapping_error(ndev->dev.parent, 230 le32_to_cpu(desc->dptr))) 231 dma_unmap_single(ndev->dev.parent, 232 le32_to_cpu(desc->dptr), 233 priv->rx_buf_sz, 234 DMA_FROM_DEVICE); 235 } 236 ring_size = sizeof(struct ravb_ex_rx_desc) * 237 (priv->num_rx_ring[q] + 1); 238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 239 priv->rx_desc_dma[q]); 240 priv->rx_ring[q] = NULL; 241 } 242 243 if (priv->tx_ring[q]) { 244 ravb_tx_free(ndev, q, false); 245 246 ring_size = sizeof(struct ravb_tx_desc) * 247 (priv->num_tx_ring[q] * num_tx_desc + 1); 248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 249 priv->tx_desc_dma[q]); 250 priv->tx_ring[q] = NULL; 251 } 252 253 /* Free RX skb ringbuffer */ 254 if (priv->rx_skb[q]) { 255 for (i = 0; i < priv->num_rx_ring[q]; i++) 256 dev_kfree_skb(priv->rx_skb[q][i]); 257 } 258 kfree(priv->rx_skb[q]); 259 priv->rx_skb[q] = NULL; 260 261 /* Free aligned TX buffers */ 262 kfree(priv->tx_align[q]); 263 priv->tx_align[q] = NULL; 264 265 /* Free TX skb ringbuffer. 266 * SKBs are freed by ravb_tx_free() call above. 267 */ 268 kfree(priv->tx_skb[q]); 269 priv->tx_skb[q] = NULL; 270 } 271 272 /* Format skb and descriptor buffer for Ethernet AVB */ 273 static void ravb_ring_format(struct net_device *ndev, int q) 274 { 275 struct ravb_private *priv = netdev_priv(ndev); 276 int num_tx_desc = priv->num_tx_desc; 277 struct ravb_ex_rx_desc *rx_desc; 278 struct ravb_tx_desc *tx_desc; 279 struct ravb_desc *desc; 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 282 num_tx_desc; 283 dma_addr_t dma_addr; 284 int i; 285 286 priv->cur_rx[q] = 0; 287 priv->cur_tx[q] = 0; 288 priv->dirty_rx[q] = 0; 289 priv->dirty_tx[q] = 0; 290 291 memset(priv->rx_ring[q], 0, rx_ring_size); 292 /* Build RX ring buffer */ 293 for (i = 0; i < priv->num_rx_ring[q]; i++) { 294 /* RX descriptor */ 295 rx_desc = &priv->rx_ring[q][i]; 296 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 298 priv->rx_buf_sz, 299 DMA_FROM_DEVICE); 300 /* We just set the data size to 0 for a failed mapping which 301 * should prevent DMA from happening... 302 */ 303 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 304 rx_desc->ds_cc = cpu_to_le16(0); 305 rx_desc->dptr = cpu_to_le32(dma_addr); 306 rx_desc->die_dt = DT_FEMPTY; 307 } 308 rx_desc = &priv->rx_ring[q][i]; 309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 310 rx_desc->die_dt = DT_LINKFIX; /* type */ 311 312 memset(priv->tx_ring[q], 0, tx_ring_size); 313 /* Build TX ring buffer */ 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 315 i++, tx_desc++) { 316 tx_desc->die_dt = DT_EEMPTY; 317 if (num_tx_desc > 1) { 318 tx_desc++; 319 tx_desc->die_dt = DT_EEMPTY; 320 } 321 } 322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 323 tx_desc->die_dt = DT_LINKFIX; /* type */ 324 325 /* RX descriptor base address for best effort */ 326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 327 desc->die_dt = DT_LINKFIX; /* type */ 328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 329 330 /* TX descriptor base address for best effort */ 331 desc = &priv->desc_bat[q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 334 } 335 336 /* Init skb and descriptor buffer for Ethernet AVB */ 337 static int ravb_ring_init(struct net_device *ndev, int q) 338 { 339 struct ravb_private *priv = netdev_priv(ndev); 340 int num_tx_desc = priv->num_tx_desc; 341 struct sk_buff *skb; 342 int ring_size; 343 int i; 344 345 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 346 ETH_HLEN + VLAN_HLEN + sizeof(__sum16); 347 348 /* Allocate RX and TX skb rings */ 349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 350 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 352 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 353 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 354 goto error; 355 356 for (i = 0; i < priv->num_rx_ring[q]; i++) { 357 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 358 if (!skb) 359 goto error; 360 ravb_set_buffer_align(skb); 361 priv->rx_skb[q][i] = skb; 362 } 363 364 if (num_tx_desc > 1) { 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 } 371 372 /* Allocate all RX descriptors. */ 373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 375 &priv->rx_desc_dma[q], 376 GFP_KERNEL); 377 if (!priv->rx_ring[q]) 378 goto error; 379 380 priv->dirty_rx[q] = 0; 381 382 /* Allocate all TX descriptors. */ 383 ring_size = sizeof(struct ravb_tx_desc) * 384 (priv->num_tx_ring[q] * num_tx_desc + 1); 385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 386 &priv->tx_desc_dma[q], 387 GFP_KERNEL); 388 if (!priv->tx_ring[q]) 389 goto error; 390 391 return 0; 392 393 error: 394 ravb_ring_free(ndev, q); 395 396 return -ENOMEM; 397 } 398 399 /* E-MAC init function */ 400 static void ravb_emac_init(struct net_device *ndev) 401 { 402 /* Receive frame limit set register */ 403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 404 405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 406 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 /* Set AVB RX */ 451 ravb_write(ndev, 452 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 453 454 /* Set FIFO size */ 455 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 456 457 /* Timestamp enable */ 458 ravb_write(ndev, TCCR_TFEN, TCCR); 459 460 /* Interrupt init: */ 461 if (priv->chip_id == RCAR_GEN3) { 462 /* Clear DIL.DPLx */ 463 ravb_write(ndev, 0, DIL); 464 /* Set queue specific interrupt */ 465 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 466 } 467 /* Frame receive */ 468 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 469 /* Disable FIFO full warning */ 470 ravb_write(ndev, 0, RIC1); 471 /* Receive FIFO full error, descriptor empty */ 472 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 473 /* Frame transmitted, timestamp FIFO updated */ 474 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 475 476 /* Setting the control will start the AVB-DMAC process. */ 477 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 478 479 return 0; 480 } 481 482 static void ravb_get_tx_tstamp(struct net_device *ndev) 483 { 484 struct ravb_private *priv = netdev_priv(ndev); 485 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 486 struct skb_shared_hwtstamps shhwtstamps; 487 struct sk_buff *skb; 488 struct timespec64 ts; 489 u16 tag, tfa_tag; 490 int count; 491 u32 tfa2; 492 493 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 494 while (count--) { 495 tfa2 = ravb_read(ndev, TFA2); 496 tfa_tag = (tfa2 & TFA2_TST) >> 16; 497 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 498 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 499 ravb_read(ndev, TFA1); 500 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 501 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 502 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 503 list) { 504 skb = ts_skb->skb; 505 tag = ts_skb->tag; 506 list_del(&ts_skb->list); 507 kfree(ts_skb); 508 if (tag == tfa_tag) { 509 skb_tstamp_tx(skb, &shhwtstamps); 510 dev_consume_skb_any(skb); 511 break; 512 } else { 513 dev_kfree_skb_any(skb); 514 } 515 } 516 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 517 } 518 } 519 520 static void ravb_rx_csum(struct sk_buff *skb) 521 { 522 u8 *hw_csum; 523 524 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 525 * appended to packet data 526 */ 527 if (unlikely(skb->len < sizeof(__sum16))) 528 return; 529 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 530 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 531 skb->ip_summed = CHECKSUM_COMPLETE; 532 skb_trim(skb, skb->len - sizeof(__sum16)); 533 } 534 535 /* Packet receive function for Ethernet AVB */ 536 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 537 { 538 struct ravb_private *priv = netdev_priv(ndev); 539 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 540 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 541 priv->cur_rx[q]; 542 struct net_device_stats *stats = &priv->stats[q]; 543 struct ravb_ex_rx_desc *desc; 544 struct sk_buff *skb; 545 dma_addr_t dma_addr; 546 struct timespec64 ts; 547 u8 desc_status; 548 u16 pkt_len; 549 int limit; 550 551 boguscnt = min(boguscnt, *quota); 552 limit = boguscnt; 553 desc = &priv->rx_ring[q][entry]; 554 while (desc->die_dt != DT_FEMPTY) { 555 /* Descriptor type must be checked before all other reads */ 556 dma_rmb(); 557 desc_status = desc->msc; 558 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 559 560 if (--boguscnt < 0) 561 break; 562 563 /* We use 0-byte descriptors to mark the DMA mapping errors */ 564 if (!pkt_len) 565 continue; 566 567 if (desc_status & MSC_MC) 568 stats->multicast++; 569 570 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 571 MSC_CEEF)) { 572 stats->rx_errors++; 573 if (desc_status & MSC_CRC) 574 stats->rx_crc_errors++; 575 if (desc_status & MSC_RFE) 576 stats->rx_frame_errors++; 577 if (desc_status & (MSC_RTLF | MSC_RTSF)) 578 stats->rx_length_errors++; 579 if (desc_status & MSC_CEEF) 580 stats->rx_missed_errors++; 581 } else { 582 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 583 584 skb = priv->rx_skb[q][entry]; 585 priv->rx_skb[q][entry] = NULL; 586 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 587 priv->rx_buf_sz, 588 DMA_FROM_DEVICE); 589 get_ts &= (q == RAVB_NC) ? 590 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 591 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 592 if (get_ts) { 593 struct skb_shared_hwtstamps *shhwtstamps; 594 595 shhwtstamps = skb_hwtstamps(skb); 596 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 597 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 598 32) | le32_to_cpu(desc->ts_sl); 599 ts.tv_nsec = le32_to_cpu(desc->ts_n); 600 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 601 } 602 603 skb_put(skb, pkt_len); 604 skb->protocol = eth_type_trans(skb, ndev); 605 if (ndev->features & NETIF_F_RXCSUM) 606 ravb_rx_csum(skb); 607 napi_gro_receive(&priv->napi[q], skb); 608 stats->rx_packets++; 609 stats->rx_bytes += pkt_len; 610 } 611 612 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 613 desc = &priv->rx_ring[q][entry]; 614 } 615 616 /* Refill the RX ring buffers. */ 617 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 618 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 619 desc = &priv->rx_ring[q][entry]; 620 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 621 622 if (!priv->rx_skb[q][entry]) { 623 skb = netdev_alloc_skb(ndev, 624 priv->rx_buf_sz + 625 RAVB_ALIGN - 1); 626 if (!skb) 627 break; /* Better luck next round. */ 628 ravb_set_buffer_align(skb); 629 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 630 le16_to_cpu(desc->ds_cc), 631 DMA_FROM_DEVICE); 632 skb_checksum_none_assert(skb); 633 /* We just set the data size to 0 for a failed mapping 634 * which should prevent DMA from happening... 635 */ 636 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 637 desc->ds_cc = cpu_to_le16(0); 638 desc->dptr = cpu_to_le32(dma_addr); 639 priv->rx_skb[q][entry] = skb; 640 } 641 /* Descriptor type must be set after all the above writes */ 642 dma_wmb(); 643 desc->die_dt = DT_FEMPTY; 644 } 645 646 *quota -= limit - (++boguscnt); 647 648 return boguscnt <= 0; 649 } 650 651 static void ravb_rcv_snd_disable(struct net_device *ndev) 652 { 653 /* Disable TX and RX */ 654 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 655 } 656 657 static void ravb_rcv_snd_enable(struct net_device *ndev) 658 { 659 /* Enable TX and RX */ 660 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 661 } 662 663 /* function for waiting dma process finished */ 664 static int ravb_stop_dma(struct net_device *ndev) 665 { 666 int error; 667 668 /* Wait for stopping the hardware TX process */ 669 error = ravb_wait(ndev, TCCR, 670 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 671 if (error) 672 return error; 673 674 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 675 0); 676 if (error) 677 return error; 678 679 /* Stop the E-MAC's RX/TX processes. */ 680 ravb_rcv_snd_disable(ndev); 681 682 /* Wait for stopping the RX DMA process */ 683 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 684 if (error) 685 return error; 686 687 /* Stop AVB-DMAC process */ 688 return ravb_config(ndev); 689 } 690 691 /* E-MAC interrupt handler */ 692 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 693 { 694 struct ravb_private *priv = netdev_priv(ndev); 695 u32 ecsr, psr; 696 697 ecsr = ravb_read(ndev, ECSR); 698 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 699 700 if (ecsr & ECSR_MPD) 701 pm_wakeup_event(&priv->pdev->dev, 0); 702 if (ecsr & ECSR_ICD) 703 ndev->stats.tx_carrier_errors++; 704 if (ecsr & ECSR_LCHNG) { 705 /* Link changed */ 706 if (priv->no_avb_link) 707 return; 708 psr = ravb_read(ndev, PSR); 709 if (priv->avb_link_active_low) 710 psr ^= PSR_LMON; 711 if (!(psr & PSR_LMON)) { 712 /* DIsable RX and TX */ 713 ravb_rcv_snd_disable(ndev); 714 } else { 715 /* Enable RX and TX */ 716 ravb_rcv_snd_enable(ndev); 717 } 718 } 719 } 720 721 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 722 { 723 struct net_device *ndev = dev_id; 724 struct ravb_private *priv = netdev_priv(ndev); 725 726 spin_lock(&priv->lock); 727 ravb_emac_interrupt_unlocked(ndev); 728 spin_unlock(&priv->lock); 729 return IRQ_HANDLED; 730 } 731 732 /* Error interrupt handler */ 733 static void ravb_error_interrupt(struct net_device *ndev) 734 { 735 struct ravb_private *priv = netdev_priv(ndev); 736 u32 eis, ris2; 737 738 eis = ravb_read(ndev, EIS); 739 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 740 if (eis & EIS_QFS) { 741 ris2 = ravb_read(ndev, RIS2); 742 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 743 RIS2); 744 745 /* Receive Descriptor Empty int */ 746 if (ris2 & RIS2_QFF0) 747 priv->stats[RAVB_BE].rx_over_errors++; 748 749 /* Receive Descriptor Empty int */ 750 if (ris2 & RIS2_QFF1) 751 priv->stats[RAVB_NC].rx_over_errors++; 752 753 /* Receive FIFO Overflow int */ 754 if (ris2 & RIS2_RFFF) 755 priv->rx_fifo_errors++; 756 } 757 } 758 759 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 760 { 761 struct ravb_private *priv = netdev_priv(ndev); 762 u32 ris0 = ravb_read(ndev, RIS0); 763 u32 ric0 = ravb_read(ndev, RIC0); 764 u32 tis = ravb_read(ndev, TIS); 765 u32 tic = ravb_read(ndev, TIC); 766 767 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 768 if (napi_schedule_prep(&priv->napi[q])) { 769 /* Mask RX and TX interrupts */ 770 if (priv->chip_id == RCAR_GEN2) { 771 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 772 ravb_write(ndev, tic & ~BIT(q), TIC); 773 } else { 774 ravb_write(ndev, BIT(q), RID0); 775 ravb_write(ndev, BIT(q), TID); 776 } 777 __napi_schedule(&priv->napi[q]); 778 } else { 779 netdev_warn(ndev, 780 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 781 ris0, ric0); 782 netdev_warn(ndev, 783 " tx status 0x%08x, tx mask 0x%08x.\n", 784 tis, tic); 785 } 786 return true; 787 } 788 return false; 789 } 790 791 static bool ravb_timestamp_interrupt(struct net_device *ndev) 792 { 793 u32 tis = ravb_read(ndev, TIS); 794 795 if (tis & TIS_TFUF) { 796 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 797 ravb_get_tx_tstamp(ndev); 798 return true; 799 } 800 return false; 801 } 802 803 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 804 { 805 struct net_device *ndev = dev_id; 806 struct ravb_private *priv = netdev_priv(ndev); 807 irqreturn_t result = IRQ_NONE; 808 u32 iss; 809 810 spin_lock(&priv->lock); 811 /* Get interrupt status */ 812 iss = ravb_read(ndev, ISS); 813 814 /* Received and transmitted interrupts */ 815 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 816 int q; 817 818 /* Timestamp updated */ 819 if (ravb_timestamp_interrupt(ndev)) 820 result = IRQ_HANDLED; 821 822 /* Network control and best effort queue RX/TX */ 823 for (q = RAVB_NC; q >= RAVB_BE; q--) { 824 if (ravb_queue_interrupt(ndev, q)) 825 result = IRQ_HANDLED; 826 } 827 } 828 829 /* E-MAC status summary */ 830 if (iss & ISS_MS) { 831 ravb_emac_interrupt_unlocked(ndev); 832 result = IRQ_HANDLED; 833 } 834 835 /* Error status summary */ 836 if (iss & ISS_ES) { 837 ravb_error_interrupt(ndev); 838 result = IRQ_HANDLED; 839 } 840 841 /* gPTP interrupt status summary */ 842 if (iss & ISS_CGIS) { 843 ravb_ptp_interrupt(ndev); 844 result = IRQ_HANDLED; 845 } 846 847 spin_unlock(&priv->lock); 848 return result; 849 } 850 851 /* Timestamp/Error/gPTP interrupt handler */ 852 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 853 { 854 struct net_device *ndev = dev_id; 855 struct ravb_private *priv = netdev_priv(ndev); 856 irqreturn_t result = IRQ_NONE; 857 u32 iss; 858 859 spin_lock(&priv->lock); 860 /* Get interrupt status */ 861 iss = ravb_read(ndev, ISS); 862 863 /* Timestamp updated */ 864 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 865 result = IRQ_HANDLED; 866 867 /* Error status summary */ 868 if (iss & ISS_ES) { 869 ravb_error_interrupt(ndev); 870 result = IRQ_HANDLED; 871 } 872 873 /* gPTP interrupt status summary */ 874 if (iss & ISS_CGIS) { 875 ravb_ptp_interrupt(ndev); 876 result = IRQ_HANDLED; 877 } 878 879 spin_unlock(&priv->lock); 880 return result; 881 } 882 883 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 884 { 885 struct net_device *ndev = dev_id; 886 struct ravb_private *priv = netdev_priv(ndev); 887 irqreturn_t result = IRQ_NONE; 888 889 spin_lock(&priv->lock); 890 891 /* Network control/Best effort queue RX/TX */ 892 if (ravb_queue_interrupt(ndev, q)) 893 result = IRQ_HANDLED; 894 895 spin_unlock(&priv->lock); 896 return result; 897 } 898 899 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 900 { 901 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 902 } 903 904 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 905 { 906 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 907 } 908 909 static int ravb_poll(struct napi_struct *napi, int budget) 910 { 911 struct net_device *ndev = napi->dev; 912 struct ravb_private *priv = netdev_priv(ndev); 913 unsigned long flags; 914 int q = napi - priv->napi; 915 int mask = BIT(q); 916 int quota = budget; 917 u32 ris0, tis; 918 919 for (;;) { 920 tis = ravb_read(ndev, TIS); 921 ris0 = ravb_read(ndev, RIS0); 922 if (!((ris0 & mask) || (tis & mask))) 923 break; 924 925 /* Processing RX Descriptor Ring */ 926 if (ris0 & mask) { 927 /* Clear RX interrupt */ 928 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 929 if (ravb_rx(ndev, "a, q)) 930 goto out; 931 } 932 /* Processing TX Descriptor Ring */ 933 if (tis & mask) { 934 spin_lock_irqsave(&priv->lock, flags); 935 /* Clear TX interrupt */ 936 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 937 ravb_tx_free(ndev, q, true); 938 netif_wake_subqueue(ndev, q); 939 spin_unlock_irqrestore(&priv->lock, flags); 940 } 941 } 942 943 napi_complete(napi); 944 945 /* Re-enable RX/TX interrupts */ 946 spin_lock_irqsave(&priv->lock, flags); 947 if (priv->chip_id == RCAR_GEN2) { 948 ravb_modify(ndev, RIC0, mask, mask); 949 ravb_modify(ndev, TIC, mask, mask); 950 } else { 951 ravb_write(ndev, mask, RIE0); 952 ravb_write(ndev, mask, TIE); 953 } 954 spin_unlock_irqrestore(&priv->lock, flags); 955 956 /* Receive error message handling */ 957 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 958 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 959 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 960 ndev->stats.rx_over_errors = priv->rx_over_errors; 961 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 962 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 963 out: 964 return budget - quota; 965 } 966 967 /* PHY state control function */ 968 static void ravb_adjust_link(struct net_device *ndev) 969 { 970 struct ravb_private *priv = netdev_priv(ndev); 971 struct phy_device *phydev = ndev->phydev; 972 bool new_state = false; 973 unsigned long flags; 974 975 spin_lock_irqsave(&priv->lock, flags); 976 977 /* Disable TX and RX right over here, if E-MAC change is ignored */ 978 if (priv->no_avb_link) 979 ravb_rcv_snd_disable(ndev); 980 981 if (phydev->link) { 982 if (phydev->speed != priv->speed) { 983 new_state = true; 984 priv->speed = phydev->speed; 985 ravb_set_rate(ndev); 986 } 987 if (!priv->link) { 988 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 989 new_state = true; 990 priv->link = phydev->link; 991 } 992 } else if (priv->link) { 993 new_state = true; 994 priv->link = 0; 995 priv->speed = 0; 996 } 997 998 /* Enable TX and RX right over here, if E-MAC change is ignored */ 999 if (priv->no_avb_link && phydev->link) 1000 ravb_rcv_snd_enable(ndev); 1001 1002 spin_unlock_irqrestore(&priv->lock, flags); 1003 1004 if (new_state && netif_msg_link(priv)) 1005 phy_print_status(phydev); 1006 } 1007 1008 static const struct soc_device_attribute r8a7795es10[] = { 1009 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1010 { /* sentinel */ } 1011 }; 1012 1013 /* PHY init function */ 1014 static int ravb_phy_init(struct net_device *ndev) 1015 { 1016 struct device_node *np = ndev->dev.parent->of_node; 1017 struct ravb_private *priv = netdev_priv(ndev); 1018 struct phy_device *phydev; 1019 struct device_node *pn; 1020 int err; 1021 1022 priv->link = 0; 1023 priv->speed = 0; 1024 1025 /* Try connecting to PHY */ 1026 pn = of_parse_phandle(np, "phy-handle", 0); 1027 if (!pn) { 1028 /* In the case of a fixed PHY, the DT node associated 1029 * to the PHY is the Ethernet MAC DT node. 1030 */ 1031 if (of_phy_is_fixed_link(np)) { 1032 err = of_phy_register_fixed_link(np); 1033 if (err) 1034 return err; 1035 } 1036 pn = of_node_get(np); 1037 } 1038 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1039 priv->phy_interface); 1040 of_node_put(pn); 1041 if (!phydev) { 1042 netdev_err(ndev, "failed to connect PHY\n"); 1043 err = -ENOENT; 1044 goto err_deregister_fixed_link; 1045 } 1046 1047 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1048 * at this time. 1049 */ 1050 if (soc_device_match(r8a7795es10)) { 1051 err = phy_set_max_speed(phydev, SPEED_100); 1052 if (err) { 1053 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1054 goto err_phy_disconnect; 1055 } 1056 1057 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1058 } 1059 1060 /* 10BASE, Pause and Asym Pause is not supported */ 1061 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1062 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1063 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1064 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1065 1066 /* Half Duplex is not supported */ 1067 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1068 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1069 1070 phy_attached_info(phydev); 1071 1072 return 0; 1073 1074 err_phy_disconnect: 1075 phy_disconnect(phydev); 1076 err_deregister_fixed_link: 1077 if (of_phy_is_fixed_link(np)) 1078 of_phy_deregister_fixed_link(np); 1079 1080 return err; 1081 } 1082 1083 /* PHY control start function */ 1084 static int ravb_phy_start(struct net_device *ndev) 1085 { 1086 int error; 1087 1088 error = ravb_phy_init(ndev); 1089 if (error) 1090 return error; 1091 1092 phy_start(ndev->phydev); 1093 1094 return 0; 1095 } 1096 1097 static u32 ravb_get_msglevel(struct net_device *ndev) 1098 { 1099 struct ravb_private *priv = netdev_priv(ndev); 1100 1101 return priv->msg_enable; 1102 } 1103 1104 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1105 { 1106 struct ravb_private *priv = netdev_priv(ndev); 1107 1108 priv->msg_enable = value; 1109 } 1110 1111 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1112 "rx_queue_0_current", 1113 "tx_queue_0_current", 1114 "rx_queue_0_dirty", 1115 "tx_queue_0_dirty", 1116 "rx_queue_0_packets", 1117 "tx_queue_0_packets", 1118 "rx_queue_0_bytes", 1119 "tx_queue_0_bytes", 1120 "rx_queue_0_mcast_packets", 1121 "rx_queue_0_errors", 1122 "rx_queue_0_crc_errors", 1123 "rx_queue_0_frame_errors", 1124 "rx_queue_0_length_errors", 1125 "rx_queue_0_missed_errors", 1126 "rx_queue_0_over_errors", 1127 1128 "rx_queue_1_current", 1129 "tx_queue_1_current", 1130 "rx_queue_1_dirty", 1131 "tx_queue_1_dirty", 1132 "rx_queue_1_packets", 1133 "tx_queue_1_packets", 1134 "rx_queue_1_bytes", 1135 "tx_queue_1_bytes", 1136 "rx_queue_1_mcast_packets", 1137 "rx_queue_1_errors", 1138 "rx_queue_1_crc_errors", 1139 "rx_queue_1_frame_errors", 1140 "rx_queue_1_length_errors", 1141 "rx_queue_1_missed_errors", 1142 "rx_queue_1_over_errors", 1143 }; 1144 1145 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1146 1147 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1148 { 1149 switch (sset) { 1150 case ETH_SS_STATS: 1151 return RAVB_STATS_LEN; 1152 default: 1153 return -EOPNOTSUPP; 1154 } 1155 } 1156 1157 static void ravb_get_ethtool_stats(struct net_device *ndev, 1158 struct ethtool_stats *estats, u64 *data) 1159 { 1160 struct ravb_private *priv = netdev_priv(ndev); 1161 int i = 0; 1162 int q; 1163 1164 /* Device-specific stats */ 1165 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1166 struct net_device_stats *stats = &priv->stats[q]; 1167 1168 data[i++] = priv->cur_rx[q]; 1169 data[i++] = priv->cur_tx[q]; 1170 data[i++] = priv->dirty_rx[q]; 1171 data[i++] = priv->dirty_tx[q]; 1172 data[i++] = stats->rx_packets; 1173 data[i++] = stats->tx_packets; 1174 data[i++] = stats->rx_bytes; 1175 data[i++] = stats->tx_bytes; 1176 data[i++] = stats->multicast; 1177 data[i++] = stats->rx_errors; 1178 data[i++] = stats->rx_crc_errors; 1179 data[i++] = stats->rx_frame_errors; 1180 data[i++] = stats->rx_length_errors; 1181 data[i++] = stats->rx_missed_errors; 1182 data[i++] = stats->rx_over_errors; 1183 } 1184 } 1185 1186 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1187 { 1188 switch (stringset) { 1189 case ETH_SS_STATS: 1190 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1191 break; 1192 } 1193 } 1194 1195 static void ravb_get_ringparam(struct net_device *ndev, 1196 struct ethtool_ringparam *ring) 1197 { 1198 struct ravb_private *priv = netdev_priv(ndev); 1199 1200 ring->rx_max_pending = BE_RX_RING_MAX; 1201 ring->tx_max_pending = BE_TX_RING_MAX; 1202 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1203 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1204 } 1205 1206 static int ravb_set_ringparam(struct net_device *ndev, 1207 struct ethtool_ringparam *ring) 1208 { 1209 struct ravb_private *priv = netdev_priv(ndev); 1210 int error; 1211 1212 if (ring->tx_pending > BE_TX_RING_MAX || 1213 ring->rx_pending > BE_RX_RING_MAX || 1214 ring->tx_pending < BE_TX_RING_MIN || 1215 ring->rx_pending < BE_RX_RING_MIN) 1216 return -EINVAL; 1217 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1218 return -EINVAL; 1219 1220 if (netif_running(ndev)) { 1221 netif_device_detach(ndev); 1222 /* Stop PTP Clock driver */ 1223 if (priv->chip_id == RCAR_GEN2) 1224 ravb_ptp_stop(ndev); 1225 /* Wait for DMA stopping */ 1226 error = ravb_stop_dma(ndev); 1227 if (error) { 1228 netdev_err(ndev, 1229 "cannot set ringparam! Any AVB processes are still running?\n"); 1230 return error; 1231 } 1232 synchronize_irq(ndev->irq); 1233 1234 /* Free all the skb's in the RX queue and the DMA buffers. */ 1235 ravb_ring_free(ndev, RAVB_BE); 1236 ravb_ring_free(ndev, RAVB_NC); 1237 } 1238 1239 /* Set new parameters */ 1240 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1241 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1242 1243 if (netif_running(ndev)) { 1244 error = ravb_dmac_init(ndev); 1245 if (error) { 1246 netdev_err(ndev, 1247 "%s: ravb_dmac_init() failed, error %d\n", 1248 __func__, error); 1249 return error; 1250 } 1251 1252 ravb_emac_init(ndev); 1253 1254 /* Initialise PTP Clock driver */ 1255 if (priv->chip_id == RCAR_GEN2) 1256 ravb_ptp_init(ndev, priv->pdev); 1257 1258 netif_device_attach(ndev); 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int ravb_get_ts_info(struct net_device *ndev, 1265 struct ethtool_ts_info *info) 1266 { 1267 struct ravb_private *priv = netdev_priv(ndev); 1268 1269 info->so_timestamping = 1270 SOF_TIMESTAMPING_TX_SOFTWARE | 1271 SOF_TIMESTAMPING_RX_SOFTWARE | 1272 SOF_TIMESTAMPING_SOFTWARE | 1273 SOF_TIMESTAMPING_TX_HARDWARE | 1274 SOF_TIMESTAMPING_RX_HARDWARE | 1275 SOF_TIMESTAMPING_RAW_HARDWARE; 1276 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1277 info->rx_filters = 1278 (1 << HWTSTAMP_FILTER_NONE) | 1279 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1280 (1 << HWTSTAMP_FILTER_ALL); 1281 info->phc_index = ptp_clock_index(priv->ptp.clock); 1282 1283 return 0; 1284 } 1285 1286 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1287 { 1288 struct ravb_private *priv = netdev_priv(ndev); 1289 1290 wol->supported = WAKE_MAGIC; 1291 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1292 } 1293 1294 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1295 { 1296 struct ravb_private *priv = netdev_priv(ndev); 1297 1298 if (wol->wolopts & ~WAKE_MAGIC) 1299 return -EOPNOTSUPP; 1300 1301 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1302 1303 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1304 1305 return 0; 1306 } 1307 1308 static const struct ethtool_ops ravb_ethtool_ops = { 1309 .nway_reset = phy_ethtool_nway_reset, 1310 .get_msglevel = ravb_get_msglevel, 1311 .set_msglevel = ravb_set_msglevel, 1312 .get_link = ethtool_op_get_link, 1313 .get_strings = ravb_get_strings, 1314 .get_ethtool_stats = ravb_get_ethtool_stats, 1315 .get_sset_count = ravb_get_sset_count, 1316 .get_ringparam = ravb_get_ringparam, 1317 .set_ringparam = ravb_set_ringparam, 1318 .get_ts_info = ravb_get_ts_info, 1319 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1320 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1321 .get_wol = ravb_get_wol, 1322 .set_wol = ravb_set_wol, 1323 }; 1324 1325 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1326 struct net_device *ndev, struct device *dev, 1327 const char *ch) 1328 { 1329 char *name; 1330 int error; 1331 1332 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1333 if (!name) 1334 return -ENOMEM; 1335 error = request_irq(irq, handler, 0, name, ndev); 1336 if (error) 1337 netdev_err(ndev, "cannot request IRQ %s\n", name); 1338 1339 return error; 1340 } 1341 1342 /* Network device open function for Ethernet AVB */ 1343 static int ravb_open(struct net_device *ndev) 1344 { 1345 struct ravb_private *priv = netdev_priv(ndev); 1346 struct platform_device *pdev = priv->pdev; 1347 struct device *dev = &pdev->dev; 1348 int error; 1349 1350 napi_enable(&priv->napi[RAVB_BE]); 1351 napi_enable(&priv->napi[RAVB_NC]); 1352 1353 if (priv->chip_id == RCAR_GEN2) { 1354 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1355 ndev->name, ndev); 1356 if (error) { 1357 netdev_err(ndev, "cannot request IRQ\n"); 1358 goto out_napi_off; 1359 } 1360 } else { 1361 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1362 dev, "ch22:multi"); 1363 if (error) 1364 goto out_napi_off; 1365 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1366 dev, "ch24:emac"); 1367 if (error) 1368 goto out_free_irq; 1369 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1370 ndev, dev, "ch0:rx_be"); 1371 if (error) 1372 goto out_free_irq_emac; 1373 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1374 ndev, dev, "ch18:tx_be"); 1375 if (error) 1376 goto out_free_irq_be_rx; 1377 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1378 ndev, dev, "ch1:rx_nc"); 1379 if (error) 1380 goto out_free_irq_be_tx; 1381 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1382 ndev, dev, "ch19:tx_nc"); 1383 if (error) 1384 goto out_free_irq_nc_rx; 1385 } 1386 1387 /* Device init */ 1388 error = ravb_dmac_init(ndev); 1389 if (error) 1390 goto out_free_irq_nc_tx; 1391 ravb_emac_init(ndev); 1392 1393 /* Initialise PTP Clock driver */ 1394 if (priv->chip_id == RCAR_GEN2) 1395 ravb_ptp_init(ndev, priv->pdev); 1396 1397 netif_tx_start_all_queues(ndev); 1398 1399 /* PHY control start */ 1400 error = ravb_phy_start(ndev); 1401 if (error) 1402 goto out_ptp_stop; 1403 1404 return 0; 1405 1406 out_ptp_stop: 1407 /* Stop PTP Clock driver */ 1408 if (priv->chip_id == RCAR_GEN2) 1409 ravb_ptp_stop(ndev); 1410 out_free_irq_nc_tx: 1411 if (priv->chip_id == RCAR_GEN2) 1412 goto out_free_irq; 1413 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1414 out_free_irq_nc_rx: 1415 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1416 out_free_irq_be_tx: 1417 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1418 out_free_irq_be_rx: 1419 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1420 out_free_irq_emac: 1421 free_irq(priv->emac_irq, ndev); 1422 out_free_irq: 1423 free_irq(ndev->irq, ndev); 1424 out_napi_off: 1425 napi_disable(&priv->napi[RAVB_NC]); 1426 napi_disable(&priv->napi[RAVB_BE]); 1427 return error; 1428 } 1429 1430 /* Timeout function for Ethernet AVB */ 1431 static void ravb_tx_timeout(struct net_device *ndev) 1432 { 1433 struct ravb_private *priv = netdev_priv(ndev); 1434 1435 netif_err(priv, tx_err, ndev, 1436 "transmit timed out, status %08x, resetting...\n", 1437 ravb_read(ndev, ISS)); 1438 1439 /* tx_errors count up */ 1440 ndev->stats.tx_errors++; 1441 1442 schedule_work(&priv->work); 1443 } 1444 1445 static void ravb_tx_timeout_work(struct work_struct *work) 1446 { 1447 struct ravb_private *priv = container_of(work, struct ravb_private, 1448 work); 1449 struct net_device *ndev = priv->ndev; 1450 1451 netif_tx_stop_all_queues(ndev); 1452 1453 /* Stop PTP Clock driver */ 1454 if (priv->chip_id == RCAR_GEN2) 1455 ravb_ptp_stop(ndev); 1456 1457 /* Wait for DMA stopping */ 1458 ravb_stop_dma(ndev); 1459 1460 ravb_ring_free(ndev, RAVB_BE); 1461 ravb_ring_free(ndev, RAVB_NC); 1462 1463 /* Device init */ 1464 ravb_dmac_init(ndev); 1465 ravb_emac_init(ndev); 1466 1467 /* Initialise PTP Clock driver */ 1468 if (priv->chip_id == RCAR_GEN2) 1469 ravb_ptp_init(ndev, priv->pdev); 1470 1471 netif_tx_start_all_queues(ndev); 1472 } 1473 1474 /* Packet transmit function for Ethernet AVB */ 1475 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1476 { 1477 struct ravb_private *priv = netdev_priv(ndev); 1478 int num_tx_desc = priv->num_tx_desc; 1479 u16 q = skb_get_queue_mapping(skb); 1480 struct ravb_tstamp_skb *ts_skb; 1481 struct ravb_tx_desc *desc; 1482 unsigned long flags; 1483 u32 dma_addr; 1484 void *buffer; 1485 u32 entry; 1486 u32 len; 1487 1488 spin_lock_irqsave(&priv->lock, flags); 1489 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1490 num_tx_desc) { 1491 netif_err(priv, tx_queued, ndev, 1492 "still transmitting with the full ring!\n"); 1493 netif_stop_subqueue(ndev, q); 1494 spin_unlock_irqrestore(&priv->lock, flags); 1495 return NETDEV_TX_BUSY; 1496 } 1497 1498 if (skb_put_padto(skb, ETH_ZLEN)) 1499 goto exit; 1500 1501 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1502 priv->tx_skb[q][entry / num_tx_desc] = skb; 1503 1504 if (num_tx_desc > 1) { 1505 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1506 entry / num_tx_desc * DPTR_ALIGN; 1507 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1508 1509 /* Zero length DMA descriptors are problematic as they seem 1510 * to terminate DMA transfers. Avoid them by simply using a 1511 * length of DPTR_ALIGN (4) when skb data is aligned to 1512 * DPTR_ALIGN. 1513 * 1514 * As skb is guaranteed to have at least ETH_ZLEN (60) 1515 * bytes of data by the call to skb_put_padto() above this 1516 * is safe with respect to both the length of the first DMA 1517 * descriptor (len) overflowing the available data and the 1518 * length of the second DMA descriptor (skb->len - len) 1519 * being negative. 1520 */ 1521 if (len == 0) 1522 len = DPTR_ALIGN; 1523 1524 memcpy(buffer, skb->data, len); 1525 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1526 DMA_TO_DEVICE); 1527 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1528 goto drop; 1529 1530 desc = &priv->tx_ring[q][entry]; 1531 desc->ds_tagl = cpu_to_le16(len); 1532 desc->dptr = cpu_to_le32(dma_addr); 1533 1534 buffer = skb->data + len; 1535 len = skb->len - len; 1536 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1537 DMA_TO_DEVICE); 1538 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1539 goto unmap; 1540 1541 desc++; 1542 } else { 1543 desc = &priv->tx_ring[q][entry]; 1544 len = skb->len; 1545 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1546 DMA_TO_DEVICE); 1547 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1548 goto drop; 1549 } 1550 desc->ds_tagl = cpu_to_le16(len); 1551 desc->dptr = cpu_to_le32(dma_addr); 1552 1553 /* TX timestamp required */ 1554 if (q == RAVB_NC) { 1555 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1556 if (!ts_skb) { 1557 if (num_tx_desc > 1) { 1558 desc--; 1559 dma_unmap_single(ndev->dev.parent, dma_addr, 1560 len, DMA_TO_DEVICE); 1561 } 1562 goto unmap; 1563 } 1564 ts_skb->skb = skb_get(skb); 1565 ts_skb->tag = priv->ts_skb_tag++; 1566 priv->ts_skb_tag &= 0x3ff; 1567 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1568 1569 /* TAG and timestamp required flag */ 1570 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1571 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1572 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1573 } 1574 1575 skb_tx_timestamp(skb); 1576 /* Descriptor type must be set after all the above writes */ 1577 dma_wmb(); 1578 if (num_tx_desc > 1) { 1579 desc->die_dt = DT_FEND; 1580 desc--; 1581 desc->die_dt = DT_FSTART; 1582 } else { 1583 desc->die_dt = DT_FSINGLE; 1584 } 1585 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1586 1587 priv->cur_tx[q] += num_tx_desc; 1588 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1589 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1590 !ravb_tx_free(ndev, q, true)) 1591 netif_stop_subqueue(ndev, q); 1592 1593 exit: 1594 spin_unlock_irqrestore(&priv->lock, flags); 1595 return NETDEV_TX_OK; 1596 1597 unmap: 1598 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1599 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1600 drop: 1601 dev_kfree_skb_any(skb); 1602 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1603 goto exit; 1604 } 1605 1606 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1607 struct net_device *sb_dev) 1608 { 1609 /* If skb needs TX timestamp, it is handled in network control queue */ 1610 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1611 RAVB_BE; 1612 1613 } 1614 1615 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1616 { 1617 struct ravb_private *priv = netdev_priv(ndev); 1618 struct net_device_stats *nstats, *stats0, *stats1; 1619 1620 nstats = &ndev->stats; 1621 stats0 = &priv->stats[RAVB_BE]; 1622 stats1 = &priv->stats[RAVB_NC]; 1623 1624 if (priv->chip_id == RCAR_GEN3) { 1625 nstats->tx_dropped += ravb_read(ndev, TROCR); 1626 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1627 } 1628 1629 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1630 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1631 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1632 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1633 nstats->multicast = stats0->multicast + stats1->multicast; 1634 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1635 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1636 nstats->rx_frame_errors = 1637 stats0->rx_frame_errors + stats1->rx_frame_errors; 1638 nstats->rx_length_errors = 1639 stats0->rx_length_errors + stats1->rx_length_errors; 1640 nstats->rx_missed_errors = 1641 stats0->rx_missed_errors + stats1->rx_missed_errors; 1642 nstats->rx_over_errors = 1643 stats0->rx_over_errors + stats1->rx_over_errors; 1644 1645 return nstats; 1646 } 1647 1648 /* Update promiscuous bit */ 1649 static void ravb_set_rx_mode(struct net_device *ndev) 1650 { 1651 struct ravb_private *priv = netdev_priv(ndev); 1652 unsigned long flags; 1653 1654 spin_lock_irqsave(&priv->lock, flags); 1655 ravb_modify(ndev, ECMR, ECMR_PRM, 1656 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1657 spin_unlock_irqrestore(&priv->lock, flags); 1658 } 1659 1660 /* Device close function for Ethernet AVB */ 1661 static int ravb_close(struct net_device *ndev) 1662 { 1663 struct device_node *np = ndev->dev.parent->of_node; 1664 struct ravb_private *priv = netdev_priv(ndev); 1665 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1666 1667 netif_tx_stop_all_queues(ndev); 1668 1669 /* Disable interrupts by clearing the interrupt masks. */ 1670 ravb_write(ndev, 0, RIC0); 1671 ravb_write(ndev, 0, RIC2); 1672 ravb_write(ndev, 0, TIC); 1673 1674 /* Stop PTP Clock driver */ 1675 if (priv->chip_id == RCAR_GEN2) 1676 ravb_ptp_stop(ndev); 1677 1678 /* Set the config mode to stop the AVB-DMAC's processes */ 1679 if (ravb_stop_dma(ndev) < 0) 1680 netdev_err(ndev, 1681 "device will be stopped after h/w processes are done.\n"); 1682 1683 /* Clear the timestamp list */ 1684 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1685 list_del(&ts_skb->list); 1686 kfree_skb(ts_skb->skb); 1687 kfree(ts_skb); 1688 } 1689 1690 /* PHY disconnect */ 1691 if (ndev->phydev) { 1692 phy_stop(ndev->phydev); 1693 phy_disconnect(ndev->phydev); 1694 if (of_phy_is_fixed_link(np)) 1695 of_phy_deregister_fixed_link(np); 1696 } 1697 1698 if (priv->chip_id != RCAR_GEN2) { 1699 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1700 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1701 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1702 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1703 free_irq(priv->emac_irq, ndev); 1704 } 1705 free_irq(ndev->irq, ndev); 1706 1707 napi_disable(&priv->napi[RAVB_NC]); 1708 napi_disable(&priv->napi[RAVB_BE]); 1709 1710 /* Free all the skb's in the RX queue and the DMA buffers. */ 1711 ravb_ring_free(ndev, RAVB_BE); 1712 ravb_ring_free(ndev, RAVB_NC); 1713 1714 return 0; 1715 } 1716 1717 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1718 { 1719 struct ravb_private *priv = netdev_priv(ndev); 1720 struct hwtstamp_config config; 1721 1722 config.flags = 0; 1723 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1724 HWTSTAMP_TX_OFF; 1725 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1726 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1727 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1728 config.rx_filter = HWTSTAMP_FILTER_ALL; 1729 else 1730 config.rx_filter = HWTSTAMP_FILTER_NONE; 1731 1732 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1733 -EFAULT : 0; 1734 } 1735 1736 /* Control hardware time stamping */ 1737 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1738 { 1739 struct ravb_private *priv = netdev_priv(ndev); 1740 struct hwtstamp_config config; 1741 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1742 u32 tstamp_tx_ctrl; 1743 1744 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1745 return -EFAULT; 1746 1747 /* Reserved for future extensions */ 1748 if (config.flags) 1749 return -EINVAL; 1750 1751 switch (config.tx_type) { 1752 case HWTSTAMP_TX_OFF: 1753 tstamp_tx_ctrl = 0; 1754 break; 1755 case HWTSTAMP_TX_ON: 1756 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1757 break; 1758 default: 1759 return -ERANGE; 1760 } 1761 1762 switch (config.rx_filter) { 1763 case HWTSTAMP_FILTER_NONE: 1764 tstamp_rx_ctrl = 0; 1765 break; 1766 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1767 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1768 break; 1769 default: 1770 config.rx_filter = HWTSTAMP_FILTER_ALL; 1771 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1772 } 1773 1774 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1775 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1776 1777 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1778 -EFAULT : 0; 1779 } 1780 1781 /* ioctl to device function */ 1782 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1783 { 1784 struct phy_device *phydev = ndev->phydev; 1785 1786 if (!netif_running(ndev)) 1787 return -EINVAL; 1788 1789 if (!phydev) 1790 return -ENODEV; 1791 1792 switch (cmd) { 1793 case SIOCGHWTSTAMP: 1794 return ravb_hwtstamp_get(ndev, req); 1795 case SIOCSHWTSTAMP: 1796 return ravb_hwtstamp_set(ndev, req); 1797 } 1798 1799 return phy_mii_ioctl(phydev, req, cmd); 1800 } 1801 1802 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1803 { 1804 if (netif_running(ndev)) 1805 return -EBUSY; 1806 1807 ndev->mtu = new_mtu; 1808 netdev_update_features(ndev); 1809 1810 return 0; 1811 } 1812 1813 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1814 { 1815 struct ravb_private *priv = netdev_priv(ndev); 1816 unsigned long flags; 1817 1818 spin_lock_irqsave(&priv->lock, flags); 1819 1820 /* Disable TX and RX */ 1821 ravb_rcv_snd_disable(ndev); 1822 1823 /* Modify RX Checksum setting */ 1824 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1825 1826 /* Enable TX and RX */ 1827 ravb_rcv_snd_enable(ndev); 1828 1829 spin_unlock_irqrestore(&priv->lock, flags); 1830 } 1831 1832 static int ravb_set_features(struct net_device *ndev, 1833 netdev_features_t features) 1834 { 1835 netdev_features_t changed = ndev->features ^ features; 1836 1837 if (changed & NETIF_F_RXCSUM) 1838 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1839 1840 ndev->features = features; 1841 1842 return 0; 1843 } 1844 1845 static const struct net_device_ops ravb_netdev_ops = { 1846 .ndo_open = ravb_open, 1847 .ndo_stop = ravb_close, 1848 .ndo_start_xmit = ravb_start_xmit, 1849 .ndo_select_queue = ravb_select_queue, 1850 .ndo_get_stats = ravb_get_stats, 1851 .ndo_set_rx_mode = ravb_set_rx_mode, 1852 .ndo_tx_timeout = ravb_tx_timeout, 1853 .ndo_do_ioctl = ravb_do_ioctl, 1854 .ndo_change_mtu = ravb_change_mtu, 1855 .ndo_validate_addr = eth_validate_addr, 1856 .ndo_set_mac_address = eth_mac_addr, 1857 .ndo_set_features = ravb_set_features, 1858 }; 1859 1860 /* MDIO bus init function */ 1861 static int ravb_mdio_init(struct ravb_private *priv) 1862 { 1863 struct platform_device *pdev = priv->pdev; 1864 struct device *dev = &pdev->dev; 1865 int error; 1866 1867 /* Bitbang init */ 1868 priv->mdiobb.ops = &bb_ops; 1869 1870 /* MII controller setting */ 1871 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1872 if (!priv->mii_bus) 1873 return -ENOMEM; 1874 1875 /* Hook up MII support for ethtool */ 1876 priv->mii_bus->name = "ravb_mii"; 1877 priv->mii_bus->parent = dev; 1878 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1879 pdev->name, pdev->id); 1880 1881 /* Register MDIO bus */ 1882 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1883 if (error) 1884 goto out_free_bus; 1885 1886 return 0; 1887 1888 out_free_bus: 1889 free_mdio_bitbang(priv->mii_bus); 1890 return error; 1891 } 1892 1893 /* MDIO bus release function */ 1894 static int ravb_mdio_release(struct ravb_private *priv) 1895 { 1896 /* Unregister mdio bus */ 1897 mdiobus_unregister(priv->mii_bus); 1898 1899 /* Free bitbang info */ 1900 free_mdio_bitbang(priv->mii_bus); 1901 1902 return 0; 1903 } 1904 1905 static const struct of_device_id ravb_match_table[] = { 1906 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1907 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1908 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1909 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1910 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1911 { } 1912 }; 1913 MODULE_DEVICE_TABLE(of, ravb_match_table); 1914 1915 static int ravb_set_gti(struct net_device *ndev) 1916 { 1917 struct ravb_private *priv = netdev_priv(ndev); 1918 struct device *dev = ndev->dev.parent; 1919 unsigned long rate; 1920 uint64_t inc; 1921 1922 rate = clk_get_rate(priv->clk); 1923 if (!rate) 1924 return -EINVAL; 1925 1926 inc = 1000000000ULL << 20; 1927 do_div(inc, rate); 1928 1929 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1930 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1931 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1932 return -EINVAL; 1933 } 1934 1935 ravb_write(ndev, inc, GTI); 1936 1937 return 0; 1938 } 1939 1940 static void ravb_set_config_mode(struct net_device *ndev) 1941 { 1942 struct ravb_private *priv = netdev_priv(ndev); 1943 1944 if (priv->chip_id == RCAR_GEN2) { 1945 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1946 /* Set CSEL value */ 1947 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1948 } else { 1949 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1950 CCC_GAC | CCC_CSEL_HPB); 1951 } 1952 } 1953 1954 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = { 1955 { .soc_id = "r8a774c0" }, 1956 { .soc_id = "r8a77990" }, 1957 { .soc_id = "r8a77995" }, 1958 { /* sentinel */ } 1959 }; 1960 1961 /* Set tx and rx clock internal delay modes */ 1962 static void ravb_set_delay_mode(struct net_device *ndev) 1963 { 1964 struct ravb_private *priv = netdev_priv(ndev); 1965 int set = 0; 1966 1967 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1968 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1969 set |= APSR_DM_RDM; 1970 1971 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1972 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1973 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match), 1974 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree", 1975 phy_modes(priv->phy_interface))) 1976 set |= APSR_DM_TDM; 1977 } 1978 1979 ravb_modify(ndev, APSR, APSR_DM, set); 1980 } 1981 1982 static int ravb_probe(struct platform_device *pdev) 1983 { 1984 struct device_node *np = pdev->dev.of_node; 1985 struct ravb_private *priv; 1986 enum ravb_chip_id chip_id; 1987 struct net_device *ndev; 1988 int error, irq, q; 1989 struct resource *res; 1990 int i; 1991 1992 if (!np) { 1993 dev_err(&pdev->dev, 1994 "this driver is required to be instantiated from device tree\n"); 1995 return -EINVAL; 1996 } 1997 1998 /* Get base address */ 1999 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2000 if (!res) { 2001 dev_err(&pdev->dev, "invalid resource\n"); 2002 return -EINVAL; 2003 } 2004 2005 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2006 NUM_TX_QUEUE, NUM_RX_QUEUE); 2007 if (!ndev) 2008 return -ENOMEM; 2009 2010 ndev->features = NETIF_F_RXCSUM; 2011 ndev->hw_features = NETIF_F_RXCSUM; 2012 2013 pm_runtime_enable(&pdev->dev); 2014 pm_runtime_get_sync(&pdev->dev); 2015 2016 /* The Ether-specific entries in the device structure. */ 2017 ndev->base_addr = res->start; 2018 2019 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2020 2021 if (chip_id == RCAR_GEN3) 2022 irq = platform_get_irq_byname(pdev, "ch22"); 2023 else 2024 irq = platform_get_irq(pdev, 0); 2025 if (irq < 0) { 2026 error = irq; 2027 goto out_release; 2028 } 2029 ndev->irq = irq; 2030 2031 SET_NETDEV_DEV(ndev, &pdev->dev); 2032 2033 priv = netdev_priv(ndev); 2034 priv->ndev = ndev; 2035 priv->pdev = pdev; 2036 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2037 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2038 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2039 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2040 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2041 if (IS_ERR(priv->addr)) { 2042 error = PTR_ERR(priv->addr); 2043 goto out_release; 2044 } 2045 2046 spin_lock_init(&priv->lock); 2047 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2048 2049 priv->phy_interface = of_get_phy_mode(np); 2050 2051 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2052 priv->avb_link_active_low = 2053 of_property_read_bool(np, "renesas,ether-link-active-low"); 2054 2055 if (chip_id == RCAR_GEN3) { 2056 irq = platform_get_irq_byname(pdev, "ch24"); 2057 if (irq < 0) { 2058 error = irq; 2059 goto out_release; 2060 } 2061 priv->emac_irq = irq; 2062 for (i = 0; i < NUM_RX_QUEUE; i++) { 2063 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2064 if (irq < 0) { 2065 error = irq; 2066 goto out_release; 2067 } 2068 priv->rx_irqs[i] = irq; 2069 } 2070 for (i = 0; i < NUM_TX_QUEUE; i++) { 2071 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2072 if (irq < 0) { 2073 error = irq; 2074 goto out_release; 2075 } 2076 priv->tx_irqs[i] = irq; 2077 } 2078 } 2079 2080 priv->chip_id = chip_id; 2081 2082 priv->clk = devm_clk_get(&pdev->dev, NULL); 2083 if (IS_ERR(priv->clk)) { 2084 error = PTR_ERR(priv->clk); 2085 goto out_release; 2086 } 2087 2088 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2089 ndev->min_mtu = ETH_MIN_MTU; 2090 2091 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2092 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2093 2094 /* Set function */ 2095 ndev->netdev_ops = &ravb_netdev_ops; 2096 ndev->ethtool_ops = &ravb_ethtool_ops; 2097 2098 /* Set AVB config mode */ 2099 ravb_set_config_mode(ndev); 2100 2101 /* Set GTI value */ 2102 error = ravb_set_gti(ndev); 2103 if (error) 2104 goto out_release; 2105 2106 /* Request GTI loading */ 2107 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2108 2109 if (priv->chip_id != RCAR_GEN2) 2110 ravb_set_delay_mode(ndev); 2111 2112 /* Allocate descriptor base address table */ 2113 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2114 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2115 &priv->desc_bat_dma, GFP_KERNEL); 2116 if (!priv->desc_bat) { 2117 dev_err(&pdev->dev, 2118 "Cannot allocate desc base address table (size %d bytes)\n", 2119 priv->desc_bat_size); 2120 error = -ENOMEM; 2121 goto out_release; 2122 } 2123 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2124 priv->desc_bat[q].die_dt = DT_EOS; 2125 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2126 2127 /* Initialise HW timestamp list */ 2128 INIT_LIST_HEAD(&priv->ts_skb_list); 2129 2130 /* Initialise PTP Clock driver */ 2131 if (chip_id != RCAR_GEN2) 2132 ravb_ptp_init(ndev, pdev); 2133 2134 /* Debug message level */ 2135 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2136 2137 /* Read and set MAC address */ 2138 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2139 if (!is_valid_ether_addr(ndev->dev_addr)) { 2140 dev_warn(&pdev->dev, 2141 "no valid MAC address supplied, using a random one\n"); 2142 eth_hw_addr_random(ndev); 2143 } 2144 2145 /* MDIO bus init */ 2146 error = ravb_mdio_init(priv); 2147 if (error) { 2148 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2149 goto out_dma_free; 2150 } 2151 2152 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2153 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2154 2155 /* Network device register */ 2156 error = register_netdev(ndev); 2157 if (error) 2158 goto out_napi_del; 2159 2160 device_set_wakeup_capable(&pdev->dev, 1); 2161 2162 /* Print device information */ 2163 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2164 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2165 2166 platform_set_drvdata(pdev, ndev); 2167 2168 return 0; 2169 2170 out_napi_del: 2171 netif_napi_del(&priv->napi[RAVB_NC]); 2172 netif_napi_del(&priv->napi[RAVB_BE]); 2173 ravb_mdio_release(priv); 2174 out_dma_free: 2175 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2176 priv->desc_bat_dma); 2177 2178 /* Stop PTP Clock driver */ 2179 if (chip_id != RCAR_GEN2) 2180 ravb_ptp_stop(ndev); 2181 out_release: 2182 free_netdev(ndev); 2183 2184 pm_runtime_put(&pdev->dev); 2185 pm_runtime_disable(&pdev->dev); 2186 return error; 2187 } 2188 2189 static int ravb_remove(struct platform_device *pdev) 2190 { 2191 struct net_device *ndev = platform_get_drvdata(pdev); 2192 struct ravb_private *priv = netdev_priv(ndev); 2193 2194 /* Stop PTP Clock driver */ 2195 if (priv->chip_id != RCAR_GEN2) 2196 ravb_ptp_stop(ndev); 2197 2198 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2199 priv->desc_bat_dma); 2200 /* Set reset mode */ 2201 ravb_write(ndev, CCC_OPC_RESET, CCC); 2202 pm_runtime_put_sync(&pdev->dev); 2203 unregister_netdev(ndev); 2204 netif_napi_del(&priv->napi[RAVB_NC]); 2205 netif_napi_del(&priv->napi[RAVB_BE]); 2206 ravb_mdio_release(priv); 2207 pm_runtime_disable(&pdev->dev); 2208 free_netdev(ndev); 2209 platform_set_drvdata(pdev, NULL); 2210 2211 return 0; 2212 } 2213 2214 static int ravb_wol_setup(struct net_device *ndev) 2215 { 2216 struct ravb_private *priv = netdev_priv(ndev); 2217 2218 /* Disable interrupts by clearing the interrupt masks. */ 2219 ravb_write(ndev, 0, RIC0); 2220 ravb_write(ndev, 0, RIC2); 2221 ravb_write(ndev, 0, TIC); 2222 2223 /* Only allow ECI interrupts */ 2224 synchronize_irq(priv->emac_irq); 2225 napi_disable(&priv->napi[RAVB_NC]); 2226 napi_disable(&priv->napi[RAVB_BE]); 2227 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2228 2229 /* Enable MagicPacket */ 2230 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2231 2232 return enable_irq_wake(priv->emac_irq); 2233 } 2234 2235 static int ravb_wol_restore(struct net_device *ndev) 2236 { 2237 struct ravb_private *priv = netdev_priv(ndev); 2238 int ret; 2239 2240 napi_enable(&priv->napi[RAVB_NC]); 2241 napi_enable(&priv->napi[RAVB_BE]); 2242 2243 /* Disable MagicPacket */ 2244 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2245 2246 ret = ravb_close(ndev); 2247 if (ret < 0) 2248 return ret; 2249 2250 return disable_irq_wake(priv->emac_irq); 2251 } 2252 2253 static int __maybe_unused ravb_suspend(struct device *dev) 2254 { 2255 struct net_device *ndev = dev_get_drvdata(dev); 2256 struct ravb_private *priv = netdev_priv(ndev); 2257 int ret; 2258 2259 if (!netif_running(ndev)) 2260 return 0; 2261 2262 netif_device_detach(ndev); 2263 2264 if (priv->wol_enabled) 2265 ret = ravb_wol_setup(ndev); 2266 else 2267 ret = ravb_close(ndev); 2268 2269 return ret; 2270 } 2271 2272 static int __maybe_unused ravb_resume(struct device *dev) 2273 { 2274 struct net_device *ndev = dev_get_drvdata(dev); 2275 struct ravb_private *priv = netdev_priv(ndev); 2276 int ret = 0; 2277 2278 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2279 if (priv->wol_enabled) 2280 ravb_write(ndev, CCC_OPC_RESET, CCC); 2281 2282 /* All register have been reset to default values. 2283 * Restore all registers which where setup at probe time and 2284 * reopen device if it was running before system suspended. 2285 */ 2286 2287 /* Set AVB config mode */ 2288 ravb_set_config_mode(ndev); 2289 2290 /* Set GTI value */ 2291 ret = ravb_set_gti(ndev); 2292 if (ret) 2293 return ret; 2294 2295 /* Request GTI loading */ 2296 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2297 2298 if (priv->chip_id != RCAR_GEN2) 2299 ravb_set_delay_mode(ndev); 2300 2301 /* Restore descriptor base address table */ 2302 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2303 2304 if (netif_running(ndev)) { 2305 if (priv->wol_enabled) { 2306 ret = ravb_wol_restore(ndev); 2307 if (ret) 2308 return ret; 2309 } 2310 ret = ravb_open(ndev); 2311 if (ret < 0) 2312 return ret; 2313 netif_device_attach(ndev); 2314 } 2315 2316 return ret; 2317 } 2318 2319 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2320 { 2321 /* Runtime PM callback shared between ->runtime_suspend() 2322 * and ->runtime_resume(). Simply returns success. 2323 * 2324 * This driver re-initializes all registers after 2325 * pm_runtime_get_sync() anyway so there is no need 2326 * to save and restore registers here. 2327 */ 2328 return 0; 2329 } 2330 2331 static const struct dev_pm_ops ravb_dev_pm_ops = { 2332 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2333 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2334 }; 2335 2336 static struct platform_driver ravb_driver = { 2337 .probe = ravb_probe, 2338 .remove = ravb_remove, 2339 .driver = { 2340 .name = "ravb", 2341 .pm = &ravb_dev_pm_ops, 2342 .of_match_table = ravb_match_table, 2343 }, 2344 }; 2345 2346 module_platform_driver(ravb_driver); 2347 2348 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2349 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2350 MODULE_LICENSE("GPL v2"); 2351