1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 10G controller driver for Samsung SoCs
3  *
4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5  *		http://www.samsung.com
6  *
7  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
8  */
9 
10 #ifndef __SXGBE_COMMON_H__
11 #define __SXGBE_COMMON_H__
12 
13 /* forward references */
14 struct sxgbe_desc_ops;
15 struct sxgbe_dma_ops;
16 struct sxgbe_mtl_ops;
17 
18 #define SXGBE_RESOURCE_NAME	"sam_sxgbeeth"
19 #define DRV_MODULE_VERSION	"November_2013"
20 
21 /* MAX HW feature words */
22 #define SXGBE_HW_WORDS 3
23 
24 #define SXGBE_RX_COE_NONE	0
25 
26 /* CSR Frequency Access Defines*/
27 #define SXGBE_CSR_F_150M	150000000
28 #define SXGBE_CSR_F_250M	250000000
29 #define SXGBE_CSR_F_300M	300000000
30 #define SXGBE_CSR_F_350M	350000000
31 #define SXGBE_CSR_F_400M	400000000
32 #define SXGBE_CSR_F_500M	500000000
33 
34 /* pause time */
35 #define SXGBE_PAUSE_TIME 0x200
36 
37 /* tx queues */
38 #define SXGBE_TX_QUEUES   8
39 #define SXGBE_RX_QUEUES   16
40 
41 /* Calculated based how much time does it take to fill 256KB Rx memory
42  * at 10Gb speed at 156MHz clock rate and considered little less then
43  * the actual value.
44  */
45 #define SXGBE_MAX_DMA_RIWT	0x70
46 #define SXGBE_MIN_DMA_RIWT	0x01
47 
48 /* Tx coalesce parameters */
49 #define SXGBE_COAL_TX_TIMER	40000
50 #define SXGBE_MAX_COAL_TX_TICK	100000
51 #define SXGBE_TX_MAX_FRAMES	512
52 #define SXGBE_TX_FRAMES	128
53 
54 /* SXGBE TX FIFO is 8K, Rx FIFO is 16K */
55 #define BUF_SIZE_16KiB 16384
56 #define BUF_SIZE_8KiB 8192
57 #define BUF_SIZE_4KiB 4096
58 #define BUF_SIZE_2KiB 2048
59 
60 #define SXGBE_DEFAULT_LIT_LS	0x3E8
61 #define SXGBE_DEFAULT_TWT_LS	0x0
62 
63 /* Flow Control defines */
64 #define SXGBE_FLOW_OFF		0
65 #define SXGBE_FLOW_RX		1
66 #define SXGBE_FLOW_TX		2
67 #define SXGBE_FLOW_AUTO		(SXGBE_FLOW_TX | SXGBE_FLOW_RX)
68 
69 #define SF_DMA_MODE 1		/* DMA STORE-AND-FORWARD Operation Mode */
70 
71 /* errors */
72 #define RX_GMII_ERR		0x01
73 #define RX_WATCHDOG_ERR		0x02
74 #define RX_CRC_ERR		0x03
75 #define RX_GAINT_ERR		0x04
76 #define RX_IP_HDR_ERR		0x05
77 #define RX_PAYLOAD_ERR		0x06
78 #define RX_OVERFLOW_ERR		0x07
79 
80 /* pkt type */
81 #define RX_LEN_PKT		0x00
82 #define RX_MACCTL_PKT		0x01
83 #define RX_DCBCTL_PKT		0x02
84 #define RX_ARP_PKT		0x03
85 #define RX_OAM_PKT		0x04
86 #define RX_UNTAG_PKT		0x05
87 #define RX_OTHER_PKT		0x07
88 #define RX_SVLAN_PKT		0x08
89 #define RX_CVLAN_PKT		0x09
90 #define RX_DVLAN_OCVLAN_ICVLAN_PKT		0x0A
91 #define RX_DVLAN_OSVLAN_ISVLAN_PKT		0x0B
92 #define RX_DVLAN_OSVLAN_ICVLAN_PKT		0x0C
93 #define RX_DVLAN_OCVLAN_ISVLAN_PKT		0x0D
94 
95 #define RX_NOT_IP_PKT		0x00
96 #define RX_IPV4_TCP_PKT		0x01
97 #define RX_IPV4_UDP_PKT		0x02
98 #define RX_IPV4_ICMP_PKT	0x03
99 #define RX_IPV4_UNKNOWN_PKT	0x07
100 #define RX_IPV6_TCP_PKT		0x09
101 #define RX_IPV6_UDP_PKT		0x0A
102 #define RX_IPV6_ICMP_PKT	0x0B
103 #define RX_IPV6_UNKNOWN_PKT	0x0F
104 
105 #define RX_NO_PTP		0x00
106 #define RX_PTP_SYNC		0x01
107 #define RX_PTP_FOLLOW_UP	0x02
108 #define RX_PTP_DELAY_REQ	0x03
109 #define RX_PTP_DELAY_RESP	0x04
110 #define RX_PTP_PDELAY_REQ	0x05
111 #define RX_PTP_PDELAY_RESP	0x06
112 #define RX_PTP_PDELAY_FOLLOW_UP	0x07
113 #define RX_PTP_ANNOUNCE		0x08
114 #define RX_PTP_MGMT		0x09
115 #define RX_PTP_SIGNAL		0x0A
116 #define RX_PTP_RESV_MSG		0x0F
117 
118 /* EEE-LPI mode  flags*/
119 #define TX_ENTRY_LPI_MODE	0x10
120 #define TX_EXIT_LPI_MODE	0x20
121 #define RX_ENTRY_LPI_MODE	0x40
122 #define RX_EXIT_LPI_MODE	0x80
123 
124 /* EEE-LPI Interrupt status flag */
125 #define LPI_INT_STATUS		BIT(5)
126 
127 /* EEE-LPI Default timer values */
128 #define LPI_LINK_STATUS_TIMER	0x3E8
129 #define LPI_MAC_WAIT_TIMER	0x00
130 
131 /* EEE-LPI Control and status definitions */
132 #define LPI_CTRL_STATUS_TXA	BIT(19)
133 #define LPI_CTRL_STATUS_PLSDIS	BIT(18)
134 #define LPI_CTRL_STATUS_PLS	BIT(17)
135 #define LPI_CTRL_STATUS_LPIEN	BIT(16)
136 #define LPI_CTRL_STATUS_TXRSTP	BIT(11)
137 #define LPI_CTRL_STATUS_RXRSTP	BIT(10)
138 #define LPI_CTRL_STATUS_RLPIST	BIT(9)
139 #define LPI_CTRL_STATUS_TLPIST	BIT(8)
140 #define LPI_CTRL_STATUS_RLPIEX	BIT(3)
141 #define LPI_CTRL_STATUS_RLPIEN	BIT(2)
142 #define LPI_CTRL_STATUS_TLPIEX	BIT(1)
143 #define LPI_CTRL_STATUS_TLPIEN	BIT(0)
144 
145 enum dma_irq_status {
146 	tx_hard_error	= BIT(0),
147 	tx_bump_tc	= BIT(1),
148 	handle_tx	= BIT(2),
149 	rx_hard_error	= BIT(3),
150 	rx_bump_tc	= BIT(4),
151 	handle_rx	= BIT(5),
152 };
153 
154 #define NETIF_F_HW_VLAN_ALL     (NETIF_F_HW_VLAN_CTAG_RX |	\
155 				 NETIF_F_HW_VLAN_STAG_RX |	\
156 				 NETIF_F_HW_VLAN_CTAG_TX |	\
157 				 NETIF_F_HW_VLAN_STAG_TX |	\
158 				 NETIF_F_HW_VLAN_CTAG_FILTER |	\
159 				 NETIF_F_HW_VLAN_STAG_FILTER)
160 
161 /* MMC control defines */
162 #define SXGBE_MMC_CTRL_CNT_FRZ  0x00000008
163 
164 /* SXGBE HW ADDR regs */
165 #define SXGBE_ADDR_HIGH(reg)    (((reg > 15) ? 0x00000800 : 0x00000040) + \
166 				 (reg * 8))
167 #define SXGBE_ADDR_LOW(reg)     (((reg > 15) ? 0x00000804 : 0x00000044) + \
168 				 (reg * 8))
169 #define SXGBE_MAX_PERFECT_ADDRESSES 32 /* Maximum unicast perfect filtering */
170 #define SXGBE_FRAME_FILTER       0x00000004      /* Frame Filter */
171 
172 /* SXGBE Frame Filter defines */
173 #define SXGBE_FRAME_FILTER_PR    0x00000001      /* Promiscuous Mode */
174 #define SXGBE_FRAME_FILTER_HUC   0x00000002      /* Hash Unicast */
175 #define SXGBE_FRAME_FILTER_HMC   0x00000004      /* Hash Multicast */
176 #define SXGBE_FRAME_FILTER_DAIF  0x00000008      /* DA Inverse Filtering */
177 #define SXGBE_FRAME_FILTER_PM    0x00000010      /* Pass all multicast */
178 #define SXGBE_FRAME_FILTER_DBF   0x00000020      /* Disable Broadcast frames */
179 #define SXGBE_FRAME_FILTER_SAIF  0x00000100      /* Inverse Filtering */
180 #define SXGBE_FRAME_FILTER_SAF   0x00000200      /* Source Address Filter */
181 #define SXGBE_FRAME_FILTER_HPF   0x00000400      /* Hash or perfect Filter */
182 #define SXGBE_FRAME_FILTER_RA    0x80000000      /* Receive all mode */
183 
184 #define SXGBE_HASH_TABLE_SIZE    64
185 #define SXGBE_HASH_HIGH          0x00000008      /* Multicast Hash Table High */
186 #define SXGBE_HASH_LOW           0x0000000c      /* Multicast Hash Table Low */
187 
188 #define SXGBE_HI_REG_AE          0x80000000
189 
190 /* Minimum and maximum MTU */
191 #define MIN_MTU         68
192 #define MAX_MTU         9000
193 
194 #define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num)			\
195 	for (queue_num = 0; queue_num < max_queues; queue_num++)
196 
197 #define DRV_VERSION "1.0.0"
198 
199 #define SXGBE_MAX_RX_CHANNELS	16
200 #define SXGBE_MAX_TX_CHANNELS	16
201 
202 #define START_MAC_REG_OFFSET	0x0000
203 #define MAX_MAC_REG_OFFSET	0x0DFC
204 #define START_MTL_REG_OFFSET	0x1000
205 #define MAX_MTL_REG_OFFSET	0x18FC
206 #define START_DMA_REG_OFFSET	0x3000
207 #define MAX_DMA_REG_OFFSET	0x38FC
208 
209 #define REG_SPACE_SIZE		0x2000
210 
211 /* sxgbe statistics counters */
212 struct sxgbe_extra_stats {
213 	/* TX/RX IRQ events */
214 	unsigned long tx_underflow_irq;
215 	unsigned long tx_process_stopped_irq;
216 	unsigned long tx_ctxt_desc_err;
217 	unsigned long tx_threshold;
218 	unsigned long rx_threshold;
219 	unsigned long tx_pkt_n;
220 	unsigned long rx_pkt_n;
221 	unsigned long normal_irq_n;
222 	unsigned long tx_normal_irq_n;
223 	unsigned long rx_normal_irq_n;
224 	unsigned long napi_poll;
225 	unsigned long tx_clean;
226 	unsigned long tx_reset_ic_bit;
227 	unsigned long rx_process_stopped_irq;
228 	unsigned long rx_underflow_irq;
229 
230 	/* Bus access errors */
231 	unsigned long fatal_bus_error_irq;
232 	unsigned long tx_read_transfer_err;
233 	unsigned long tx_write_transfer_err;
234 	unsigned long tx_desc_access_err;
235 	unsigned long tx_buffer_access_err;
236 	unsigned long tx_data_transfer_err;
237 	unsigned long rx_read_transfer_err;
238 	unsigned long rx_write_transfer_err;
239 	unsigned long rx_desc_access_err;
240 	unsigned long rx_buffer_access_err;
241 	unsigned long rx_data_transfer_err;
242 
243 	/* EEE-LPI stats */
244 	unsigned long tx_lpi_entry_n;
245 	unsigned long tx_lpi_exit_n;
246 	unsigned long rx_lpi_entry_n;
247 	unsigned long rx_lpi_exit_n;
248 	unsigned long eee_wakeup_error_n;
249 
250 	/* RX specific */
251 	/* L2 error */
252 	unsigned long rx_code_gmii_err;
253 	unsigned long rx_watchdog_err;
254 	unsigned long rx_crc_err;
255 	unsigned long rx_gaint_pkt_err;
256 	unsigned long ip_hdr_err;
257 	unsigned long ip_payload_err;
258 	unsigned long overflow_error;
259 
260 	/* L2 Pkt type */
261 	unsigned long len_pkt;
262 	unsigned long mac_ctl_pkt;
263 	unsigned long dcb_ctl_pkt;
264 	unsigned long arp_pkt;
265 	unsigned long oam_pkt;
266 	unsigned long untag_okt;
267 	unsigned long other_pkt;
268 	unsigned long svlan_tag_pkt;
269 	unsigned long cvlan_tag_pkt;
270 	unsigned long dvlan_ocvlan_icvlan_pkt;
271 	unsigned long dvlan_osvlan_isvlan_pkt;
272 	unsigned long dvlan_osvlan_icvlan_pkt;
273 	unsigned long dvan_ocvlan_icvlan_pkt;
274 
275 	/* L3/L4 Pkt type */
276 	unsigned long not_ip_pkt;
277 	unsigned long ip4_tcp_pkt;
278 	unsigned long ip4_udp_pkt;
279 	unsigned long ip4_icmp_pkt;
280 	unsigned long ip4_unknown_pkt;
281 	unsigned long ip6_tcp_pkt;
282 	unsigned long ip6_udp_pkt;
283 	unsigned long ip6_icmp_pkt;
284 	unsigned long ip6_unknown_pkt;
285 
286 	/* Filter specific */
287 	unsigned long vlan_filter_match;
288 	unsigned long sa_filter_fail;
289 	unsigned long da_filter_fail;
290 	unsigned long hash_filter_pass;
291 	unsigned long l3_filter_match;
292 	unsigned long l4_filter_match;
293 
294 	/* RX context specific */
295 	unsigned long timestamp_dropped;
296 	unsigned long rx_msg_type_no_ptp;
297 	unsigned long rx_ptp_type_sync;
298 	unsigned long rx_ptp_type_follow_up;
299 	unsigned long rx_ptp_type_delay_req;
300 	unsigned long rx_ptp_type_delay_resp;
301 	unsigned long rx_ptp_type_pdelay_req;
302 	unsigned long rx_ptp_type_pdelay_resp;
303 	unsigned long rx_ptp_type_pdelay_follow_up;
304 	unsigned long rx_ptp_announce;
305 	unsigned long rx_ptp_mgmt;
306 	unsigned long rx_ptp_signal;
307 	unsigned long rx_ptp_resv_msg_type;
308 };
309 
310 struct mac_link {
311 	int port;
312 	int duplex;
313 	int speed;
314 };
315 
316 struct mii_regs {
317 	unsigned int addr;	/* MII Address */
318 	unsigned int data;	/* MII Data */
319 };
320 
321 struct sxgbe_core_ops {
322 	/* MAC core initialization */
323 	void (*core_init)(void __iomem *ioaddr);
324 	/* Dump MAC registers */
325 	void (*dump_regs)(void __iomem *ioaddr);
326 	/* Handle extra events on specific interrupts hw dependent */
327 	int (*host_irq_status)(void __iomem *ioaddr,
328 			       struct sxgbe_extra_stats *x);
329 	/* Set power management mode (e.g. magic frame) */
330 	void (*pmt)(void __iomem *ioaddr, unsigned long mode);
331 	/* Set/Get Unicast MAC addresses */
332 	void (*set_umac_addr)(void __iomem *ioaddr, const unsigned char *addr,
333 			      unsigned int reg_n);
334 	void (*get_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
335 			      unsigned int reg_n);
336 	void (*enable_rx)(void __iomem *ioaddr, bool enable);
337 	void (*enable_tx)(void __iomem *ioaddr, bool enable);
338 
339 	/* controller version specific operations */
340 	int (*get_controller_version)(void __iomem *ioaddr);
341 
342 	/* If supported then get the optional core features */
343 	unsigned int (*get_hw_feature)(void __iomem *ioaddr,
344 				       unsigned char feature_index);
345 	/* adjust SXGBE speed */
346 	void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
347 
348 	/* EEE-LPI specific operations */
349 	void (*set_eee_mode)(void __iomem *ioaddr);
350 	void (*reset_eee_mode)(void __iomem *ioaddr);
351 	void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
352 			      const int tw);
353 	void (*set_eee_pls)(void __iomem *ioaddr, const int link);
354 
355 	/* Enable disable checksum offload operations */
356 	void (*enable_rx_csum)(void __iomem *ioaddr);
357 	void (*disable_rx_csum)(void __iomem *ioaddr);
358 	void (*enable_rxqueue)(void __iomem *ioaddr, int queue_num);
359 	void (*disable_rxqueue)(void __iomem *ioaddr, int queue_num);
360 };
361 
362 const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
363 
364 struct sxgbe_ops {
365 	const struct sxgbe_core_ops *mac;
366 	const struct sxgbe_desc_ops *desc;
367 	const struct sxgbe_dma_ops *dma;
368 	const struct sxgbe_mtl_ops *mtl;
369 	struct mii_regs mii;	/* MII register Addresses */
370 	struct mac_link link;
371 	unsigned int ctrl_uid;
372 	unsigned int ctrl_id;
373 };
374 
375 /* SXGBE private data structures */
376 struct sxgbe_tx_queue {
377 	unsigned int irq_no;
378 	struct sxgbe_priv_data *priv_ptr;
379 	struct sxgbe_tx_norm_desc *dma_tx;
380 	dma_addr_t dma_tx_phy;
381 	dma_addr_t *tx_skbuff_dma;
382 	struct sk_buff **tx_skbuff;
383 	struct timer_list txtimer;
384 	unsigned int cur_tx;
385 	unsigned int dirty_tx;
386 	u32 tx_count_frames;
387 	u32 tx_coal_frames;
388 	u32 tx_coal_timer;
389 	int hwts_tx_en;
390 	u16 prev_mss;
391 	u8 queue_no;
392 };
393 
394 struct sxgbe_rx_queue {
395 	struct sxgbe_priv_data *priv_ptr;
396 	struct sxgbe_rx_norm_desc *dma_rx;
397 	struct sk_buff **rx_skbuff;
398 	unsigned int cur_rx;
399 	unsigned int dirty_rx;
400 	unsigned int irq_no;
401 	u32 rx_riwt;
402 	dma_addr_t *rx_skbuff_dma;
403 	dma_addr_t dma_rx_phy;
404 	u8 queue_no;
405 };
406 
407 /* SXGBE HW capabilities */
408 struct sxgbe_hw_features {
409 	/****** CAP [0] *******/
410 	unsigned int pmt_remote_wake_up;
411 	unsigned int pmt_magic_frame;
412 	/* IEEE 1588-2008 */
413 	unsigned int atime_stamp;
414 
415 	unsigned int eee;
416 
417 	unsigned int tx_csum_offload;
418 	unsigned int rx_csum_offload;
419 	unsigned int multi_macaddr;
420 	unsigned int tstamp_srcselect;
421 	unsigned int sa_vlan_insert;
422 
423 	/****** CAP [1] *******/
424 	unsigned int rxfifo_size;
425 	unsigned int txfifo_size;
426 	unsigned int atstmap_hword;
427 	unsigned int dcb_enable;
428 	unsigned int splithead_enable;
429 	unsigned int tcpseg_offload;
430 	unsigned int debug_mem;
431 	unsigned int rss_enable;
432 	unsigned int hash_tsize;
433 	unsigned int l3l4_filer_size;
434 
435 	/* This value is in bytes and
436 	 * as mentioned in HW features
437 	 * of SXGBE data book
438 	 */
439 	unsigned int rx_mtl_qsize;
440 	unsigned int tx_mtl_qsize;
441 
442 	/****** CAP [2] *******/
443 	/* TX and RX number of channels */
444 	unsigned int rx_mtl_queues;
445 	unsigned int tx_mtl_queues;
446 	unsigned int rx_dma_channels;
447 	unsigned int tx_dma_channels;
448 	unsigned int pps_output_count;
449 	unsigned int aux_input_count;
450 };
451 
452 struct sxgbe_priv_data {
453 	/* DMA descriptos */
454 	struct sxgbe_tx_queue *txq[SXGBE_TX_QUEUES];
455 	struct sxgbe_rx_queue *rxq[SXGBE_RX_QUEUES];
456 	u8 cur_rx_qnum;
457 
458 	unsigned int dma_tx_size;
459 	unsigned int dma_rx_size;
460 	unsigned int dma_buf_sz;
461 	u32 rx_riwt;
462 
463 	struct napi_struct napi;
464 
465 	void __iomem *ioaddr;
466 	struct net_device *dev;
467 	struct device *device;
468 	struct sxgbe_ops *hw;	/* sxgbe specific ops */
469 	int no_csum_insertion;
470 	int irq;
471 	int rxcsum_insertion;
472 	spinlock_t stats_lock;	/* lock for tx/rx statatics */
473 
474 	int oldlink;
475 	int speed;
476 	int oldduplex;
477 	struct mii_bus *mii;
478 	int mii_irq[PHY_MAX_ADDR];
479 	u8 rx_pause;
480 	u8 tx_pause;
481 
482 	struct sxgbe_extra_stats xstats;
483 	struct sxgbe_plat_data *plat;
484 	struct sxgbe_hw_features hw_cap;
485 
486 	u32 msg_enable;
487 
488 	struct clk *sxgbe_clk;
489 	int clk_csr;
490 	unsigned int mode;
491 	unsigned int default_addend;
492 
493 	/* advanced time stamp support */
494 	u32 adv_ts;
495 	int use_riwt;
496 	struct ptp_clock *ptp_clock;
497 
498 	/* tc control */
499 	int tx_tc;
500 	int rx_tc;
501 	/* EEE-LPI specific members */
502 	struct timer_list eee_ctrl_timer;
503 	bool tx_path_in_lpi_mode;
504 	int lpi_irq;
505 	int eee_enabled;
506 	int eee_active;
507 	int tx_lpi_timer;
508 };
509 
510 /* Function prototypes */
511 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
512 					struct sxgbe_plat_data *plat_dat,
513 					void __iomem *addr);
514 int sxgbe_drv_remove(struct net_device *ndev);
515 void sxgbe_set_ethtool_ops(struct net_device *netdev);
516 int sxgbe_mdio_unregister(struct net_device *ndev);
517 int sxgbe_mdio_register(struct net_device *ndev);
518 int sxgbe_register_platform(void);
519 void sxgbe_unregister_platform(void);
520 
521 #ifdef CONFIG_PM
522 int sxgbe_suspend(struct net_device *ndev);
523 int sxgbe_resume(struct net_device *ndev);
524 int sxgbe_freeze(struct net_device *ndev);
525 int sxgbe_restore(struct net_device *ndev);
526 #endif /* CONFIG_PM */
527 
528 const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
529 
530 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv);
531 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv);
532 #endif /* __SXGBE_COMMON_H__ */
533