1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2019 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include "efx.h" 13 #include "nic.h" 14 #include "mcdi_functions.h" 15 #include "mcdi.h" 16 #include "mcdi_pcol.h" 17 18 int efx_mcdi_free_vis(struct efx_nic *efx) 19 { 20 MCDI_DECLARE_BUF_ERR(outbuf); 21 size_t outlen; 22 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 23 outbuf, sizeof(outbuf), &outlen); 24 25 /* -EALREADY means nothing to free, so ignore */ 26 if (rc == -EALREADY) 27 rc = 0; 28 if (rc) 29 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 30 rc); 31 return rc; 32 } 33 34 int efx_mcdi_alloc_vis(struct efx_nic *efx, unsigned int min_vis, 35 unsigned int max_vis, unsigned int *vi_base, 36 unsigned int *allocated_vis) 37 { 38 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 39 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 40 size_t outlen; 41 int rc; 42 43 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 44 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 45 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 46 outbuf, sizeof(outbuf), &outlen); 47 if (rc != 0) 48 return rc; 49 50 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 51 return -EIO; 52 53 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 54 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 55 56 if (vi_base) 57 *vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 58 if (allocated_vis) 59 *allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 60 return 0; 61 } 62 63 int efx_mcdi_ev_probe(struct efx_channel *channel) 64 { 65 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 66 (channel->eventq_mask + 1) * 67 sizeof(efx_qword_t), 68 GFP_KERNEL); 69 } 70 71 int efx_mcdi_ev_init(struct efx_channel *channel, bool v1_cut_thru, bool v2) 72 { 73 MCDI_DECLARE_BUF(inbuf, 74 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 75 EFX_BUF_SIZE)); 76 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN); 77 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 78 struct efx_nic *efx = channel->efx; 79 size_t inlen, outlen; 80 dma_addr_t dma_addr; 81 int rc, i; 82 83 /* Fill event queue with all ones (i.e. empty events) */ 84 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 85 86 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 87 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 88 /* INIT_EVQ expects index in vector table, not absolute */ 89 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 90 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 91 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 92 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 93 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 94 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 95 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 96 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 97 98 if (v2) { 99 /* Use the new generic approach to specifying event queue 100 * configuration, requesting lower latency or higher throughput. 101 * The options that actually get used appear in the output. 102 */ 103 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS, 104 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1, 105 INIT_EVQ_V2_IN_FLAG_TYPE, 106 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO); 107 } else { 108 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 109 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 110 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 111 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 112 INIT_EVQ_IN_FLAG_CUT_THRU, v1_cut_thru); 113 } 114 115 dma_addr = channel->eventq.buf.dma_addr; 116 for (i = 0; i < entries; ++i) { 117 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 118 dma_addr += EFX_BUF_SIZE; 119 } 120 121 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 122 123 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 124 outbuf, sizeof(outbuf), &outlen); 125 126 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN) 127 netif_dbg(efx, drv, efx->net_dev, 128 "Channel %d using event queue flags %08x\n", 129 channel->channel, 130 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS)); 131 132 return rc; 133 } 134 135 void efx_mcdi_ev_remove(struct efx_channel *channel) 136 { 137 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 138 } 139 140 void efx_mcdi_ev_fini(struct efx_channel *channel) 141 { 142 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 143 MCDI_DECLARE_BUF_ERR(outbuf); 144 struct efx_nic *efx = channel->efx; 145 size_t outlen; 146 int rc; 147 148 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 149 150 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 151 outbuf, sizeof(outbuf), &outlen); 152 153 if (rc && rc != -EALREADY) 154 goto fail; 155 156 return; 157 158 fail: 159 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 160 outbuf, outlen, rc); 161 } 162 163 int efx_mcdi_tx_init(struct efx_tx_queue *tx_queue, bool tso_v2) 164 { 165 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 166 EFX_BUF_SIZE)); 167 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 168 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 169 struct efx_channel *channel = tx_queue->channel; 170 struct efx_nic *efx = tx_queue->efx; 171 struct efx_ef10_nic_data *nic_data; 172 dma_addr_t dma_addr; 173 size_t inlen; 174 int rc, i; 175 176 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 177 178 nic_data = efx->nic_data; 179 180 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 181 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 182 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 183 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 184 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 185 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 186 187 dma_addr = tx_queue->txd.buf.dma_addr; 188 189 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 190 tx_queue->queue, entries, (u64)dma_addr); 191 192 for (i = 0; i < entries; ++i) { 193 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 194 dma_addr += EFX_BUF_SIZE; 195 } 196 197 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 198 199 do { 200 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS, 201 /* This flag was removed from mcdi_pcol.h for 202 * the non-_EXT version of INIT_TXQ. However, 203 * firmware still honours it. 204 */ 205 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2, 206 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 207 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload, 208 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP, 209 tx_queue->timestamping); 210 211 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 212 NULL, 0, NULL); 213 if (rc == -ENOSPC && tso_v2) { 214 /* Retry without TSOv2 if we're short on contexts. */ 215 tso_v2 = false; 216 netif_warn(efx, probe, efx->net_dev, 217 "TSOv2 context not available to segment in " 218 "hardware. TCP performance may be reduced.\n" 219 ); 220 } else if (rc) { 221 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ, 222 MC_CMD_INIT_TXQ_EXT_IN_LEN, 223 NULL, 0, rc); 224 goto fail; 225 } 226 } while (rc); 227 228 return 0; 229 230 fail: 231 return rc; 232 } 233 234 void efx_mcdi_tx_remove(struct efx_tx_queue *tx_queue) 235 { 236 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 237 } 238 239 void efx_mcdi_tx_fini(struct efx_tx_queue *tx_queue) 240 { 241 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 242 MCDI_DECLARE_BUF_ERR(outbuf); 243 struct efx_nic *efx = tx_queue->efx; 244 size_t outlen; 245 int rc; 246 247 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 248 tx_queue->queue); 249 250 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 251 outbuf, sizeof(outbuf), &outlen); 252 253 if (rc && rc != -EALREADY) 254 goto fail; 255 256 return; 257 258 fail: 259 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 260 outbuf, outlen, rc); 261 } 262 263 int efx_mcdi_rx_probe(struct efx_rx_queue *rx_queue) 264 { 265 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 266 (rx_queue->ptr_mask + 1) * 267 sizeof(efx_qword_t), 268 GFP_KERNEL); 269 } 270 271 void efx_mcdi_rx_init(struct efx_rx_queue *rx_queue) 272 { 273 MCDI_DECLARE_BUF(inbuf, 274 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 275 EFX_BUF_SIZE)); 276 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 277 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 278 struct efx_nic *efx = rx_queue->efx; 279 struct efx_ef10_nic_data *nic_data = efx->nic_data; 280 dma_addr_t dma_addr; 281 size_t inlen; 282 int rc; 283 int i; 284 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 285 286 rx_queue->scatter_n = 0; 287 rx_queue->scatter_len = 0; 288 289 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 290 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 291 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 292 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 293 efx_rx_queue_index(rx_queue)); 294 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 295 INIT_RXQ_IN_FLAG_PREFIX, 1, 296 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 297 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 298 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 299 300 dma_addr = rx_queue->rxd.buf.dma_addr; 301 302 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 303 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 304 305 for (i = 0; i < entries; ++i) { 306 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 307 dma_addr += EFX_BUF_SIZE; 308 } 309 310 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 311 312 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 313 NULL, 0, NULL); 314 if (rc) 315 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 316 efx_rx_queue_index(rx_queue)); 317 } 318 319 void efx_mcdi_rx_remove(struct efx_rx_queue *rx_queue) 320 { 321 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 322 } 323 324 void efx_mcdi_rx_fini(struct efx_rx_queue *rx_queue) 325 { 326 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 327 MCDI_DECLARE_BUF_ERR(outbuf); 328 struct efx_nic *efx = rx_queue->efx; 329 size_t outlen; 330 int rc; 331 332 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 333 efx_rx_queue_index(rx_queue)); 334 335 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 336 outbuf, sizeof(outbuf), &outlen); 337 338 if (rc && rc != -EALREADY) 339 goto fail; 340 341 return; 342 343 fail: 344 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 345 outbuf, outlen, rc); 346 } 347 348 int efx_mcdi_window_mode_to_stride(struct efx_nic *efx, u8 vi_window_mode) 349 { 350 switch (vi_window_mode) { 351 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K: 352 efx->vi_stride = 8192; 353 break; 354 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K: 355 efx->vi_stride = 16384; 356 break; 357 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K: 358 efx->vi_stride = 65536; 359 break; 360 default: 361 netif_err(efx, probe, efx->net_dev, 362 "Unrecognised VI window mode %d\n", 363 vi_window_mode); 364 return -EIO; 365 } 366 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n", 367 efx->vi_stride); 368 return 0; 369 } 370 371 int efx_get_pf_index(struct efx_nic *efx, unsigned int *pf_index) 372 { 373 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 374 size_t outlen; 375 int rc; 376 377 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 378 sizeof(outbuf), &outlen); 379 if (rc) 380 return rc; 381 if (outlen < sizeof(outbuf)) 382 return -EIO; 383 384 *pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 385 return 0; 386 } 387