1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2009-2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 6 */ 7 8 9 #ifndef MCDI_PCOL_H 10 #define MCDI_PCOL_H 11 12 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 13 /* Power-on reset state */ 14 #define MC_FW_STATE_POR (1) 15 /* If this is set in MC_RESET_STATE_REG then it should be 16 * possible to jump into IMEM without loading code from flash. */ 17 #define MC_FW_WARM_BOOT_OK (2) 18 /* The MC main image has started to boot. */ 19 #define MC_FW_STATE_BOOTING (4) 20 /* The Scheduler has started. */ 21 #define MC_FW_STATE_SCHED (8) 22 /* If this is set in MC_RESET_STATE_REG then it should be 23 * possible to jump into IMEM without loading code from flash. 24 * Unlike a warm boot, assume DMEM has been reloaded, so that 25 * the MC persistent data must be reinitialised. */ 26 #define MC_FW_TEPID_BOOT_OK (16) 27 /* We have entered the main firmware via recovery mode. This 28 * means that MC persistent data must be reinitialised, but that 29 * we shouldn't touch PCIe config. */ 30 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 31 /* BIST state has been initialized */ 32 #define MC_FW_BIST_INIT_OK (128) 33 34 /* Siena MC shared memmory offsets */ 35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 36 #define MC_SMEM_P0_DOORBELL_OFST 0x000 37 #define MC_SMEM_P1_DOORBELL_OFST 0x004 38 /* The rest of these are firmware-defined */ 39 #define MC_SMEM_P0_PDU_OFST 0x008 40 #define MC_SMEM_P1_PDU_OFST 0x108 41 #define MC_SMEM_PDU_LEN 0x100 42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 43 #define MC_SMEM_P0_STATUS_OFST 0x7f8 44 #define MC_SMEM_P1_STATUS_OFST 0x7fc 45 46 /* Values to be written to the per-port status dword in shared 47 * memory on reboot and assert */ 48 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 50 51 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 52 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 53 54 /* The current version of the MCDI protocol. 55 * 56 * Note that the ROM burnt into the card only talks V0, so at the very 57 * least every driver must support version 0 and MCDI_PCOL_VERSION 58 */ 59 #define MCDI_PCOL_VERSION 2 60 61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 62 63 /* MCDI version 1 64 * 65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 66 * structure, filled in by the client. 67 * 68 * 0 7 8 16 20 22 23 24 31 69 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 70 * | | | 71 * | | \--- Response 72 * | \------- Error 73 * \------------------------------ Resync (always set) 74 * 75 * The client writes it's request into MC shared memory, and rings the 76 * doorbell. Each request is completed by either by the MC writing 77 * back into shared memory, or by writing out an event. 78 * 79 * All MCDI commands support completion by shared memory response. Each 80 * request may also contain additional data (accounted for by HEADER.LEN), 81 * and some response's may also contain additional data (again, accounted 82 * for by HEADER.LEN). 83 * 84 * Some MCDI commands support completion by event, in which any associated 85 * response data is included in the event. 86 * 87 * The protocol requires one response to be delivered for every request, a 88 * request should not be sent unless the response for the previous request 89 * has been received (either by polling shared memory, or by receiving 90 * an event). 91 */ 92 93 /** Request/Response structure */ 94 #define MCDI_HEADER_OFST 0 95 #define MCDI_HEADER_CODE_LBN 0 96 #define MCDI_HEADER_CODE_WIDTH 7 97 #define MCDI_HEADER_RESYNC_LBN 7 98 #define MCDI_HEADER_RESYNC_WIDTH 1 99 #define MCDI_HEADER_DATALEN_LBN 8 100 #define MCDI_HEADER_DATALEN_WIDTH 8 101 #define MCDI_HEADER_SEQ_LBN 16 102 #define MCDI_HEADER_SEQ_WIDTH 4 103 #define MCDI_HEADER_RSVD_LBN 20 104 #define MCDI_HEADER_RSVD_WIDTH 1 105 #define MCDI_HEADER_NOT_EPOCH_LBN 21 106 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 107 #define MCDI_HEADER_ERROR_LBN 22 108 #define MCDI_HEADER_ERROR_WIDTH 1 109 #define MCDI_HEADER_RESPONSE_LBN 23 110 #define MCDI_HEADER_RESPONSE_WIDTH 1 111 #define MCDI_HEADER_XFLAGS_LBN 24 112 #define MCDI_HEADER_XFLAGS_WIDTH 8 113 /* Request response using event */ 114 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 115 /* Request (and signal) early doorbell return */ 116 #define MCDI_HEADER_XFLAGS_DBRET 0x02 117 118 /* Maximum number of payload bytes */ 119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 121 122 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 123 124 125 /* The MC can generate events for two reasons: 126 * - To advance a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 128 * via MC_CMD_LOG_CTRL 129 * 130 * Both events share a common structure: 131 * 132 * 0 32 33 36 44 52 60 133 * | Data | Cont | Level | Src | Code | Rsvd | 134 * | 135 * \ There is another event pending in this notification 136 * 137 * If Code==CMDDONE, then the fields are further interpreted as: 138 * 139 * - LEVEL==INFO Command succeeded 140 * - LEVEL==ERR Command failed 141 * 142 * 0 8 16 24 32 143 * | Seq | Datalen | Errno | Rsvd | 144 * 145 * These fields are taken directly out of the standard MCDI header, i.e., 146 * LEVEL==ERR, Datalen == 0 => Reboot 147 * 148 * Events can be squirted out of the UART (using LOG_CTRL) without a 149 * MCDI header. An event can be distinguished from a MCDI response by 150 * examining the first byte which is 0xc0. This corresponds to the 151 * non-existent MCDI command MC_CMD_DEBUG_LOG. 152 * 153 * 0 7 8 154 * | command | Resync | = 0xc0 155 * 156 * Since the event is written in big-endian byte order, this works 157 * providing bits 56-63 of the event are 0xc0. 158 * 159 * 56 60 63 160 * | Rsvd | Code | = 0xc0 161 * 162 * Which means for convenience the event code is 0xc for all MC 163 * generated events. 164 */ 165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 166 167 168 /* Operation not permitted. */ 169 #define MC_CMD_ERR_EPERM 1 170 /* Non-existent command target */ 171 #define MC_CMD_ERR_ENOENT 2 172 /* assert() has killed the MC */ 173 #define MC_CMD_ERR_EINTR 4 174 /* I/O failure */ 175 #define MC_CMD_ERR_EIO 5 176 /* Already exists */ 177 #define MC_CMD_ERR_EEXIST 6 178 /* Try again */ 179 #define MC_CMD_ERR_EAGAIN 11 180 /* Out of memory */ 181 #define MC_CMD_ERR_ENOMEM 12 182 /* Caller does not hold required locks */ 183 #define MC_CMD_ERR_EACCES 13 184 /* Resource is currently unavailable (e.g. lock contention) */ 185 #define MC_CMD_ERR_EBUSY 16 186 /* No such device */ 187 #define MC_CMD_ERR_ENODEV 19 188 /* Invalid argument to target */ 189 #define MC_CMD_ERR_EINVAL 22 190 /* Broken pipe */ 191 #define MC_CMD_ERR_EPIPE 32 192 /* Read-only */ 193 #define MC_CMD_ERR_EROFS 30 194 /* Out of range */ 195 #define MC_CMD_ERR_ERANGE 34 196 /* Non-recursive resource is already acquired */ 197 #define MC_CMD_ERR_EDEADLK 35 198 /* Operation not implemented */ 199 #define MC_CMD_ERR_ENOSYS 38 200 /* Operation timed out */ 201 #define MC_CMD_ERR_ETIME 62 202 /* Link has been severed */ 203 #define MC_CMD_ERR_ENOLINK 67 204 /* Protocol error */ 205 #define MC_CMD_ERR_EPROTO 71 206 /* Operation not supported */ 207 #define MC_CMD_ERR_ENOTSUP 95 208 /* Address not available */ 209 #define MC_CMD_ERR_EADDRNOTAVAIL 99 210 /* Not connected */ 211 #define MC_CMD_ERR_ENOTCONN 107 212 /* Operation already in progress */ 213 #define MC_CMD_ERR_EALREADY 114 214 215 /* Resource allocation failed. */ 216 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 217 /* V-adaptor not found. */ 218 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 219 /* EVB port not found. */ 220 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 221 /* V-switch not found. */ 222 #define MC_CMD_ERR_NO_VSWITCH 0x1003 223 /* Too many VLAN tags. */ 224 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 225 /* Bad PCI function number. */ 226 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 227 /* Invalid VLAN mode. */ 228 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 229 /* Invalid v-switch type. */ 230 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 231 /* Invalid v-port type. */ 232 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 233 /* MAC address exists. */ 234 #define MC_CMD_ERR_MAC_EXIST 0x1009 235 /* Slave core not present */ 236 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 237 /* The datapath is disabled. */ 238 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 239 /* The requesting client is not a function */ 240 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 241 /* The requested operation might require the 242 command to be passed between MCs, and the 243 transport doesn't support that. Should 244 only ever been seen over the UART. */ 245 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 246 /* VLAN tag(s) exists */ 247 #define MC_CMD_ERR_VLAN_EXIST 0x100e 248 /* No MAC address assigned to an EVB port */ 249 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 250 /* Notifies the driver that the request has been relayed 251 * to an admin function for authorization. The driver should 252 * wait for a PROXY_RESPONSE event and then resend its request. 253 * This error code is followed by a 32-bit handle that 254 * helps matching it with the respective PROXY_RESPONSE event. */ 255 #define MC_CMD_ERR_PROXY_PENDING 0x1010 256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 257 /* The request cannot be passed for authorization because 258 * another request from the same function is currently being 259 * authorized. The drvier should try again later. */ 260 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 261 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 262 * that has enabled proxying or BLOCK_INDEX points to a function that 263 * doesn't await an authorization. */ 264 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 265 /* This code is currently only used internally in FW. Its meaning is that 266 * an operation failed due to lack of SR-IOV privilege. 267 * Normally it is translated to EPERM by send_cmd_err(), 268 * but it may also be used to trigger some special mechanism 269 * for handling such case, e.g. to relay the failed request 270 * to a designated admin function for authorization. */ 271 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 272 /* Workaround 26807 could not be turned on/off because some functions 273 * have already installed filters. See the comment at 274 * MC_CMD_WORKAROUND_BUG26807. 275 * May also returned for other operations such as sub-variant switching. */ 276 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 277 /* The clock whose frequency you've attempted to set set 278 * doesn't exist on this NIC */ 279 #define MC_CMD_ERR_NO_CLOCK 0x1015 280 /* Returned by MC_CMD_TESTASSERT if the action that should 281 * have caused an assertion failed to do so. */ 282 #define MC_CMD_ERR_UNREACHABLE 0x1016 283 /* This command needs to be processed in the background but there were no 284 * resources to do so. Send it again after a command has completed. */ 285 #define MC_CMD_ERR_QUEUE_FULL 0x1017 286 /* The operation could not be completed because the PCIe link has gone 287 * away. This error code is never expected to be returned over the TLP 288 * transport. */ 289 #define MC_CMD_ERR_NO_PCIE 0x1018 290 /* The operation could not be completed because the datapath has gone 291 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 292 * datapath absence may be temporary*/ 293 #define MC_CMD_ERR_NO_DATAPATH 0x1019 294 /* The operation could not complete because some VIs are allocated */ 295 #define MC_CMD_ERR_VIS_PRESENT 0x101a 296 /* The operation could not complete because some PIO buffers are allocated */ 297 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b 298 299 #define MC_CMD_ERR_CODE_OFST 0 300 301 /* We define 8 "escape" commands to allow 302 for command number space extension */ 303 304 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 305 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 306 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 307 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 308 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 309 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 310 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 311 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 312 313 /* Vectors in the boot ROM */ 314 /* Point to the copycode entry point. */ 315 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 316 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 317 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 318 /* Points to the recovery mode entry point. Misnamed but kept for compatibility. */ 319 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 320 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 321 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 322 /* Points to the recovery mode entry point. Same as above, but the right name. */ 323 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4) 324 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4) 325 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4) 326 327 /* Points to noflash mode entry point. */ 328 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4) 329 330 /* The command set exported by the boot ROM (MCDI v0) */ 331 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 332 (1 << MC_CMD_READ32) | \ 333 (1 << MC_CMD_WRITE32) | \ 334 (1 << MC_CMD_COPYCODE) | \ 335 (1 << MC_CMD_GET_VERSION), \ 336 0, 0, 0 } 337 338 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 339 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 340 341 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 345 346 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 350 351 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 355 356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 357 * stack ID (which must be in the range 1-255) along with an EVB port ID. 358 */ 359 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 360 361 362 /* Version 2 adds an optional argument to error returns: the errno value 363 * may be followed by the (0-based) number of the first argument that 364 * could not be processed. 365 */ 366 #define MC_CMD_ERR_ARG_OFST 4 367 368 /* No space */ 369 #define MC_CMD_ERR_ENOSPC 28 370 371 /* MCDI_EVENT structuredef */ 372 #define MCDI_EVENT_LEN 8 373 #define MCDI_EVENT_CONT_LBN 32 374 #define MCDI_EVENT_CONT_WIDTH 1 375 #define MCDI_EVENT_LEVEL_LBN 33 376 #define MCDI_EVENT_LEVEL_WIDTH 3 377 /* enum: Info. */ 378 #define MCDI_EVENT_LEVEL_INFO 0x0 379 /* enum: Warning. */ 380 #define MCDI_EVENT_LEVEL_WARN 0x1 381 /* enum: Error. */ 382 #define MCDI_EVENT_LEVEL_ERR 0x2 383 /* enum: Fatal. */ 384 #define MCDI_EVENT_LEVEL_FATAL 0x3 385 #define MCDI_EVENT_DATA_OFST 0 386 #define MCDI_EVENT_DATA_LEN 4 387 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0 388 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 389 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 390 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0 391 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 392 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 393 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0 394 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 395 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 396 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0 397 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 398 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 399 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0 400 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 401 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 402 /* enum: Link is down or link speed could not be determined */ 403 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0 404 /* enum: 100Mbs */ 405 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 406 /* enum: 1Gbs */ 407 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 408 /* enum: 10Gbs */ 409 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 410 /* enum: 40Gbs */ 411 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 412 /* enum: 25Gbs */ 413 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 414 /* enum: 50Gbs */ 415 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 416 /* enum: 100Gbs */ 417 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 418 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0 419 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 420 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 421 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0 422 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 423 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 424 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0 425 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 426 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 427 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0 428 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 429 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 430 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0 431 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 432 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 433 #define MCDI_EVENT_FWALERT_DATA_OFST 0 434 #define MCDI_EVENT_FWALERT_DATA_LBN 8 435 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 436 #define MCDI_EVENT_FWALERT_REASON_OFST 0 437 #define MCDI_EVENT_FWALERT_REASON_LBN 0 438 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 439 /* enum: SRAM Access. */ 440 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 441 #define MCDI_EVENT_FLR_VF_OFST 0 442 #define MCDI_EVENT_FLR_VF_LBN 0 443 #define MCDI_EVENT_FLR_VF_WIDTH 8 444 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0 445 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 446 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 447 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0 448 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 449 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 450 /* enum: Descriptor loader reported failure */ 451 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 452 /* enum: Descriptor ring empty and no EOP seen for packet */ 453 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 454 /* enum: Overlength packet */ 455 #define MCDI_EVENT_TX_ERR_2BIG 0x3 456 /* enum: Malformed option descriptor */ 457 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 458 /* enum: Option descriptor part way through a packet */ 459 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 460 /* enum: DMA or PIO data access error */ 461 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 462 #define MCDI_EVENT_TX_ERR_INFO_OFST 0 463 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 464 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 465 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0 466 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 467 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 468 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0 469 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 470 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 471 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0 472 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 473 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 474 /* enum: PLL lost lock */ 475 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 476 /* enum: Filter overflow (PDMA) */ 477 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 478 /* enum: FIFO overflow (FPGA) */ 479 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 480 /* enum: Merge queue overflow */ 481 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 482 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0 483 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 484 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 485 /* enum: AOE failed to load - no valid image? */ 486 #define MCDI_EVENT_AOE_NO_LOAD 0x1 487 /* enum: AOE FC reported an exception */ 488 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 489 /* enum: AOE FC watchdogged */ 490 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 491 /* enum: AOE FC failed to start */ 492 #define MCDI_EVENT_AOE_FC_NO_START 0x4 493 /* enum: Generic AOE fault - likely to have been reported via other means too 494 * but intended for use by aoex driver. 495 */ 496 #define MCDI_EVENT_AOE_FAULT 0x5 497 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 498 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 499 /* enum: AOE loaded successfully */ 500 #define MCDI_EVENT_AOE_LOAD 0x7 501 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 502 #define MCDI_EVENT_AOE_DMA 0x8 503 /* enum: AOE byteblaster connected/disconnected (Connection status in 504 * AOE_ERR_DATA) 505 */ 506 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 507 /* enum: DDR ECC status update */ 508 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 509 /* enum: PTP status update */ 510 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 511 /* enum: FPGA header incorrect */ 512 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 513 /* enum: FPGA Powered Off due to error in powering up FPGA */ 514 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 515 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 516 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 517 /* enum: Notify that invalid flash type detected */ 518 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 519 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 520 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 521 /* enum: Failure to probe one or more FPGA boot flash chips */ 522 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 523 /* enum: FPGA boot-flash contains an invalid image header */ 524 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 525 /* enum: Failed to program clocks required by the FPGA */ 526 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 527 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */ 528 #define MCDI_EVENT_AOE_FC_RUNNING 0x14 529 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0 530 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 531 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 532 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0 533 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 534 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 535 /* enum: FC Assert happened, but the register information is not available */ 536 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 537 /* enum: The register information for FC Assert is ready for readinng by driver 538 */ 539 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 540 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0 541 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 542 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 543 /* enum: Reading from NV failed */ 544 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 545 /* enum: Invalid Magic Number if FPGA header */ 546 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 547 /* enum: Invalid Silicon type detected in header */ 548 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 549 /* enum: Unsupported VRatio */ 550 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 551 /* enum: Unsupported DDR Type */ 552 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 553 /* enum: DDR Voltage out of supported range */ 554 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 555 /* enum: Unsupported DDR speed */ 556 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 557 /* enum: Unsupported DDR size */ 558 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 559 /* enum: Unsupported DDR rank */ 560 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 561 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0 562 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 563 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 564 /* enum: Primary boot flash */ 565 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 566 /* enum: Secondary boot flash */ 567 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 568 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0 569 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 570 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 571 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0 572 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 573 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 574 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0 575 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 576 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 577 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0 578 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 579 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 580 #define MCDI_EVENT_RX_ERR_INFO_OFST 0 581 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 582 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 583 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0 584 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 585 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 586 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0 587 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 588 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 589 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0 590 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 591 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 592 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0 593 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 594 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 595 /* enum: MUM failed to load - no valid image? */ 596 #define MCDI_EVENT_MUM_NO_LOAD 0x1 597 /* enum: MUM f/w reported an exception */ 598 #define MCDI_EVENT_MUM_ASSERT 0x2 599 /* enum: MUM not kicking watchdog */ 600 #define MCDI_EVENT_MUM_WATCHDOG 0x3 601 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0 602 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 603 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 604 #define MCDI_EVENT_DBRET_SEQ_OFST 0 605 #define MCDI_EVENT_DBRET_SEQ_LBN 0 606 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8 607 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0 608 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 609 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 610 /* enum: Corrupted or bad SUC application. */ 611 #define MCDI_EVENT_SUC_BAD_APP 0x1 612 /* enum: SUC application reported an assert. */ 613 #define MCDI_EVENT_SUC_ASSERT 0x2 614 /* enum: SUC application reported an exception. */ 615 #define MCDI_EVENT_SUC_EXCEPTION 0x3 616 /* enum: SUC watchdog timer expired. */ 617 #define MCDI_EVENT_SUC_WATCHDOG 0x4 618 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0 619 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 620 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 621 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0 622 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8 623 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 624 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0 625 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0 626 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24 627 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0 628 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24 629 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4 630 /* Enum values, see field(s): */ 631 /* MCDI_EVENT/LINKCHANGE_SPEED */ 632 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0 633 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28 634 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1 635 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0 636 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29 637 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3 638 /* Enum values, see field(s): */ 639 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 640 #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0 641 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0 642 #define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30 643 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0 644 #define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30 645 #define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2 646 #define MCDI_EVENT_DATA_LBN 0 647 #define MCDI_EVENT_DATA_WIDTH 32 648 /* Alias for PTP_DATA. */ 649 #define MCDI_EVENT_SRC_LBN 36 650 #define MCDI_EVENT_SRC_WIDTH 8 651 /* Data associated with PTP events which doesn't fit into the main DATA field 652 */ 653 #define MCDI_EVENT_PTP_DATA_LBN 36 654 #define MCDI_EVENT_PTP_DATA_WIDTH 8 655 /* EF100 specific. Defined by QDMA. The phase bit, changes each time round the 656 * event ring 657 */ 658 #define MCDI_EVENT_EV_EVQ_PHASE_LBN 59 659 #define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1 660 #define MCDI_EVENT_EV_CODE_LBN 60 661 #define MCDI_EVENT_EV_CODE_WIDTH 4 662 #define MCDI_EVENT_CODE_LBN 44 663 #define MCDI_EVENT_CODE_WIDTH 8 664 /* enum: Event generated by host software */ 665 #define MCDI_EVENT_SW_EVENT 0x0 666 /* enum: Bad assert. */ 667 #define MCDI_EVENT_CODE_BADSSERT 0x1 668 /* enum: PM Notice. */ 669 #define MCDI_EVENT_CODE_PMNOTICE 0x2 670 /* enum: Command done. */ 671 #define MCDI_EVENT_CODE_CMDDONE 0x3 672 /* enum: Link change. */ 673 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 674 /* enum: Sensor Event. */ 675 #define MCDI_EVENT_CODE_SENSOREVT 0x5 676 /* enum: Schedule error. */ 677 #define MCDI_EVENT_CODE_SCHEDERR 0x6 678 /* enum: Reboot. */ 679 #define MCDI_EVENT_CODE_REBOOT 0x7 680 /* enum: Mac stats DMA. */ 681 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 682 /* enum: Firmware alert. */ 683 #define MCDI_EVENT_CODE_FWALERT 0x9 684 /* enum: Function level reset. */ 685 #define MCDI_EVENT_CODE_FLR 0xa 686 /* enum: Transmit error */ 687 #define MCDI_EVENT_CODE_TX_ERR 0xb 688 /* enum: Tx flush has completed */ 689 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 690 /* enum: PTP packet received timestamp */ 691 #define MCDI_EVENT_CODE_PTP_RX 0xd 692 /* enum: PTP NIC failure */ 693 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 694 /* enum: PTP PPS event */ 695 #define MCDI_EVENT_CODE_PTP_PPS 0xf 696 /* enum: Rx flush has completed */ 697 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 698 /* enum: Receive error */ 699 #define MCDI_EVENT_CODE_RX_ERR 0x11 700 /* enum: AOE fault */ 701 #define MCDI_EVENT_CODE_AOE 0x12 702 /* enum: Network port calibration failed (VCAL). */ 703 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 704 /* enum: HW PPS event */ 705 #define MCDI_EVENT_CODE_HW_PPS 0x14 706 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 707 * a different format) 708 */ 709 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 710 /* enum: the MC has detected a parity error */ 711 #define MCDI_EVENT_CODE_PAR_ERR 0x16 712 /* enum: the MC has detected a correctable error */ 713 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 714 /* enum: the MC has detected an uncorrectable error */ 715 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 716 /* enum: The MC has entered offline BIST mode */ 717 #define MCDI_EVENT_CODE_MC_BIST 0x19 718 /* enum: PTP tick event providing current NIC time */ 719 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 720 /* enum: MUM fault */ 721 #define MCDI_EVENT_CODE_MUM 0x1b 722 /* enum: notify the designated PF of a new authorization request */ 723 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 724 /* enum: notify a function that awaits an authorization that its request has 725 * been processed and it may now resend the command 726 */ 727 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 728 /* enum: MCDI command accepted. New commands can be issued but this command is 729 * not done yet. 730 */ 731 #define MCDI_EVENT_CODE_DBRET 0x1e 732 /* enum: The MC has detected a fault on the SUC */ 733 #define MCDI_EVENT_CODE_SUC 0x1f 734 /* enum: Link change. This event is sent instead of LINKCHANGE if 735 * WANT_V2_LINKCHANGES was set on driver attach. 736 */ 737 #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20 738 /* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach 739 * when the local device capabilities changes. This will usually correspond to 740 * a module change. 741 */ 742 #define MCDI_EVENT_CODE_MODULECHANGE 0x21 743 /* enum: Notification that the sensors have been added and/or removed from the 744 * sensor table. This event includes the new sensor table generation count, if 745 * this does not match the driver's local copy it is expected to call 746 * DYNAMIC_SENSORS_LIST to refresh it. 747 */ 748 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22 749 /* enum: Notification that a sensor has changed state as a result of a reading 750 * crossing a threshold. This is sent as two events, the first event contains 751 * the handle and the sensor's state (in the SRC field), and the second 752 * contains the value. 753 */ 754 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23 755 /* enum: Notification that a descriptor proxy function configuration has been 756 * pushed to "live" status (visible to host). SRC field contains the handle of 757 * the affected descriptor proxy function. DATA field contains the generation 758 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET / 759 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details. 760 */ 761 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24 762 /* enum: Notification that a descriptor proxy function has been reset. SRC 763 * field contains the handle of the affected descriptor proxy function. See 764 * SF-122927-TC for details. 765 */ 766 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25 767 /* enum: Notification that a driver attached to a descriptor proxy function. 768 * SRC field contains the handle of the affected descriptor proxy function. For 769 * Virtio proxy functions this message consists of two MCDI events, where the 770 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0 771 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy 772 * functions event length and meaning of DATA field is not yet defined. See 773 * SF-122927-TC for details. 774 */ 775 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26 776 /* enum: Artificial event generated by host and posted via MC for test 777 * purposes. 778 */ 779 #define MCDI_EVENT_CODE_TESTGEN 0xfa 780 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 781 #define MCDI_EVENT_CMDDONE_DATA_LEN 4 782 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 783 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 784 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 785 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 786 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 787 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 788 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 789 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 790 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 791 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 792 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 793 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 794 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 795 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 796 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 797 #define MCDI_EVENT_TX_ERR_DATA_LEN 4 798 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 799 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 800 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 801 * timestamp 802 */ 803 #define MCDI_EVENT_PTP_SECONDS_OFST 0 804 #define MCDI_EVENT_PTP_SECONDS_LEN 4 805 #define MCDI_EVENT_PTP_SECONDS_LBN 0 806 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 807 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 808 * timestamp 809 */ 810 #define MCDI_EVENT_PTP_MAJOR_OFST 0 811 #define MCDI_EVENT_PTP_MAJOR_LEN 4 812 #define MCDI_EVENT_PTP_MAJOR_LBN 0 813 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 814 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 815 * of timestamp 816 */ 817 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 818 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 819 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 820 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 821 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 822 * timestamp 823 */ 824 #define MCDI_EVENT_PTP_MINOR_OFST 0 825 #define MCDI_EVENT_PTP_MINOR_LEN 4 826 #define MCDI_EVENT_PTP_MINOR_LBN 0 827 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 828 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 829 */ 830 #define MCDI_EVENT_PTP_UUID_OFST 0 831 #define MCDI_EVENT_PTP_UUID_LEN 4 832 #define MCDI_EVENT_PTP_UUID_LBN 0 833 #define MCDI_EVENT_PTP_UUID_WIDTH 32 834 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 835 #define MCDI_EVENT_RX_ERR_DATA_LEN 4 836 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 837 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 838 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 839 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4 840 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 841 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 842 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 843 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 844 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 845 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 846 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 847 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 848 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 849 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 850 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 851 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 852 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 853 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 854 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 855 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 856 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 857 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 858 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 859 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19. 860 */ 861 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 862 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 863 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 864 * whether the NIC clock has ever been set 865 */ 866 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 867 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 868 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 869 * whether the NIC and System clocks are in sync 870 */ 871 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 872 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 873 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 874 * the minor value of the PTP clock 875 */ 876 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 877 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 878 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 879 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21. 880 */ 881 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 882 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 883 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 884 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 885 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 886 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 887 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 888 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 889 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 890 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 891 /* Zero means that the request has been completed or authorized, and the driver 892 * should resend it. A non-zero value means that the authorization has been 893 * denied, and gives the reason. Typically it will be EPERM. 894 */ 895 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 896 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 897 #define MCDI_EVENT_DBRET_DATA_OFST 0 898 #define MCDI_EVENT_DBRET_DATA_LEN 4 899 #define MCDI_EVENT_DBRET_DATA_LBN 0 900 #define MCDI_EVENT_DBRET_DATA_WIDTH 32 901 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0 902 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4 903 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0 904 #define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32 905 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0 906 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4 907 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0 908 #define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32 909 /* The new generation count after a sensor has been added or deleted. */ 910 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0 911 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4 912 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0 913 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32 914 /* The handle of a dynamic sensor. */ 915 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0 916 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4 917 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0 918 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32 919 /* The current values of a sensor. */ 920 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0 921 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4 922 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0 923 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32 924 /* The current state of a sensor. */ 925 #define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36 926 #define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8 927 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0 928 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4 929 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0 930 #define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32 931 /* Generation count of applied configuration set */ 932 #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0 933 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4 934 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0 935 #define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32 936 /* Virtio features negotiated with the host driver. First event (CONT=1) 937 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63. 938 */ 939 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0 940 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4 941 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0 942 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32 943 944 /* FCDI_EVENT structuredef */ 945 #define FCDI_EVENT_LEN 8 946 #define FCDI_EVENT_CONT_LBN 32 947 #define FCDI_EVENT_CONT_WIDTH 1 948 #define FCDI_EVENT_LEVEL_LBN 33 949 #define FCDI_EVENT_LEVEL_WIDTH 3 950 /* enum: Info. */ 951 #define FCDI_EVENT_LEVEL_INFO 0x0 952 /* enum: Warning. */ 953 #define FCDI_EVENT_LEVEL_WARN 0x1 954 /* enum: Error. */ 955 #define FCDI_EVENT_LEVEL_ERR 0x2 956 /* enum: Fatal. */ 957 #define FCDI_EVENT_LEVEL_FATAL 0x3 958 #define FCDI_EVENT_DATA_OFST 0 959 #define FCDI_EVENT_DATA_LEN 4 960 #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0 961 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 962 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 963 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 964 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 965 #define FCDI_EVENT_DATA_LBN 0 966 #define FCDI_EVENT_DATA_WIDTH 32 967 #define FCDI_EVENT_SRC_LBN 36 968 #define FCDI_EVENT_SRC_WIDTH 8 969 #define FCDI_EVENT_EV_CODE_LBN 60 970 #define FCDI_EVENT_EV_CODE_WIDTH 4 971 #define FCDI_EVENT_CODE_LBN 44 972 #define FCDI_EVENT_CODE_WIDTH 8 973 /* enum: The FC was rebooted. */ 974 #define FCDI_EVENT_CODE_REBOOT 0x1 975 /* enum: Bad assert. */ 976 #define FCDI_EVENT_CODE_ASSERT 0x2 977 /* enum: DDR3 test result. */ 978 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 979 /* enum: Link status. */ 980 #define FCDI_EVENT_CODE_LINK_STATE 0x4 981 /* enum: A timed read is ready to be serviced. */ 982 #define FCDI_EVENT_CODE_TIMED_READ 0x5 983 /* enum: One or more PPS IN events */ 984 #define FCDI_EVENT_CODE_PPS_IN 0x6 985 /* enum: Tick event from PTP clock */ 986 #define FCDI_EVENT_CODE_PTP_TICK 0x7 987 /* enum: ECC error counters */ 988 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 989 /* enum: Current status of PTP */ 990 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 991 /* enum: Port id config to map MC-FC port idx */ 992 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 993 /* enum: Boot result or error code */ 994 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 995 #define FCDI_EVENT_REBOOT_SRC_LBN 36 996 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 997 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 998 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 999 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 1000 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 1001 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 1002 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 1003 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 1004 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 1005 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 1006 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 1007 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 1008 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 1009 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 1010 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 1011 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 1012 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 1013 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 1014 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 1015 #define FCDI_EVENT_PTP_STATE_OFST 0 1016 #define FCDI_EVENT_PTP_STATE_LEN 4 1017 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 1018 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 1019 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 1020 #define FCDI_EVENT_PTP_STATE_LBN 0 1021 #define FCDI_EVENT_PTP_STATE_WIDTH 32 1022 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 1023 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 1024 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 1025 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 1026 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 1027 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 1028 /* Index of MC port being referred to */ 1029 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 1030 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 1031 /* FC Port index that matches the MC port index in SRC */ 1032 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 1033 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 1034 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 1035 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 1036 #define FCDI_EVENT_BOOT_RESULT_OFST 0 1037 #define FCDI_EVENT_BOOT_RESULT_LEN 4 1038 /* Enum values, see field(s): */ 1039 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 1040 #define FCDI_EVENT_BOOT_RESULT_LBN 0 1041 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 1042 1043 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 1044 * to the MC. Note that this structure | is overlayed over a normal FCDI event 1045 * such that bits 32-63 containing | event code, level, source etc remain the 1046 * same. In this case the data | field of the header is defined to be the 1047 * number of timestamps 1048 */ 1049 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 1050 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 1051 #define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016 1052 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 1053 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8) 1054 /* Number of timestamps following */ 1055 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 1056 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 1057 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 1058 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 1059 /* Seconds field of a timestamp record */ 1060 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 1061 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 1062 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 1063 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 1064 /* Nanoseconds field of a timestamp record */ 1065 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 1066 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 1067 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 1068 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 1069 /* Timestamp records comprising the event */ 1070 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 1071 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 1072 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 1073 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 1074 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 1075 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 1076 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126 1077 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 1078 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 1079 1080 /* MUM_EVENT structuredef */ 1081 #define MUM_EVENT_LEN 8 1082 #define MUM_EVENT_CONT_LBN 32 1083 #define MUM_EVENT_CONT_WIDTH 1 1084 #define MUM_EVENT_LEVEL_LBN 33 1085 #define MUM_EVENT_LEVEL_WIDTH 3 1086 /* enum: Info. */ 1087 #define MUM_EVENT_LEVEL_INFO 0x0 1088 /* enum: Warning. */ 1089 #define MUM_EVENT_LEVEL_WARN 0x1 1090 /* enum: Error. */ 1091 #define MUM_EVENT_LEVEL_ERR 0x2 1092 /* enum: Fatal. */ 1093 #define MUM_EVENT_LEVEL_FATAL 0x3 1094 #define MUM_EVENT_DATA_OFST 0 1095 #define MUM_EVENT_DATA_LEN 4 1096 #define MUM_EVENT_SENSOR_ID_OFST 0 1097 #define MUM_EVENT_SENSOR_ID_LBN 0 1098 #define MUM_EVENT_SENSOR_ID_WIDTH 8 1099 /* Enum values, see field(s): */ 1100 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 1101 #define MUM_EVENT_SENSOR_STATE_OFST 0 1102 #define MUM_EVENT_SENSOR_STATE_LBN 8 1103 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 1104 #define MUM_EVENT_PORT_PHY_READY_OFST 0 1105 #define MUM_EVENT_PORT_PHY_READY_LBN 0 1106 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 1107 #define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0 1108 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 1109 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 1110 #define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0 1111 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 1112 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 1113 #define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0 1114 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 1115 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 1116 #define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0 1117 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 1118 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 1119 #define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0 1120 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 1121 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 1122 #define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0 1123 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 1124 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 1125 #define MUM_EVENT_DATA_LBN 0 1126 #define MUM_EVENT_DATA_WIDTH 32 1127 #define MUM_EVENT_SRC_LBN 36 1128 #define MUM_EVENT_SRC_WIDTH 8 1129 #define MUM_EVENT_EV_CODE_LBN 60 1130 #define MUM_EVENT_EV_CODE_WIDTH 4 1131 #define MUM_EVENT_CODE_LBN 44 1132 #define MUM_EVENT_CODE_WIDTH 8 1133 /* enum: The MUM was rebooted. */ 1134 #define MUM_EVENT_CODE_REBOOT 0x1 1135 /* enum: Bad assert. */ 1136 #define MUM_EVENT_CODE_ASSERT 0x2 1137 /* enum: Sensor failure. */ 1138 #define MUM_EVENT_CODE_SENSOR 0x3 1139 /* enum: Link fault has been asserted, or has cleared. */ 1140 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 1141 #define MUM_EVENT_SENSOR_DATA_OFST 0 1142 #define MUM_EVENT_SENSOR_DATA_LEN 4 1143 #define MUM_EVENT_SENSOR_DATA_LBN 0 1144 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 1145 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 1146 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 1147 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 1148 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 1149 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 1150 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 1151 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 1152 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 1153 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 1154 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4 1155 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 1156 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 1157 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 1158 #define MUM_EVENT_PORT_PHY_TECH_LEN 4 1159 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 1160 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 1161 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 1162 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 1163 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 1164 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 1165 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 1166 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 1167 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 1168 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 1169 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 1170 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 1171 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 1172 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 1173 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 1174 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 1175 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 1176 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 1177 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 1178 1179 1180 /***********************************/ 1181 /* MC_CMD_READ32 1182 * Read multiple 32byte words from MC memory. Note - this command really 1183 * belongs to INSECURE category but is required by shmboot. The command handler 1184 * has additional checks to reject insecure calls. 1185 */ 1186 #define MC_CMD_READ32 0x1 1187 #undef MC_CMD_0x1_PRIVILEGE_CTG 1188 1189 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1190 1191 /* MC_CMD_READ32_IN msgrequest */ 1192 #define MC_CMD_READ32_IN_LEN 8 1193 #define MC_CMD_READ32_IN_ADDR_OFST 0 1194 #define MC_CMD_READ32_IN_ADDR_LEN 4 1195 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 1196 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4 1197 1198 /* MC_CMD_READ32_OUT msgresponse */ 1199 #define MC_CMD_READ32_OUT_LENMIN 4 1200 #define MC_CMD_READ32_OUT_LENMAX 252 1201 #define MC_CMD_READ32_OUT_LENMAX_MCDI2 1020 1202 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 1203 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4) 1204 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 1205 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 1206 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 1207 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 1208 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255 1209 1210 1211 /***********************************/ 1212 /* MC_CMD_WRITE32 1213 * Write multiple 32byte words to MC memory. 1214 */ 1215 #define MC_CMD_WRITE32 0x2 1216 #undef MC_CMD_0x2_PRIVILEGE_CTG 1217 1218 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1219 1220 /* MC_CMD_WRITE32_IN msgrequest */ 1221 #define MC_CMD_WRITE32_IN_LENMIN 8 1222 #define MC_CMD_WRITE32_IN_LENMAX 252 1223 #define MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020 1224 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 1225 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4) 1226 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 1227 #define MC_CMD_WRITE32_IN_ADDR_LEN 4 1228 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 1229 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 1230 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 1231 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 1232 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254 1233 1234 /* MC_CMD_WRITE32_OUT msgresponse */ 1235 #define MC_CMD_WRITE32_OUT_LEN 0 1236 1237 1238 /***********************************/ 1239 /* MC_CMD_COPYCODE 1240 * Copy MC code between two locations and jump. Note - this command really 1241 * belongs to INSECURE category but is required by shmboot. The command handler 1242 * has additional checks to reject insecure calls. 1243 */ 1244 #define MC_CMD_COPYCODE 0x3 1245 #undef MC_CMD_0x3_PRIVILEGE_CTG 1246 1247 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1248 1249 /* MC_CMD_COPYCODE_IN msgrequest */ 1250 #define MC_CMD_COPYCODE_IN_LEN 16 1251 /* Source address 1252 * 1253 * The main image should be entered via a copy of a single word from and to a 1254 * magic address, which controls various aspects of the boot. The magic address 1255 * is a bitfield, with each bit as documented below. 1256 */ 1257 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1258 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1259 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1260 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1261 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1262 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1263 */ 1264 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1265 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1266 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1267 * below) 1268 */ 1269 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1270 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0 1271 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1272 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1273 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0 1274 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1275 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1276 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0 1277 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1278 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1279 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0 1280 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1281 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1282 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0 1283 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1284 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1285 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0 1286 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1287 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1288 /* Destination address */ 1289 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1290 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1291 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1292 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1293 /* Address of where to jump after copy. */ 1294 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1295 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1296 /* enum: Control should return to the caller rather than jumping */ 1297 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1298 1299 /* MC_CMD_COPYCODE_OUT msgresponse */ 1300 #define MC_CMD_COPYCODE_OUT_LEN 0 1301 1302 1303 /***********************************/ 1304 /* MC_CMD_SET_FUNC 1305 * Select function for function-specific commands. 1306 */ 1307 #define MC_CMD_SET_FUNC 0x4 1308 #undef MC_CMD_0x4_PRIVILEGE_CTG 1309 1310 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1311 1312 /* MC_CMD_SET_FUNC_IN msgrequest */ 1313 #define MC_CMD_SET_FUNC_IN_LEN 4 1314 /* Set function */ 1315 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1316 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1317 1318 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1319 #define MC_CMD_SET_FUNC_OUT_LEN 0 1320 1321 1322 /***********************************/ 1323 /* MC_CMD_GET_BOOT_STATUS 1324 * Get the instruction address from which the MC booted. 1325 */ 1326 #define MC_CMD_GET_BOOT_STATUS 0x5 1327 #undef MC_CMD_0x5_PRIVILEGE_CTG 1328 1329 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1330 1331 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1332 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1333 1334 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1335 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1336 /* ?? */ 1337 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1338 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4 1339 /* enum: indicates that the MC wasn't flash booted */ 1340 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1341 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1342 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4 1343 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4 1344 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1345 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1346 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4 1347 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1348 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1349 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4 1350 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1351 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1352 1353 1354 /***********************************/ 1355 /* MC_CMD_GET_ASSERTS 1356 * Get (and optionally clear) the current assertion status. Only 1357 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1358 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1359 */ 1360 #define MC_CMD_GET_ASSERTS 0x6 1361 #undef MC_CMD_0x6_PRIVILEGE_CTG 1362 1363 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1364 1365 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1366 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1367 /* Set to clear assertion */ 1368 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1369 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4 1370 1371 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1372 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1373 /* Assertion status flag. */ 1374 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1375 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 1376 /* enum: No assertions have failed. */ 1377 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1378 /* enum: A system-level assertion has failed. */ 1379 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1380 /* enum: A thread-level assertion has failed. */ 1381 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1382 /* enum: The system was reset by the watchdog. */ 1383 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1384 /* enum: An illegal address trap stopped the system (huntington and later) */ 1385 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1386 /* Failing PC value */ 1387 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1388 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 1389 /* Saved GP regs */ 1390 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1391 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1392 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1393 /* enum: A magic value hinting that the value in this register at the time of 1394 * the failure has likely been lost. 1395 */ 1396 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1397 /* Failing thread address */ 1398 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1399 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 1400 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1401 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 1402 1403 /* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs 1404 * found on Riverhead designs 1405 */ 1406 #define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240 1407 /* Assertion status flag. */ 1408 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0 1409 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4 1410 /* enum: No assertions have failed. */ 1411 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */ 1412 /* enum: A system-level assertion has failed. */ 1413 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */ 1414 /* enum: A thread-level assertion has failed. */ 1415 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */ 1416 /* enum: The system was reset by the watchdog. */ 1417 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */ 1418 /* enum: An illegal address trap stopped the system (huntington and later) */ 1419 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */ 1420 /* Failing PC value */ 1421 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4 1422 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4 1423 /* Saved GP regs */ 1424 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8 1425 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4 1426 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31 1427 /* enum: A magic value hinting that the value in this register at the time of 1428 * the failure has likely been lost. 1429 */ 1430 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */ 1431 /* Failing thread address */ 1432 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132 1433 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4 1434 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136 1435 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4 1436 /* Saved Special Function Registers */ 1437 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136 1438 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4 1439 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26 1440 1441 /* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted 1442 * firmware version information 1443 */ 1444 #define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360 1445 /* Assertion status flag. */ 1446 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0 1447 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4 1448 /* enum: No assertions have failed. */ 1449 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */ 1450 /* enum: A system-level assertion has failed. */ 1451 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */ 1452 /* enum: A thread-level assertion has failed. */ 1453 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */ 1454 /* enum: The system was reset by the watchdog. */ 1455 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */ 1456 /* enum: An illegal address trap stopped the system (huntington and later) */ 1457 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */ 1458 /* Failing PC value */ 1459 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4 1460 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4 1461 /* Saved GP regs */ 1462 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8 1463 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4 1464 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31 1465 /* enum: A magic value hinting that the value in this register at the time of 1466 * the failure has likely been lost. 1467 */ 1468 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */ 1469 /* Failing thread address */ 1470 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132 1471 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4 1472 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136 1473 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4 1474 /* Saved Special Function Registers */ 1475 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136 1476 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4 1477 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26 1478 /* MC firmware unique build ID (as binary SHA-1 value) */ 1479 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240 1480 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20 1481 /* MC firmware build date (as Unix timestamp) */ 1482 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260 1483 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8 1484 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260 1485 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264 1486 /* MC firmware version number */ 1487 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268 1488 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8 1489 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268 1490 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272 1491 /* MC firmware security level */ 1492 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276 1493 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4 1494 /* MC firmware extra version info (as null-terminated US-ASCII string) */ 1495 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280 1496 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16 1497 /* MC firmware build name (as null-terminated US-ASCII string) */ 1498 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296 1499 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64 1500 1501 1502 /***********************************/ 1503 /* MC_CMD_LOG_CTRL 1504 * Configure the output stream for log events such as link state changes, 1505 * sensor notifications and MCDI completions 1506 */ 1507 #define MC_CMD_LOG_CTRL 0x7 1508 #undef MC_CMD_0x7_PRIVILEGE_CTG 1509 1510 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1511 1512 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1513 #define MC_CMD_LOG_CTRL_IN_LEN 8 1514 /* Log destination */ 1515 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1516 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 1517 /* enum: UART. */ 1518 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1519 /* enum: Event queue. */ 1520 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1521 /* Legacy argument. Must be zero. */ 1522 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1523 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4 1524 1525 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1526 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1527 1528 1529 /***********************************/ 1530 /* MC_CMD_GET_VERSION 1531 * Get version information about adapter components. 1532 */ 1533 #define MC_CMD_GET_VERSION 0x8 1534 #undef MC_CMD_0x8_PRIVILEGE_CTG 1535 1536 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1537 1538 /* MC_CMD_GET_VERSION_IN msgrequest */ 1539 #define MC_CMD_GET_VERSION_IN_LEN 0 1540 1541 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1542 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1543 /* placeholder, set to 0 */ 1544 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1545 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4 1546 1547 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1548 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1549 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1550 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 1551 /* enum: Reserved version number to indicate "any" version. */ 1552 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1553 /* enum: Bootrom version value for Siena. */ 1554 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1555 /* enum: Bootrom version value for Huntington. */ 1556 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1557 /* enum: Bootrom version value for Medford2. */ 1558 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002 1559 1560 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1561 #define MC_CMD_GET_VERSION_OUT_LEN 32 1562 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1563 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1564 /* Enum values, see field(s): */ 1565 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1566 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1567 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4 1568 /* 128bit mask of functions supported by the current firmware */ 1569 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1570 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1571 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1572 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1573 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1574 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1575 1576 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1577 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1578 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1579 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1580 /* Enum values, see field(s): */ 1581 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1582 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1583 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4 1584 /* 128bit mask of functions supported by the current firmware */ 1585 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1586 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1587 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1588 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1589 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1590 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1591 /* extra info */ 1592 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1593 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1594 1595 /* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version 1596 * information for all adapter components. For Riverhead based designs, base MC 1597 * firmware version fields refer to NMC firmware, while CMC firmware data is in 1598 * dedicated CMC fields. Flags indicate which data is present in the response 1599 * (depending on which components exist on a particular adapter) 1600 */ 1601 #define MC_CMD_GET_VERSION_V2_OUT_LEN 304 1602 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1603 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1604 /* Enum values, see field(s): */ 1605 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1606 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4 1607 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4 1608 /* 128bit mask of functions supported by the current firmware */ 1609 #define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8 1610 #define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16 1611 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24 1612 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8 1613 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24 1614 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28 1615 /* extra info */ 1616 #define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32 1617 #define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16 1618 /* Flags indicating which extended fields are valid */ 1619 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48 1620 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4 1621 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48 1622 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0 1623 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1 1624 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48 1625 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1 1626 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1 1627 #define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48 1628 #define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2 1629 #define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1 1630 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48 1631 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3 1632 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1 1633 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48 1634 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4 1635 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1 1636 /* MC firmware unique build ID (as binary SHA-1 value) */ 1637 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52 1638 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20 1639 /* MC firmware security level */ 1640 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72 1641 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4 1642 /* MC firmware build name (as null-terminated US-ASCII string) */ 1643 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76 1644 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64 1645 /* The SUC firmware version as four numbers - a.b.c.d */ 1646 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140 1647 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4 1648 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4 1649 /* SUC firmware build date (as 64-bit Unix timestamp) */ 1650 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156 1651 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8 1652 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156 1653 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160 1654 /* The ID of the SUC chip. This is specific to the platform but typically 1655 * indicates family, memory sizes etc. See SF-116728-SW for further details. 1656 */ 1657 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164 1658 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4 1659 /* The CMC firmware version as four numbers - a.b.c.d */ 1660 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168 1661 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4 1662 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4 1663 /* CMC firmware build date (as 64-bit Unix timestamp) */ 1664 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184 1665 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8 1666 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184 1667 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188 1668 /* FPGA version as three numbers. On Riverhead based systems this field uses 1669 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG): 1670 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1 1671 * => B, ...) FPGA_VERSION[2]: Sub-revision number 1672 */ 1673 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192 1674 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4 1675 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3 1676 /* Extra FPGA revision information (as null-terminated US-ASCII string) */ 1677 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204 1678 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16 1679 /* Board name / adapter model (as null-terminated US-ASCII string) */ 1680 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220 1681 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16 1682 /* Board revision number */ 1683 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236 1684 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4 1685 /* Board serial number (as null-terminated US-ASCII string) */ 1686 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240 1687 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64 1688 1689 1690 /***********************************/ 1691 /* MC_CMD_PTP 1692 * Perform PTP operation 1693 */ 1694 #define MC_CMD_PTP 0xb 1695 #undef MC_CMD_0xb_PRIVILEGE_CTG 1696 1697 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1698 1699 /* MC_CMD_PTP_IN msgrequest */ 1700 #define MC_CMD_PTP_IN_LEN 1 1701 /* PTP operation code */ 1702 #define MC_CMD_PTP_IN_OP_OFST 0 1703 #define MC_CMD_PTP_IN_OP_LEN 1 1704 /* enum: Enable PTP packet timestamping operation. */ 1705 #define MC_CMD_PTP_OP_ENABLE 0x1 1706 /* enum: Disable PTP packet timestamping operation. */ 1707 #define MC_CMD_PTP_OP_DISABLE 0x2 1708 /* enum: Send a PTP packet. This operation is used on Siena and Huntington. 1709 * From Medford onwards it is not supported: on those platforms PTP transmit 1710 * timestamping is done using the fast path. 1711 */ 1712 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1713 /* enum: Read the current NIC time. */ 1714 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1715 /* enum: Get the current PTP status. Note that the clock frequency returned (in 1716 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666). 1717 */ 1718 #define MC_CMD_PTP_OP_STATUS 0x5 1719 /* enum: Adjust the PTP NIC's time. */ 1720 #define MC_CMD_PTP_OP_ADJUST 0x6 1721 /* enum: Synchronize host and NIC time. */ 1722 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1723 /* enum: Basic manufacturing tests. Siena PTP adapters only. */ 1724 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1725 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */ 1726 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1727 /* enum: Reset some of the PTP related statistics */ 1728 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1729 /* enum: Debug operations to MC. */ 1730 #define MC_CMD_PTP_OP_DEBUG 0xb 1731 /* enum: Read an FPGA register. Siena PTP adapters only. */ 1732 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1733 /* enum: Write an FPGA register. Siena PTP adapters only. */ 1734 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1735 /* enum: Apply an offset to the NIC clock */ 1736 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1737 /* enum: Change the frequency correction applied to the NIC clock */ 1738 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1739 /* enum: Set the MC packet filter VLAN tags for received PTP packets. 1740 * Deprecated for Huntington onwards. 1741 */ 1742 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1743 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for 1744 * Huntington onwards. 1745 */ 1746 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1747 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated 1748 * for Huntington onwards. 1749 */ 1750 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1751 /* enum: Set the clock source. Required for snapper tests on Huntington and 1752 * Medford. Not implemented for Siena or Medford2. 1753 */ 1754 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1755 /* enum: Reset value of Timer Reg. Not implemented. */ 1756 #define MC_CMD_PTP_OP_RST_CLK 0x14 1757 /* enum: Enable the forwarding of PPS events to the host */ 1758 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1759 /* enum: Get the time format used by this NIC for PTP operations */ 1760 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1761 /* enum: Get the clock attributes. NOTE- extended version of 1762 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1763 */ 1764 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1765 /* enum: Get corrections that should be applied to the various different 1766 * timestamps 1767 */ 1768 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1769 /* enum: Subscribe to receive periodic time events indicating the current NIC 1770 * time 1771 */ 1772 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1773 /* enum: Unsubscribe to stop receiving time events */ 1774 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1775 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1776 * input on the same NIC. Siena PTP adapters only. 1777 */ 1778 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1779 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1780 * subscribers. 1781 */ 1782 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1783 /* enum: Above this for future use. */ 1784 #define MC_CMD_PTP_OP_MAX 0x1c 1785 1786 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1787 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1788 #define MC_CMD_PTP_IN_CMD_OFST 0 1789 #define MC_CMD_PTP_IN_CMD_LEN 4 1790 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1791 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 1792 /* Not used. Events are always sent to function relative queue 0. */ 1793 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1794 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 1795 /* PTP timestamping mode. Not used from Huntington onwards. */ 1796 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1797 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 1798 /* enum: PTP, version 1 */ 1799 #define MC_CMD_PTP_MODE_V1 0x0 1800 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1801 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1802 /* enum: PTP, version 2 */ 1803 #define MC_CMD_PTP_MODE_V2 0x2 1804 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1805 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1806 /* enum: PTP, version 2, with improved UUID filtering */ 1807 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1808 /* enum: FCoE (seconds and microseconds) */ 1809 #define MC_CMD_PTP_MODE_FCOE 0x5 1810 1811 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1812 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1813 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1814 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1815 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1816 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1817 1818 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1819 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1820 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1821 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020 1822 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1823 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1) 1824 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1825 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1826 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1827 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1828 /* Transmit packet length */ 1829 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1830 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4 1831 /* Transmit packet data */ 1832 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1833 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1834 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1835 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1836 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008 1837 1838 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1839 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1840 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1841 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1842 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1843 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1844 1845 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */ 1846 #define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8 1847 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1848 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1849 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1850 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1851 1852 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1853 #define MC_CMD_PTP_IN_STATUS_LEN 8 1854 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1855 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1856 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1857 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1858 1859 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1860 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1861 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1862 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1863 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1864 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1865 /* Frequency adjustment 40 bit fixed point ns */ 1866 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1867 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1868 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1869 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1870 /* enum: Number of fractional bits in frequency adjustment */ 1871 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1872 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1873 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1874 * field. 1875 */ 1876 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c 1877 /* Time adjustment in seconds */ 1878 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1879 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4 1880 /* Time adjustment major value */ 1881 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1882 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4 1883 /* Time adjustment in nanoseconds */ 1884 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1885 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4 1886 /* Time adjustment minor value */ 1887 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1888 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4 1889 1890 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */ 1891 #define MC_CMD_PTP_IN_ADJUST_V2_LEN 28 1892 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1893 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1894 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1895 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1896 /* Frequency adjustment 40 bit fixed point ns */ 1897 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8 1898 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8 1899 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8 1900 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12 1901 /* enum: Number of fractional bits in frequency adjustment */ 1902 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1903 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1904 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1905 * field. 1906 */ 1907 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */ 1908 /* Time adjustment in seconds */ 1909 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16 1910 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4 1911 /* Time adjustment major value */ 1912 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16 1913 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4 1914 /* Time adjustment in nanoseconds */ 1915 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20 1916 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4 1917 /* Time adjustment minor value */ 1918 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20 1919 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4 1920 /* Upper 32bits of major time offset adjustment */ 1921 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24 1922 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4 1923 1924 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1925 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1926 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1927 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1928 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1929 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1930 /* Number of time readings to capture */ 1931 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1932 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4 1933 /* Host address in which to write "synchronization started" indication (64 1934 * bits) 1935 */ 1936 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1937 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1938 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1939 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1940 1941 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1942 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1943 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1944 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1945 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1946 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1947 1948 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1949 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1950 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1951 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1952 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1953 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1954 /* Enable or disable packet testing */ 1955 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1956 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4 1957 1958 /* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */ 1959 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1960 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1961 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1962 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1963 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1964 1965 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1966 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1967 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1968 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1969 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1970 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1971 /* Debug operations */ 1972 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1973 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4 1974 1975 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1976 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1977 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1978 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1979 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1980 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1981 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1982 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4 1983 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1984 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4 1985 1986 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1987 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1988 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1989 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020 1990 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1991 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1) 1992 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1993 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1994 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1995 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1996 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1997 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4 1998 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1999 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 2000 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 2001 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 2002 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008 2003 2004 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 2005 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 2006 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2007 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2008 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2009 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2010 /* Time adjustment in seconds */ 2011 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 2012 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4 2013 /* Time adjustment major value */ 2014 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 2015 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4 2016 /* Time adjustment in nanoseconds */ 2017 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 2018 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4 2019 /* Time adjustment minor value */ 2020 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 2021 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4 2022 2023 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */ 2024 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20 2025 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2026 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2027 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2028 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2029 /* Time adjustment in seconds */ 2030 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8 2031 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4 2032 /* Time adjustment major value */ 2033 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8 2034 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4 2035 /* Time adjustment in nanoseconds */ 2036 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12 2037 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4 2038 /* Time adjustment minor value */ 2039 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12 2040 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4 2041 /* Upper 32bits of major time offset adjustment */ 2042 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16 2043 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4 2044 2045 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 2046 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 2047 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2048 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2049 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2050 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2051 /* Frequency adjustment 40 bit fixed point ns */ 2052 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 2053 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 2054 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 2055 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 2056 /* Enum values, see field(s): */ 2057 /* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */ 2058 2059 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 2060 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 2061 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2062 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2063 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2064 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2065 /* Number of VLAN tags, 0 if not VLAN */ 2066 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 2067 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4 2068 /* Set of VLAN tags to filter against */ 2069 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 2070 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 2071 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 2072 2073 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 2074 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 2075 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2076 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2077 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2078 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2079 /* 1 to enable UUID filtering, 0 to disable */ 2080 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 2081 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4 2082 /* UUID to filter against */ 2083 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 2084 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 2085 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 2086 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 2087 2088 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 2089 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 2090 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2091 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2092 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2093 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2094 /* 1 to enable Domain filtering, 0 to disable */ 2095 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 2096 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4 2097 /* Domain number to filter against */ 2098 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 2099 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4 2100 2101 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 2102 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 2103 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2104 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2105 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2106 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2107 /* Set the clock source. */ 2108 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 2109 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4 2110 /* enum: Internal. */ 2111 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 2112 /* enum: External. */ 2113 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 2114 2115 /* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */ 2116 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 2117 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2118 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2119 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2120 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2121 2122 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 2123 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 2124 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2125 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2126 /* Enable or disable */ 2127 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 2128 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4 2129 /* enum: Enable */ 2130 #define MC_CMD_PTP_ENABLE_PPS 0x0 2131 /* enum: Disable */ 2132 #define MC_CMD_PTP_DISABLE_PPS 0x1 2133 /* Not used. Events are always sent to function relative queue 0. */ 2134 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 2135 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4 2136 2137 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 2138 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 2139 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2140 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2141 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2142 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2143 2144 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 2145 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 2146 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2147 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2148 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2149 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2150 2151 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 2152 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 2153 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2154 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2155 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2156 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2157 2158 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 2159 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 2160 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2161 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2162 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2163 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2164 /* Original field containing queue ID. Now extended to include flags. */ 2165 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 2166 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4 2167 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8 2168 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 2169 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 2170 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8 2171 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 2172 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 2173 2174 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 2175 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 2176 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2177 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2178 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2179 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2180 /* Unsubscribe options */ 2181 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 2182 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4 2183 /* enum: Unsubscribe a single queue */ 2184 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 2185 /* enum: Unsubscribe all queues */ 2186 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 2187 /* Event queue ID */ 2188 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 2189 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 2190 2191 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 2192 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 2193 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2194 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2195 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2196 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2197 /* 1 to enable PPS test mode, 0 to disable and return result. */ 2198 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 2199 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4 2200 2201 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 2202 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 2203 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 2204 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 2205 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 2206 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 2207 /* NIC - Host System Clock Synchronization status */ 2208 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 2209 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 2210 /* enum: Host System clock and NIC clock are not in sync */ 2211 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 2212 /* enum: Host System clock and NIC clock are synchronized */ 2213 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 2214 /* If synchronized, number of seconds until clocks should be considered to be 2215 * no longer in sync. 2216 */ 2217 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 2218 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 2219 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 2220 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 2221 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 2222 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 2223 2224 /* MC_CMD_PTP_OUT msgresponse */ 2225 #define MC_CMD_PTP_OUT_LEN 0 2226 2227 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 2228 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 2229 /* Value of seconds timestamp */ 2230 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 2231 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4 2232 /* Timestamp major value */ 2233 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 2234 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4 2235 /* Value of nanoseconds timestamp */ 2236 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 2237 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4 2238 /* Timestamp minor value */ 2239 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 2240 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4 2241 2242 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 2243 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 2244 2245 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 2246 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 2247 2248 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 2249 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 2250 /* Value of seconds timestamp */ 2251 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 2252 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 2253 /* Timestamp major value */ 2254 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 2255 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 2256 /* Value of nanoseconds timestamp */ 2257 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 2258 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 2259 /* Timestamp minor value */ 2260 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 2261 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4 2262 2263 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ 2264 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 2265 /* Value of seconds timestamp */ 2266 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 2267 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 2268 /* Timestamp major value */ 2269 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 2270 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 2271 /* Value of nanoseconds timestamp */ 2272 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 2273 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 2274 /* Timestamp minor value */ 2275 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 2276 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 2277 /* Upper 32bits of major timestamp value */ 2278 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 2279 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4 2280 2281 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 2282 #define MC_CMD_PTP_OUT_STATUS_LEN 64 2283 /* Frequency of NIC's hardware clock */ 2284 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 2285 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 2286 /* Number of packets transmitted and timestamped */ 2287 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 2288 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 2289 /* Number of packets received and timestamped */ 2290 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 2291 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 2292 /* Number of packets timestamped by the FPGA */ 2293 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 2294 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 2295 /* Number of packets filter matched */ 2296 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 2297 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 2298 /* Number of packets not filter matched */ 2299 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 2300 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 2301 /* Number of PPS overflows (noise on input?) */ 2302 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 2303 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 2304 /* Number of PPS bad periods */ 2305 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 2306 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 2307 /* Minimum period of PPS pulse in nanoseconds */ 2308 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 2309 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 2310 /* Maximum period of PPS pulse in nanoseconds */ 2311 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 2312 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 2313 /* Last period of PPS pulse in nanoseconds */ 2314 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 2315 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 2316 /* Mean period of PPS pulse in nanoseconds */ 2317 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 2318 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 2319 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 2320 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 2321 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 2322 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 2323 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 2324 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 2325 /* Last offset of PPS pulse in nanoseconds (signed) */ 2326 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 2327 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 2328 /* Mean offset of PPS pulse in nanoseconds (signed) */ 2329 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 2330 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4 2331 2332 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 2333 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 2334 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 2335 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020 2336 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 2337 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20) 2338 /* A set of host and NIC times */ 2339 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 2340 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 2341 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 2342 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 2343 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51 2344 /* Host time immediately before NIC's hardware clock read */ 2345 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 2346 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 2347 /* Value of seconds timestamp */ 2348 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 2349 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 2350 /* Timestamp major value */ 2351 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 2352 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 2353 /* Value of nanoseconds timestamp */ 2354 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 2355 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 2356 /* Timestamp minor value */ 2357 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 2358 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 2359 /* Host time immediately after NIC's hardware clock read */ 2360 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 2361 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 2362 /* Number of nanoseconds waited after reading NIC's hardware clock */ 2363 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 2364 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4 2365 2366 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 2367 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 2368 /* Results of testing */ 2369 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 2370 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 2371 /* enum: Successful test */ 2372 #define MC_CMD_PTP_MANF_SUCCESS 0x0 2373 /* enum: FPGA load failed */ 2374 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 2375 /* enum: FPGA version invalid */ 2376 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 2377 /* enum: FPGA registers incorrect */ 2378 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 2379 /* enum: Oscillator possibly not working? */ 2380 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 2381 /* enum: Timestamps not increasing */ 2382 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 2383 /* enum: Mismatched packet count */ 2384 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 2385 /* enum: Mismatched packet count (Siena filter and FPGA) */ 2386 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 2387 /* enum: Not enough packets to perform timestamp check */ 2388 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 2389 /* enum: Timestamp trigger GPIO not working */ 2390 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 2391 /* enum: Insufficient PPS events to perform checks */ 2392 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 2393 /* enum: PPS time event period not sufficiently close to 1s. */ 2394 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 2395 /* enum: PPS time event nS reading not sufficiently close to zero. */ 2396 #define MC_CMD_PTP_MANF_PPS_NS 0xc 2397 /* enum: PTP peripheral registers incorrect */ 2398 #define MC_CMD_PTP_MANF_REGISTERS 0xd 2399 /* enum: Failed to read time from PTP peripheral */ 2400 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 2401 /* Presence of external oscillator */ 2402 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 2403 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4 2404 2405 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 2406 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 2407 /* Results of testing */ 2408 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 2409 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 2410 /* Number of packets received by FPGA */ 2411 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 2412 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 2413 /* Number of packets received by Siena filters */ 2414 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 2415 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4 2416 2417 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 2418 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 2419 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 2420 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020 2421 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 2422 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1) 2423 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 2424 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 2425 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 2426 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 2427 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020 2428 2429 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 2430 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 2431 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2432 * operations that pass times between the host and firmware. If this operation 2433 * is not supported (older firmware) a format of seconds and nanoseconds should 2434 * be assumed. Note this enum is deprecated. Do not add to it- use the 2435 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead. 2436 */ 2437 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 2438 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 2439 /* enum: Times are in seconds and nanoseconds */ 2440 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 2441 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2442 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 2443 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2444 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 2445 2446 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 2447 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 2448 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2449 * operations that pass times between the host and firmware. If this operation 2450 * is not supported (older firmware) a format of seconds and nanoseconds should 2451 * be assumed. 2452 */ 2453 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 2454 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 2455 /* enum: Times are in seconds and nanoseconds */ 2456 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 2457 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2458 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 2459 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2460 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 2461 /* enum: Major register units are seconds, minor units are quarter nanoseconds 2462 */ 2463 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 2464 /* Minimum acceptable value for a corrected synchronization timeset. When 2465 * comparing host and NIC clock times, the MC returns a set of samples that 2466 * contain the host start and end time, the MC time when the host start was 2467 * detected and the time the MC waited between reading the time and detecting 2468 * the host end. The corrected sync window is the difference between the host 2469 * end and start times minus the time that the MC waited for host end. 2470 */ 2471 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 2472 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 2473 /* Various PTP capabilities */ 2474 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 2475 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 2476 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8 2477 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 2478 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 2479 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8 2480 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 2481 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 2482 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8 2483 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 2484 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 2485 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8 2486 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 2487 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 2488 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 2489 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 2490 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 2491 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 2492 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 2493 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4 2494 2495 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 2496 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 2497 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2498 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 2499 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 2500 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2501 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 2502 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 2503 /* Uncorrected error on PPS output in NIC clock format */ 2504 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 2505 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 2506 /* Uncorrected error on PPS input in NIC clock format */ 2507 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 2508 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4 2509 2510 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 2511 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 2512 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2513 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 2514 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 2515 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2516 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 2517 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 2518 /* Uncorrected error on PPS output in NIC clock format */ 2519 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 2520 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 2521 /* Uncorrected error on PPS input in NIC clock format */ 2522 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 2523 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 2524 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 2525 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 2526 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 2527 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 2528 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 2529 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4 2530 2531 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 2532 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 2533 /* Results of testing */ 2534 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 2535 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4 2536 /* Enum values, see field(s): */ 2537 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 2538 2539 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 2540 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 2541 2542 2543 /***********************************/ 2544 /* MC_CMD_CSR_READ32 2545 * Read 32bit words from the indirect memory map. 2546 */ 2547 #define MC_CMD_CSR_READ32 0xc 2548 #undef MC_CMD_0xc_PRIVILEGE_CTG 2549 2550 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2551 2552 /* MC_CMD_CSR_READ32_IN msgrequest */ 2553 #define MC_CMD_CSR_READ32_IN_LEN 12 2554 /* Address */ 2555 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 2556 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 2557 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 2558 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4 2559 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 2560 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 2561 2562 /* MC_CMD_CSR_READ32_OUT msgresponse */ 2563 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 2564 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 2565 #define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020 2566 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 2567 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4) 2568 /* The last dword is the status, not a value read */ 2569 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 2570 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 2571 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 2572 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 2573 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255 2574 2575 2576 /***********************************/ 2577 /* MC_CMD_CSR_WRITE32 2578 * Write 32bit dwords to the indirect memory map. 2579 */ 2580 #define MC_CMD_CSR_WRITE32 0xd 2581 #undef MC_CMD_0xd_PRIVILEGE_CTG 2582 2583 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2584 2585 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 2586 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 2587 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 2588 #define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020 2589 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 2590 #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4) 2591 /* Address */ 2592 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 2593 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 2594 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 2595 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 2596 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 2597 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 2598 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 2599 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 2600 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253 2601 2602 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 2603 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 2604 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 2605 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 2606 2607 2608 /***********************************/ 2609 /* MC_CMD_HP 2610 * These commands are used for HP related features. They are grouped under one 2611 * MCDI command to avoid creating too many MCDI commands. 2612 */ 2613 #define MC_CMD_HP 0x54 2614 #undef MC_CMD_0x54_PRIVILEGE_CTG 2615 2616 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2617 2618 /* MC_CMD_HP_IN msgrequest */ 2619 #define MC_CMD_HP_IN_LEN 16 2620 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 2621 * the specified address with the specified interval.When address is NULL, 2622 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 2623 * state / 2: (debug) Show temperature reported by one of the supported 2624 * sensors. 2625 */ 2626 #define MC_CMD_HP_IN_SUBCMD_OFST 0 2627 #define MC_CMD_HP_IN_SUBCMD_LEN 4 2628 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 2629 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 2630 /* enum: Last known valid HP sub-command. */ 2631 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 2632 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 2633 */ 2634 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 2635 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 2636 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 2637 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 2638 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 2639 * NULL.) 2640 */ 2641 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 2642 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 2643 2644 /* MC_CMD_HP_OUT msgresponse */ 2645 #define MC_CMD_HP_OUT_LEN 4 2646 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 2647 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 2648 /* enum: OCSD stopped for this card. */ 2649 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 2650 /* enum: OCSD was successfully started with the address provided. */ 2651 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 2652 /* enum: OCSD was already started for this card. */ 2653 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 2654 2655 2656 /***********************************/ 2657 /* MC_CMD_STACKINFO 2658 * Get stack information. 2659 */ 2660 #define MC_CMD_STACKINFO 0xf 2661 #undef MC_CMD_0xf_PRIVILEGE_CTG 2662 2663 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2664 2665 /* MC_CMD_STACKINFO_IN msgrequest */ 2666 #define MC_CMD_STACKINFO_IN_LEN 0 2667 2668 /* MC_CMD_STACKINFO_OUT msgresponse */ 2669 #define MC_CMD_STACKINFO_OUT_LENMIN 12 2670 #define MC_CMD_STACKINFO_OUT_LENMAX 252 2671 #define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020 2672 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 2673 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12) 2674 /* (thread ptr, stack size, free space) for each thread in system */ 2675 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 2676 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 2677 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 2678 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 2679 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85 2680 2681 2682 /***********************************/ 2683 /* MC_CMD_MDIO_READ 2684 * MDIO register read. 2685 */ 2686 #define MC_CMD_MDIO_READ 0x10 2687 #undef MC_CMD_0x10_PRIVILEGE_CTG 2688 2689 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2690 2691 /* MC_CMD_MDIO_READ_IN msgrequest */ 2692 #define MC_CMD_MDIO_READ_IN_LEN 16 2693 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2694 * external devices. 2695 */ 2696 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 2697 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 2698 /* enum: Internal. */ 2699 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 2700 /* enum: External. */ 2701 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 2702 /* Port address */ 2703 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 2704 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 2705 /* Device Address or clause 22. */ 2706 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 2707 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 2708 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2709 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2710 */ 2711 #define MC_CMD_MDIO_CLAUSE22 0x20 2712 /* Address */ 2713 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 2714 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 2715 2716 /* MC_CMD_MDIO_READ_OUT msgresponse */ 2717 #define MC_CMD_MDIO_READ_OUT_LEN 8 2718 /* Value */ 2719 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 2720 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 2721 /* Status the MDIO commands return the raw status bits from the MDIO block. A 2722 * "good" transaction should have the DONE bit set and all other bits clear. 2723 */ 2724 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 2725 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 2726 /* enum: Good. */ 2727 #define MC_CMD_MDIO_STATUS_GOOD 0x8 2728 2729 2730 /***********************************/ 2731 /* MC_CMD_MDIO_WRITE 2732 * MDIO register write. 2733 */ 2734 #define MC_CMD_MDIO_WRITE 0x11 2735 #undef MC_CMD_0x11_PRIVILEGE_CTG 2736 2737 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2738 2739 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 2740 #define MC_CMD_MDIO_WRITE_IN_LEN 20 2741 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2742 * external devices. 2743 */ 2744 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 2745 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 2746 /* enum: Internal. */ 2747 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 2748 /* enum: External. */ 2749 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 2750 /* Port address */ 2751 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 2752 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 2753 /* Device Address or clause 22. */ 2754 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 2755 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 2756 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2757 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2758 */ 2759 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 2760 /* Address */ 2761 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 2762 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 2763 /* Value */ 2764 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 2765 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 2766 2767 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 2768 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 2769 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 2770 * "good" transaction should have the DONE bit set and all other bits clear. 2771 */ 2772 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 2773 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 2774 /* enum: Good. */ 2775 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 2776 2777 2778 /***********************************/ 2779 /* MC_CMD_DBI_WRITE 2780 * Write DBI register(s). 2781 */ 2782 #define MC_CMD_DBI_WRITE 0x12 2783 #undef MC_CMD_0x12_PRIVILEGE_CTG 2784 2785 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2786 2787 /* MC_CMD_DBI_WRITE_IN msgrequest */ 2788 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 2789 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 2790 #define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020 2791 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 2792 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12) 2793 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 2794 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 2795 */ 2796 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 2797 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 2798 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 2799 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 2800 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85 2801 2802 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 2803 #define MC_CMD_DBI_WRITE_OUT_LEN 0 2804 2805 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 2806 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 2807 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 2808 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 2809 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 2810 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 2811 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 2812 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 2813 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4 2814 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 2815 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 2816 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4 2817 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 2818 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 2819 #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4 2820 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 2821 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 2822 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 2823 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 2824 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 2825 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 2826 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 2827 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 2828 2829 2830 /***********************************/ 2831 /* MC_CMD_PORT_READ32 2832 * Read a 32-bit register from the indirect port register map. The port to 2833 * access is implied by the Shared memory channel used. 2834 */ 2835 #define MC_CMD_PORT_READ32 0x14 2836 2837 /* MC_CMD_PORT_READ32_IN msgrequest */ 2838 #define MC_CMD_PORT_READ32_IN_LEN 4 2839 /* Address */ 2840 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 2841 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 2842 2843 /* MC_CMD_PORT_READ32_OUT msgresponse */ 2844 #define MC_CMD_PORT_READ32_OUT_LEN 8 2845 /* Value */ 2846 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 2847 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 2848 /* Status */ 2849 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 2850 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 2851 2852 2853 /***********************************/ 2854 /* MC_CMD_PORT_WRITE32 2855 * Write a 32-bit register to the indirect port register map. The port to 2856 * access is implied by the Shared memory channel used. 2857 */ 2858 #define MC_CMD_PORT_WRITE32 0x15 2859 2860 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 2861 #define MC_CMD_PORT_WRITE32_IN_LEN 8 2862 /* Address */ 2863 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 2864 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 2865 /* Value */ 2866 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 2867 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 2868 2869 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 2870 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 2871 /* Status */ 2872 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 2873 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 2874 2875 2876 /***********************************/ 2877 /* MC_CMD_PORT_READ128 2878 * Read a 128-bit register from the indirect port register map. The port to 2879 * access is implied by the Shared memory channel used. 2880 */ 2881 #define MC_CMD_PORT_READ128 0x16 2882 2883 /* MC_CMD_PORT_READ128_IN msgrequest */ 2884 #define MC_CMD_PORT_READ128_IN_LEN 4 2885 /* Address */ 2886 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2887 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 2888 2889 /* MC_CMD_PORT_READ128_OUT msgresponse */ 2890 #define MC_CMD_PORT_READ128_OUT_LEN 20 2891 /* Value */ 2892 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2893 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2894 /* Status */ 2895 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2896 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 2897 2898 2899 /***********************************/ 2900 /* MC_CMD_PORT_WRITE128 2901 * Write a 128-bit register to the indirect port register map. The port to 2902 * access is implied by the Shared memory channel used. 2903 */ 2904 #define MC_CMD_PORT_WRITE128 0x17 2905 2906 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2907 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2908 /* Address */ 2909 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2910 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 2911 /* Value */ 2912 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2913 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2914 2915 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2916 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2917 /* Status */ 2918 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2919 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 2920 2921 /* MC_CMD_CAPABILITIES structuredef */ 2922 #define MC_CMD_CAPABILITIES_LEN 4 2923 /* Small buf table. */ 2924 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2925 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2926 /* Turbo mode (for Maranello). */ 2927 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2928 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2929 /* Turbo mode active (for Maranello). */ 2930 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2931 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2932 /* PTP offload. */ 2933 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2934 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2935 /* AOE mode. */ 2936 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2937 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2938 /* AOE mode active. */ 2939 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2940 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2941 /* AOE mode active. */ 2942 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2943 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2944 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2945 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2946 2947 2948 /***********************************/ 2949 /* MC_CMD_GET_BOARD_CFG 2950 * Returns the MC firmware configuration structure. 2951 */ 2952 #define MC_CMD_GET_BOARD_CFG 0x18 2953 #undef MC_CMD_0x18_PRIVILEGE_CTG 2954 2955 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2956 2957 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2958 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2959 2960 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2961 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2962 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2963 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136 2964 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2965 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2) 2966 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2967 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 2968 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2969 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2970 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on 2971 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2972 */ 2973 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2974 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 2975 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on 2976 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2977 */ 2978 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2979 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 2980 /* Base MAC address for Siena Port0. Unused on EF10 and later (use 2981 * MC_CMD_GET_MAC_ADDRESSES). 2982 */ 2983 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2984 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2985 /* Base MAC address for Siena Port1. Unused on EF10 and later (use 2986 * MC_CMD_GET_MAC_ADDRESSES). 2987 */ 2988 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2989 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2990 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use 2991 * MC_CMD_GET_MAC_ADDRESSES). 2992 */ 2993 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2994 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 2995 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use 2996 * MC_CMD_GET_MAC_ADDRESSES). 2997 */ 2998 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2999 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 3000 /* Increment between addresses in MAC address pool for Siena Port0. Unused on 3001 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 3002 */ 3003 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 3004 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 3005 /* Increment between addresses in MAC address pool for Siena Port1. Unused on 3006 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 3007 */ 3008 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 3009 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 3010 /* Siena only. This field contains a 16-bit value for each of the types of 3011 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a 3012 * specific board type, but otherwise have no meaning to the MC; they are used 3013 * by the driver to manage selection of appropriate firmware updates. Unused on 3014 * EF10 and later (use MC_CMD_NVRAM_METADATA). 3015 */ 3016 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 3017 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 3018 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 3019 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 3020 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32 3021 3022 3023 /***********************************/ 3024 /* MC_CMD_DBI_READX 3025 * Read DBI register(s) -- extended functionality 3026 */ 3027 #define MC_CMD_DBI_READX 0x19 3028 #undef MC_CMD_0x19_PRIVILEGE_CTG 3029 3030 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3031 3032 /* MC_CMD_DBI_READX_IN msgrequest */ 3033 #define MC_CMD_DBI_READX_IN_LENMIN 8 3034 #define MC_CMD_DBI_READX_IN_LENMAX 248 3035 #define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016 3036 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 3037 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8) 3038 /* Each Read op consists of an address (offset 0), VF/CS2) */ 3039 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 3040 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 3041 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 3042 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 3043 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 3044 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 3045 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127 3046 3047 /* MC_CMD_DBI_READX_OUT msgresponse */ 3048 #define MC_CMD_DBI_READX_OUT_LENMIN 4 3049 #define MC_CMD_DBI_READX_OUT_LENMAX 252 3050 #define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020 3051 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 3052 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4) 3053 /* Value */ 3054 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 3055 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 3056 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 3057 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 3058 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255 3059 3060 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 3061 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 3062 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 3063 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 3064 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 3065 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 3066 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 3067 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 3068 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4 3069 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 3070 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 3071 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4 3072 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 3073 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 3074 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4 3075 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 3076 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 3077 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 3078 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 3079 3080 3081 /***********************************/ 3082 /* MC_CMD_SET_RAND_SEED 3083 * Set the 16byte seed for the MC pseudo-random generator. 3084 */ 3085 #define MC_CMD_SET_RAND_SEED 0x1a 3086 #undef MC_CMD_0x1a_PRIVILEGE_CTG 3087 3088 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3089 3090 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 3091 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 3092 /* Seed value. */ 3093 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 3094 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 3095 3096 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 3097 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 3098 3099 3100 /***********************************/ 3101 /* MC_CMD_LTSSM_HIST 3102 * Retrieve the history of the LTSSM, if the build supports it. 3103 */ 3104 #define MC_CMD_LTSSM_HIST 0x1b 3105 3106 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 3107 #define MC_CMD_LTSSM_HIST_IN_LEN 0 3108 3109 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 3110 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 3111 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 3112 #define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020 3113 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 3114 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4) 3115 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 3116 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 3117 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 3118 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 3119 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 3120 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255 3121 3122 3123 /***********************************/ 3124 /* MC_CMD_DRV_ATTACH 3125 * Inform MCPU that this port is managed on the host (i.e. driver active). For 3126 * Huntington, also request the preferred datapath firmware to use if possible 3127 * (it may not be possible for this request to be fulfilled; the driver must 3128 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 3129 * features are actually available). The FIRMWARE_ID field is ignored by older 3130 * platforms. 3131 */ 3132 #define MC_CMD_DRV_ATTACH 0x1c 3133 #undef MC_CMD_0x1c_PRIVILEGE_CTG 3134 3135 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3136 3137 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 3138 #define MC_CMD_DRV_ATTACH_IN_LEN 12 3139 /* new state to set if UPDATE=1 */ 3140 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 3141 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 3142 #define MC_CMD_DRV_ATTACH_OFST 0 3143 #define MC_CMD_DRV_ATTACH_LBN 0 3144 #define MC_CMD_DRV_ATTACH_WIDTH 1 3145 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0 3146 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0 3147 #define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1 3148 #define MC_CMD_DRV_PREBOOT_OFST 0 3149 #define MC_CMD_DRV_PREBOOT_LBN 1 3150 #define MC_CMD_DRV_PREBOOT_WIDTH 1 3151 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0 3152 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1 3153 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1 3154 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0 3155 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2 3156 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1 3157 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0 3158 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3 3159 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1 3160 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0 3161 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4 3162 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1 3163 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0 3164 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5 3165 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1 3166 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0 3167 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5 3168 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1 3169 /* 1 to set new state, or 0 to just report the existing state */ 3170 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 3171 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 3172 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 3173 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 3174 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 3175 /* enum: Prefer to use full featured firmware */ 3176 #define MC_CMD_FW_FULL_FEATURED 0x0 3177 /* enum: Prefer to use firmware with fewer features but lower latency */ 3178 #define MC_CMD_FW_LOW_LATENCY 0x1 3179 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 3180 #define MC_CMD_FW_PACKED_STREAM 0x2 3181 /* enum: Prefer to use firmware with fewer features and simpler TX event 3182 * batching but higher TX packet rate 3183 */ 3184 #define MC_CMD_FW_HIGH_TX_RATE 0x3 3185 /* enum: Reserved value */ 3186 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 3187 /* enum: Prefer to use firmware with additional "rules engine" filtering 3188 * support 3189 */ 3190 #define MC_CMD_FW_RULES_ENGINE 0x5 3191 /* enum: Prefer to use firmware with additional DPDK support */ 3192 #define MC_CMD_FW_DPDK 0x6 3193 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and 3194 * bug69716) 3195 */ 3196 #define MC_CMD_FW_L3XUDP 0x7 3197 /* enum: Requests that the MC keep whatever datapath firmware is currently 3198 * running. It's used for test purposes, where we want to be able to shmboot 3199 * special test firmware variants. This option is only recognised in eftest 3200 * (i.e. non-production) builds. 3201 */ 3202 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe 3203 /* enum: Only this option is allowed for non-admin functions */ 3204 #define MC_CMD_FW_DONT_CARE 0xffffffff 3205 3206 /* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver 3207 * version 3208 */ 3209 #define MC_CMD_DRV_ATTACH_IN_V2_LEN 32 3210 /* new state to set if UPDATE=1 */ 3211 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0 3212 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4 3213 /* MC_CMD_DRV_ATTACH_OFST 0 */ 3214 /* MC_CMD_DRV_ATTACH_LBN 0 */ 3215 /* MC_CMD_DRV_ATTACH_WIDTH 1 */ 3216 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0 3217 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0 3218 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1 3219 /* MC_CMD_DRV_PREBOOT_OFST 0 */ 3220 /* MC_CMD_DRV_PREBOOT_LBN 1 */ 3221 /* MC_CMD_DRV_PREBOOT_WIDTH 1 */ 3222 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0 3223 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1 3224 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1 3225 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0 3226 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2 3227 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1 3228 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0 3229 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3 3230 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1 3231 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0 3232 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4 3233 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1 3234 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0 3235 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5 3236 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1 3237 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0 3238 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5 3239 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1 3240 /* 1 to set new state, or 0 to just report the existing state */ 3241 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4 3242 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4 3243 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 3244 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8 3245 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4 3246 /* enum: Prefer to use full featured firmware */ 3247 /* MC_CMD_FW_FULL_FEATURED 0x0 */ 3248 /* enum: Prefer to use firmware with fewer features but lower latency */ 3249 /* MC_CMD_FW_LOW_LATENCY 0x1 */ 3250 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 3251 /* MC_CMD_FW_PACKED_STREAM 0x2 */ 3252 /* enum: Prefer to use firmware with fewer features and simpler TX event 3253 * batching but higher TX packet rate 3254 */ 3255 /* MC_CMD_FW_HIGH_TX_RATE 0x3 */ 3256 /* enum: Reserved value */ 3257 /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */ 3258 /* enum: Prefer to use firmware with additional "rules engine" filtering 3259 * support 3260 */ 3261 /* MC_CMD_FW_RULES_ENGINE 0x5 */ 3262 /* enum: Prefer to use firmware with additional DPDK support */ 3263 /* MC_CMD_FW_DPDK 0x6 */ 3264 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and 3265 * bug69716) 3266 */ 3267 /* MC_CMD_FW_L3XUDP 0x7 */ 3268 /* enum: Requests that the MC keep whatever datapath firmware is currently 3269 * running. It's used for test purposes, where we want to be able to shmboot 3270 * special test firmware variants. This option is only recognised in eftest 3271 * (i.e. non-production) builds. 3272 */ 3273 /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */ 3274 /* enum: Only this option is allowed for non-admin functions */ 3275 /* MC_CMD_FW_DONT_CARE 0xffffffff */ 3276 /* Version of the driver to be reported by management protocols (e.g. NC-SI) 3277 * handled by the NIC. This is a zero-terminated ASCII string. 3278 */ 3279 #define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12 3280 #define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20 3281 3282 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 3283 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 3284 /* previous or existing state, see the bitmask at NEW_STATE */ 3285 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 3286 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4 3287 3288 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 3289 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 3290 /* previous or existing state, see the bitmask at NEW_STATE */ 3291 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 3292 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 3293 /* Flags associated with this function */ 3294 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 3295 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 3296 /* enum: Labels the lowest-numbered function visible to the OS */ 3297 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 3298 /* enum: The function can control the link state of the physical port it is 3299 * bound to. 3300 */ 3301 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 3302 /* enum: The function can perform privileged operations */ 3303 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 3304 /* enum: The function does not have an active port associated with it. The port 3305 * refers to the Sorrento external FPGA port. 3306 */ 3307 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 3308 /* enum: If set, indicates that VI spreading is currently enabled. Will always 3309 * indicate the current state, regardless of the value in the WANT_VI_SPREADING 3310 * input. 3311 */ 3312 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4 3313 /* enum: Used during development only. Should no longer be used. */ 3314 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5 3315 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered 3316 * TXQs will use one engine, and odd-numbered TXQs will use the other. This 3317 * also has the effect that only even-numbered RXQs will receive traffic. 3318 */ 3319 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5 3320 3321 3322 /***********************************/ 3323 /* MC_CMD_SHMUART 3324 * Route UART output to circular buffer in shared memory instead. 3325 */ 3326 #define MC_CMD_SHMUART 0x1f 3327 3328 /* MC_CMD_SHMUART_IN msgrequest */ 3329 #define MC_CMD_SHMUART_IN_LEN 4 3330 /* ??? */ 3331 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 3332 #define MC_CMD_SHMUART_IN_FLAG_LEN 4 3333 3334 /* MC_CMD_SHMUART_OUT msgresponse */ 3335 #define MC_CMD_SHMUART_OUT_LEN 0 3336 3337 3338 /***********************************/ 3339 /* MC_CMD_PORT_RESET 3340 * Generic per-port reset. There is no equivalent for per-board reset. Locks 3341 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 3342 * use MC_CMD_ENTITY_RESET instead. 3343 */ 3344 #define MC_CMD_PORT_RESET 0x20 3345 #undef MC_CMD_0x20_PRIVILEGE_CTG 3346 3347 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3348 3349 /* MC_CMD_PORT_RESET_IN msgrequest */ 3350 #define MC_CMD_PORT_RESET_IN_LEN 0 3351 3352 /* MC_CMD_PORT_RESET_OUT msgresponse */ 3353 #define MC_CMD_PORT_RESET_OUT_LEN 0 3354 3355 3356 /***********************************/ 3357 /* MC_CMD_ENTITY_RESET 3358 * Generic per-resource reset. There is no equivalent for per-board reset. 3359 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 3360 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 3361 */ 3362 #define MC_CMD_ENTITY_RESET 0x20 3363 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 3364 3365 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 3366 #define MC_CMD_ENTITY_RESET_IN_LEN 4 3367 /* Optional flags field. Omitting this will perform a "legacy" reset action 3368 * (TBD). 3369 */ 3370 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 3371 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4 3372 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0 3373 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 3374 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 3375 3376 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 3377 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 3378 3379 3380 /***********************************/ 3381 /* MC_CMD_PCIE_CREDITS 3382 * Read instantaneous and minimum flow control thresholds. 3383 */ 3384 #define MC_CMD_PCIE_CREDITS 0x21 3385 3386 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 3387 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 3388 /* poll period. 0 is disabled */ 3389 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 3390 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 3391 /* wipe statistics */ 3392 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 3393 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 3394 3395 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 3396 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 3397 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 3398 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 3399 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 3400 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 3401 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 3402 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 3403 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 3404 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 3405 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 3406 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 3407 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 3408 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 3409 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 3410 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 3411 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 3412 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 3413 3414 3415 /***********************************/ 3416 /* MC_CMD_RXD_MONITOR 3417 * Get histogram of RX queue fill level. 3418 */ 3419 #define MC_CMD_RXD_MONITOR 0x22 3420 3421 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 3422 #define MC_CMD_RXD_MONITOR_IN_LEN 12 3423 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 3424 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 3425 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 3426 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 3427 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 3428 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 3429 3430 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 3431 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 3432 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 3433 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 3434 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 3435 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 3436 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 3437 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 3438 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 3439 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 3440 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 3441 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 3442 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 3443 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 3444 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 3445 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 3446 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 3447 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 3448 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 3449 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 3450 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 3451 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 3452 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 3453 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 3454 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 3455 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 3456 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 3457 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 3458 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 3459 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 3460 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 3461 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 3462 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 3463 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 3464 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 3465 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 3466 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 3467 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 3468 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 3469 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 3470 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 3471 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 3472 3473 3474 /***********************************/ 3475 /* MC_CMD_PUTS 3476 * Copy the given ASCII string out onto UART and/or out of the network port. 3477 */ 3478 #define MC_CMD_PUTS 0x23 3479 #undef MC_CMD_0x23_PRIVILEGE_CTG 3480 3481 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE 3482 3483 /* MC_CMD_PUTS_IN msgrequest */ 3484 #define MC_CMD_PUTS_IN_LENMIN 13 3485 #define MC_CMD_PUTS_IN_LENMAX 252 3486 #define MC_CMD_PUTS_IN_LENMAX_MCDI2 1020 3487 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 3488 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1) 3489 #define MC_CMD_PUTS_IN_DEST_OFST 0 3490 #define MC_CMD_PUTS_IN_DEST_LEN 4 3491 #define MC_CMD_PUTS_IN_UART_OFST 0 3492 #define MC_CMD_PUTS_IN_UART_LBN 0 3493 #define MC_CMD_PUTS_IN_UART_WIDTH 1 3494 #define MC_CMD_PUTS_IN_PORT_OFST 0 3495 #define MC_CMD_PUTS_IN_PORT_LBN 1 3496 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 3497 #define MC_CMD_PUTS_IN_DHOST_OFST 4 3498 #define MC_CMD_PUTS_IN_DHOST_LEN 6 3499 #define MC_CMD_PUTS_IN_STRING_OFST 12 3500 #define MC_CMD_PUTS_IN_STRING_LEN 1 3501 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 3502 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 3503 #define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008 3504 3505 /* MC_CMD_PUTS_OUT msgresponse */ 3506 #define MC_CMD_PUTS_OUT_LEN 0 3507 3508 3509 /***********************************/ 3510 /* MC_CMD_GET_PHY_CFG 3511 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 3512 * 'zombie' state. Locks required: None 3513 */ 3514 #define MC_CMD_GET_PHY_CFG 0x24 3515 #undef MC_CMD_0x24_PRIVILEGE_CTG 3516 3517 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3518 3519 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 3520 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 3521 3522 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 3523 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 3524 /* flags */ 3525 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 3526 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4 3527 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0 3528 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 3529 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 3530 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0 3531 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 3532 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 3533 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0 3534 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 3535 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 3536 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0 3537 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 3538 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 3539 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0 3540 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 3541 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 3542 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0 3543 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 3544 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 3545 #define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0 3546 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 3547 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 3548 /* ?? */ 3549 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 3550 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4 3551 /* Bitmask of supported capabilities */ 3552 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 3553 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4 3554 #define MC_CMD_PHY_CAP_10HDX_OFST 8 3555 #define MC_CMD_PHY_CAP_10HDX_LBN 1 3556 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 3557 #define MC_CMD_PHY_CAP_10FDX_OFST 8 3558 #define MC_CMD_PHY_CAP_10FDX_LBN 2 3559 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 3560 #define MC_CMD_PHY_CAP_100HDX_OFST 8 3561 #define MC_CMD_PHY_CAP_100HDX_LBN 3 3562 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 3563 #define MC_CMD_PHY_CAP_100FDX_OFST 8 3564 #define MC_CMD_PHY_CAP_100FDX_LBN 4 3565 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 3566 #define MC_CMD_PHY_CAP_1000HDX_OFST 8 3567 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 3568 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 3569 #define MC_CMD_PHY_CAP_1000FDX_OFST 8 3570 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 3571 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 3572 #define MC_CMD_PHY_CAP_10000FDX_OFST 8 3573 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 3574 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 3575 #define MC_CMD_PHY_CAP_PAUSE_OFST 8 3576 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 3577 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 3578 #define MC_CMD_PHY_CAP_ASYM_OFST 8 3579 #define MC_CMD_PHY_CAP_ASYM_LBN 9 3580 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 3581 #define MC_CMD_PHY_CAP_AN_OFST 8 3582 #define MC_CMD_PHY_CAP_AN_LBN 10 3583 #define MC_CMD_PHY_CAP_AN_WIDTH 1 3584 #define MC_CMD_PHY_CAP_40000FDX_OFST 8 3585 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 3586 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 3587 #define MC_CMD_PHY_CAP_DDM_OFST 8 3588 #define MC_CMD_PHY_CAP_DDM_LBN 12 3589 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 3590 #define MC_CMD_PHY_CAP_100000FDX_OFST 8 3591 #define MC_CMD_PHY_CAP_100000FDX_LBN 13 3592 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1 3593 #define MC_CMD_PHY_CAP_25000FDX_OFST 8 3594 #define MC_CMD_PHY_CAP_25000FDX_LBN 14 3595 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1 3596 #define MC_CMD_PHY_CAP_50000FDX_OFST 8 3597 #define MC_CMD_PHY_CAP_50000FDX_LBN 15 3598 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1 3599 #define MC_CMD_PHY_CAP_BASER_FEC_OFST 8 3600 #define MC_CMD_PHY_CAP_BASER_FEC_LBN 16 3601 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1 3602 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8 3603 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17 3604 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1 3605 #define MC_CMD_PHY_CAP_RS_FEC_OFST 8 3606 #define MC_CMD_PHY_CAP_RS_FEC_LBN 18 3607 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1 3608 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8 3609 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19 3610 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1 3611 #define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8 3612 #define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20 3613 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1 3614 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8 3615 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 3616 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 3617 /* ?? */ 3618 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 3619 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 3620 /* ?? */ 3621 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 3622 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4 3623 /* ?? */ 3624 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 3625 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4 3626 /* ?? */ 3627 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 3628 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 3629 /* ?? */ 3630 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 3631 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4 3632 /* enum: Xaui. */ 3633 #define MC_CMD_MEDIA_XAUI 0x1 3634 /* enum: CX4. */ 3635 #define MC_CMD_MEDIA_CX4 0x2 3636 /* enum: KX4. */ 3637 #define MC_CMD_MEDIA_KX4 0x3 3638 /* enum: XFP Far. */ 3639 #define MC_CMD_MEDIA_XFP 0x4 3640 /* enum: SFP+. */ 3641 #define MC_CMD_MEDIA_SFP_PLUS 0x5 3642 /* enum: 10GBaseT. */ 3643 #define MC_CMD_MEDIA_BASE_T 0x6 3644 /* enum: QSFP+. */ 3645 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 3646 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 3647 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 3648 /* enum: Native clause 22 */ 3649 #define MC_CMD_MMD_CLAUSE22 0x0 3650 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 3651 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 3652 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 3653 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 3654 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 3655 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 3656 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 3657 /* enum: Clause22 proxied over clause45 by PHY. */ 3658 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 3659 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 3660 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 3661 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 3662 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 3663 3664 3665 /***********************************/ 3666 /* MC_CMD_START_BIST 3667 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 3668 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 3669 */ 3670 #define MC_CMD_START_BIST 0x25 3671 #undef MC_CMD_0x25_PRIVILEGE_CTG 3672 3673 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3674 3675 /* MC_CMD_START_BIST_IN msgrequest */ 3676 #define MC_CMD_START_BIST_IN_LEN 4 3677 /* Type of test. */ 3678 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 3679 #define MC_CMD_START_BIST_IN_TYPE_LEN 4 3680 /* enum: Run the PHY's short cable BIST. */ 3681 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 3682 /* enum: Run the PHY's long cable BIST. */ 3683 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 3684 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 3685 #define MC_CMD_BPX_SERDES_BIST 0x3 3686 /* enum: Run the MC loopback tests. */ 3687 #define MC_CMD_MC_LOOPBACK_BIST 0x4 3688 /* enum: Run the PHY's standard BIST. */ 3689 #define MC_CMD_PHY_BIST 0x5 3690 /* enum: Run MC RAM test. */ 3691 #define MC_CMD_MC_MEM_BIST 0x6 3692 /* enum: Run Port RAM test. */ 3693 #define MC_CMD_PORT_MEM_BIST 0x7 3694 /* enum: Run register test. */ 3695 #define MC_CMD_REG_BIST 0x8 3696 3697 /* MC_CMD_START_BIST_OUT msgresponse */ 3698 #define MC_CMD_START_BIST_OUT_LEN 0 3699 3700 3701 /***********************************/ 3702 /* MC_CMD_POLL_BIST 3703 * Poll for BIST completion. Returns a single status code, and optionally some 3704 * PHY specific bist output. The driver should only consume the BIST output 3705 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 3706 * successfully parse the BIST output, it should still respect the pass/Fail in 3707 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 3708 * EACCES (if PHY_LOCK is not held). 3709 */ 3710 #define MC_CMD_POLL_BIST 0x26 3711 #undef MC_CMD_0x26_PRIVILEGE_CTG 3712 3713 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3714 3715 /* MC_CMD_POLL_BIST_IN msgrequest */ 3716 #define MC_CMD_POLL_BIST_IN_LEN 0 3717 3718 /* MC_CMD_POLL_BIST_OUT msgresponse */ 3719 #define MC_CMD_POLL_BIST_OUT_LEN 8 3720 /* result */ 3721 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 3722 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 3723 /* enum: Running. */ 3724 #define MC_CMD_POLL_BIST_RUNNING 0x1 3725 /* enum: Passed. */ 3726 #define MC_CMD_POLL_BIST_PASSED 0x2 3727 /* enum: Failed. */ 3728 #define MC_CMD_POLL_BIST_FAILED 0x3 3729 /* enum: Timed-out. */ 3730 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 3731 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 3732 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4 3733 3734 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 3735 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 3736 /* result */ 3737 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3738 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3739 /* Enum values, see field(s): */ 3740 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3741 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 3742 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4 3743 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 3744 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4 3745 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 3746 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4 3747 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 3748 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4 3749 /* Status of each channel A */ 3750 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 3751 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4 3752 /* enum: Ok. */ 3753 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 3754 /* enum: Open. */ 3755 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 3756 /* enum: Intra-pair short. */ 3757 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 3758 /* enum: Inter-pair short. */ 3759 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 3760 /* enum: Busy. */ 3761 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 3762 /* Status of each channel B */ 3763 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 3764 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4 3765 /* Enum values, see field(s): */ 3766 /* CABLE_STATUS_A */ 3767 /* Status of each channel C */ 3768 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 3769 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4 3770 /* Enum values, see field(s): */ 3771 /* CABLE_STATUS_A */ 3772 /* Status of each channel D */ 3773 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 3774 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4 3775 /* Enum values, see field(s): */ 3776 /* CABLE_STATUS_A */ 3777 3778 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 3779 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 3780 /* result */ 3781 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3782 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3783 /* Enum values, see field(s): */ 3784 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3785 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 3786 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4 3787 /* enum: Complete. */ 3788 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 3789 /* enum: Bus switch off I2C write. */ 3790 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 3791 /* enum: Bus switch off I2C no access IO exp. */ 3792 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 3793 /* enum: Bus switch off I2C no access module. */ 3794 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 3795 /* enum: IO exp I2C configure. */ 3796 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 3797 /* enum: Bus switch I2C no cross talk. */ 3798 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 3799 /* enum: Module presence. */ 3800 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 3801 /* enum: Module ID I2C access. */ 3802 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 3803 /* enum: Module ID sane value. */ 3804 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 3805 3806 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 3807 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 3808 /* result */ 3809 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3810 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3811 /* Enum values, see field(s): */ 3812 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3813 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 3814 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4 3815 /* enum: Test has completed. */ 3816 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 3817 /* enum: RAM test - walk ones. */ 3818 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 3819 /* enum: RAM test - walk zeros. */ 3820 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 3821 /* enum: RAM test - walking inversions zeros/ones. */ 3822 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 3823 /* enum: RAM test - walking inversions checkerboard. */ 3824 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 3825 /* enum: Register test - set / clear individual bits. */ 3826 #define MC_CMD_POLL_BIST_MEM_REG 0x5 3827 /* enum: ECC error detected. */ 3828 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 3829 /* Failure address, only valid if result is POLL_BIST_FAILED */ 3830 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 3831 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4 3832 /* Bus or address space to which the failure address corresponds */ 3833 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 3834 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4 3835 /* enum: MC MIPS bus. */ 3836 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 3837 /* enum: CSR IREG bus. */ 3838 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 3839 /* enum: RX0 DPCPU bus. */ 3840 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 3841 /* enum: TX0 DPCPU bus. */ 3842 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 3843 /* enum: TX1 DPCPU bus. */ 3844 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 3845 /* enum: RX0 DICPU bus. */ 3846 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 3847 /* enum: TX DICPU bus. */ 3848 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 3849 /* enum: RX1 DPCPU bus. */ 3850 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 3851 /* enum: RX1 DICPU bus. */ 3852 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 3853 /* Pattern written to RAM / register */ 3854 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 3855 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4 3856 /* Actual value read from RAM / register */ 3857 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 3858 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4 3859 /* ECC error mask */ 3860 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 3861 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4 3862 /* ECC parity error mask */ 3863 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 3864 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4 3865 /* ECC fatal error mask */ 3866 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 3867 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 3868 3869 3870 /***********************************/ 3871 /* MC_CMD_FLUSH_RX_QUEUES 3872 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 3873 * flushes should be initiated via this MCDI operation, rather than via 3874 * directly writing FLUSH_CMD. 3875 * 3876 * The flush is completed (either done/fail) asynchronously (after this command 3877 * returns). The driver must still wait for flush done/failure events as usual. 3878 */ 3879 #define MC_CMD_FLUSH_RX_QUEUES 0x27 3880 3881 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 3882 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 3883 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 3884 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020 3885 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 3886 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4) 3887 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 3888 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 3889 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 3890 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 3891 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255 3892 3893 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 3894 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 3895 3896 3897 /***********************************/ 3898 /* MC_CMD_GET_LOOPBACK_MODES 3899 * Returns a bitmask of loopback modes available at each speed. 3900 */ 3901 #define MC_CMD_GET_LOOPBACK_MODES 0x28 3902 #undef MC_CMD_0x28_PRIVILEGE_CTG 3903 3904 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3905 3906 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 3907 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 3908 3909 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 3910 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 3911 /* Supported loopbacks. */ 3912 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 3913 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 3914 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 3915 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 3916 /* enum: None. */ 3917 #define MC_CMD_LOOPBACK_NONE 0x0 3918 /* enum: Data. */ 3919 #define MC_CMD_LOOPBACK_DATA 0x1 3920 /* enum: GMAC. */ 3921 #define MC_CMD_LOOPBACK_GMAC 0x2 3922 /* enum: XGMII. */ 3923 #define MC_CMD_LOOPBACK_XGMII 0x3 3924 /* enum: XGXS. */ 3925 #define MC_CMD_LOOPBACK_XGXS 0x4 3926 /* enum: XAUI. */ 3927 #define MC_CMD_LOOPBACK_XAUI 0x5 3928 /* enum: GMII. */ 3929 #define MC_CMD_LOOPBACK_GMII 0x6 3930 /* enum: SGMII. */ 3931 #define MC_CMD_LOOPBACK_SGMII 0x7 3932 /* enum: XGBR. */ 3933 #define MC_CMD_LOOPBACK_XGBR 0x8 3934 /* enum: XFI. */ 3935 #define MC_CMD_LOOPBACK_XFI 0x9 3936 /* enum: XAUI Far. */ 3937 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 3938 /* enum: GMII Far. */ 3939 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 3940 /* enum: SGMII Far. */ 3941 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 3942 /* enum: XFI Far. */ 3943 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 3944 /* enum: GPhy. */ 3945 #define MC_CMD_LOOPBACK_GPHY 0xe 3946 /* enum: PhyXS. */ 3947 #define MC_CMD_LOOPBACK_PHYXS 0xf 3948 /* enum: PCS. */ 3949 #define MC_CMD_LOOPBACK_PCS 0x10 3950 /* enum: PMA-PMD. */ 3951 #define MC_CMD_LOOPBACK_PMAPMD 0x11 3952 /* enum: Cross-Port. */ 3953 #define MC_CMD_LOOPBACK_XPORT 0x12 3954 /* enum: XGMII-Wireside. */ 3955 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 3956 /* enum: XAUI Wireside. */ 3957 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 3958 /* enum: XAUI Wireside Far. */ 3959 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 3960 /* enum: XAUI Wireside near. */ 3961 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 3962 /* enum: GMII Wireside. */ 3963 #define MC_CMD_LOOPBACK_GMII_WS 0x17 3964 /* enum: XFI Wireside. */ 3965 #define MC_CMD_LOOPBACK_XFI_WS 0x18 3966 /* enum: XFI Wireside Far. */ 3967 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 3968 /* enum: PhyXS Wireside. */ 3969 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 3970 /* enum: PMA lanes MAC-Serdes. */ 3971 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 3972 /* enum: KR Serdes Parallel (Encoder). */ 3973 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 3974 /* enum: KR Serdes Serial. */ 3975 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 3976 /* enum: PMA lanes MAC-Serdes Wireside. */ 3977 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 3978 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3979 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 3980 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3981 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 3982 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3983 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 3984 /* enum: KR Serdes Serial Wireside. */ 3985 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 3986 /* enum: Near side of AOE Siena side port */ 3987 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 3988 /* enum: Medford Wireside datapath loopback */ 3989 #define MC_CMD_LOOPBACK_DATA_WS 0x24 3990 /* enum: Force link up without setting up any physical loopback (snapper use 3991 * only) 3992 */ 3993 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 3994 /* Supported loopbacks. */ 3995 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 3996 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 3997 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 3998 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 3999 /* Enum values, see field(s): */ 4000 /* 100M */ 4001 /* Supported loopbacks. */ 4002 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 4003 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 4004 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 4005 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 4006 /* Enum values, see field(s): */ 4007 /* 100M */ 4008 /* Supported loopbacks. */ 4009 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 4010 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 4011 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 4012 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 4013 /* Enum values, see field(s): */ 4014 /* 100M */ 4015 /* Supported loopbacks. */ 4016 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 4017 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 4018 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 4019 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 4020 /* Enum values, see field(s): */ 4021 /* 100M */ 4022 4023 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for 4024 * newer NICs with 25G/50G/100G support 4025 */ 4026 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64 4027 /* Supported loopbacks. */ 4028 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0 4029 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8 4030 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0 4031 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4 4032 /* enum: None. */ 4033 /* MC_CMD_LOOPBACK_NONE 0x0 */ 4034 /* enum: Data. */ 4035 /* MC_CMD_LOOPBACK_DATA 0x1 */ 4036 /* enum: GMAC. */ 4037 /* MC_CMD_LOOPBACK_GMAC 0x2 */ 4038 /* enum: XGMII. */ 4039 /* MC_CMD_LOOPBACK_XGMII 0x3 */ 4040 /* enum: XGXS. */ 4041 /* MC_CMD_LOOPBACK_XGXS 0x4 */ 4042 /* enum: XAUI. */ 4043 /* MC_CMD_LOOPBACK_XAUI 0x5 */ 4044 /* enum: GMII. */ 4045 /* MC_CMD_LOOPBACK_GMII 0x6 */ 4046 /* enum: SGMII. */ 4047 /* MC_CMD_LOOPBACK_SGMII 0x7 */ 4048 /* enum: XGBR. */ 4049 /* MC_CMD_LOOPBACK_XGBR 0x8 */ 4050 /* enum: XFI. */ 4051 /* MC_CMD_LOOPBACK_XFI 0x9 */ 4052 /* enum: XAUI Far. */ 4053 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 4054 /* enum: GMII Far. */ 4055 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 4056 /* enum: SGMII Far. */ 4057 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 4058 /* enum: XFI Far. */ 4059 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 4060 /* enum: GPhy. */ 4061 /* MC_CMD_LOOPBACK_GPHY 0xe */ 4062 /* enum: PhyXS. */ 4063 /* MC_CMD_LOOPBACK_PHYXS 0xf */ 4064 /* enum: PCS. */ 4065 /* MC_CMD_LOOPBACK_PCS 0x10 */ 4066 /* enum: PMA-PMD. */ 4067 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 4068 /* enum: Cross-Port. */ 4069 /* MC_CMD_LOOPBACK_XPORT 0x12 */ 4070 /* enum: XGMII-Wireside. */ 4071 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 4072 /* enum: XAUI Wireside. */ 4073 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 4074 /* enum: XAUI Wireside Far. */ 4075 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 4076 /* enum: XAUI Wireside near. */ 4077 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 4078 /* enum: GMII Wireside. */ 4079 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 4080 /* enum: XFI Wireside. */ 4081 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 4082 /* enum: XFI Wireside Far. */ 4083 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 4084 /* enum: PhyXS Wireside. */ 4085 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 4086 /* enum: PMA lanes MAC-Serdes. */ 4087 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 4088 /* enum: KR Serdes Parallel (Encoder). */ 4089 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 4090 /* enum: KR Serdes Serial. */ 4091 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 4092 /* enum: PMA lanes MAC-Serdes Wireside. */ 4093 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 4094 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 4095 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 4096 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 4097 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 4098 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 4099 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 4100 /* enum: KR Serdes Serial Wireside. */ 4101 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 4102 /* enum: Near side of AOE Siena side port */ 4103 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 4104 /* enum: Medford Wireside datapath loopback */ 4105 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 4106 /* enum: Force link up without setting up any physical loopback (snapper use 4107 * only) 4108 */ 4109 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 4110 /* Supported loopbacks. */ 4111 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8 4112 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8 4113 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8 4114 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12 4115 /* Enum values, see field(s): */ 4116 /* 100M */ 4117 /* Supported loopbacks. */ 4118 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16 4119 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8 4120 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16 4121 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20 4122 /* Enum values, see field(s): */ 4123 /* 100M */ 4124 /* Supported loopbacks. */ 4125 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24 4126 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8 4127 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24 4128 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28 4129 /* Enum values, see field(s): */ 4130 /* 100M */ 4131 /* Supported loopbacks. */ 4132 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32 4133 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8 4134 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32 4135 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36 4136 /* Enum values, see field(s): */ 4137 /* 100M */ 4138 /* Supported 25G loopbacks. */ 4139 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40 4140 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8 4141 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40 4142 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44 4143 /* Enum values, see field(s): */ 4144 /* 100M */ 4145 /* Supported 50 loopbacks. */ 4146 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48 4147 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8 4148 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48 4149 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52 4150 /* Enum values, see field(s): */ 4151 /* 100M */ 4152 /* Supported 100G loopbacks. */ 4153 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56 4154 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8 4155 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56 4156 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60 4157 /* Enum values, see field(s): */ 4158 /* 100M */ 4159 4160 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */ 4161 #define AN_TYPE_LEN 4 4162 #define AN_TYPE_TYPE_OFST 0 4163 #define AN_TYPE_TYPE_LEN 4 4164 /* enum: None, AN disabled or not supported */ 4165 #define MC_CMD_AN_NONE 0x0 4166 /* enum: Clause 28 - BASE-T */ 4167 #define MC_CMD_AN_CLAUSE28 0x1 4168 /* enum: Clause 37 - BASE-X */ 4169 #define MC_CMD_AN_CLAUSE37 0x2 4170 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable 4171 * assemblies. Includes Clause 72/Clause 92 link-training. 4172 */ 4173 #define MC_CMD_AN_CLAUSE73 0x3 4174 #define AN_TYPE_TYPE_LBN 0 4175 #define AN_TYPE_TYPE_WIDTH 32 4176 4177 /* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3 4178 */ 4179 #define FEC_TYPE_LEN 4 4180 #define FEC_TYPE_TYPE_OFST 0 4181 #define FEC_TYPE_TYPE_LEN 4 4182 /* enum: No FEC */ 4183 #define MC_CMD_FEC_NONE 0x0 4184 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */ 4185 #define MC_CMD_FEC_BASER 0x1 4186 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */ 4187 #define MC_CMD_FEC_RS 0x2 4188 #define FEC_TYPE_TYPE_LBN 0 4189 #define FEC_TYPE_TYPE_WIDTH 32 4190 4191 4192 /***********************************/ 4193 /* MC_CMD_GET_LINK 4194 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 4195 * ETIME. 4196 */ 4197 #define MC_CMD_GET_LINK 0x29 4198 #undef MC_CMD_0x29_PRIVILEGE_CTG 4199 4200 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4201 4202 /* MC_CMD_GET_LINK_IN msgrequest */ 4203 #define MC_CMD_GET_LINK_IN_LEN 0 4204 4205 /* MC_CMD_GET_LINK_OUT msgresponse */ 4206 #define MC_CMD_GET_LINK_OUT_LEN 28 4207 /* Near-side advertised capabilities. Refer to 4208 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4209 */ 4210 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 4211 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4 4212 /* Link-partner advertised capabilities. Refer to 4213 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4214 */ 4215 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 4216 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4 4217 /* Autonegotiated speed in mbit/s. The link may still be down even if this 4218 * reads non-zero. 4219 */ 4220 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 4221 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4 4222 /* Current loopback setting. */ 4223 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 4224 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4 4225 /* Enum values, see field(s): */ 4226 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 4227 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 4228 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4 4229 #define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16 4230 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 4231 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 4232 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16 4233 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 4234 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 4235 #define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16 4236 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 4237 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 4238 #define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16 4239 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 4240 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 4241 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16 4242 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 4243 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 4244 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16 4245 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 4246 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 4247 #define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16 4248 #define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8 4249 #define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1 4250 #define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16 4251 #define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9 4252 #define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1 4253 /* This returns the negotiated flow control value. */ 4254 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 4255 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 4256 /* Enum values, see field(s): */ 4257 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 4258 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 4259 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4 4260 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 4261 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 4262 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 4263 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 4264 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 4265 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 4266 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 4267 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 4268 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 4269 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 4270 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 4271 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 4272 4273 /* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */ 4274 #define MC_CMD_GET_LINK_OUT_V2_LEN 44 4275 /* Near-side advertised capabilities. Refer to 4276 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4277 */ 4278 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0 4279 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4 4280 /* Link-partner advertised capabilities. Refer to 4281 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4282 */ 4283 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4 4284 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4 4285 /* Autonegotiated speed in mbit/s. The link may still be down even if this 4286 * reads non-zero. 4287 */ 4288 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8 4289 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4 4290 /* Current loopback setting. */ 4291 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12 4292 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4 4293 /* Enum values, see field(s): */ 4294 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 4295 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16 4296 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4 4297 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16 4298 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0 4299 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1 4300 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16 4301 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1 4302 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1 4303 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16 4304 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2 4305 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1 4306 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16 4307 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3 4308 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1 4309 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16 4310 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6 4311 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1 4312 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16 4313 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7 4314 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1 4315 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16 4316 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8 4317 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1 4318 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16 4319 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9 4320 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1 4321 /* This returns the negotiated flow control value. */ 4322 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20 4323 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4 4324 /* Enum values, see field(s): */ 4325 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 4326 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24 4327 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4 4328 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */ 4329 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */ 4330 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */ 4331 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */ 4332 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */ 4333 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */ 4334 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */ 4335 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */ 4336 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */ 4337 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */ 4338 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */ 4339 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */ 4340 /* True local device capabilities (taking into account currently used PMD/MDI, 4341 * e.g. plugged-in module). In general, subset of 4342 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST 4343 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal 4344 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to 4345 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4346 */ 4347 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28 4348 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4 4349 /* Auto-negotiation type used on the link */ 4350 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32 4351 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4 4352 /* Enum values, see field(s): */ 4353 /* AN_TYPE/TYPE */ 4354 /* Forward error correction used on the link */ 4355 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36 4356 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4 4357 /* Enum values, see field(s): */ 4358 /* FEC_TYPE/TYPE */ 4359 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40 4360 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4 4361 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40 4362 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0 4363 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1 4364 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40 4365 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1 4366 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1 4367 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40 4368 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2 4369 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1 4370 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40 4371 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3 4372 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1 4373 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40 4374 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4 4375 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1 4376 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40 4377 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5 4378 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1 4379 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40 4380 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6 4381 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1 4382 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40 4383 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7 4384 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1 4385 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40 4386 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8 4387 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1 4388 #define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40 4389 #define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9 4390 #define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1 4391 4392 4393 /***********************************/ 4394 /* MC_CMD_SET_LINK 4395 * Write the unified MAC/PHY link configuration. Locks required: None. Return 4396 * code: 0, EINVAL, ETIME, EAGAIN 4397 */ 4398 #define MC_CMD_SET_LINK 0x2a 4399 #undef MC_CMD_0x2a_PRIVILEGE_CTG 4400 4401 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 4402 4403 /* MC_CMD_SET_LINK_IN msgrequest */ 4404 #define MC_CMD_SET_LINK_IN_LEN 16 4405 /* Near-side advertised capabilities. Refer to 4406 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4407 */ 4408 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 4409 #define MC_CMD_SET_LINK_IN_CAP_LEN 4 4410 /* Flags */ 4411 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 4412 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4 4413 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4 4414 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 4415 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 4416 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4 4417 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 4418 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 4419 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4 4420 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 4421 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 4422 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4 4423 #define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3 4424 #define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1 4425 /* Loopback mode. */ 4426 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 4427 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4 4428 /* Enum values, see field(s): */ 4429 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 4430 /* A loopback speed of "0" is supported, and means (choose any available 4431 * speed). 4432 */ 4433 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 4434 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4 4435 4436 /* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence 4437 * number to ensure this SET_LINK command corresponds to the latest 4438 * MODULECHANGE event. 4439 */ 4440 #define MC_CMD_SET_LINK_IN_V2_LEN 17 4441 /* Near-side advertised capabilities. Refer to 4442 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 4443 */ 4444 #define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0 4445 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4 4446 /* Flags */ 4447 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4 4448 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4 4449 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4 4450 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0 4451 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1 4452 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4 4453 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1 4454 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1 4455 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4 4456 #define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2 4457 #define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1 4458 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4 4459 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3 4460 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1 4461 /* Loopback mode. */ 4462 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8 4463 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4 4464 /* Enum values, see field(s): */ 4465 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 4466 /* A loopback speed of "0" is supported, and means (choose any available 4467 * speed). 4468 */ 4469 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12 4470 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4 4471 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16 4472 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1 4473 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16 4474 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0 4475 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7 4476 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16 4477 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7 4478 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1 4479 4480 /* MC_CMD_SET_LINK_OUT msgresponse */ 4481 #define MC_CMD_SET_LINK_OUT_LEN 0 4482 4483 4484 /***********************************/ 4485 /* MC_CMD_SET_ID_LED 4486 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 4487 */ 4488 #define MC_CMD_SET_ID_LED 0x2b 4489 #undef MC_CMD_0x2b_PRIVILEGE_CTG 4490 4491 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 4492 4493 /* MC_CMD_SET_ID_LED_IN msgrequest */ 4494 #define MC_CMD_SET_ID_LED_IN_LEN 4 4495 /* Set LED state. */ 4496 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 4497 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4 4498 #define MC_CMD_LED_OFF 0x0 /* enum */ 4499 #define MC_CMD_LED_ON 0x1 /* enum */ 4500 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 4501 4502 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 4503 #define MC_CMD_SET_ID_LED_OUT_LEN 0 4504 4505 4506 /***********************************/ 4507 /* MC_CMD_SET_MAC 4508 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 4509 */ 4510 #define MC_CMD_SET_MAC 0x2c 4511 #undef MC_CMD_0x2c_PRIVILEGE_CTG 4512 4513 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4514 4515 /* MC_CMD_SET_MAC_IN msgrequest */ 4516 #define MC_CMD_SET_MAC_IN_LEN 28 4517 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 4518 * EtherII, VLAN, bug16011 padding). 4519 */ 4520 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 4521 #define MC_CMD_SET_MAC_IN_MTU_LEN 4 4522 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 4523 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4 4524 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 4525 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 4526 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 4527 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 4528 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 4529 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4 4530 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16 4531 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 4532 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 4533 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16 4534 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 4535 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 4536 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 4537 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 4538 /* enum: Flow control is off. */ 4539 #define MC_CMD_FCNTL_OFF 0x0 4540 /* enum: Respond to flow control. */ 4541 #define MC_CMD_FCNTL_RESPOND 0x1 4542 /* enum: Respond to and Issue flow control. */ 4543 #define MC_CMD_FCNTL_BIDIR 0x2 4544 /* enum: Auto neg flow control. */ 4545 #define MC_CMD_FCNTL_AUTO 0x3 4546 /* enum: Priority flow control (eftest builds only). */ 4547 #define MC_CMD_FCNTL_QBB 0x4 4548 /* enum: Issue flow control. */ 4549 #define MC_CMD_FCNTL_GENERATE 0x5 4550 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 4551 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 4552 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24 4553 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 4554 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 4555 4556 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 4557 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 4558 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 4559 * EtherII, VLAN, bug16011 padding). 4560 */ 4561 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 4562 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4 4563 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 4564 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4 4565 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 4566 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 4567 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 4568 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 4569 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 4570 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4 4571 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16 4572 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 4573 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 4574 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16 4575 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 4576 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 4577 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 4578 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4 4579 /* enum: Flow control is off. */ 4580 /* MC_CMD_FCNTL_OFF 0x0 */ 4581 /* enum: Respond to flow control. */ 4582 /* MC_CMD_FCNTL_RESPOND 0x1 */ 4583 /* enum: Respond to and Issue flow control. */ 4584 /* MC_CMD_FCNTL_BIDIR 0x2 */ 4585 /* enum: Auto neg flow control. */ 4586 /* MC_CMD_FCNTL_AUTO 0x3 */ 4587 /* enum: Priority flow control (eftest builds only). */ 4588 /* MC_CMD_FCNTL_QBB 0x4 */ 4589 /* enum: Issue flow control. */ 4590 /* MC_CMD_FCNTL_GENERATE 0x5 */ 4591 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 4592 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4 4593 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24 4594 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 4595 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 4596 /* Select which parameters to configure. A parameter will only be modified if 4597 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 4598 * capabilities then this field is ignored (and all flags are assumed to be 4599 * set). 4600 */ 4601 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 4602 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4 4603 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28 4604 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 4605 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 4606 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28 4607 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 4608 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 4609 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28 4610 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 4611 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 4612 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28 4613 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 4614 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 4615 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28 4616 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 4617 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 4618 4619 /* MC_CMD_SET_MAC_OUT msgresponse */ 4620 #define MC_CMD_SET_MAC_OUT_LEN 0 4621 4622 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 4623 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 4624 /* MTU as configured after processing the request. See comment at 4625 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 4626 * to 0. 4627 */ 4628 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 4629 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 4630 4631 4632 /***********************************/ 4633 /* MC_CMD_PHY_STATS 4634 * Get generic PHY statistics. This call returns the statistics for a generic 4635 * PHY in a sparse array (indexed by the enumerate). Each value is represented 4636 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 4637 * statistics may be read from the message response. If DMA_ADDR != 0, then the 4638 * statistics are dmad to that (page-aligned location). Locks required: None. 4639 * Returns: 0, ETIME 4640 */ 4641 #define MC_CMD_PHY_STATS 0x2d 4642 #undef MC_CMD_0x2d_PRIVILEGE_CTG 4643 4644 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 4645 4646 /* MC_CMD_PHY_STATS_IN msgrequest */ 4647 #define MC_CMD_PHY_STATS_IN_LEN 8 4648 /* ??? */ 4649 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 4650 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 4651 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 4652 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 4653 4654 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 4655 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 4656 4657 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 4658 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 4659 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 4660 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 4661 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 4662 /* enum: OUI. */ 4663 #define MC_CMD_OUI 0x0 4664 /* enum: PMA-PMD Link Up. */ 4665 #define MC_CMD_PMA_PMD_LINK_UP 0x1 4666 /* enum: PMA-PMD RX Fault. */ 4667 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 4668 /* enum: PMA-PMD TX Fault. */ 4669 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 4670 /* enum: PMA-PMD Signal */ 4671 #define MC_CMD_PMA_PMD_SIGNAL 0x4 4672 /* enum: PMA-PMD SNR A. */ 4673 #define MC_CMD_PMA_PMD_SNR_A 0x5 4674 /* enum: PMA-PMD SNR B. */ 4675 #define MC_CMD_PMA_PMD_SNR_B 0x6 4676 /* enum: PMA-PMD SNR C. */ 4677 #define MC_CMD_PMA_PMD_SNR_C 0x7 4678 /* enum: PMA-PMD SNR D. */ 4679 #define MC_CMD_PMA_PMD_SNR_D 0x8 4680 /* enum: PCS Link Up. */ 4681 #define MC_CMD_PCS_LINK_UP 0x9 4682 /* enum: PCS RX Fault. */ 4683 #define MC_CMD_PCS_RX_FAULT 0xa 4684 /* enum: PCS TX Fault. */ 4685 #define MC_CMD_PCS_TX_FAULT 0xb 4686 /* enum: PCS BER. */ 4687 #define MC_CMD_PCS_BER 0xc 4688 /* enum: PCS Block Errors. */ 4689 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 4690 /* enum: PhyXS Link Up. */ 4691 #define MC_CMD_PHYXS_LINK_UP 0xe 4692 /* enum: PhyXS RX Fault. */ 4693 #define MC_CMD_PHYXS_RX_FAULT 0xf 4694 /* enum: PhyXS TX Fault. */ 4695 #define MC_CMD_PHYXS_TX_FAULT 0x10 4696 /* enum: PhyXS Align. */ 4697 #define MC_CMD_PHYXS_ALIGN 0x11 4698 /* enum: PhyXS Sync. */ 4699 #define MC_CMD_PHYXS_SYNC 0x12 4700 /* enum: AN link-up. */ 4701 #define MC_CMD_AN_LINK_UP 0x13 4702 /* enum: AN Complete. */ 4703 #define MC_CMD_AN_COMPLETE 0x14 4704 /* enum: AN 10GBaseT Status. */ 4705 #define MC_CMD_AN_10GBT_STATUS 0x15 4706 /* enum: Clause 22 Link-Up. */ 4707 #define MC_CMD_CL22_LINK_UP 0x16 4708 /* enum: (Last entry) */ 4709 #define MC_CMD_PHY_NSTATS 0x17 4710 4711 4712 /***********************************/ 4713 /* MC_CMD_MAC_STATS 4714 * Get generic MAC statistics. This call returns unified statistics maintained 4715 * by the MC as it switches between the GMAC and XMAC. The MC will write out 4716 * all supported stats. The driver should zero initialise the buffer to 4717 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 4718 * performed, and the statistics may be read from the message response. If 4719 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 4720 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 4721 * effect. Returns: 0, ETIME 4722 */ 4723 #define MC_CMD_MAC_STATS 0x2e 4724 #undef MC_CMD_0x2e_PRIVILEGE_CTG 4725 4726 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4727 4728 /* MC_CMD_MAC_STATS_IN msgrequest */ 4729 #define MC_CMD_MAC_STATS_IN_LEN 20 4730 /* ??? */ 4731 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 4732 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 4733 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 4734 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 4735 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 4736 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4 4737 #define MC_CMD_MAC_STATS_IN_DMA_OFST 8 4738 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 4739 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 4740 #define MC_CMD_MAC_STATS_IN_CLEAR_OFST 8 4741 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 4742 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 4743 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8 4744 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 4745 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 4746 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8 4747 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 4748 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 4749 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8 4750 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 4751 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 4752 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8 4753 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 4754 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 4755 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8 4756 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 4757 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 4758 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 4759 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 4760 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 4761 * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 4762 */ 4763 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 4764 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4 4765 /* port id so vadapter stats can be provided */ 4766 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 4767 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 4768 4769 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 4770 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 4771 4772 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 4773 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 4774 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 4775 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 4776 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 4777 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 4778 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 4779 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 4780 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 4781 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 4782 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 4783 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 4784 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 4785 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 4786 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 4787 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 4788 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 4789 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 4790 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 4791 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 4792 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 4793 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 4794 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 4795 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 4796 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 4797 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 4798 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 4799 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 4800 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 4801 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 4802 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 4803 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 4804 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 4805 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 4806 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 4807 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 4808 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 4809 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 4810 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 4811 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 4812 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 4813 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 4814 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 4815 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 4816 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 4817 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 4818 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 4819 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 4820 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 4821 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 4822 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 4823 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 4824 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 4825 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 4826 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 4827 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 4828 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 4829 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 4830 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 4831 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 4832 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 4833 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 4834 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 4835 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 4836 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 4837 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 4838 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 4839 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 4840 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4841 * capability only. 4842 */ 4843 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 4844 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 4845 * PM_AND_RXDP_COUNTERS capability only. 4846 */ 4847 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 4848 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4849 * capability only. 4850 */ 4851 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 4852 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 4853 * PM_AND_RXDP_COUNTERS capability only. 4854 */ 4855 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 4856 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4857 * capability only. 4858 */ 4859 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 4860 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4861 * capability only. 4862 */ 4863 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 4864 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4865 * capability only. 4866 */ 4867 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 4868 /* enum: RXDP counter: Number of packets dropped due to the queue being 4869 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4870 */ 4871 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 4872 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 4873 * with PM_AND_RXDP_COUNTERS capability only. 4874 */ 4875 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 4876 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 4877 * PM_AND_RXDP_COUNTERS capability only. 4878 */ 4879 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 4880 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 4881 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4882 */ 4883 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 4884 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 4885 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4886 */ 4887 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 4888 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 4889 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 4890 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 4891 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 4892 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 4893 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 4894 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 4895 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 4896 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 4897 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 4898 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 4899 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 4900 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 4901 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 4902 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 4903 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 4904 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 4905 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 4906 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 4907 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 4908 /* enum: Start of GMAC stats buffer space, for Siena only. */ 4909 #define MC_CMD_GMAC_DMABUF_START 0x40 4910 /* enum: End of GMAC stats buffer space, for Siena only. */ 4911 #define MC_CMD_GMAC_DMABUF_END 0x5f 4912 /* enum: GENERATION_END value, used together with GENERATION_START to verify 4913 * consistency of DMAd data. For legacy firmware / drivers without extended 4914 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS * 4915 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise, 4916 * this value is invalid/ reserved and GENERATION_END is written as the last 4917 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that 4918 * this is consistent with the legacy behaviour, in the sense that entry 96 is 4919 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS * 4920 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details. 4921 */ 4922 #define MC_CMD_MAC_GENERATION_END 0x60 4923 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 4924 4925 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */ 4926 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0 4927 4928 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ 4929 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) 4930 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 4931 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 4932 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 4933 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 4934 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 4935 /* enum: Start of FEC stats buffer space, Medford2 and up */ 4936 #define MC_CMD_MAC_FEC_DMABUF_START 0x61 4937 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) 4938 */ 4939 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 4940 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2) 4941 */ 4942 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 4943 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 4944 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 4945 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 4946 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 4947 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 4948 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 4949 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 4950 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 4951 /* enum: This includes the space at offset 103 which is the final 4952 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused. 4953 */ 4954 #define MC_CMD_MAC_NSTATS_V2 0x68 4955 /* Other enum values, see field(s): */ 4956 /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */ 4957 4958 /* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */ 4959 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0 4960 4961 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */ 4962 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3) 4963 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0 4964 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8 4965 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0 4966 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4 4967 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 4968 /* enum: Start of CTPIO stats buffer space, Medford2 and up */ 4969 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 4970 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the 4971 * target VI 4972 */ 4973 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68 4974 /* enum: Number of times a CTPIO send wrote beyond frame end (informational 4975 * only) 4976 */ 4977 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69 4978 /* enum: Number of CTPIO failures because the TX doorbell was written before 4979 * the end of the frame data 4980 */ 4981 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a 4982 /* enum: Number of CTPIO failures because the internal FIFO overflowed */ 4983 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b 4984 /* enum: Number of CTPIO failures because the host did not deliver data fast 4985 * enough to avoid MAC underflow 4986 */ 4987 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c 4988 /* enum: Number of CTPIO failures because the host did not deliver all the 4989 * frame data within the timeout 4990 */ 4991 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d 4992 /* enum: Number of CTPIO failures because the frame data arrived out of order 4993 * or with gaps 4994 */ 4995 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e 4996 /* enum: Number of CTPIO failures because the host started a new frame before 4997 * completing the previous one 4998 */ 4999 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f 5000 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits 5001 * or not 32-bit aligned 5002 */ 5003 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70 5004 /* enum: Number of CTPIO fallbacks because another VI on the same port was 5005 * sending a CTPIO frame 5006 */ 5007 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71 5008 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled 5009 */ 5010 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72 5011 /* enum: Number of CTPIO fallbacks because length in header was less than 29 5012 * bytes 5013 */ 5014 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73 5015 /* enum: Total number of successful CTPIO sends on this port */ 5016 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74 5017 /* enum: Total number of CTPIO fallbacks on this port */ 5018 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75 5019 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or 5020 * not 5021 */ 5022 #define MC_CMD_MAC_CTPIO_POISON 0x76 5023 /* enum: Total number of CTPIO erased frames on this port */ 5024 #define MC_CMD_MAC_CTPIO_ERASE 0x77 5025 /* enum: This includes the space at offset 120 which is the final 5026 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused. 5027 */ 5028 #define MC_CMD_MAC_NSTATS_V3 0x79 5029 /* Other enum values, see field(s): */ 5030 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */ 5031 5032 /* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */ 5033 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0 5034 5035 /* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */ 5036 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3) 5037 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0 5038 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8 5039 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0 5040 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4 5041 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4 5042 /* enum: Start of V4 stats buffer space */ 5043 #define MC_CMD_MAC_V4_DMABUF_START 0x79 5044 /* enum: RXDP counter: Number of packets truncated because scattering was 5045 * disabled. 5046 */ 5047 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79 5048 /* enum: RXDP counter: Number of times the RXDP head of line blocked waiting 5049 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set. 5050 */ 5051 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a 5052 /* enum: RXDP counter: Number of times the RXDP timed out while head of line 5053 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set. 5054 */ 5055 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b 5056 /* enum: This includes the space at offset 124 which is the final 5057 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused. 5058 */ 5059 #define MC_CMD_MAC_NSTATS_V4 0x7d 5060 /* Other enum values, see field(s): */ 5061 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */ 5062 5063 5064 /***********************************/ 5065 /* MC_CMD_SRIOV 5066 * to be documented 5067 */ 5068 #define MC_CMD_SRIOV 0x30 5069 5070 /* MC_CMD_SRIOV_IN msgrequest */ 5071 #define MC_CMD_SRIOV_IN_LEN 12 5072 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5073 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4 5074 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5075 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 5076 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5077 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 5078 5079 /* MC_CMD_SRIOV_OUT msgresponse */ 5080 #define MC_CMD_SRIOV_OUT_LEN 8 5081 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5082 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 5083 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5084 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 5085 5086 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5087 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5088 /* this is only used for the first record */ 5089 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5090 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 5091 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5092 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5093 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5094 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 5095 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5096 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5097 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5098 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5099 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5100 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5101 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5102 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5103 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5104 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 5105 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5106 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5107 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5108 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5109 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5110 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5111 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5112 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5113 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5114 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5115 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 5116 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5117 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5118 5119 5120 /***********************************/ 5121 /* MC_CMD_MEMCPY 5122 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5123 * embedded directly in the command. 5124 * 5125 * A common pattern is for a client to use generation counts to signal a dma 5126 * update of a datastructure. To facilitate this, this MCDI operation can 5127 * contain multiple requests which are executed in strict order. Requests take 5128 * the form of duplicating the entire MCDI request continuously (including the 5129 * requests record, which is ignored in all but the first structure) 5130 * 5131 * The source data can either come from a DMA from the host, or it can be 5132 * embedded within the request directly, thereby eliminating a DMA read. To 5133 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5134 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5135 * payload. It's the callers responsibility to ensure that the embedded data 5136 * doesn't overlap the records. 5137 * 5138 * Returns: 0, EINVAL (invalid RID) 5139 */ 5140 #define MC_CMD_MEMCPY 0x31 5141 5142 /* MC_CMD_MEMCPY_IN msgrequest */ 5143 #define MC_CMD_MEMCPY_IN_LENMIN 32 5144 #define MC_CMD_MEMCPY_IN_LENMAX 224 5145 #define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992 5146 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5147 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32) 5148 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5149 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5150 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5151 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5152 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5153 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31 5154 5155 /* MC_CMD_MEMCPY_OUT msgresponse */ 5156 #define MC_CMD_MEMCPY_OUT_LEN 0 5157 5158 5159 /***********************************/ 5160 /* MC_CMD_WOL_FILTER_SET 5161 * Set a WoL filter. 5162 */ 5163 #define MC_CMD_WOL_FILTER_SET 0x32 5164 #undef MC_CMD_0x32_PRIVILEGE_CTG 5165 5166 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5167 5168 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5169 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5170 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5171 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 5172 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5173 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5174 /* A type value of 1 is unused. */ 5175 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5176 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 5177 /* enum: Magic */ 5178 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5179 /* enum: MS Windows Magic */ 5180 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5181 /* enum: IPv4 Syn */ 5182 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5183 /* enum: IPv6 Syn */ 5184 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5185 /* enum: Bitmap */ 5186 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5187 /* enum: Link */ 5188 #define MC_CMD_WOL_TYPE_LINK 0x6 5189 /* enum: (Above this for future use) */ 5190 #define MC_CMD_WOL_TYPE_MAX 0x7 5191 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5192 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5193 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5194 5195 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5196 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5197 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5198 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 5199 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5200 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 5201 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5202 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5203 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5204 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5205 5206 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5207 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5208 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5209 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 5210 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5211 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 5212 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5213 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4 5214 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5215 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4 5216 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5217 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5218 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5219 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5220 5221 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5222 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5223 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5224 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 5225 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5226 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 5227 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5228 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5229 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5230 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5231 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5232 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5233 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5234 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5235 5236 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5237 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5238 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5239 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 5240 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5241 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 5242 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5243 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5244 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5245 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5246 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5247 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5248 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5249 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5250 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5251 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 5252 5253 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 5254 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 5255 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5256 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 5257 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5258 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 5259 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 5260 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4 5261 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8 5262 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 5263 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 5264 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8 5265 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 5266 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 5267 5268 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 5269 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 5270 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 5271 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 5272 5273 5274 /***********************************/ 5275 /* MC_CMD_WOL_FILTER_REMOVE 5276 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 5277 */ 5278 #define MC_CMD_WOL_FILTER_REMOVE 0x33 5279 #undef MC_CMD_0x33_PRIVILEGE_CTG 5280 5281 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 5282 5283 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 5284 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 5285 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 5286 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4 5287 5288 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 5289 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 5290 5291 5292 /***********************************/ 5293 /* MC_CMD_WOL_FILTER_RESET 5294 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 5295 * ENOSYS 5296 */ 5297 #define MC_CMD_WOL_FILTER_RESET 0x34 5298 #undef MC_CMD_0x34_PRIVILEGE_CTG 5299 5300 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 5301 5302 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 5303 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 5304 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 5305 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 5306 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 5307 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 5308 5309 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 5310 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 5311 5312 5313 /***********************************/ 5314 /* MC_CMD_SET_MCAST_HASH 5315 * Set the MCAST hash value without otherwise reconfiguring the MAC 5316 */ 5317 #define MC_CMD_SET_MCAST_HASH 0x35 5318 5319 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 5320 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 5321 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 5322 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 5323 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 5324 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 5325 5326 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 5327 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 5328 5329 5330 /***********************************/ 5331 /* MC_CMD_NVRAM_TYPES 5332 * Return bitfield indicating available types of virtual NVRAM partitions. 5333 * Locks required: none. Returns: 0 5334 */ 5335 #define MC_CMD_NVRAM_TYPES 0x36 5336 #undef MC_CMD_0x36_PRIVILEGE_CTG 5337 5338 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5339 5340 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 5341 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 5342 5343 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 5344 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 5345 /* Bit mask of supported types. */ 5346 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 5347 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 5348 /* enum: Disabled callisto. */ 5349 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 5350 /* enum: MC firmware. */ 5351 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 5352 /* enum: MC backup firmware. */ 5353 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 5354 /* enum: Static configuration Port0. */ 5355 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 5356 /* enum: Static configuration Port1. */ 5357 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 5358 /* enum: Dynamic configuration Port0. */ 5359 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 5360 /* enum: Dynamic configuration Port1. */ 5361 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 5362 /* enum: Expansion Rom. */ 5363 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 5364 /* enum: Expansion Rom Configuration Port0. */ 5365 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 5366 /* enum: Expansion Rom Configuration Port1. */ 5367 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 5368 /* enum: Phy Configuration Port0. */ 5369 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 5370 /* enum: Phy Configuration Port1. */ 5371 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 5372 /* enum: Log. */ 5373 #define MC_CMD_NVRAM_TYPE_LOG 0xc 5374 /* enum: FPGA image. */ 5375 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 5376 /* enum: FPGA backup image */ 5377 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 5378 /* enum: FC firmware. */ 5379 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 5380 /* enum: FC backup firmware. */ 5381 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 5382 /* enum: CPLD image. */ 5383 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 5384 /* enum: Licensing information. */ 5385 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 5386 /* enum: FC Log. */ 5387 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 5388 /* enum: Additional flash on FPGA. */ 5389 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 5390 5391 5392 /***********************************/ 5393 /* MC_CMD_NVRAM_INFO 5394 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 5395 * EINVAL (bad type). 5396 */ 5397 #define MC_CMD_NVRAM_INFO 0x37 5398 #undef MC_CMD_0x37_PRIVILEGE_CTG 5399 5400 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5401 5402 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 5403 #define MC_CMD_NVRAM_INFO_IN_LEN 4 5404 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 5405 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4 5406 /* Enum values, see field(s): */ 5407 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5408 5409 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 5410 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 5411 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 5412 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4 5413 /* Enum values, see field(s): */ 5414 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5415 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 5416 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4 5417 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 5418 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4 5419 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 5420 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4 5421 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12 5422 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 5423 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 5424 #define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12 5425 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 5426 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 5427 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12 5428 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 5429 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 5430 #define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12 5431 #define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3 5432 #define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1 5433 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12 5434 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 5435 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 5436 #define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12 5437 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 5438 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 5439 #define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12 5440 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 5441 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 5442 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 5443 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4 5444 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 5445 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4 5446 5447 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 5448 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 5449 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 5450 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4 5451 /* Enum values, see field(s): */ 5452 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5453 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 5454 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4 5455 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 5456 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4 5457 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 5458 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4 5459 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12 5460 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 5461 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 5462 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12 5463 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 5464 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 5465 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12 5466 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 5467 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 5468 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12 5469 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 5470 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 5471 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12 5472 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 5473 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 5474 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 5475 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 5476 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 5477 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4 5478 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 5479 */ 5480 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 5481 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 5482 5483 5484 /***********************************/ 5485 /* MC_CMD_NVRAM_UPDATE_START 5486 * Start a group of update operations on a virtual NVRAM partition. Locks 5487 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 5488 * PHY_LOCK required and not held). In an adapter bound to a TSA controller, 5489 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types 5490 * i.e. static config, dynamic config and expansion ROM config. Attempting to 5491 * perform this operation on a restricted partition will return the error 5492 * EPERM. 5493 */ 5494 #define MC_CMD_NVRAM_UPDATE_START 0x38 5495 #undef MC_CMD_0x38_PRIVILEGE_CTG 5496 5497 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5498 5499 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 5500 * Use NVRAM_UPDATE_START_V2_IN in new code 5501 */ 5502 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 5503 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 5504 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 5505 /* Enum values, see field(s): */ 5506 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5507 5508 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 5509 * request with additional flags indicating version of command in use. See 5510 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 5511 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 5512 */ 5513 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 5514 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 5515 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 5516 /* Enum values, see field(s): */ 5517 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5518 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 5519 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 5520 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4 5521 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 5522 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 5523 5524 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 5525 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 5526 5527 5528 /***********************************/ 5529 /* MC_CMD_NVRAM_READ 5530 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 5531 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5532 * PHY_LOCK required and not held) 5533 */ 5534 #define MC_CMD_NVRAM_READ 0x39 5535 #undef MC_CMD_0x39_PRIVILEGE_CTG 5536 5537 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5538 5539 /* MC_CMD_NVRAM_READ_IN msgrequest */ 5540 #define MC_CMD_NVRAM_READ_IN_LEN 12 5541 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 5542 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4 5543 /* Enum values, see field(s): */ 5544 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5545 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 5546 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4 5547 /* amount to read in bytes */ 5548 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 5549 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4 5550 5551 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 5552 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 5553 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 5554 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 5555 /* Enum values, see field(s): */ 5556 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5557 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 5558 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 5559 /* amount to read in bytes */ 5560 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 5561 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 5562 /* Optional control info. If a partition is stored with an A/B versioning 5563 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 5564 * this to control which underlying physical partition is used to read data 5565 * from. This allows it to perform a read-modify-write-verify with the write 5566 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 5567 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 5568 * verifying by reading with MODE=TARGET_BACKUP. 5569 */ 5570 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 5571 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 5572 /* enum: Same as omitting MODE: caller sees data in current partition unless it 5573 * holds the write lock in which case it sees data in the partition it is 5574 * updating. 5575 */ 5576 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 5577 /* enum: Read from the current partition of an A/B pair, even if holding the 5578 * write lock. 5579 */ 5580 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 5581 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 5582 * pair 5583 */ 5584 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 5585 5586 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 5587 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 5588 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 5589 #define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020 5590 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 5591 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1) 5592 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 5593 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 5594 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 5595 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 5596 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020 5597 5598 5599 /***********************************/ 5600 /* MC_CMD_NVRAM_WRITE 5601 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 5602 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5603 * PHY_LOCK required and not held) 5604 */ 5605 #define MC_CMD_NVRAM_WRITE 0x3a 5606 #undef MC_CMD_0x3a_PRIVILEGE_CTG 5607 5608 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5609 5610 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 5611 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 5612 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 5613 #define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020 5614 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 5615 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1) 5616 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 5617 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4 5618 /* Enum values, see field(s): */ 5619 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5620 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 5621 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4 5622 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 5623 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4 5624 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 5625 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 5626 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 5627 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 5628 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008 5629 5630 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 5631 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 5632 5633 5634 /***********************************/ 5635 /* MC_CMD_NVRAM_ERASE 5636 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 5637 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5638 * PHY_LOCK required and not held) 5639 */ 5640 #define MC_CMD_NVRAM_ERASE 0x3b 5641 #undef MC_CMD_0x3b_PRIVILEGE_CTG 5642 5643 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5644 5645 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 5646 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 5647 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 5648 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4 5649 /* Enum values, see field(s): */ 5650 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5651 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 5652 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4 5653 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 5654 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4 5655 5656 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 5657 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 5658 5659 5660 /***********************************/ 5661 /* MC_CMD_NVRAM_UPDATE_FINISH 5662 * Finish a group of update operations on a virtual NVRAM partition. Locks 5663 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/ 5664 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to 5665 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of 5666 * partition types i.e. static config, dynamic config and expansion ROM config. 5667 * Attempting to perform this operation on a restricted partition will return 5668 * the error EPERM. 5669 */ 5670 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 5671 #undef MC_CMD_0x3c_PRIVILEGE_CTG 5672 5673 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5674 5675 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 5676 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 5677 */ 5678 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 5679 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 5680 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 5681 /* Enum values, see field(s): */ 5682 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5683 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 5684 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4 5685 5686 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 5687 * request with additional flags indicating version of NVRAM_UPDATE commands in 5688 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 5689 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 5690 */ 5691 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 5692 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 5693 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 5694 /* Enum values, see field(s): */ 5695 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5696 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 5697 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 5698 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 5699 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 5700 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8 5701 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 5702 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 5703 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8 5704 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1 5705 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1 5706 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8 5707 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2 5708 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1 5709 5710 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 5711 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 5712 */ 5713 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 5714 5715 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 5716 * 5717 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 5718 * firmware validation where applicable back to the host. 5719 * 5720 * Medford only: For signed firmware images, such as those for medford, the MC 5721 * firmware verifies the signature before marking the firmware image as valid. 5722 * This process takes a few seconds to complete. So is likely to take more than 5723 * the MCDI timeout. Hence signature verification is initiated when 5724 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 5725 * MCDI command is run in a background MCDI processing thread. This response 5726 * payload includes the results of the signature verification. Note that the 5727 * per-partition nvram lock in firmware is only released after the verification 5728 * has completed. 5729 */ 5730 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 5731 /* Result of nvram update completion processing. Result codes that indicate an 5732 * internal build failure and therefore not expected to be seen by customers in 5733 * the field are marked with a prefix 'Internal-error'. 5734 */ 5735 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 5736 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 5737 /* enum: Invalid return code; only non-zero values are defined. Defined as 5738 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 5739 */ 5740 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 5741 /* enum: Verify succeeded without any errors. */ 5742 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 5743 /* enum: CMS format verification failed due to an internal error. */ 5744 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 5745 /* enum: Invalid CMS format in image metadata. */ 5746 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 5747 /* enum: Message digest verification failed due to an internal error. */ 5748 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 5749 /* enum: Error in message digest calculated over the reflash-header, payload 5750 * and reflash-trailer. 5751 */ 5752 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 5753 /* enum: Signature verification failed due to an internal error. */ 5754 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 5755 /* enum: There are no valid signatures in the image. */ 5756 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 5757 /* enum: Trusted approvers verification failed due to an internal error. */ 5758 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 5759 /* enum: The Trusted approver's list is empty. */ 5760 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 5761 /* enum: Signature chain verification failed due to an internal error. */ 5762 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 5763 /* enum: The signers of the signatures in the image are not listed in the 5764 * Trusted approver's list. 5765 */ 5766 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 5767 /* enum: The image contains a test-signed certificate, but the adapter accepts 5768 * only production signed images. 5769 */ 5770 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 5771 /* enum: The image has a lower security level than the current firmware. */ 5772 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd 5773 /* enum: Internal-error. The signed image is missing the 'contents' section, 5774 * where the 'contents' section holds the actual image payload to be applied. 5775 */ 5776 #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe 5777 /* enum: Internal-error. The bundle header is invalid. */ 5778 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf 5779 /* enum: Internal-error. The bundle does not have a valid reflash image layout. 5780 */ 5781 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10 5782 /* enum: Internal-error. The bundle has an inconsistent layout of components or 5783 * incorrect checksum. 5784 */ 5785 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11 5786 /* enum: Internal-error. The bundle manifest is inconsistent with components in 5787 * the bundle. 5788 */ 5789 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12 5790 /* enum: Internal-error. The number of components in a bundle do not match the 5791 * number of components advertised by the bundle manifest. 5792 */ 5793 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13 5794 /* enum: Internal-error. The bundle contains too many components for the MC 5795 * firmware to process 5796 */ 5797 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14 5798 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent 5799 * component. 5800 */ 5801 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15 5802 /* enum: Internal-error. The hash of a component does not match the hash stored 5803 * in the bundle manifest. 5804 */ 5805 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16 5806 /* enum: Internal-error. Component hash calculation failed. */ 5807 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17 5808 /* enum: Internal-error. The component does not have a valid reflash image 5809 * layout. 5810 */ 5811 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18 5812 /* enum: The bundle processing code failed to copy a component to its target 5813 * partition. 5814 */ 5815 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 5816 /* enum: The update operation is in-progress. */ 5817 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a 5818 5819 5820 /***********************************/ 5821 /* MC_CMD_REBOOT 5822 * Reboot the MC. 5823 * 5824 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 5825 * assertion failure (at which point it is expected to perform a complete tear 5826 * down and reinitialise), to allow both ports to reset the MC once in an 5827 * atomic fashion. 5828 * 5829 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 5830 * which means that they will automatically reboot out of the assertion 5831 * handler, so this is in practise an optional operation. It is still 5832 * recommended that drivers execute this to support custom firmwares with 5833 * REBOOT_ON_ASSERT=0. 5834 * 5835 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 5836 * DATALEN=0 5837 */ 5838 #define MC_CMD_REBOOT 0x3d 5839 #undef MC_CMD_0x3d_PRIVILEGE_CTG 5840 5841 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5842 5843 /* MC_CMD_REBOOT_IN msgrequest */ 5844 #define MC_CMD_REBOOT_IN_LEN 4 5845 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 5846 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4 5847 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 5848 5849 /* MC_CMD_REBOOT_OUT msgresponse */ 5850 #define MC_CMD_REBOOT_OUT_LEN 0 5851 5852 5853 /***********************************/ 5854 /* MC_CMD_SCHEDINFO 5855 * Request scheduler info. Locks required: NONE. Returns: An array of 5856 * (timeslice,maximum overrun), one for each thread, in ascending order of 5857 * thread address. 5858 */ 5859 #define MC_CMD_SCHEDINFO 0x3e 5860 #undef MC_CMD_0x3e_PRIVILEGE_CTG 5861 5862 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5863 5864 /* MC_CMD_SCHEDINFO_IN msgrequest */ 5865 #define MC_CMD_SCHEDINFO_IN_LEN 0 5866 5867 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 5868 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 5869 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 5870 #define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020 5871 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 5872 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4) 5873 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 5874 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 5875 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 5876 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 5877 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255 5878 5879 5880 /***********************************/ 5881 /* MC_CMD_REBOOT_MODE 5882 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 5883 * mode to the specified value. Returns the old mode. 5884 */ 5885 #define MC_CMD_REBOOT_MODE 0x3f 5886 #undef MC_CMD_0x3f_PRIVILEGE_CTG 5887 5888 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5889 5890 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 5891 #define MC_CMD_REBOOT_MODE_IN_LEN 4 5892 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 5893 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 5894 /* enum: Normal. */ 5895 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 5896 /* enum: Power-on Reset. */ 5897 #define MC_CMD_REBOOT_MODE_POR 0x2 5898 /* enum: Snapper. */ 5899 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 5900 /* enum: snapper fake POR */ 5901 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 5902 #define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0 5903 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 5904 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 5905 5906 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 5907 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 5908 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 5909 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 5910 5911 5912 /***********************************/ 5913 /* MC_CMD_SENSOR_INFO 5914 * Returns information about every available sensor. 5915 * 5916 * Each sensor has a single (16bit) value, and a corresponding state. The 5917 * mapping between value and state is nominally determined by the MC, but may 5918 * be implemented using up to 2 ranges per sensor. 5919 * 5920 * This call returns a mask (32bit) of the sensors that are supported by this 5921 * platform, then an array of sensor information structures, in order of sensor 5922 * type (but without gaps for unimplemented sensors). Each structure defines 5923 * the ranges for the corresponding sensor. An unused range is indicated by 5924 * equal limit values. If one range is used, a value outside that range results 5925 * in STATE_FATAL. If two ranges are used, a value outside the second range 5926 * results in STATE_FATAL while a value outside the first and inside the second 5927 * range results in STATE_WARNING. 5928 * 5929 * Sensor masks and sensor information arrays are organised into pages. For 5930 * backward compatibility, older host software can only use sensors in page 0. 5931 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 5932 * as the next page flag. 5933 * 5934 * If the request does not contain a PAGE value then firmware will only return 5935 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 5936 * 5937 * If the request contains a PAGE value then firmware responds with the sensor 5938 * mask and sensor information array for that page of sensors. In this case bit 5939 * 31 in the mask is set if another page exists. 5940 * 5941 * Locks required: None Returns: 0 5942 */ 5943 #define MC_CMD_SENSOR_INFO 0x41 5944 #undef MC_CMD_0x41_PRIVILEGE_CTG 5945 5946 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5947 5948 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 5949 #define MC_CMD_SENSOR_INFO_IN_LEN 0 5950 5951 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 5952 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 5953 /* Which page of sensors to report. 5954 * 5955 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 5956 * 5957 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 5958 */ 5959 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 5960 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4 5961 5962 /* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */ 5963 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8 5964 /* Which page of sensors to report. 5965 * 5966 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 5967 * 5968 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 5969 */ 5970 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0 5971 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4 5972 /* Flags controlling information retrieved */ 5973 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4 5974 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4 5975 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4 5976 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0 5977 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1 5978 5979 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 5980 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 5981 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 5982 #define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020 5983 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 5984 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8) 5985 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 5986 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 5987 /* enum: Controller temperature: degC */ 5988 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 5989 /* enum: Phy common temperature: degC */ 5990 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 5991 /* enum: Controller cooling: bool */ 5992 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 5993 /* enum: Phy 0 temperature: degC */ 5994 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 5995 /* enum: Phy 0 cooling: bool */ 5996 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 5997 /* enum: Phy 1 temperature: degC */ 5998 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 5999 /* enum: Phy 1 cooling: bool */ 6000 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6001 /* enum: 1.0v power: mV */ 6002 #define MC_CMD_SENSOR_IN_1V0 0x7 6003 /* enum: 1.2v power: mV */ 6004 #define MC_CMD_SENSOR_IN_1V2 0x8 6005 /* enum: 1.8v power: mV */ 6006 #define MC_CMD_SENSOR_IN_1V8 0x9 6007 /* enum: 2.5v power: mV */ 6008 #define MC_CMD_SENSOR_IN_2V5 0xa 6009 /* enum: 3.3v power: mV */ 6010 #define MC_CMD_SENSOR_IN_3V3 0xb 6011 /* enum: 12v power: mV */ 6012 #define MC_CMD_SENSOR_IN_12V0 0xc 6013 /* enum: 1.2v analogue power: mV */ 6014 #define MC_CMD_SENSOR_IN_1V2A 0xd 6015 /* enum: reference voltage: mV */ 6016 #define MC_CMD_SENSOR_IN_VREF 0xe 6017 /* enum: AOE FPGA power: mV */ 6018 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6019 /* enum: AOE FPGA temperature: degC */ 6020 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6021 /* enum: AOE FPGA PSU temperature: degC */ 6022 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6023 /* enum: AOE PSU temperature: degC */ 6024 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6025 /* enum: Fan 0 speed: RPM */ 6026 #define MC_CMD_SENSOR_FAN_0 0x13 6027 /* enum: Fan 1 speed: RPM */ 6028 #define MC_CMD_SENSOR_FAN_1 0x14 6029 /* enum: Fan 2 speed: RPM */ 6030 #define MC_CMD_SENSOR_FAN_2 0x15 6031 /* enum: Fan 3 speed: RPM */ 6032 #define MC_CMD_SENSOR_FAN_3 0x16 6033 /* enum: Fan 4 speed: RPM */ 6034 #define MC_CMD_SENSOR_FAN_4 0x17 6035 /* enum: AOE FPGA input power: mV */ 6036 #define MC_CMD_SENSOR_IN_VAOE 0x18 6037 /* enum: AOE FPGA current: mA */ 6038 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6039 /* enum: AOE FPGA input current: mA */ 6040 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6041 /* enum: NIC power consumption: W */ 6042 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6043 /* enum: 0.9v power voltage: mV */ 6044 #define MC_CMD_SENSOR_IN_0V9 0x1c 6045 /* enum: 0.9v power current: mA */ 6046 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6047 /* enum: 1.2v power current: mA */ 6048 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6049 /* enum: Not a sensor: reserved for the next page flag */ 6050 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6051 /* enum: 0.9v power voltage (at ADC): mV */ 6052 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6053 /* enum: Controller temperature 2: degC */ 6054 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6055 /* enum: Voltage regulator internal temperature: degC */ 6056 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6057 /* enum: 0.9V voltage regulator temperature: degC */ 6058 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6059 /* enum: 1.2V voltage regulator temperature: degC */ 6060 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6061 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6062 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6063 /* enum: controller internal temperature (internal ADC): degC */ 6064 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6065 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6066 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6067 /* enum: controller internal temperature (external ADC): degC */ 6068 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6069 /* enum: ambient temperature: degC */ 6070 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6071 /* enum: air flow: bool */ 6072 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6073 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6074 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6075 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6076 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6077 /* enum: Hotpoint temperature: degC */ 6078 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6079 /* enum: Port 0 PHY power switch over-current: bool */ 6080 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6081 /* enum: Port 1 PHY power switch over-current: bool */ 6082 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6083 /* enum: Mop-up microcontroller reference voltage: mV */ 6084 #define MC_CMD_SENSOR_MUM_VCC 0x30 6085 /* enum: 0.9v power phase A voltage: mV */ 6086 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6087 /* enum: 0.9v power phase A current: mA */ 6088 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6089 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6090 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6091 /* enum: 0.9v power phase B voltage: mV */ 6092 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6093 /* enum: 0.9v power phase B current: mA */ 6094 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6095 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6096 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6097 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6098 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6099 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6100 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6101 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6102 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6103 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6104 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6105 /* enum: CCOM RTS temperature: degC */ 6106 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 6107 /* enum: Not a sensor: reserved for the next page flag */ 6108 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6109 /* enum: controller internal temperature sensor voltage on master core 6110 * (internal ADC): mV 6111 */ 6112 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6113 /* enum: controller internal temperature on master core (internal ADC): degC */ 6114 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6115 /* enum: controller internal temperature sensor voltage on master core 6116 * (external ADC): mV 6117 */ 6118 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6119 /* enum: controller internal temperature on master core (external ADC): degC */ 6120 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6121 /* enum: controller internal temperature on slave core sensor voltage (internal 6122 * ADC): mV 6123 */ 6124 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6125 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6126 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6127 /* enum: controller internal temperature on slave core sensor voltage (external 6128 * ADC): mV 6129 */ 6130 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6131 /* enum: controller internal temperature on slave core (external ADC): degC */ 6132 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6133 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6134 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6135 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6136 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6137 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6138 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6139 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6140 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6141 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6142 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6143 /* enum: Controller die temperature (TDIODE): degC */ 6144 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 6145 /* enum: Board temperature (front): degC */ 6146 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 6147 /* enum: Board temperature (back): degC */ 6148 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 6149 /* enum: 1.8v power current: mA */ 6150 #define MC_CMD_SENSOR_IN_I1V8 0x51 6151 /* enum: 2.5v power current: mA */ 6152 #define MC_CMD_SENSOR_IN_I2V5 0x52 6153 /* enum: 3.3v power current: mA */ 6154 #define MC_CMD_SENSOR_IN_I3V3 0x53 6155 /* enum: 12v power current: mA */ 6156 #define MC_CMD_SENSOR_IN_I12V0 0x54 6157 /* enum: 1.3v power: mV */ 6158 #define MC_CMD_SENSOR_IN_1V3 0x55 6159 /* enum: 1.3v power current: mA */ 6160 #define MC_CMD_SENSOR_IN_I1V3 0x56 6161 /* enum: Engineering sensor 1 */ 6162 #define MC_CMD_SENSOR_ENGINEERING_1 0x57 6163 /* enum: Engineering sensor 2 */ 6164 #define MC_CMD_SENSOR_ENGINEERING_2 0x58 6165 /* enum: Engineering sensor 3 */ 6166 #define MC_CMD_SENSOR_ENGINEERING_3 0x59 6167 /* enum: Engineering sensor 4 */ 6168 #define MC_CMD_SENSOR_ENGINEERING_4 0x5a 6169 /* enum: Engineering sensor 5 */ 6170 #define MC_CMD_SENSOR_ENGINEERING_5 0x5b 6171 /* enum: Engineering sensor 6 */ 6172 #define MC_CMD_SENSOR_ENGINEERING_6 0x5c 6173 /* enum: Engineering sensor 7 */ 6174 #define MC_CMD_SENSOR_ENGINEERING_7 0x5d 6175 /* enum: Engineering sensor 8 */ 6176 #define MC_CMD_SENSOR_ENGINEERING_8 0x5e 6177 /* enum: Not a sensor: reserved for the next page flag */ 6178 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f 6179 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6180 #define MC_CMD_SENSOR_ENTRY_OFST 4 6181 #define MC_CMD_SENSOR_ENTRY_LEN 8 6182 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6183 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6184 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6185 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6186 #define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 6187 6188 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6189 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6190 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6191 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020 6192 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6193 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8) 6194 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6195 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4 6196 /* Enum values, see field(s): */ 6197 /* MC_CMD_SENSOR_INFO_OUT */ 6198 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0 6199 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6200 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6201 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6202 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6203 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6204 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6205 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6206 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6207 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6208 /* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */ 6209 6210 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6211 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6212 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6213 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6214 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6215 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6216 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6217 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6218 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6219 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6220 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6221 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6222 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6223 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6224 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6225 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6226 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6227 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6228 6229 6230 /***********************************/ 6231 /* MC_CMD_READ_SENSORS 6232 * Returns the current reading from each sensor. DMAs an array of sensor 6233 * readings, in order of sensor type (but without gaps for unimplemented 6234 * sensors), into host memory. Each array element is a 6235 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6236 * 6237 * If the request does not contain the LENGTH field then only sensors 0 to 30 6238 * are reported, to avoid DMA buffer overflow in older host software. If the 6239 * sensor reading require more space than the LENGTH allows, then return 6240 * EINVAL. 6241 * 6242 * The MC will send a SENSOREVT event every time any sensor changes state. The 6243 * driver is responsible for ensuring that it doesn't miss any events. The 6244 * board will function normally if all sensors are in STATE_OK or 6245 * STATE_WARNING. Otherwise the board should not be expected to function. 6246 */ 6247 #define MC_CMD_READ_SENSORS 0x42 6248 #undef MC_CMD_0x42_PRIVILEGE_CTG 6249 6250 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6251 6252 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6253 #define MC_CMD_READ_SENSORS_IN_LEN 8 6254 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). 6255 * 6256 * If the address is 0xffffffffffffffff send the readings in the response (used 6257 * by cmdclient). 6258 */ 6259 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6260 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6261 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6262 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6263 6264 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6265 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6266 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). 6267 * 6268 * If the address is 0xffffffffffffffff send the readings in the response (used 6269 * by cmdclient). 6270 */ 6271 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6272 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6273 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6274 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6275 /* Size in bytes of host buffer. */ 6276 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6277 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4 6278 6279 /* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */ 6280 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16 6281 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). 6282 * 6283 * If the address is 0xffffffffffffffff send the readings in the response (used 6284 * by cmdclient). 6285 */ 6286 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0 6287 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8 6288 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0 6289 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4 6290 /* Size in bytes of host buffer. */ 6291 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8 6292 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4 6293 /* Flags controlling information retrieved */ 6294 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12 6295 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4 6296 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12 6297 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0 6298 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1 6299 6300 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6301 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6302 6303 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6304 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6305 6306 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6307 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6308 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6309 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6310 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6311 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6312 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6313 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6314 /* enum: Ok. */ 6315 #define MC_CMD_SENSOR_STATE_OK 0x0 6316 /* enum: Breached warning threshold. */ 6317 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6318 /* enum: Breached fatal threshold. */ 6319 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6320 /* enum: Fault with sensor. */ 6321 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6322 /* enum: Sensor is working but does not currently have a reading. */ 6323 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6324 /* enum: Sensor initialisation failed. */ 6325 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6326 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6327 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6328 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6329 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6330 /* Enum values, see field(s): */ 6331 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6332 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6333 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6334 6335 6336 /***********************************/ 6337 /* MC_CMD_GET_PHY_STATE 6338 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6339 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6340 * code: 0 6341 */ 6342 #define MC_CMD_GET_PHY_STATE 0x43 6343 #undef MC_CMD_0x43_PRIVILEGE_CTG 6344 6345 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6346 6347 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6348 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6349 6350 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6351 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6352 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6353 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4 6354 /* enum: Ok. */ 6355 #define MC_CMD_PHY_STATE_OK 0x1 6356 /* enum: Faulty. */ 6357 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6358 6359 6360 /***********************************/ 6361 /* MC_CMD_SETUP_8021QBB 6362 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6363 * disable 802.Qbb for a given priority. 6364 */ 6365 #define MC_CMD_SETUP_8021QBB 0x44 6366 6367 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6368 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6369 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6370 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6371 6372 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6373 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6374 6375 6376 /***********************************/ 6377 /* MC_CMD_WOL_FILTER_GET 6378 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6379 */ 6380 #define MC_CMD_WOL_FILTER_GET 0x45 6381 #undef MC_CMD_0x45_PRIVILEGE_CTG 6382 6383 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6384 6385 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6386 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6387 6388 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6389 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6390 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6391 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 6392 6393 6394 /***********************************/ 6395 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6396 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6397 * Returns: 0, ENOSYS 6398 */ 6399 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6400 #undef MC_CMD_0x46_PRIVILEGE_CTG 6401 6402 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6403 6404 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6405 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6406 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6407 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020 6408 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6409 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4) 6410 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6411 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 6412 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6413 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6414 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6415 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6416 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6417 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6418 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254 6419 6420 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6421 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6422 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6423 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 6424 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6425 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6426 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6427 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 6428 6429 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6430 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6431 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6432 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 6433 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6434 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6435 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6436 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6437 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6438 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6439 6440 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6441 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6442 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6443 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 6444 6445 6446 /***********************************/ 6447 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6448 * Remove a protocol offload from NIC for lights-out state. Locks required: 6449 * None. Returns: 0, ENOSYS 6450 */ 6451 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6452 #undef MC_CMD_0x47_PRIVILEGE_CTG 6453 6454 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6455 6456 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6457 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6458 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6459 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 6460 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6461 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 6462 6463 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6464 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6465 6466 6467 /***********************************/ 6468 /* MC_CMD_MAC_RESET_RESTORE 6469 * Restore MAC after block reset. Locks required: None. Returns: 0. 6470 */ 6471 #define MC_CMD_MAC_RESET_RESTORE 0x48 6472 6473 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6474 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6475 6476 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6477 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6478 6479 6480 /***********************************/ 6481 /* MC_CMD_TESTASSERT 6482 * Deliberately trigger an assert-detonation in the firmware for testing 6483 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6484 * required: None Returns: 0 6485 */ 6486 #define MC_CMD_TESTASSERT 0x49 6487 #undef MC_CMD_0x49_PRIVILEGE_CTG 6488 6489 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6490 6491 /* MC_CMD_TESTASSERT_IN msgrequest */ 6492 #define MC_CMD_TESTASSERT_IN_LEN 0 6493 6494 /* MC_CMD_TESTASSERT_OUT msgresponse */ 6495 #define MC_CMD_TESTASSERT_OUT_LEN 0 6496 6497 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 6498 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 6499 /* How to provoke the assertion */ 6500 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 6501 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 6502 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 6503 * you're testing firmware, this is what you want. 6504 */ 6505 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 6506 /* enum: Assert using assert(0); */ 6507 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 6508 /* enum: Deliberately trigger a watchdog */ 6509 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 6510 /* enum: Deliberately trigger a trap by loading from an invalid address */ 6511 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 6512 /* enum: Deliberately trigger a trap by storing to an invalid address */ 6513 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 6514 /* enum: Jump to an invalid address */ 6515 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 6516 6517 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 6518 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 6519 6520 6521 /***********************************/ 6522 /* MC_CMD_WORKAROUND 6523 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 6524 * understand the given workaround number - which should not be treated as a 6525 * hard error by client code. This op does not imply any semantics about each 6526 * workaround, that's between the driver and the mcfw on a per-workaround 6527 * basis. Locks required: None. Returns: 0, EINVAL . 6528 */ 6529 #define MC_CMD_WORKAROUND 0x4a 6530 #undef MC_CMD_0x4a_PRIVILEGE_CTG 6531 6532 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6533 6534 /* MC_CMD_WORKAROUND_IN msgrequest */ 6535 #define MC_CMD_WORKAROUND_IN_LEN 8 6536 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 6537 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 6538 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 6539 /* enum: Bug 17230 work around. */ 6540 #define MC_CMD_WORKAROUND_BUG17230 0x1 6541 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 6542 #define MC_CMD_WORKAROUND_BUG35388 0x2 6543 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 6544 #define MC_CMD_WORKAROUND_BUG35017 0x3 6545 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 6546 #define MC_CMD_WORKAROUND_BUG41750 0x4 6547 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 6548 * - before adding code that queries this workaround, remember that there's 6549 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 6550 * and will hence (incorrectly) report that the bug doesn't exist. 6551 */ 6552 #define MC_CMD_WORKAROUND_BUG42008 0x5 6553 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 6554 * This feature cannot be turned on/off while there are any filters already 6555 * present. The behaviour in such case depends on the acting client's privilege 6556 * level. If the client has the admin privilege, then all functions that have 6557 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 6558 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 6559 */ 6560 #define MC_CMD_WORKAROUND_BUG26807 0x6 6561 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 6562 #define MC_CMD_WORKAROUND_BUG61265 0x7 6563 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 6564 * the workaround 6565 */ 6566 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 6567 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4 6568 6569 /* MC_CMD_WORKAROUND_OUT msgresponse */ 6570 #define MC_CMD_WORKAROUND_OUT_LEN 0 6571 6572 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 6573 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 6574 */ 6575 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 6576 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 6577 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 6578 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0 6579 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 6580 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 6581 6582 6583 /***********************************/ 6584 /* MC_CMD_GET_PHY_MEDIA_INFO 6585 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 6586 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 6587 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 6588 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 6589 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 6590 * Anything else: currently undefined. Locks required: None. Return code: 0. 6591 */ 6592 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 6593 #undef MC_CMD_0x4b_PRIVILEGE_CTG 6594 6595 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6596 6597 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 6598 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 6599 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 6600 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4 6601 6602 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 6603 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 6604 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 6605 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020 6606 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 6607 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1) 6608 /* in bytes */ 6609 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 6610 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4 6611 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 6612 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 6613 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 6614 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 6615 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016 6616 6617 6618 /***********************************/ 6619 /* MC_CMD_NVRAM_TEST 6620 * Test a particular NVRAM partition for valid contents (where "valid" depends 6621 * on the type of partition). 6622 */ 6623 #define MC_CMD_NVRAM_TEST 0x4c 6624 #undef MC_CMD_0x4c_PRIVILEGE_CTG 6625 6626 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6627 6628 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 6629 #define MC_CMD_NVRAM_TEST_IN_LEN 4 6630 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 6631 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4 6632 /* Enum values, see field(s): */ 6633 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6634 6635 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 6636 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 6637 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 6638 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4 6639 /* enum: Passed. */ 6640 #define MC_CMD_NVRAM_TEST_PASS 0x0 6641 /* enum: Failed. */ 6642 #define MC_CMD_NVRAM_TEST_FAIL 0x1 6643 /* enum: Not supported. */ 6644 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 6645 6646 6647 /***********************************/ 6648 /* MC_CMD_MRSFP_TWEAK 6649 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 6650 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 6651 * they are configured first. Locks required: None. Return code: 0, EINVAL. 6652 */ 6653 #define MC_CMD_MRSFP_TWEAK 0x4d 6654 6655 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 6656 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 6657 /* 0-6 low->high de-emph. */ 6658 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 6659 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 6660 /* 0-8 low->high ref.V */ 6661 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 6662 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 6663 /* 0-8 0-8 low->high boost */ 6664 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 6665 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 6666 /* 0-8 low->high ref.V */ 6667 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 6668 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 6669 6670 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 6671 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 6672 6673 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 6674 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 6675 /* input bits */ 6676 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 6677 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 6678 /* output bits */ 6679 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 6680 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 6681 /* direction */ 6682 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 6683 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 6684 /* enum: Out. */ 6685 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 6686 /* enum: In. */ 6687 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 6688 6689 6690 /***********************************/ 6691 /* MC_CMD_SENSOR_SET_LIMS 6692 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 6693 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 6694 * of range. 6695 */ 6696 #define MC_CMD_SENSOR_SET_LIMS 0x4e 6697 #undef MC_CMD_0x4e_PRIVILEGE_CTG 6698 6699 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6700 6701 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 6702 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 6703 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 6704 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 6705 /* Enum values, see field(s): */ 6706 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6707 /* interpretation is is sensor-specific. */ 6708 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 6709 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 6710 /* interpretation is is sensor-specific. */ 6711 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 6712 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 6713 /* interpretation is is sensor-specific. */ 6714 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 6715 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 6716 /* interpretation is is sensor-specific. */ 6717 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 6718 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 6719 6720 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 6721 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 6722 6723 6724 /***********************************/ 6725 /* MC_CMD_GET_RESOURCE_LIMITS 6726 */ 6727 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 6728 6729 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 6730 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 6731 6732 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 6733 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 6734 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 6735 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 6736 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 6737 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 6738 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 6739 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 6740 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 6741 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 6742 6743 6744 /***********************************/ 6745 /* MC_CMD_NVRAM_PARTITIONS 6746 * Reads the list of available virtual NVRAM partition types. Locks required: 6747 * none. Returns: 0, EINVAL (bad type). 6748 */ 6749 #define MC_CMD_NVRAM_PARTITIONS 0x51 6750 #undef MC_CMD_0x51_PRIVILEGE_CTG 6751 6752 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6753 6754 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 6755 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 6756 6757 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 6758 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 6759 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 6760 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020 6761 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 6762 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4) 6763 /* total number of partitions */ 6764 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 6765 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4 6766 /* type ID code for each of NUM_PARTITIONS partitions */ 6767 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 6768 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 6769 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 6770 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 6771 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254 6772 6773 6774 /***********************************/ 6775 /* MC_CMD_NVRAM_METADATA 6776 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 6777 * none. Returns: 0, EINVAL (bad type). 6778 */ 6779 #define MC_CMD_NVRAM_METADATA 0x52 6780 #undef MC_CMD_0x52_PRIVILEGE_CTG 6781 6782 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6783 6784 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 6785 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 6786 /* Partition type ID code */ 6787 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 6788 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4 6789 6790 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 6791 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 6792 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 6793 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020 6794 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 6795 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1) 6796 /* Partition type ID code */ 6797 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 6798 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 6799 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 6800 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 6801 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4 6802 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 6803 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 6804 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4 6805 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 6806 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 6807 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4 6808 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 6809 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 6810 /* Subtype ID code for content of this partition */ 6811 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 6812 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 6813 /* 1st component of W.X.Y.Z version number for content of this partition */ 6814 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 6815 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 6816 /* 2nd component of W.X.Y.Z version number for content of this partition */ 6817 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 6818 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 6819 /* 3rd component of W.X.Y.Z version number for content of this partition */ 6820 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 6821 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 6822 /* 4th component of W.X.Y.Z version number for content of this partition */ 6823 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 6824 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 6825 /* Zero-terminated string describing the content of this partition */ 6826 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 6827 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 6828 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 6829 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 6830 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000 6831 6832 6833 /***********************************/ 6834 /* MC_CMD_GET_MAC_ADDRESSES 6835 * Returns the base MAC, count and stride for the requesting function 6836 */ 6837 #define MC_CMD_GET_MAC_ADDRESSES 0x55 6838 #undef MC_CMD_0x55_PRIVILEGE_CTG 6839 6840 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6841 6842 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 6843 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 6844 6845 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 6846 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 6847 /* Base MAC address */ 6848 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 6849 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 6850 /* Padding */ 6851 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 6852 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 6853 /* Number of allocated MAC addresses */ 6854 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 6855 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 6856 /* Spacing of allocated MAC addresses */ 6857 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 6858 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 6859 6860 6861 /***********************************/ 6862 /* MC_CMD_CLP 6863 * Perform a CLP related operation, see SF-110495-PS for details of CLP 6864 * processing. This command has been extended to accomodate the requirements of 6865 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC, 6866 * SF-120509-TC and SF-117282-PS. 6867 */ 6868 #define MC_CMD_CLP 0x56 6869 #undef MC_CMD_0x56_PRIVILEGE_CTG 6870 6871 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6872 6873 /* MC_CMD_CLP_IN msgrequest */ 6874 #define MC_CMD_CLP_IN_LEN 4 6875 /* Sub operation */ 6876 #define MC_CMD_CLP_IN_OP_OFST 0 6877 #define MC_CMD_CLP_IN_OP_LEN 4 6878 /* enum: Return to factory default settings */ 6879 #define MC_CMD_CLP_OP_DEFAULT 0x1 6880 /* enum: Set MAC address */ 6881 #define MC_CMD_CLP_OP_SET_MAC 0x2 6882 /* enum: Get MAC address */ 6883 #define MC_CMD_CLP_OP_GET_MAC 0x3 6884 /* enum: Set UEFI/GPXE boot mode */ 6885 #define MC_CMD_CLP_OP_SET_BOOT 0x4 6886 /* enum: Get UEFI/GPXE boot mode */ 6887 #define MC_CMD_CLP_OP_GET_BOOT 0x5 6888 6889 /* MC_CMD_CLP_OUT msgresponse */ 6890 #define MC_CMD_CLP_OUT_LEN 0 6891 6892 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 6893 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 6894 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6895 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6896 6897 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 6898 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 6899 6900 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 6901 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 6902 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6903 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6904 /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 6905 * restores the permanent (factory-programmed) MAC address associated with the 6906 * port. A non-zero MAC address persists until a PCIe reset or a power cycle. 6907 */ 6908 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 6909 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 6910 /* Padding */ 6911 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 6912 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 6913 6914 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 6915 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 6916 6917 /* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */ 6918 #define MC_CMD_CLP_IN_SET_MAC_V2_LEN 16 6919 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6920 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6921 /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 6922 * restores the permanent (factory-programmed) MAC address associated with the 6923 * port. A non-zero MAC address persists until a PCIe reset or a power cycle. 6924 */ 6925 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4 6926 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6 6927 /* Padding */ 6928 #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10 6929 #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2 6930 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12 6931 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4 6932 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12 6933 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0 6934 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1 6935 6936 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 6937 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 6938 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6939 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6940 6941 /* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */ 6942 #define MC_CMD_CLP_IN_GET_MAC_V2_LEN 8 6943 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6944 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6945 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4 6946 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4 6947 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4 6948 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0 6949 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1 6950 6951 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 6952 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 6953 /* MAC address assigned to port */ 6954 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 6955 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 6956 /* Padding */ 6957 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 6958 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 6959 6960 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 6961 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 6962 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6963 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6964 /* Boot flag */ 6965 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 6966 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 6967 6968 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 6969 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 6970 6971 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 6972 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 6973 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6974 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6975 6976 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 6977 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 6978 /* Boot flag */ 6979 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 6980 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 6981 /* Padding */ 6982 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 6983 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 6984 6985 6986 /***********************************/ 6987 /* MC_CMD_MUM 6988 * Perform a MUM operation 6989 */ 6990 #define MC_CMD_MUM 0x57 6991 #undef MC_CMD_0x57_PRIVILEGE_CTG 6992 6993 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6994 6995 /* MC_CMD_MUM_IN msgrequest */ 6996 #define MC_CMD_MUM_IN_LEN 4 6997 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 6998 #define MC_CMD_MUM_IN_OP_HDR_LEN 4 6999 #define MC_CMD_MUM_IN_OP_OFST 0 7000 #define MC_CMD_MUM_IN_OP_LBN 0 7001 #define MC_CMD_MUM_IN_OP_WIDTH 8 7002 /* enum: NULL MCDI command to MUM */ 7003 #define MC_CMD_MUM_OP_NULL 0x1 7004 /* enum: Get MUM version */ 7005 #define MC_CMD_MUM_OP_GET_VERSION 0x2 7006 /* enum: Issue raw I2C command to MUM */ 7007 #define MC_CMD_MUM_OP_RAW_CMD 0x3 7008 /* enum: Read from registers on devices connected to MUM. */ 7009 #define MC_CMD_MUM_OP_READ 0x4 7010 /* enum: Write to registers on devices connected to MUM. */ 7011 #define MC_CMD_MUM_OP_WRITE 0x5 7012 /* enum: Control UART logging. */ 7013 #define MC_CMD_MUM_OP_LOG 0x6 7014 /* enum: Operations on MUM GPIO lines */ 7015 #define MC_CMD_MUM_OP_GPIO 0x7 7016 /* enum: Get sensor readings from MUM */ 7017 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 7018 /* enum: Initiate clock programming on the MUM */ 7019 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 7020 /* enum: Initiate FPGA load from flash on the MUM */ 7021 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 7022 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 7023 * MUM ATB 7024 */ 7025 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 7026 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 7027 * operations 7028 */ 7029 #define MC_CMD_MUM_OP_QSFP 0xc 7030 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 7031 * level) from MUM 7032 */ 7033 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 7034 7035 /* MC_CMD_MUM_IN_NULL msgrequest */ 7036 #define MC_CMD_MUM_IN_NULL_LEN 4 7037 /* MUM cmd header */ 7038 #define MC_CMD_MUM_IN_CMD_OFST 0 7039 #define MC_CMD_MUM_IN_CMD_LEN 4 7040 7041 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 7042 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 7043 /* MUM cmd header */ 7044 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7045 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7046 7047 /* MC_CMD_MUM_IN_READ msgrequest */ 7048 #define MC_CMD_MUM_IN_READ_LEN 16 7049 /* MUM cmd header */ 7050 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7051 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7052 /* ID of (device connected to MUM) to read from registers of */ 7053 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 7054 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 7055 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7056 #define MC_CMD_MUM_DEV_HITTITE 0x1 7057 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 7058 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 7059 /* 32-bit address to read from */ 7060 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 7061 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4 7062 /* Number of words to read. */ 7063 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 7064 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 7065 7066 /* MC_CMD_MUM_IN_WRITE msgrequest */ 7067 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 7068 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 7069 #define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020 7070 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 7071 #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4) 7072 /* MUM cmd header */ 7073 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7074 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7075 /* ID of (device connected to MUM) to write to registers of */ 7076 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 7077 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 7078 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7079 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 7080 /* 32-bit address to write to */ 7081 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 7082 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 7083 /* Words to write */ 7084 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 7085 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 7086 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 7087 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 7088 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252 7089 7090 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 7091 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 7092 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 7093 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020 7094 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 7095 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1) 7096 /* MUM cmd header */ 7097 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7098 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7099 /* MUM I2C cmd code */ 7100 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 7101 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 7102 /* Number of bytes to write */ 7103 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 7104 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 7105 /* Number of bytes to read */ 7106 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7107 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 7108 /* Bytes to write */ 7109 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7110 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7111 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7112 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7113 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004 7114 7115 /* MC_CMD_MUM_IN_LOG msgrequest */ 7116 #define MC_CMD_MUM_IN_LOG_LEN 8 7117 /* MUM cmd header */ 7118 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7119 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7120 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7121 #define MC_CMD_MUM_IN_LOG_OP_LEN 4 7122 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7123 7124 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7125 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7126 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7127 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7128 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7129 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 7130 /* Enable/disable debug output to UART */ 7131 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7132 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 7133 7134 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7135 #define MC_CMD_MUM_IN_GPIO_LEN 8 7136 /* MUM cmd header */ 7137 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7138 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7139 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7140 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 7141 #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4 7142 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7143 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7144 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7145 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7146 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7147 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7148 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7149 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7150 7151 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7152 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7153 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7154 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7155 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7156 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 7157 7158 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7159 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7160 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7161 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7162 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7163 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 7164 /* The first 32-bit word to be written to the GPIO OUT register. */ 7165 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7166 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 7167 /* The second 32-bit word to be written to the GPIO OUT register. */ 7168 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7169 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 7170 7171 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7172 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7173 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7174 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7175 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7176 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 7177 7178 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7179 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7180 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7181 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7182 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7183 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 7184 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7185 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7186 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 7187 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7188 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7189 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 7190 7191 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7192 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7193 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7194 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7195 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7196 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 7197 7198 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7199 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7200 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7201 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7202 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7203 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 7204 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4 7205 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7206 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7207 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7208 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7209 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7210 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7211 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4 7212 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7213 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7214 7215 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7216 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7217 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7218 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7219 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7220 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 7221 7222 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7223 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7224 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7225 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7226 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7227 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 7228 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4 7229 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7230 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7231 7232 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7233 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7234 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7235 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7236 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7237 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 7238 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4 7239 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7240 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7241 7242 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7243 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7244 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7245 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7246 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7247 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 7248 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4 7249 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7250 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7251 7252 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7253 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7254 /* MUM cmd header */ 7255 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7256 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7257 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7258 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 7259 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4 7260 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7261 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7262 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4 7263 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7264 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7265 7266 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7267 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7268 /* MUM cmd header */ 7269 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7270 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7271 /* Bit-mask of clocks to be programmed */ 7272 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7273 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 7274 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7275 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7276 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7277 /* Control flags for clock programming */ 7278 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7279 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 7280 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8 7281 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7282 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7283 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8 7284 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 7285 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 7286 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8 7287 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 7288 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 7289 7290 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7291 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7292 /* MUM cmd header */ 7293 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7294 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7295 /* Enable/Disable FPGA config from flash */ 7296 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7297 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 7298 7299 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7300 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7301 /* MUM cmd header */ 7302 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7303 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7304 7305 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7306 #define MC_CMD_MUM_IN_QSFP_LEN 12 7307 /* MUM cmd header */ 7308 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7309 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7310 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7311 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 7312 #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4 7313 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7314 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7315 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7316 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7317 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7318 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7319 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7320 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7321 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7322 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 7323 7324 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7325 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7326 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7327 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7328 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7329 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 7330 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7331 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 7332 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7333 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 7334 7335 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7336 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7337 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7338 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7339 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7340 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 7341 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7342 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 7343 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7344 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 7345 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7346 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 7347 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7348 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 7349 7350 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7351 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7352 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7353 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7354 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7355 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 7356 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7357 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 7358 7359 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7360 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7361 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7362 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7363 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7364 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 7365 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7366 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 7367 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7368 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 7369 7370 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7371 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7372 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7373 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7374 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7375 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 7376 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7377 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 7378 7379 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7380 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7381 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7382 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7383 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7384 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 7385 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7386 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 7387 7388 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 7389 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 7390 /* MUM cmd header */ 7391 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7392 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 7393 7394 /* MC_CMD_MUM_OUT msgresponse */ 7395 #define MC_CMD_MUM_OUT_LEN 0 7396 7397 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7398 #define MC_CMD_MUM_OUT_NULL_LEN 0 7399 7400 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7401 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7402 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7403 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 7404 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7405 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7406 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7407 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7408 7409 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7410 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7411 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7412 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020 7413 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7414 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1) 7415 /* returned data */ 7416 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7417 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7418 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7419 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7420 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020 7421 7422 /* MC_CMD_MUM_OUT_READ msgresponse */ 7423 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7424 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7425 #define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020 7426 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7427 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4) 7428 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7429 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7430 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7431 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7432 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255 7433 7434 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7435 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7436 7437 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7438 #define MC_CMD_MUM_OUT_LOG_LEN 0 7439 7440 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7441 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7442 7443 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7444 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7445 /* The first 32-bit word read from the GPIO IN register. */ 7446 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7447 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 7448 /* The second 32-bit word read from the GPIO IN register. */ 7449 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7450 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 7451 7452 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7453 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7454 7455 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7456 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7457 /* The first 32-bit word read from the GPIO OUT register. */ 7458 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7459 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 7460 /* The second 32-bit word read from the GPIO OUT register. */ 7461 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7462 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 7463 7464 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7465 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7466 7467 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7468 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7469 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7470 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 7471 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7472 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 7473 7474 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7475 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7476 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7477 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 7478 7479 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7480 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7481 7482 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7483 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7484 7485 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7486 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7487 7488 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7489 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7490 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7491 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020 7492 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7493 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4) 7494 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7495 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7496 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7497 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7498 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255 7499 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0 7500 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7501 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7502 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0 7503 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7504 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7505 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0 7506 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7507 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7508 7509 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7510 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7511 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7512 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 7513 7514 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7515 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7516 7517 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7518 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7519 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7520 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 7521 7522 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7523 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7524 7525 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7526 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7527 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7528 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 7529 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7530 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 7531 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4 7532 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7533 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7534 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4 7535 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7536 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7537 7538 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7539 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7540 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7541 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 7542 7543 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7544 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7545 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7546 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020 7547 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7548 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) 7549 /* in bytes */ 7550 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7551 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 7552 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7553 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7554 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7555 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7556 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 7557 7558 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7559 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7560 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7561 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 7562 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7563 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 7564 7565 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7566 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7567 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7568 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 7569 7570 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 7571 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 7572 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 7573 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016 7574 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 7575 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8) 7576 /* Discrete (soldered) DDR resistor strap info */ 7577 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 7578 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 7579 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0 7580 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 7581 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 7582 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0 7583 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 7584 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 7585 /* Number of SODIMM info records */ 7586 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 7587 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 7588 /* Array of SODIMM info records */ 7589 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 7590 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 7591 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 7592 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 7593 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 7594 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 7595 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126 7596 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8 7597 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 7598 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 7599 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 7600 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 7601 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 7602 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 7603 /* enum: Total number of SODIMM banks */ 7604 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 7605 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8 7606 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 7607 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 7608 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8 7609 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 7610 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 7611 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8 7612 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 7613 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 7614 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 7615 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 7616 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 7617 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 7618 /* enum: Values 5-15 are reserved for future usage */ 7619 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 7620 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8 7621 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 7622 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 7623 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8 7624 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 7625 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 7626 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8 7627 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 7628 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 7629 /* enum: No module present */ 7630 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 7631 /* enum: Module present supported and powered on */ 7632 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 7633 /* enum: Module present but bad type */ 7634 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 7635 /* enum: Module present but incompatible voltage */ 7636 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 7637 /* enum: Module present but unknown SPD */ 7638 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 7639 /* enum: Module present but slot cannot support it */ 7640 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 7641 /* enum: Modules may or may not be present, but cannot establish contact by I2C 7642 */ 7643 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 7644 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8 7645 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 7646 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 7647 7648 /* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This 7649 * should match the equivalent structure in the sensor_query SPHINX service. 7650 */ 7651 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24 7652 /* A value below this will trigger a warning event. */ 7653 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0 7654 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4 7655 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0 7656 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32 7657 /* A value below this will trigger a critical event. */ 7658 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4 7659 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4 7660 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32 7661 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32 7662 /* A value below this will shut down the card. */ 7663 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8 7664 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4 7665 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64 7666 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32 7667 /* A value above this will trigger a warning event. */ 7668 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12 7669 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4 7670 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96 7671 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32 7672 /* A value above this will trigger a critical event. */ 7673 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16 7674 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4 7675 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128 7676 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32 7677 /* A value above this will shut down the card. */ 7678 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20 7679 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4 7680 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160 7681 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32 7682 7683 /* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor. 7684 * This should match the equivalent structure in the sensor_query SPHINX 7685 * service. 7686 */ 7687 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64 7688 /* The handle used to identify the sensor in calls to 7689 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES 7690 */ 7691 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0 7692 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4 7693 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0 7694 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32 7695 /* A human-readable name for the sensor (zero terminated string, max 32 bytes) 7696 */ 7697 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4 7698 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32 7699 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32 7700 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256 7701 /* The type of the sensor device, and by implication the unit of that the 7702 * values will be reported in 7703 */ 7704 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36 7705 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4 7706 /* enum: A voltage sensor. Unit is mV */ 7707 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0 7708 /* enum: A current sensor. Unit is mA */ 7709 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1 7710 /* enum: A power sensor. Unit is mW */ 7711 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2 7712 /* enum: A temperature sensor. Unit is Celsius */ 7713 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3 7714 /* enum: A cooling fan sensor. Unit is RPM */ 7715 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4 7716 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288 7717 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32 7718 /* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */ 7719 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40 7720 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24 7721 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320 7722 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192 7723 7724 /* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor. 7725 * This should match the equivalent structure in the sensor_query SPHINX 7726 * service. 7727 */ 7728 #define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12 7729 /* The handle used to identify the sensor */ 7730 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0 7731 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4 7732 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0 7733 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32 7734 /* The current value of the sensor */ 7735 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4 7736 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4 7737 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32 7738 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32 7739 /* The sensor's condition, e.g. good, broken or removed */ 7740 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8 7741 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4 7742 /* enum: Sensor working normally within limits */ 7743 #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0 7744 /* enum: Warning threshold breached */ 7745 #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1 7746 /* enum: Critical threshold breached */ 7747 #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2 7748 /* enum: Fatal threshold breached */ 7749 #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3 7750 /* enum: Sensor not working */ 7751 #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4 7752 /* enum: Sensor working but no reading available */ 7753 #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5 7754 /* enum: Sensor initialization failed */ 7755 #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6 7756 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64 7757 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32 7758 7759 7760 /***********************************/ 7761 /* MC_CMD_DYNAMIC_SENSORS_LIST 7762 * Return a complete list of handles for sensors currently managed by the MC, 7763 * and a generation count for this version of the sensor table. On systems 7764 * advertising the DYNAMIC_SENSORS capability bit, this replaces the 7765 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors 7766 * added by the NMC. 7767 * 7768 * Sensor handles are persistent for the lifetime of the sensor and are used to 7769 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and 7770 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES. 7771 * 7772 * The generation count is maintained by the MC, is persistent across reboots 7773 * and will be incremented each time the sensor table is modified. When the 7774 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated 7775 * containing the new generation count. The driver should compare this against 7776 * the current generation count, and if it is different, call 7777 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table. 7778 * 7779 * The sensor count is provided to allow a future path to supporting more than 7780 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e. 7781 * the maximum number that will fit in a single response. As this is a fairly 7782 * large number (253) it is not anticipated that this will be needed in the 7783 * near future, so can currently be ignored. 7784 * 7785 * On Riverhead this command is implemented as a a wrapper for `list` in the 7786 * sensor_query SPHINX service. 7787 */ 7788 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66 7789 #undef MC_CMD_0x66_PRIVILEGE_CTG 7790 7791 #define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7792 7793 /* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */ 7794 #define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0 7795 7796 /* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */ 7797 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8 7798 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252 7799 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020 7800 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num)) 7801 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4) 7802 /* Generation count, which will be updated each time a sensor is added to or 7803 * removed from the MC sensor table. 7804 */ 7805 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0 7806 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4 7807 /* Number of sensors managed by the MC. Note that in principle, this can be 7808 * larger than the size of the HANDLES array. 7809 */ 7810 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4 7811 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4 7812 /* Array of sensor handles */ 7813 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8 7814 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4 7815 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0 7816 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61 7817 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253 7818 7819 7820 /***********************************/ 7821 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 7822 * Get descriptions for a set of sensors, specified as an array of sensor 7823 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST 7824 * 7825 * Any handles which do not correspond to a sensor currently managed by the MC 7826 * will be dropped from from the response. This may happen when a sensor table 7827 * update is in progress, and effectively means the set of usable sensors is 7828 * the intersection between the sets of sensors known to the driver and the MC. 7829 * 7830 * On Riverhead this command is implemented as a a wrapper for 7831 * `get_descriptions` in the sensor_query SPHINX service. 7832 */ 7833 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67 7834 #undef MC_CMD_0x67_PRIVILEGE_CTG 7835 7836 #define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7837 7838 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */ 7839 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0 7840 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252 7841 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020 7842 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num)) 7843 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4) 7844 /* Array of sensor handles */ 7845 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0 7846 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4 7847 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0 7848 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63 7849 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255 7850 7851 /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */ 7852 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0 7853 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192 7854 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960 7855 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num)) 7856 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64) 7857 /* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */ 7858 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0 7859 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64 7860 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0 7861 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3 7862 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15 7863 7864 7865 /***********************************/ 7866 /* MC_CMD_DYNAMIC_SENSORS_GET_READINGS 7867 * Read the state and value for a set of sensors, specified as an array of 7868 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. 7869 * 7870 * In the case of a broken sensor, then the state of the response's 7871 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value 7872 * provided should be treated as erroneous. 7873 * 7874 * Any handles which do not correspond to a sensor currently managed by the MC 7875 * will be dropped from from the response. This may happen when a sensor table 7876 * update is in progress, and effectively means the set of usable sensors is 7877 * the intersection between the sets of sensors known to the driver and the MC. 7878 * 7879 * On Riverhead this command is implemented as a a wrapper for `get_readings` 7880 * in the sensor_query SPHINX service. 7881 */ 7882 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68 7883 #undef MC_CMD_0x68_PRIVILEGE_CTG 7884 7885 #define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7886 7887 /* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */ 7888 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0 7889 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252 7890 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020 7891 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num)) 7892 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4) 7893 /* Array of sensor handles */ 7894 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0 7895 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4 7896 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0 7897 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63 7898 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255 7899 7900 /* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */ 7901 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0 7902 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252 7903 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020 7904 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num)) 7905 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12) 7906 /* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */ 7907 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0 7908 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12 7909 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0 7910 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21 7911 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85 7912 7913 7914 /***********************************/ 7915 /* MC_CMD_EVENT_CTRL 7916 * Configure which categories of unsolicited events the driver expects to 7917 * receive (Riverhead). 7918 */ 7919 #define MC_CMD_EVENT_CTRL 0x69 7920 #undef MC_CMD_0x69_PRIVILEGE_CTG 7921 7922 #define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7923 7924 /* MC_CMD_EVENT_CTRL_IN msgrequest */ 7925 #define MC_CMD_EVENT_CTRL_IN_LENMIN 0 7926 #define MC_CMD_EVENT_CTRL_IN_LENMAX 252 7927 #define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020 7928 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num)) 7929 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4) 7930 /* Array of event categories for which the driver wishes to receive events. */ 7931 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0 7932 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4 7933 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0 7934 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63 7935 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255 7936 /* enum: Driver wishes to receive LINKCHANGE events. */ 7937 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0 7938 /* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events. 7939 */ 7940 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1 7941 /* enum: Driver wishes to receive receive errors. */ 7942 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2 7943 /* enum: Driver wishes to receive transmit errors. */ 7944 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3 7945 /* enum: Driver wishes to receive firmware alerts. */ 7946 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4 7947 /* enum: Driver wishes to receive reboot events. */ 7948 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5 7949 7950 /* MC_CMD_EVENT_CTRL_OUT msgrequest */ 7951 #define MC_CMD_EVENT_CTRL_OUT_LEN 0 7952 7953 /* EVB_PORT_ID structuredef */ 7954 #define EVB_PORT_ID_LEN 4 7955 #define EVB_PORT_ID_PORT_ID_OFST 0 7956 #define EVB_PORT_ID_PORT_ID_LEN 4 7957 /* enum: An invalid port handle. */ 7958 #define EVB_PORT_ID_NULL 0x0 7959 /* enum: The port assigned to this function.. */ 7960 #define EVB_PORT_ID_ASSIGNED 0x1000000 7961 /* enum: External network port 0 */ 7962 #define EVB_PORT_ID_MAC0 0x2000000 7963 /* enum: External network port 1 */ 7964 #define EVB_PORT_ID_MAC1 0x2000001 7965 /* enum: External network port 2 */ 7966 #define EVB_PORT_ID_MAC2 0x2000002 7967 /* enum: External network port 3 */ 7968 #define EVB_PORT_ID_MAC3 0x2000003 7969 #define EVB_PORT_ID_PORT_ID_LBN 0 7970 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7971 7972 /* EVB_VLAN_TAG structuredef */ 7973 #define EVB_VLAN_TAG_LEN 2 7974 /* The VLAN tag value */ 7975 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7976 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7977 #define EVB_VLAN_TAG_MODE_LBN 12 7978 #define EVB_VLAN_TAG_MODE_WIDTH 4 7979 /* enum: Insert the VLAN. */ 7980 #define EVB_VLAN_TAG_INSERT 0x0 7981 /* enum: Replace the VLAN if already present. */ 7982 #define EVB_VLAN_TAG_REPLACE 0x1 7983 7984 /* BUFTBL_ENTRY structuredef */ 7985 #define BUFTBL_ENTRY_LEN 12 7986 /* the owner ID */ 7987 #define BUFTBL_ENTRY_OID_OFST 0 7988 #define BUFTBL_ENTRY_OID_LEN 2 7989 #define BUFTBL_ENTRY_OID_LBN 0 7990 #define BUFTBL_ENTRY_OID_WIDTH 16 7991 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7992 #define BUFTBL_ENTRY_PGSZ_OFST 2 7993 #define BUFTBL_ENTRY_PGSZ_LEN 2 7994 #define BUFTBL_ENTRY_PGSZ_LBN 16 7995 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7996 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7997 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7998 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7999 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 8000 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 8001 #define BUFTBL_ENTRY_RAWADDR_LBN 32 8002 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 8003 8004 /* NVRAM_PARTITION_TYPE structuredef */ 8005 #define NVRAM_PARTITION_TYPE_LEN 2 8006 #define NVRAM_PARTITION_TYPE_ID_OFST 0 8007 #define NVRAM_PARTITION_TYPE_ID_LEN 2 8008 /* enum: Primary MC firmware partition */ 8009 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 8010 /* enum: Secondary MC firmware partition */ 8011 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 8012 /* enum: Expansion ROM partition */ 8013 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 8014 /* enum: Static configuration TLV partition */ 8015 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 8016 /* enum: Dynamic configuration TLV partition */ 8017 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 8018 /* enum: Expansion ROM configuration data for port 0 */ 8019 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 8020 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 8021 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 8022 /* enum: Expansion ROM configuration data for port 1 */ 8023 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 8024 /* enum: Expansion ROM configuration data for port 2 */ 8025 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 8026 /* enum: Expansion ROM configuration data for port 3 */ 8027 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 8028 /* enum: Non-volatile log output partition */ 8029 #define NVRAM_PARTITION_TYPE_LOG 0x700 8030 /* enum: Non-volatile log output of second core on dual-core device */ 8031 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 8032 /* enum: Device state dump output partition */ 8033 #define NVRAM_PARTITION_TYPE_DUMP 0x800 8034 /* enum: Application license key storage partition */ 8035 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 8036 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 8037 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 8038 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 8039 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 8040 /* enum: Primary FPGA partition */ 8041 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 8042 /* enum: Secondary FPGA partition */ 8043 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 8044 /* enum: FC firmware partition */ 8045 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 8046 /* enum: FC License partition */ 8047 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 8048 /* enum: Non-volatile log output partition for FC */ 8049 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 8050 /* enum: MUM firmware partition */ 8051 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 8052 /* enum: SUC firmware partition (this is intentionally an alias of 8053 * MUM_FIRMWARE) 8054 */ 8055 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00 8056 /* enum: MUM Non-volatile log output partition. */ 8057 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 8058 /* enum: MUM Application table partition. */ 8059 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 8060 /* enum: MUM boot rom partition. */ 8061 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 8062 /* enum: MUM production signatures & calibration rom partition. */ 8063 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 8064 /* enum: MUM user signatures & calibration rom partition. */ 8065 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 8066 /* enum: MUM fuses and lockbits partition. */ 8067 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 8068 /* enum: UEFI expansion ROM if separate from PXE */ 8069 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 8070 /* enum: Used by the expansion ROM for logging */ 8071 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000 8072 /* enum: Used for XIP code of shmbooted images */ 8073 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 8074 /* enum: Spare partition 2 */ 8075 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 8076 /* enum: Manufacturing partition. Used during manufacture to pass information 8077 * between XJTAG and Manftest. 8078 */ 8079 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 8080 /* enum: Spare partition 4 */ 8081 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 8082 /* enum: Spare partition 5 */ 8083 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 8084 /* enum: Partition for reporting MC status. See mc_flash_layout.h 8085 * medford_mc_status_hdr_t for layout on Medford. 8086 */ 8087 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 8088 /* enum: Spare partition 13 */ 8089 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700 8090 /* enum: Spare partition 14 */ 8091 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800 8092 /* enum: Spare partition 15 */ 8093 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900 8094 /* enum: Spare partition 16 */ 8095 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00 8096 /* enum: Factory defaults for dynamic configuration */ 8097 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00 8098 /* enum: Factory defaults for expansion ROM configuration */ 8099 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00 8100 /* enum: Field Replaceable Unit inventory information for use on IPMI 8101 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a 8102 * subset of the information stored in this partition. 8103 */ 8104 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00 8105 /* enum: Bundle image partition */ 8106 #define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00 8107 /* enum: Bundle metadata partition that holds additional information related to 8108 * a bundle update in TLV format 8109 */ 8110 #define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01 8111 /* enum: Bundle update non-volatile log output partition */ 8112 #define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02 8113 /* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */ 8114 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03 8115 /* enum: Start of reserved value range (firmware may use for any purpose) */ 8116 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 8117 /* enum: End of reserved value range (firmware may use for any purpose) */ 8118 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 8119 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 8120 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 8121 /* enum: Partition map (real map as stored in flash) */ 8122 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 8123 #define NVRAM_PARTITION_TYPE_ID_LBN 0 8124 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 8125 8126 /* LICENSED_APP_ID structuredef */ 8127 #define LICENSED_APP_ID_LEN 4 8128 #define LICENSED_APP_ID_ID_OFST 0 8129 #define LICENSED_APP_ID_ID_LEN 4 8130 /* enum: OpenOnload */ 8131 #define LICENSED_APP_ID_ONLOAD 0x1 8132 /* enum: PTP timestamping */ 8133 #define LICENSED_APP_ID_PTP 0x2 8134 /* enum: SolarCapture Pro */ 8135 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 8136 /* enum: SolarSecure filter engine */ 8137 #define LICENSED_APP_ID_SOLARSECURE 0x8 8138 /* enum: Performance monitor */ 8139 #define LICENSED_APP_ID_PERF_MONITOR 0x10 8140 /* enum: SolarCapture Live */ 8141 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 8142 /* enum: Capture SolarSystem */ 8143 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 8144 /* enum: Network Access Control */ 8145 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 8146 /* enum: TCP Direct */ 8147 #define LICENSED_APP_ID_TCP_DIRECT 0x100 8148 /* enum: Low Latency */ 8149 #define LICENSED_APP_ID_LOW_LATENCY 0x200 8150 /* enum: SolarCapture Tap */ 8151 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 8152 /* enum: Capture SolarSystem 40G */ 8153 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 8154 /* enum: Capture SolarSystem 1G */ 8155 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 8156 /* enum: ScaleOut Onload */ 8157 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000 8158 /* enum: SCS Network Analytics Dashboard */ 8159 #define LICENSED_APP_ID_DSHBRD 0x4000 8160 /* enum: SolarCapture Trading Analytics */ 8161 #define LICENSED_APP_ID_SCATRD 0x8000 8162 #define LICENSED_APP_ID_ID_LBN 0 8163 #define LICENSED_APP_ID_ID_WIDTH 32 8164 8165 /* LICENSED_FEATURES structuredef */ 8166 #define LICENSED_FEATURES_LEN 8 8167 /* Bitmask of licensed firmware features */ 8168 #define LICENSED_FEATURES_MASK_OFST 0 8169 #define LICENSED_FEATURES_MASK_LEN 8 8170 #define LICENSED_FEATURES_MASK_LO_OFST 0 8171 #define LICENSED_FEATURES_MASK_HI_OFST 4 8172 #define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0 8173 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 8174 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 8175 #define LICENSED_FEATURES_PIO_OFST 0 8176 #define LICENSED_FEATURES_PIO_LBN 1 8177 #define LICENSED_FEATURES_PIO_WIDTH 1 8178 #define LICENSED_FEATURES_EVQ_TIMER_OFST 0 8179 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 8180 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 8181 #define LICENSED_FEATURES_CLOCK_OFST 0 8182 #define LICENSED_FEATURES_CLOCK_LBN 3 8183 #define LICENSED_FEATURES_CLOCK_WIDTH 1 8184 #define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0 8185 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 8186 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 8187 #define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0 8188 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 8189 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 8190 #define LICENSED_FEATURES_RX_SNIFF_OFST 0 8191 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 8192 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 8193 #define LICENSED_FEATURES_TX_SNIFF_OFST 0 8194 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 8195 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 8196 #define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0 8197 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 8198 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8199 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0 8200 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 8201 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8202 #define LICENSED_FEATURES_MASK_LBN 0 8203 #define LICENSED_FEATURES_MASK_WIDTH 64 8204 8205 /* LICENSED_V3_APPS structuredef */ 8206 #define LICENSED_V3_APPS_LEN 8 8207 /* Bitmask of licensed applications */ 8208 #define LICENSED_V3_APPS_MASK_OFST 0 8209 #define LICENSED_V3_APPS_MASK_LEN 8 8210 #define LICENSED_V3_APPS_MASK_LO_OFST 0 8211 #define LICENSED_V3_APPS_MASK_HI_OFST 4 8212 #define LICENSED_V3_APPS_ONLOAD_OFST 0 8213 #define LICENSED_V3_APPS_ONLOAD_LBN 0 8214 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 8215 #define LICENSED_V3_APPS_PTP_OFST 0 8216 #define LICENSED_V3_APPS_PTP_LBN 1 8217 #define LICENSED_V3_APPS_PTP_WIDTH 1 8218 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0 8219 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 8220 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 8221 #define LICENSED_V3_APPS_SOLARSECURE_OFST 0 8222 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 8223 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 8224 #define LICENSED_V3_APPS_PERF_MONITOR_OFST 0 8225 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 8226 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 8227 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0 8228 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 8229 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 8230 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0 8231 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 8232 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 8233 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0 8234 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 8235 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 8236 #define LICENSED_V3_APPS_TCP_DIRECT_OFST 0 8237 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 8238 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 8239 #define LICENSED_V3_APPS_LOW_LATENCY_OFST 0 8240 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 8241 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 8242 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0 8243 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 8244 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 8245 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0 8246 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 8247 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 8248 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0 8249 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 8250 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 8251 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0 8252 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13 8253 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1 8254 #define LICENSED_V3_APPS_DSHBRD_OFST 0 8255 #define LICENSED_V3_APPS_DSHBRD_LBN 14 8256 #define LICENSED_V3_APPS_DSHBRD_WIDTH 1 8257 #define LICENSED_V3_APPS_SCATRD_OFST 0 8258 #define LICENSED_V3_APPS_SCATRD_LBN 15 8259 #define LICENSED_V3_APPS_SCATRD_WIDTH 1 8260 #define LICENSED_V3_APPS_MASK_LBN 0 8261 #define LICENSED_V3_APPS_MASK_WIDTH 64 8262 8263 /* LICENSED_V3_FEATURES structuredef */ 8264 #define LICENSED_V3_FEATURES_LEN 8 8265 /* Bitmask of licensed firmware features */ 8266 #define LICENSED_V3_FEATURES_MASK_OFST 0 8267 #define LICENSED_V3_FEATURES_MASK_LEN 8 8268 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 8269 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 8270 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0 8271 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 8272 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 8273 #define LICENSED_V3_FEATURES_PIO_OFST 0 8274 #define LICENSED_V3_FEATURES_PIO_LBN 1 8275 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 8276 #define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0 8277 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 8278 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 8279 #define LICENSED_V3_FEATURES_CLOCK_OFST 0 8280 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 8281 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 8282 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0 8283 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 8284 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 8285 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0 8286 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 8287 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 8288 #define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0 8289 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 8290 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 8291 #define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0 8292 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 8293 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 8294 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0 8295 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 8296 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8297 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0 8298 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 8299 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8300 #define LICENSED_V3_FEATURES_MASK_LBN 0 8301 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 8302 8303 /* TX_TIMESTAMP_EVENT structuredef */ 8304 #define TX_TIMESTAMP_EVENT_LEN 6 8305 /* lower 16 bits of timestamp data */ 8306 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 8307 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 8308 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 8309 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 8310 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 8311 */ 8312 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 8313 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 8314 /* enum: This is a TX completion event, not a timestamp */ 8315 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 8316 /* enum: This is a TX completion event for a CTPIO transmit. The event format 8317 * is the same as for TX_EV_COMPLETION. 8318 */ 8319 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11 8320 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The 8321 * event format is the same as for TX_EV_TSTAMP_LO 8322 */ 8323 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12 8324 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The 8325 * event format is the same as for TX_EV_TSTAMP_HI 8326 */ 8327 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13 8328 /* enum: This is the low part of a TX timestamp event */ 8329 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 8330 /* enum: This is the high part of a TX timestamp event */ 8331 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 8332 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 8333 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 8334 /* upper 16 bits of timestamp data */ 8335 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 8336 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 8337 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 8338 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 8339 8340 /* RSS_MODE structuredef */ 8341 #define RSS_MODE_LEN 1 8342 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 8343 * be considered as 4 bits selecting which fields are included in the hash. (A 8344 * value 0 effectively disables RSS spreading for the packet type.) The YAML 8345 * generation tools require this structure to be a whole number of bytes wide, 8346 * but only 4 bits are relevant. 8347 */ 8348 #define RSS_MODE_HASH_SELECTOR_OFST 0 8349 #define RSS_MODE_HASH_SELECTOR_LEN 1 8350 #define RSS_MODE_HASH_SRC_ADDR_OFST 0 8351 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 8352 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 8353 #define RSS_MODE_HASH_DST_ADDR_OFST 0 8354 #define RSS_MODE_HASH_DST_ADDR_LBN 1 8355 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 8356 #define RSS_MODE_HASH_SRC_PORT_OFST 0 8357 #define RSS_MODE_HASH_SRC_PORT_LBN 2 8358 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 8359 #define RSS_MODE_HASH_DST_PORT_OFST 0 8360 #define RSS_MODE_HASH_DST_PORT_LBN 3 8361 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 8362 #define RSS_MODE_HASH_SELECTOR_LBN 0 8363 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 8364 8365 /* CTPIO_STATS_MAP structuredef */ 8366 #define CTPIO_STATS_MAP_LEN 4 8367 /* The (function relative) VI number */ 8368 #define CTPIO_STATS_MAP_VI_OFST 0 8369 #define CTPIO_STATS_MAP_VI_LEN 2 8370 #define CTPIO_STATS_MAP_VI_LBN 0 8371 #define CTPIO_STATS_MAP_VI_WIDTH 16 8372 /* The target bucket for the VI */ 8373 #define CTPIO_STATS_MAP_BUCKET_OFST 2 8374 #define CTPIO_STATS_MAP_BUCKET_LEN 2 8375 #define CTPIO_STATS_MAP_BUCKET_LBN 16 8376 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 8377 8378 8379 /***********************************/ 8380 /* MC_CMD_READ_REGS 8381 * Get a dump of the MCPU registers 8382 */ 8383 #define MC_CMD_READ_REGS 0x50 8384 #undef MC_CMD_0x50_PRIVILEGE_CTG 8385 8386 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 8387 8388 /* MC_CMD_READ_REGS_IN msgrequest */ 8389 #define MC_CMD_READ_REGS_IN_LEN 0 8390 8391 /* MC_CMD_READ_REGS_OUT msgresponse */ 8392 #define MC_CMD_READ_REGS_OUT_LEN 308 8393 /* Whether the corresponding register entry contains a valid value */ 8394 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 8395 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 8396 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 8397 * fir, fp) 8398 */ 8399 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 8400 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 8401 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 8402 8403 8404 /***********************************/ 8405 /* MC_CMD_INIT_EVQ 8406 * Set up an event queue according to the supplied parameters. The IN arguments 8407 * end with an address for each 4k of host memory required to back the EVQ. 8408 */ 8409 #define MC_CMD_INIT_EVQ 0x80 8410 #undef MC_CMD_0x80_PRIVILEGE_CTG 8411 8412 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8413 8414 /* MC_CMD_INIT_EVQ_IN msgrequest */ 8415 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 8416 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 8417 #define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548 8418 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 8419 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8) 8420 /* Size, in entries */ 8421 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 8422 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4 8423 /* Desired instance. Must be set to a specific instance, which is a function 8424 * local queue index. 8425 */ 8426 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 8427 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4 8428 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8429 */ 8430 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 8431 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4 8432 /* The reload value is ignored in one-shot modes */ 8433 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 8434 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4 8435 /* tbd */ 8436 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 8437 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4 8438 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16 8439 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 8440 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 8441 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16 8442 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 8443 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 8444 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16 8445 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 8446 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 8447 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16 8448 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 8449 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 8450 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16 8451 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 8452 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 8453 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16 8454 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 8455 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 8456 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16 8457 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 8458 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 8459 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 8460 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4 8461 /* enum: Disabled */ 8462 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 8463 /* enum: Immediate */ 8464 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 8465 /* enum: Triggered */ 8466 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 8467 /* enum: Hold-off */ 8468 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 8469 /* Target EVQ for wakeups if in wakeup mode. */ 8470 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 8471 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4 8472 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8473 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8474 * purposes. 8475 */ 8476 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 8477 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4 8478 /* Event Counter Mode. */ 8479 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 8480 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4 8481 /* enum: Disabled */ 8482 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 8483 /* enum: Disabled */ 8484 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 8485 /* enum: Disabled */ 8486 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 8487 /* enum: Disabled */ 8488 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 8489 /* Event queue packet count threshold. */ 8490 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 8491 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4 8492 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8493 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 8494 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 8495 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 8496 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 8497 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 8498 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 8499 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64 8500 8501 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 8502 #define MC_CMD_INIT_EVQ_OUT_LEN 4 8503 /* Only valid if INTRFLAG was true */ 8504 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 8505 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4 8506 8507 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 8508 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 8509 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 8510 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548 8511 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 8512 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8) 8513 /* Size, in entries */ 8514 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 8515 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4 8516 /* Desired instance. Must be set to a specific instance, which is a function 8517 * local queue index. 8518 */ 8519 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 8520 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4 8521 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8522 */ 8523 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 8524 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4 8525 /* The reload value is ignored in one-shot modes */ 8526 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 8527 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4 8528 /* tbd */ 8529 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 8530 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4 8531 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16 8532 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 8533 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 8534 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16 8535 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 8536 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 8537 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16 8538 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 8539 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 8540 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16 8541 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 8542 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 8543 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16 8544 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 8545 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 8546 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16 8547 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 8548 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 8549 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16 8550 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 8551 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 8552 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16 8553 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 8554 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 8555 /* enum: All initialisation flags specified by host. */ 8556 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 8557 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8558 * over-ridden by firmware based on licenses and firmware variant in order to 8559 * provide the lowest latency achievable. See 8560 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8561 */ 8562 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 8563 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8564 * over-ridden by firmware based on licenses and firmware variant in order to 8565 * provide the best throughput achievable. See 8566 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8567 */ 8568 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 8569 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 8570 * firmware based on licenses and firmware variant. See 8571 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8572 */ 8573 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 8574 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16 8575 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11 8576 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1 8577 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 8578 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4 8579 /* enum: Disabled */ 8580 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 8581 /* enum: Immediate */ 8582 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 8583 /* enum: Triggered */ 8584 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 8585 /* enum: Hold-off */ 8586 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 8587 /* Target EVQ for wakeups if in wakeup mode. */ 8588 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 8589 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4 8590 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8591 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8592 * purposes. 8593 */ 8594 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 8595 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4 8596 /* Event Counter Mode. */ 8597 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 8598 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4 8599 /* enum: Disabled */ 8600 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 8601 /* enum: Disabled */ 8602 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 8603 /* enum: Disabled */ 8604 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 8605 /* enum: Disabled */ 8606 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 8607 /* Event queue packet count threshold. */ 8608 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 8609 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4 8610 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8611 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 8612 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 8613 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 8614 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 8615 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 8616 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 8617 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64 8618 8619 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 8620 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 8621 /* Only valid if INTRFLAG was true */ 8622 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 8623 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4 8624 /* Actual configuration applied on the card */ 8625 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 8626 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4 8627 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4 8628 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 8629 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 8630 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4 8631 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 8632 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 8633 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4 8634 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 8635 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 8636 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4 8637 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 8638 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 8639 8640 /* QUEUE_CRC_MODE structuredef */ 8641 #define QUEUE_CRC_MODE_LEN 1 8642 #define QUEUE_CRC_MODE_MODE_LBN 0 8643 #define QUEUE_CRC_MODE_MODE_WIDTH 4 8644 /* enum: No CRC. */ 8645 #define QUEUE_CRC_MODE_NONE 0x0 8646 /* enum: CRC Fiber channel over ethernet. */ 8647 #define QUEUE_CRC_MODE_FCOE 0x1 8648 /* enum: CRC (digest) iSCSI header only. */ 8649 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 8650 /* enum: CRC (digest) iSCSI header and payload. */ 8651 #define QUEUE_CRC_MODE_ISCSI 0x3 8652 /* enum: CRC Fiber channel over IP over ethernet. */ 8653 #define QUEUE_CRC_MODE_FCOIPOE 0x4 8654 /* enum: CRC MPA. */ 8655 #define QUEUE_CRC_MODE_MPA 0x5 8656 #define QUEUE_CRC_MODE_SPARE_LBN 4 8657 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 8658 8659 8660 /***********************************/ 8661 /* MC_CMD_INIT_RXQ 8662 * set up a receive queue according to the supplied parameters. The IN 8663 * arguments end with an address for each 4k of host memory required to back 8664 * the RXQ. 8665 */ 8666 #define MC_CMD_INIT_RXQ 0x81 8667 #undef MC_CMD_0x81_PRIVILEGE_CTG 8668 8669 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8670 8671 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 8672 * in new code. 8673 */ 8674 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 8675 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 8676 #define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020 8677 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 8678 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8) 8679 /* Size, in entries */ 8680 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 8681 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 8682 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8683 */ 8684 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 8685 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 8686 /* The value to put in the event data. Check hardware spec. for valid range. */ 8687 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 8688 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 8689 /* Desired instance. Must be set to a specific instance, which is a function 8690 * local queue index. 8691 */ 8692 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 8693 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 8694 /* There will be more flags here. */ 8695 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 8696 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 8697 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16 8698 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 8699 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8700 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16 8701 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 8702 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 8703 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16 8704 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 8705 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8706 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16 8707 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 8708 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 8709 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16 8710 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 8711 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 8712 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16 8713 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 8714 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 8715 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16 8716 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 8717 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8718 #define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16 8719 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 8720 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 8721 /* Owner ID to use if in buffer mode (zero if physical) */ 8722 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 8723 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 8724 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8725 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 8726 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 8727 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8728 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 8729 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 8730 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 8731 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 8732 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 8733 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 8734 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124 8735 8736 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 8737 * flags 8738 */ 8739 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 8740 /* Size, in entries */ 8741 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 8742 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 8743 /* The EVQ to send events to. This is an index originally specified to 8744 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 8745 */ 8746 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 8747 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 8748 /* The value to put in the event data. Check hardware spec. for valid range. 8749 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 8750 * == PACKED_STREAM. 8751 */ 8752 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 8753 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 8754 /* Desired instance. Must be set to a specific instance, which is a function 8755 * local queue index. 8756 */ 8757 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 8758 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 8759 /* There will be more flags here. */ 8760 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 8761 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 8762 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16 8763 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8764 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8765 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16 8766 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 8767 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 8768 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16 8769 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 8770 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8771 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16 8772 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 8773 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 8774 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16 8775 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 8776 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 8777 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16 8778 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 8779 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 8780 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16 8781 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 8782 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8783 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16 8784 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 8785 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 8786 /* enum: One packet per descriptor (for normal networking) */ 8787 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 8788 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8789 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 8790 /* enum: Pack multiple packets into large descriptors using the format designed 8791 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 8792 * multiple fixed-size packet buffers within each bucket. For a full 8793 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 8794 * firmware. 8795 */ 8796 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 8797 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 8798 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 8799 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16 8800 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 8801 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8802 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 8803 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8804 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8805 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 8806 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 8807 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 8808 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 8809 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 8810 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 8811 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8812 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8813 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16 8814 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 8815 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8816 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16 8817 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20 8818 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1 8819 /* Owner ID to use if in buffer mode (zero if physical) */ 8820 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 8821 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 8822 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8823 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 8824 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 8825 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8826 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 8827 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 8828 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8829 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8830 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 8831 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8832 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 8833 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4 8834 8835 /* MC_CMD_INIT_RXQ_V3_IN msgrequest */ 8836 #define MC_CMD_INIT_RXQ_V3_IN_LEN 560 8837 /* Size, in entries */ 8838 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0 8839 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4 8840 /* The EVQ to send events to. This is an index originally specified to 8841 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 8842 */ 8843 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4 8844 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4 8845 /* The value to put in the event data. Check hardware spec. for valid range. 8846 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 8847 * == PACKED_STREAM. 8848 */ 8849 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8 8850 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4 8851 /* Desired instance. Must be set to a specific instance, which is a function 8852 * local queue index. 8853 */ 8854 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12 8855 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4 8856 /* There will be more flags here. */ 8857 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16 8858 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4 8859 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16 8860 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0 8861 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1 8862 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16 8863 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1 8864 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1 8865 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16 8866 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2 8867 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1 8868 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16 8869 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3 8870 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4 8871 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16 8872 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7 8873 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1 8874 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16 8875 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8 8876 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1 8877 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16 8878 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9 8879 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8880 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16 8881 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10 8882 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4 8883 /* enum: One packet per descriptor (for normal networking) */ 8884 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0 8885 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8886 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1 8887 /* enum: Pack multiple packets into large descriptors using the format designed 8888 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 8889 * multiple fixed-size packet buffers within each bucket. For a full 8890 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 8891 * firmware. 8892 */ 8893 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 8894 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 8895 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 8896 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16 8897 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14 8898 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8899 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 8900 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8901 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8902 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */ 8903 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */ 8904 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */ 8905 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */ 8906 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */ 8907 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 8908 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8909 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8910 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16 8911 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19 8912 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8913 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16 8914 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20 8915 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1 8916 /* Owner ID to use if in buffer mode (zero if physical) */ 8917 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20 8918 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4 8919 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8920 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24 8921 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4 8922 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8923 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28 8924 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8 8925 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28 8926 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32 8927 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64 8928 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8929 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540 8930 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4 8931 /* The number of packet buffers that will be contained within each 8932 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field 8933 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 8934 */ 8935 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 8936 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 8937 /* The length in bytes of the area in each packet buffer that can be written to 8938 * by the adapter. This is used to store the packet prefix and the packet 8939 * payload. This length does not include any end padding added by the driver. 8940 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 8941 */ 8942 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548 8943 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4 8944 /* The length in bytes of a single packet buffer within a 8945 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless 8946 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 8947 */ 8948 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552 8949 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4 8950 /* The maximum time in nanoseconds that the datapath will be backpressured if 8951 * there are no RX descriptors available. If the timeout is reached and there 8952 * are still no descriptors then the packet will be dropped. A timeout of 0 8953 * means the datapath will never be blocked. This field is ignored unless 8954 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 8955 */ 8956 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 8957 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 8958 8959 /* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required 8960 * for systems with a QDMA (currently, Riverhead) 8961 */ 8962 #define MC_CMD_INIT_RXQ_V4_IN_LEN 564 8963 /* Size, in entries */ 8964 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0 8965 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4 8966 /* The EVQ to send events to. This is an index originally specified to 8967 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 8968 */ 8969 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4 8970 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4 8971 /* The value to put in the event data. Check hardware spec. for valid range. 8972 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 8973 * == PACKED_STREAM. 8974 */ 8975 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8 8976 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4 8977 /* Desired instance. Must be set to a specific instance, which is a function 8978 * local queue index. 8979 */ 8980 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12 8981 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4 8982 /* There will be more flags here. */ 8983 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16 8984 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4 8985 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16 8986 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0 8987 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1 8988 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16 8989 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1 8990 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1 8991 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16 8992 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2 8993 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1 8994 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16 8995 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3 8996 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4 8997 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16 8998 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7 8999 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1 9000 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16 9001 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8 9002 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1 9003 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16 9004 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9 9005 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1 9006 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16 9007 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10 9008 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4 9009 /* enum: One packet per descriptor (for normal networking) */ 9010 #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0 9011 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 9012 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1 9013 /* enum: Pack multiple packets into large descriptors using the format designed 9014 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 9015 * multiple fixed-size packet buffers within each bucket. For a full 9016 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 9017 * firmware. 9018 */ 9019 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 9020 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 9021 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 9022 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16 9023 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14 9024 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 9025 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 9026 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 9027 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 9028 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */ 9029 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */ 9030 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */ 9031 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */ 9032 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */ 9033 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 9034 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 9035 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 9036 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16 9037 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19 9038 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 9039 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16 9040 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20 9041 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1 9042 /* Owner ID to use if in buffer mode (zero if physical) */ 9043 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20 9044 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4 9045 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 9046 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24 9047 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4 9048 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 9049 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28 9050 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8 9051 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28 9052 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32 9053 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64 9054 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 9055 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540 9056 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4 9057 /* The number of packet buffers that will be contained within each 9058 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field 9059 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9060 */ 9061 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 9062 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 9063 /* The length in bytes of the area in each packet buffer that can be written to 9064 * by the adapter. This is used to store the packet prefix and the packet 9065 * payload. This length does not include any end padding added by the driver. 9066 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9067 */ 9068 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548 9069 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4 9070 /* The length in bytes of a single packet buffer within a 9071 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless 9072 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9073 */ 9074 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552 9075 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4 9076 /* The maximum time in nanoseconds that the datapath will be backpressured if 9077 * there are no RX descriptors available. If the timeout is reached and there 9078 * are still no descriptors then the packet will be dropped. A timeout of 0 9079 * means the datapath will never be blocked. This field is ignored unless 9080 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9081 */ 9082 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 9083 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 9084 /* V4 message data */ 9085 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560 9086 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4 9087 /* Size in bytes of buffers attached to descriptors posted to this queue. Set 9088 * to zero if using this message on non-QDMA based platforms. Currently in 9089 * Riverhead there is a global limit of eight different buffer sizes across all 9090 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a 9091 * request for a different buffer size will fail if there are already eight 9092 * other buffer sizes in use. In future Riverhead this limit will go away and 9093 * any size will be accepted. 9094 */ 9095 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560 9096 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4 9097 9098 /* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a 9099 * different RX packet prefix 9100 */ 9101 #define MC_CMD_INIT_RXQ_V5_IN_LEN 568 9102 /* Size, in entries */ 9103 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0 9104 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4 9105 /* The EVQ to send events to. This is an index originally specified to 9106 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 9107 */ 9108 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4 9109 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4 9110 /* The value to put in the event data. Check hardware spec. for valid range. 9111 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 9112 * == PACKED_STREAM. 9113 */ 9114 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8 9115 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4 9116 /* Desired instance. Must be set to a specific instance, which is a function 9117 * local queue index. 9118 */ 9119 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12 9120 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4 9121 /* There will be more flags here. */ 9122 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16 9123 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4 9124 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16 9125 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0 9126 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1 9127 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16 9128 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1 9129 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1 9130 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16 9131 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2 9132 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1 9133 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16 9134 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3 9135 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4 9136 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16 9137 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7 9138 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1 9139 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16 9140 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8 9141 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1 9142 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16 9143 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9 9144 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1 9145 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16 9146 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10 9147 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4 9148 /* enum: One packet per descriptor (for normal networking) */ 9149 #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0 9150 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 9151 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1 9152 /* enum: Pack multiple packets into large descriptors using the format designed 9153 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 9154 * multiple fixed-size packet buffers within each bucket. For a full 9155 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 9156 * firmware. 9157 */ 9158 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 9159 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 9160 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 9161 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16 9162 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14 9163 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 9164 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 9165 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 9166 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 9167 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */ 9168 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */ 9169 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */ 9170 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */ 9171 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */ 9172 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 9173 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 9174 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 9175 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16 9176 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19 9177 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 9178 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16 9179 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20 9180 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1 9181 /* Owner ID to use if in buffer mode (zero if physical) */ 9182 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20 9183 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4 9184 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 9185 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24 9186 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4 9187 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 9188 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28 9189 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8 9190 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28 9191 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32 9192 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64 9193 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 9194 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540 9195 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4 9196 /* The number of packet buffers that will be contained within each 9197 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field 9198 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9199 */ 9200 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 9201 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 9202 /* The length in bytes of the area in each packet buffer that can be written to 9203 * by the adapter. This is used to store the packet prefix and the packet 9204 * payload. This length does not include any end padding added by the driver. 9205 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9206 */ 9207 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548 9208 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4 9209 /* The length in bytes of a single packet buffer within a 9210 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless 9211 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9212 */ 9213 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552 9214 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4 9215 /* The maximum time in nanoseconds that the datapath will be backpressured if 9216 * there are no RX descriptors available. If the timeout is reached and there 9217 * are still no descriptors then the packet will be dropped. A timeout of 0 9218 * means the datapath will never be blocked. This field is ignored unless 9219 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 9220 */ 9221 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 9222 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 9223 /* V4 message data */ 9224 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560 9225 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4 9226 /* Size in bytes of buffers attached to descriptors posted to this queue. Set 9227 * to zero if using this message on non-QDMA based platforms. Currently in 9228 * Riverhead there is a global limit of eight different buffer sizes across all 9229 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a 9230 * request for a different buffer size will fail if there are already eight 9231 * other buffer sizes in use. In future Riverhead this limit will go away and 9232 * any size will be accepted. 9233 */ 9234 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560 9235 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4 9236 /* Prefix id for the RX prefix format to use on packets delivered this queue. 9237 * Zero is always a valid prefix id and means the default prefix format 9238 * documented for the platform. Other prefix ids can be obtained by calling 9239 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields. 9240 */ 9241 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564 9242 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4 9243 9244 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 9245 #define MC_CMD_INIT_RXQ_OUT_LEN 0 9246 9247 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 9248 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 9249 9250 /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */ 9251 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0 9252 9253 /* MC_CMD_INIT_RXQ_V4_OUT msgresponse */ 9254 #define MC_CMD_INIT_RXQ_V4_OUT_LEN 0 9255 9256 /* MC_CMD_INIT_RXQ_V5_OUT msgresponse */ 9257 #define MC_CMD_INIT_RXQ_V5_OUT_LEN 0 9258 9259 9260 /***********************************/ 9261 /* MC_CMD_INIT_TXQ 9262 */ 9263 #define MC_CMD_INIT_TXQ 0x82 9264 #undef MC_CMD_0x82_PRIVILEGE_CTG 9265 9266 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9267 9268 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 9269 * in new code. 9270 */ 9271 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 9272 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 9273 #define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020 9274 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 9275 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8) 9276 /* Size, in entries */ 9277 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 9278 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4 9279 /* The EVQ to send events to. This is an index originally specified to 9280 * INIT_EVQ. 9281 */ 9282 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 9283 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4 9284 /* The value to put in the event data. Check hardware spec. for valid range. */ 9285 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 9286 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4 9287 /* Desired instance. Must be set to a specific instance, which is a function 9288 * local queue index. 9289 */ 9290 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 9291 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4 9292 /* There will be more flags here. */ 9293 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 9294 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4 9295 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16 9296 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 9297 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 9298 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16 9299 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 9300 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 9301 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16 9302 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 9303 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 9304 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16 9305 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 9306 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 9307 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16 9308 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 9309 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 9310 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16 9311 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 9312 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 9313 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16 9314 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 9315 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 9316 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16 9317 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 9318 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 9319 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16 9320 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 9321 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 9322 /* Owner ID to use if in buffer mode (zero if physical) */ 9323 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 9324 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4 9325 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 9326 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 9327 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4 9328 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 9329 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 9330 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 9331 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 9332 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 9333 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 9334 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 9335 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124 9336 9337 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 9338 * flags 9339 */ 9340 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 9341 /* Size, in entries */ 9342 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 9343 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4 9344 /* The EVQ to send events to. This is an index originally specified to 9345 * INIT_EVQ. 9346 */ 9347 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 9348 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4 9349 /* The value to put in the event data. Check hardware spec. for valid range. */ 9350 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 9351 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4 9352 /* Desired instance. Must be set to a specific instance, which is a function 9353 * local queue index. 9354 */ 9355 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 9356 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4 9357 /* There will be more flags here. */ 9358 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 9359 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4 9360 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16 9361 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 9362 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 9363 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16 9364 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 9365 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 9366 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16 9367 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 9368 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 9369 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16 9370 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 9371 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 9372 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16 9373 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 9374 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 9375 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16 9376 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 9377 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 9378 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16 9379 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 9380 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 9381 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16 9382 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 9383 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 9384 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16 9385 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 9386 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 9387 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16 9388 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 9389 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 9390 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16 9391 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 9392 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 9393 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16 9394 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14 9395 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1 9396 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16 9397 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15 9398 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1 9399 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16 9400 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16 9401 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1 9402 /* Owner ID to use if in buffer mode (zero if physical) */ 9403 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 9404 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4 9405 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 9406 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 9407 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4 9408 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 9409 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 9410 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 9411 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 9412 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 9413 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 9414 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 9415 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64 9416 /* Flags related to Qbb flow control mode. */ 9417 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 9418 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4 9419 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540 9420 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 9421 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 9422 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540 9423 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 9424 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 9425 9426 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 9427 #define MC_CMD_INIT_TXQ_OUT_LEN 0 9428 9429 9430 /***********************************/ 9431 /* MC_CMD_FINI_EVQ 9432 * Teardown an EVQ. 9433 * 9434 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 9435 * or the operation will fail with EBUSY 9436 */ 9437 #define MC_CMD_FINI_EVQ 0x83 9438 #undef MC_CMD_0x83_PRIVILEGE_CTG 9439 9440 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9441 9442 /* MC_CMD_FINI_EVQ_IN msgrequest */ 9443 #define MC_CMD_FINI_EVQ_IN_LEN 4 9444 /* Instance of EVQ to destroy. Should be the same instance as that previously 9445 * passed to INIT_EVQ 9446 */ 9447 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 9448 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4 9449 9450 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 9451 #define MC_CMD_FINI_EVQ_OUT_LEN 0 9452 9453 9454 /***********************************/ 9455 /* MC_CMD_FINI_RXQ 9456 * Teardown a RXQ. 9457 */ 9458 #define MC_CMD_FINI_RXQ 0x84 9459 #undef MC_CMD_0x84_PRIVILEGE_CTG 9460 9461 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9462 9463 /* MC_CMD_FINI_RXQ_IN msgrequest */ 9464 #define MC_CMD_FINI_RXQ_IN_LEN 4 9465 /* Instance of RXQ to destroy */ 9466 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 9467 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4 9468 9469 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 9470 #define MC_CMD_FINI_RXQ_OUT_LEN 0 9471 9472 9473 /***********************************/ 9474 /* MC_CMD_FINI_TXQ 9475 * Teardown a TXQ. 9476 */ 9477 #define MC_CMD_FINI_TXQ 0x85 9478 #undef MC_CMD_0x85_PRIVILEGE_CTG 9479 9480 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9481 9482 /* MC_CMD_FINI_TXQ_IN msgrequest */ 9483 #define MC_CMD_FINI_TXQ_IN_LEN 4 9484 /* Instance of TXQ to destroy */ 9485 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 9486 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4 9487 9488 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 9489 #define MC_CMD_FINI_TXQ_OUT_LEN 0 9490 9491 9492 /***********************************/ 9493 /* MC_CMD_DRIVER_EVENT 9494 * Generate an event on an EVQ belonging to the function issuing the command. 9495 */ 9496 #define MC_CMD_DRIVER_EVENT 0x86 9497 #undef MC_CMD_0x86_PRIVILEGE_CTG 9498 9499 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9500 9501 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 9502 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 9503 /* Handle of target EVQ */ 9504 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 9505 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4 9506 /* Bits 0 - 63 of event */ 9507 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 9508 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 9509 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 9510 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 9511 9512 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 9513 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 9514 9515 9516 /***********************************/ 9517 /* MC_CMD_PROXY_CMD 9518 * Execute an arbitrary MCDI command on behalf of a different function, subject 9519 * to security restrictions. The command to be proxied follows immediately 9520 * afterward in the host buffer (or on the UART). This command supercedes 9521 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 9522 */ 9523 #define MC_CMD_PROXY_CMD 0x5b 9524 #undef MC_CMD_0x5b_PRIVILEGE_CTG 9525 9526 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9527 9528 /* MC_CMD_PROXY_CMD_IN msgrequest */ 9529 #define MC_CMD_PROXY_CMD_IN_LEN 4 9530 /* The handle of the target function. */ 9531 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 9532 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4 9533 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0 9534 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 9535 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 9536 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0 9537 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 9538 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 9539 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 9540 9541 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 9542 #define MC_CMD_PROXY_CMD_OUT_LEN 0 9543 9544 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 9545 * manage proxied requests 9546 */ 9547 #define MC_PROXY_STATUS_BUFFER_LEN 16 9548 /* Handle allocated by the firmware for this proxy transaction */ 9549 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 9550 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 9551 /* enum: An invalid handle. */ 9552 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 9553 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 9554 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 9555 /* The requesting physical function number */ 9556 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 9557 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 9558 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 9559 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 9560 /* The requesting virtual function number. Set to VF_NULL if the target is a 9561 * PF. 9562 */ 9563 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 9564 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 9565 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 9566 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 9567 /* The target function RID. */ 9568 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 9569 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 9570 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 9571 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 9572 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 9573 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 9574 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 9575 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 9576 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 9577 /* If a request is authorized rather than carried out by the host, this is the 9578 * elevated privilege mask granted to the requesting function. 9579 */ 9580 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 9581 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 9582 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 9583 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 9584 9585 9586 /***********************************/ 9587 /* MC_CMD_PROXY_CONFIGURE 9588 * Enable/disable authorization of MCDI requests from unprivileged functions by 9589 * a designated admin function 9590 */ 9591 #define MC_CMD_PROXY_CONFIGURE 0x58 9592 #undef MC_CMD_0x58_PRIVILEGE_CTG 9593 9594 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9595 9596 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 9597 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 9598 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 9599 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 9600 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0 9601 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 9602 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 9603 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9604 * of blocks, each of the size REQUEST_BLOCK_SIZE. 9605 */ 9606 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 9607 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 9608 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 9609 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 9610 /* Must be a power of 2 */ 9611 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 9612 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 9613 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9614 * of blocks, each of the size REPLY_BLOCK_SIZE. 9615 */ 9616 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 9617 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 9618 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 9619 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 9620 /* Must be a power of 2 */ 9621 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 9622 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 9623 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9624 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 9625 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 9626 */ 9627 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 9628 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 9629 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 9630 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 9631 /* Must be a power of 2, or zero if this buffer is not provided */ 9632 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 9633 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 9634 /* Applies to all three buffers */ 9635 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 9636 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 9637 /* A bit mask defining which MCDI operations may be proxied */ 9638 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 9639 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 9640 9641 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 9642 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 9643 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 9644 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 9645 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0 9646 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 9647 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 9648 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9649 * of blocks, each of the size REQUEST_BLOCK_SIZE. 9650 */ 9651 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 9652 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 9653 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 9654 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 9655 /* Must be a power of 2 */ 9656 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 9657 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 9658 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9659 * of blocks, each of the size REPLY_BLOCK_SIZE. 9660 */ 9661 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 9662 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 9663 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 9664 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 9665 /* Must be a power of 2 */ 9666 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 9667 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 9668 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 9669 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 9670 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 9671 */ 9672 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 9673 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 9674 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 9675 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 9676 /* Must be a power of 2, or zero if this buffer is not provided */ 9677 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 9678 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 9679 /* Applies to all three buffers */ 9680 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 9681 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 9682 /* A bit mask defining which MCDI operations may be proxied */ 9683 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 9684 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 9685 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 9686 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 9687 9688 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 9689 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 9690 9691 9692 /***********************************/ 9693 /* MC_CMD_PROXY_COMPLETE 9694 * Tells FW that a requested proxy operation has either been completed (by 9695 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 9696 * function that enabled proxying/authorization (by using 9697 * MC_CMD_PROXY_CONFIGURE). 9698 */ 9699 #define MC_CMD_PROXY_COMPLETE 0x5f 9700 #undef MC_CMD_0x5f_PRIVILEGE_CTG 9701 9702 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9703 9704 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 9705 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 9706 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 9707 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 9708 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 9709 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 9710 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 9711 * is stored in the REPLY_BUFF. 9712 */ 9713 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 9714 /* enum: The operation has been authorized. The originating function may now 9715 * try again. 9716 */ 9717 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 9718 /* enum: The operation has been declined. */ 9719 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 9720 /* enum: The authorization failed because the relevant application did not 9721 * respond in time. 9722 */ 9723 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 9724 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 9725 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 9726 9727 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 9728 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 9729 9730 9731 /***********************************/ 9732 /* MC_CMD_ALLOC_BUFTBL_CHUNK 9733 * Allocate a set of buffer table entries using the specified owner ID. This 9734 * operation allocates the required buffer table entries (and fails if it 9735 * cannot do so). The buffer table entries will initially be zeroed. 9736 */ 9737 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 9738 #undef MC_CMD_0x87_PRIVILEGE_CTG 9739 9740 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9741 9742 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 9743 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 9744 /* Owner ID to use */ 9745 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 9746 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 9747 /* Size of buffer table pages to use, in bytes (note that only a few values are 9748 * legal on any specific hardware). 9749 */ 9750 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 9751 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 9752 9753 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 9754 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 9755 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 9756 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 9757 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 9758 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 9759 /* Buffer table IDs for use in DMA descriptors. */ 9760 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 9761 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 9762 9763 9764 /***********************************/ 9765 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 9766 * Reprogram a set of buffer table entries in the specified chunk. 9767 */ 9768 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 9769 #undef MC_CMD_0x88_PRIVILEGE_CTG 9770 9771 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9772 9773 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 9774 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 9775 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 9776 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268 9777 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 9778 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8) 9779 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 9780 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 9781 /* ID */ 9782 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 9783 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 9784 /* Num entries */ 9785 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 9786 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 9787 /* Buffer table entry address */ 9788 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 9789 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 9790 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 9791 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 9792 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 9793 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 9794 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32 9795 9796 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 9797 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 9798 9799 9800 /***********************************/ 9801 /* MC_CMD_FREE_BUFTBL_CHUNK 9802 */ 9803 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 9804 #undef MC_CMD_0x89_PRIVILEGE_CTG 9805 9806 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9807 9808 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 9809 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 9810 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 9811 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 9812 9813 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 9814 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 9815 9816 9817 /***********************************/ 9818 /* MC_CMD_FILTER_OP 9819 * Multiplexed MCDI call for filter operations 9820 */ 9821 #define MC_CMD_FILTER_OP 0x8a 9822 #undef MC_CMD_0x8a_PRIVILEGE_CTG 9823 9824 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9825 9826 /* MC_CMD_FILTER_OP_IN msgrequest */ 9827 #define MC_CMD_FILTER_OP_IN_LEN 108 9828 /* identifies the type of operation requested */ 9829 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 9830 #define MC_CMD_FILTER_OP_IN_OP_LEN 4 9831 /* enum: single-recipient filter insert */ 9832 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 9833 /* enum: single-recipient filter remove */ 9834 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 9835 /* enum: multi-recipient filter subscribe */ 9836 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 9837 /* enum: multi-recipient filter unsubscribe */ 9838 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 9839 /* enum: replace one recipient with another (warning - the filter handle may 9840 * change) 9841 */ 9842 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 9843 /* filter handle (for remove / unsubscribe operations) */ 9844 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 9845 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 9846 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 9847 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 9848 /* The port ID associated with the v-adaptor which should contain this filter. 9849 */ 9850 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 9851 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 9852 /* fields to include in match criteria */ 9853 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 9854 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 9855 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16 9856 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 9857 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 9858 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16 9859 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 9860 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 9861 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16 9862 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 9863 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 9864 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16 9865 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 9866 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 9867 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16 9868 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 9869 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 9870 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16 9871 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 9872 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 9873 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16 9874 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 9875 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 9876 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16 9877 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 9878 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 9879 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16 9880 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 9881 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 9882 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16 9883 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 9884 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 9885 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16 9886 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 9887 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 9888 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16 9889 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 9890 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 9891 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 9892 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9893 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9894 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 9895 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9896 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9897 /* receive destination */ 9898 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 9899 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 9900 /* enum: drop packets */ 9901 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 9902 /* enum: receive to host */ 9903 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 9904 /* enum: receive to MC */ 9905 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 9906 /* enum: loop back to TXDP 0 */ 9907 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 9908 /* enum: loop back to TXDP 1 */ 9909 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 9910 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9911 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 9912 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 9913 /* receive mode */ 9914 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 9915 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 9916 /* enum: receive to just the specified queue */ 9917 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 9918 /* enum: receive to multiple queues using RSS context */ 9919 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 9920 /* enum: receive to multiple queues using .1p mapping */ 9921 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 9922 /* enum: install a filter entry that will never match; for test purposes only 9923 */ 9924 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9925 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9926 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9927 * MC_CMD_DOT1P_MAPPING_ALLOC. 9928 */ 9929 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 9930 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 9931 /* transmit domain (reserved; set to 0) */ 9932 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 9933 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 9934 /* transmit destination (either set the MAC and/or PM bits for explicit 9935 * control, or set this field to TX_DEST_DEFAULT for sensible default 9936 * behaviour) 9937 */ 9938 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 9939 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 9940 /* enum: request default behaviour (based on filter type) */ 9941 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 9942 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40 9943 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 9944 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 9945 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40 9946 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 9947 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 9948 /* source MAC address to match (as bytes in network order) */ 9949 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 9950 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 9951 /* source port to match (as bytes in network order) */ 9952 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 9953 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 9954 /* destination MAC address to match (as bytes in network order) */ 9955 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 9956 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 9957 /* destination port to match (as bytes in network order) */ 9958 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 9959 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 9960 /* Ethernet type to match (as bytes in network order) */ 9961 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 9962 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 9963 /* Inner VLAN tag to match (as bytes in network order) */ 9964 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 9965 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 9966 /* Outer VLAN tag to match (as bytes in network order) */ 9967 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 9968 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 9969 /* IP protocol to match (in low byte; set high byte to 0) */ 9970 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 9971 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 9972 /* Firmware defined register 0 to match (reserved; set to 0) */ 9973 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 9974 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 9975 /* Firmware defined register 1 to match (reserved; set to 0) */ 9976 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 9977 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 9978 /* source IP address to match (as bytes in network order; set last 12 bytes to 9979 * 0 for IPv4 address) 9980 */ 9981 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 9982 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 9983 /* destination IP address to match (as bytes in network order; set last 12 9984 * bytes to 0 for IPv4 address) 9985 */ 9986 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 9987 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 9988 9989 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 9990 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 9991 * supported on Medford only). 9992 */ 9993 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 9994 /* identifies the type of operation requested */ 9995 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 9996 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 9997 /* Enum values, see field(s): */ 9998 /* MC_CMD_FILTER_OP_IN/OP */ 9999 /* filter handle (for remove / unsubscribe operations) */ 10000 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 10001 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 10002 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 10003 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 10004 /* The port ID associated with the v-adaptor which should contain this filter. 10005 */ 10006 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 10007 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 10008 /* fields to include in match criteria */ 10009 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 10010 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 10011 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16 10012 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 10013 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 10014 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16 10015 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 10016 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 10017 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16 10018 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 10019 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 10020 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16 10021 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 10022 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 10023 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16 10024 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 10025 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 10026 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16 10027 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 10028 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 10029 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16 10030 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 10031 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 10032 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16 10033 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 10034 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 10035 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16 10036 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 10037 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 10038 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16 10039 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 10040 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 10041 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16 10042 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 10043 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 10044 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16 10045 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 10046 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 10047 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16 10048 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 10049 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 10050 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16 10051 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 10052 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 10053 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16 10054 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 10055 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 10056 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16 10057 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 10058 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 10059 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16 10060 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 10061 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 10062 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16 10063 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 10064 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 10065 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16 10066 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 10067 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 10068 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16 10069 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 10070 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 10071 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16 10072 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 10073 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 10074 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16 10075 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 10076 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 10077 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16 10078 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 10079 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 10080 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16 10081 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 10082 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 10083 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16 10084 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 10085 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 10086 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16 10087 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 10088 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 10089 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 10090 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 10091 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 10092 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 10093 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 10094 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 10095 /* receive destination */ 10096 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 10097 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 10098 /* enum: drop packets */ 10099 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 10100 /* enum: receive to host */ 10101 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 10102 /* enum: receive to MC */ 10103 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 10104 /* enum: loop back to TXDP 0 */ 10105 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 10106 /* enum: loop back to TXDP 1 */ 10107 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 10108 /* receive queue handle (for multiple queue modes, this is the base queue) */ 10109 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 10110 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 10111 /* receive mode */ 10112 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 10113 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 10114 /* enum: receive to just the specified queue */ 10115 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 10116 /* enum: receive to multiple queues using RSS context */ 10117 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 10118 /* enum: receive to multiple queues using .1p mapping */ 10119 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 10120 /* enum: install a filter entry that will never match; for test purposes only 10121 */ 10122 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 10123 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 10124 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 10125 * MC_CMD_DOT1P_MAPPING_ALLOC. 10126 */ 10127 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 10128 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 10129 /* transmit domain (reserved; set to 0) */ 10130 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 10131 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 10132 /* transmit destination (either set the MAC and/or PM bits for explicit 10133 * control, or set this field to TX_DEST_DEFAULT for sensible default 10134 * behaviour) 10135 */ 10136 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 10137 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 10138 /* enum: request default behaviour (based on filter type) */ 10139 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 10140 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40 10141 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 10142 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 10143 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40 10144 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 10145 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 10146 /* source MAC address to match (as bytes in network order) */ 10147 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 10148 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 10149 /* source port to match (as bytes in network order) */ 10150 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 10151 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 10152 /* destination MAC address to match (as bytes in network order) */ 10153 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 10154 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 10155 /* destination port to match (as bytes in network order) */ 10156 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 10157 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 10158 /* Ethernet type to match (as bytes in network order) */ 10159 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 10160 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 10161 /* Inner VLAN tag to match (as bytes in network order) */ 10162 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 10163 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 10164 /* Outer VLAN tag to match (as bytes in network order) */ 10165 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 10166 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 10167 /* IP protocol to match (in low byte; set high byte to 0) */ 10168 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 10169 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 10170 /* Firmware defined register 0 to match (reserved; set to 0) */ 10171 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 10172 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 10173 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 10174 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 10175 * VXLAN/NVGRE, or 1 for Geneve) 10176 */ 10177 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 10178 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 10179 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72 10180 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 10181 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 10182 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72 10183 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 10184 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 10185 /* enum: Match VXLAN traffic with this VNI */ 10186 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 10187 /* enum: Match Geneve traffic with this VNI */ 10188 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 10189 /* enum: Reserved for experimental development use */ 10190 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 10191 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72 10192 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 10193 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 10194 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72 10195 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 10196 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 10197 /* enum: Match NVGRE traffic with this VSID */ 10198 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 10199 /* source IP address to match (as bytes in network order; set last 12 bytes to 10200 * 0 for IPv4 address) 10201 */ 10202 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 10203 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 10204 /* destination IP address to match (as bytes in network order; set last 12 10205 * bytes to 0 for IPv4 address) 10206 */ 10207 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 10208 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 10209 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 10210 * order) 10211 */ 10212 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 10213 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 10214 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 10215 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 10216 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 10217 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 10218 * network order) 10219 */ 10220 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 10221 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 10222 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 10223 * order) 10224 */ 10225 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 10226 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 10227 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 10228 */ 10229 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 10230 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 10231 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 10232 */ 10233 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 10234 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 10235 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 10236 */ 10237 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 10238 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 10239 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 10240 * 0) 10241 */ 10242 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 10243 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 10244 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 10245 * to 0) 10246 */ 10247 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 10248 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 10249 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 10250 * to 0) 10251 */ 10252 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 10253 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 10254 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 10255 * order; set last 12 bytes to 0 for IPv4 address) 10256 */ 10257 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 10258 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 10259 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 10260 * order; set last 12 bytes to 0 for IPv4 address) 10261 */ 10262 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 10263 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 10264 10265 /* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional 10266 * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via 10267 * its rte_flow API. This extension is only useful with the sfc_efx driver 10268 * included as part of DPDK, used in conjunction with the dpdk datapath 10269 * firmware variant. 10270 */ 10271 #define MC_CMD_FILTER_OP_V3_IN_LEN 180 10272 /* identifies the type of operation requested */ 10273 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0 10274 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4 10275 /* Enum values, see field(s): */ 10276 /* MC_CMD_FILTER_OP_IN/OP */ 10277 /* filter handle (for remove / unsubscribe operations) */ 10278 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4 10279 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8 10280 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4 10281 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8 10282 /* The port ID associated with the v-adaptor which should contain this filter. 10283 */ 10284 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12 10285 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4 10286 /* fields to include in match criteria */ 10287 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16 10288 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4 10289 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16 10290 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0 10291 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1 10292 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16 10293 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1 10294 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1 10295 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16 10296 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2 10297 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1 10298 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16 10299 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3 10300 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1 10301 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16 10302 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4 10303 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1 10304 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16 10305 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5 10306 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1 10307 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16 10308 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6 10309 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1 10310 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16 10311 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7 10312 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1 10313 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16 10314 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8 10315 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1 10316 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16 10317 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9 10318 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1 10319 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16 10320 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10 10321 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1 10322 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16 10323 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11 10324 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1 10325 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16 10326 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12 10327 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1 10328 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16 10329 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13 10330 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1 10331 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16 10332 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14 10333 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 10334 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16 10335 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15 10336 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 10337 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16 10338 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16 10339 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1 10340 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16 10341 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17 10342 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1 10343 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16 10344 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 10345 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 10346 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16 10347 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19 10348 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 10349 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16 10350 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 10351 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 10352 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16 10353 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21 10354 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 10355 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16 10356 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22 10357 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1 10358 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16 10359 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23 10360 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1 10361 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16 10362 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 10363 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 10364 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16 10365 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 10366 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 10367 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 10368 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 10369 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 10370 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 10371 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 10372 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 10373 /* receive destination */ 10374 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20 10375 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4 10376 /* enum: drop packets */ 10377 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0 10378 /* enum: receive to host */ 10379 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1 10380 /* enum: receive to MC */ 10381 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2 10382 /* enum: loop back to TXDP 0 */ 10383 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3 10384 /* enum: loop back to TXDP 1 */ 10385 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4 10386 /* receive queue handle (for multiple queue modes, this is the base queue) */ 10387 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24 10388 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4 10389 /* receive mode */ 10390 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28 10391 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4 10392 /* enum: receive to just the specified queue */ 10393 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0 10394 /* enum: receive to multiple queues using RSS context */ 10395 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1 10396 /* enum: receive to multiple queues using .1p mapping */ 10397 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2 10398 /* enum: install a filter entry that will never match; for test purposes only 10399 */ 10400 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 10401 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 10402 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 10403 * MC_CMD_DOT1P_MAPPING_ALLOC. 10404 */ 10405 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32 10406 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4 10407 /* transmit domain (reserved; set to 0) */ 10408 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36 10409 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4 10410 /* transmit destination (either set the MAC and/or PM bits for explicit 10411 * control, or set this field to TX_DEST_DEFAULT for sensible default 10412 * behaviour) 10413 */ 10414 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40 10415 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4 10416 /* enum: request default behaviour (based on filter type) */ 10417 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff 10418 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40 10419 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0 10420 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1 10421 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40 10422 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1 10423 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1 10424 /* source MAC address to match (as bytes in network order) */ 10425 #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44 10426 #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6 10427 /* source port to match (as bytes in network order) */ 10428 #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50 10429 #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2 10430 /* destination MAC address to match (as bytes in network order) */ 10431 #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52 10432 #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6 10433 /* destination port to match (as bytes in network order) */ 10434 #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58 10435 #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2 10436 /* Ethernet type to match (as bytes in network order) */ 10437 #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60 10438 #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2 10439 /* Inner VLAN tag to match (as bytes in network order) */ 10440 #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62 10441 #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2 10442 /* Outer VLAN tag to match (as bytes in network order) */ 10443 #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64 10444 #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2 10445 /* IP protocol to match (in low byte; set high byte to 0) */ 10446 #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66 10447 #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2 10448 /* Firmware defined register 0 to match (reserved; set to 0) */ 10449 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68 10450 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4 10451 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 10452 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 10453 * VXLAN/NVGRE, or 1 for Geneve) 10454 */ 10455 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72 10456 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4 10457 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72 10458 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0 10459 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24 10460 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72 10461 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24 10462 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8 10463 /* enum: Match VXLAN traffic with this VNI */ 10464 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0 10465 /* enum: Match Geneve traffic with this VNI */ 10466 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1 10467 /* enum: Reserved for experimental development use */ 10468 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe 10469 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72 10470 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0 10471 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24 10472 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72 10473 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24 10474 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8 10475 /* enum: Match NVGRE traffic with this VSID */ 10476 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0 10477 /* source IP address to match (as bytes in network order; set last 12 bytes to 10478 * 0 for IPv4 address) 10479 */ 10480 #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76 10481 #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16 10482 /* destination IP address to match (as bytes in network order; set last 12 10483 * bytes to 0 for IPv4 address) 10484 */ 10485 #define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92 10486 #define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16 10487 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 10488 * order) 10489 */ 10490 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108 10491 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6 10492 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 10493 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114 10494 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2 10495 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 10496 * network order) 10497 */ 10498 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116 10499 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6 10500 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 10501 * order) 10502 */ 10503 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122 10504 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2 10505 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 10506 */ 10507 #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124 10508 #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2 10509 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 10510 */ 10511 #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126 10512 #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2 10513 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 10514 */ 10515 #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128 10516 #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2 10517 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 10518 * 0) 10519 */ 10520 #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130 10521 #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2 10522 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 10523 * to 0) 10524 */ 10525 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132 10526 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4 10527 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 10528 * to 0) 10529 */ 10530 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136 10531 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4 10532 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 10533 * order; set last 12 bytes to 0 for IPv4 address) 10534 */ 10535 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140 10536 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16 10537 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 10538 * order; set last 12 bytes to 0 for IPv4 address) 10539 */ 10540 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156 10541 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16 10542 /* Set an action for all packets matching this filter. The DPDK driver and dpdk 10543 * f/w variant use their own specific delivery structures, which are documented 10544 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything 10545 * other than MATCH_ACTION_NONE when the NIC is running another f/w variant 10546 * will cause the filter insertion to fail with ENOTSUP. 10547 */ 10548 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172 10549 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4 10550 /* enum: do nothing extra */ 10551 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0 10552 /* enum: Set the match flag in the packet prefix for packets matching the 10553 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 10554 * support the DPDK rte_flow "FLAG" action. 10555 */ 10556 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1 10557 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching 10558 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 10559 * support the DPDK rte_flow "MARK" action. 10560 */ 10561 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2 10562 /* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the 10563 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX) 10564 * will cause the filter insertion to fail with EINVAL. 10565 */ 10566 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176 10567 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4 10568 10569 /* MC_CMD_FILTER_OP_OUT msgresponse */ 10570 #define MC_CMD_FILTER_OP_OUT_LEN 12 10571 /* identifies the type of operation requested */ 10572 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 10573 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4 10574 /* Enum values, see field(s): */ 10575 /* MC_CMD_FILTER_OP_IN/OP */ 10576 /* Returned filter handle (for insert / subscribe operations). Note that these 10577 * handles should be considered opaque to the host, although a value of 10578 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 10579 */ 10580 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 10581 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 10582 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 10583 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 10584 /* enum: guaranteed invalid filter handle (low 32 bits) */ 10585 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 10586 /* enum: guaranteed invalid filter handle (high 32 bits) */ 10587 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 10588 10589 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 10590 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 10591 /* identifies the type of operation requested */ 10592 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 10593 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 10594 /* Enum values, see field(s): */ 10595 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 10596 /* Returned filter handle (for insert / subscribe operations). Note that these 10597 * handles should be considered opaque to the host, although a value of 10598 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 10599 */ 10600 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 10601 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 10602 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 10603 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 10604 /* Enum values, see field(s): */ 10605 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 10606 10607 10608 /***********************************/ 10609 /* MC_CMD_GET_PARSER_DISP_INFO 10610 * Get information related to the parser-dispatcher subsystem 10611 */ 10612 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 10613 #undef MC_CMD_0xe4_PRIVILEGE_CTG 10614 10615 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10616 10617 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 10618 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 10619 /* identifies the type of operation requested */ 10620 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 10621 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 10622 /* enum: read the list of supported RX filter matches */ 10623 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 10624 /* enum: read flags indicating restrictions on filter insertion for the calling 10625 * client 10626 */ 10627 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 10628 /* enum: read properties relating to security rules (Medford-only; for use by 10629 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 10630 */ 10631 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 10632 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 10633 * encapsulated frames, which follow a different match sequence to normal 10634 * frames (Medford only) 10635 */ 10636 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 10637 /* enum: read the list of supported matches for the encapsulation detection 10638 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later) 10639 */ 10640 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5 10641 10642 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 10643 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 10644 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 10645 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020 10646 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 10647 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4) 10648 /* identifies the type of operation requested */ 10649 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 10650 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 10651 /* Enum values, see field(s): */ 10652 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 10653 /* number of supported match types */ 10654 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 10655 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 10656 /* array of supported match types (valid MATCH_FIELDS values for 10657 * MC_CMD_FILTER_OP) sorted in decreasing priority order 10658 */ 10659 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 10660 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 10661 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 10662 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 10663 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253 10664 10665 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 10666 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 10667 /* identifies the type of operation requested */ 10668 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 10669 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4 10670 /* Enum values, see field(s): */ 10671 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 10672 /* bitfield of filter insertion restrictions */ 10673 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 10674 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4 10675 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4 10676 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 10677 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 10678 10679 /* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is 10680 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value 10681 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the 10682 * supported match types that can be used in the encapsulation detection rules 10683 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. 10684 */ 10685 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8 10686 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252 10687 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020 10688 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num)) 10689 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4) 10690 /* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */ 10691 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0 10692 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4 10693 /* Enum values, see field(s): */ 10694 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 10695 /* number of supported match types */ 10696 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4 10697 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4 10698 /* array of supported match types (valid MATCH_FLAGS values for 10699 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order 10700 */ 10701 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8 10702 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4 10703 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0 10704 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61 10705 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253 10706 10707 10708 /***********************************/ 10709 /* MC_CMD_PARSER_DISP_RW 10710 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 10711 * Please note that this interface is only of use to debug tools which have 10712 * knowledge of firmware and hardware data structures; nothing here is intended 10713 * for use by normal driver code. Note that although this command is in the 10714 * Admin privilege group, in tamperproof adapters, only read operations are 10715 * permitted. 10716 */ 10717 #define MC_CMD_PARSER_DISP_RW 0xe5 10718 #undef MC_CMD_0xe5_PRIVILEGE_CTG 10719 10720 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10721 10722 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 10723 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 10724 /* identifies the target of the operation */ 10725 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 10726 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 10727 /* enum: RX dispatcher CPU */ 10728 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 10729 /* enum: TX dispatcher CPU */ 10730 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 10731 /* enum: Lookup engine (with original metadata format). Deprecated; used only 10732 * by cmdclient as a fallback for very old Huntington firmware, and not 10733 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 10734 * instead. 10735 */ 10736 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 10737 /* enum: Lookup engine (with requested metadata format) */ 10738 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 10739 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 10740 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 10741 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 10742 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 10743 /* enum: Miscellaneous other state (only valid for Medford) */ 10744 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 10745 /* identifies the type of operation requested */ 10746 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 10747 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 10748 /* enum: Read a word of DICPU DMEM or a LUE entry */ 10749 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 10750 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on 10751 * tamperproof adapters. 10752 */ 10753 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 10754 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not 10755 * permitted on tamperproof adapters. 10756 */ 10757 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 10758 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 10759 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 10760 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 10761 /* selector (for MISC_STATE target) */ 10762 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 10763 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 10764 /* enum: Port to datapath mapping */ 10765 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 10766 /* value to write (for DMEM writes) */ 10767 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 10768 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 10769 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 10770 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 10771 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 10772 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 10773 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 10774 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 10775 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 10776 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 10777 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 10778 /* value to write (for LUE writes) */ 10779 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 10780 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 10781 10782 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 10783 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 10784 /* value read (for DMEM reads) */ 10785 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 10786 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 10787 /* value read (for LUE reads) */ 10788 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 10789 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 10790 /* up to 8 32-bit words of additional soft state from the LUE manager (the 10791 * exact content is firmware-dependent and intended only for debug use) 10792 */ 10793 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 10794 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 10795 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 10796 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 10797 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 10798 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 10799 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 10800 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 10801 10802 10803 /***********************************/ 10804 /* MC_CMD_GET_PF_COUNT 10805 * Get number of PFs on the device. 10806 */ 10807 #define MC_CMD_GET_PF_COUNT 0xb6 10808 #undef MC_CMD_0xb6_PRIVILEGE_CTG 10809 10810 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10811 10812 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 10813 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 10814 10815 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 10816 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 10817 /* Identifies the number of PFs on the device. */ 10818 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 10819 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 10820 10821 10822 /***********************************/ 10823 /* MC_CMD_SET_PF_COUNT 10824 * Set number of PFs on the device. 10825 */ 10826 #define MC_CMD_SET_PF_COUNT 0xb7 10827 10828 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 10829 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 10830 /* New number of PFs on the device. */ 10831 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 10832 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 10833 10834 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 10835 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 10836 10837 10838 /***********************************/ 10839 /* MC_CMD_GET_PORT_ASSIGNMENT 10840 * Get port assignment for current PCI function. 10841 */ 10842 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 10843 #undef MC_CMD_0xb8_PRIVILEGE_CTG 10844 10845 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10846 10847 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 10848 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 10849 10850 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 10851 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 10852 /* Identifies the port assignment for this function. */ 10853 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 10854 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 10855 10856 10857 /***********************************/ 10858 /* MC_CMD_SET_PORT_ASSIGNMENT 10859 * Set port assignment for current PCI function. 10860 */ 10861 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 10862 #undef MC_CMD_0xb9_PRIVILEGE_CTG 10863 10864 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10865 10866 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 10867 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 10868 /* Identifies the port assignment for this function. */ 10869 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 10870 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 10871 10872 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 10873 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 10874 10875 10876 /***********************************/ 10877 /* MC_CMD_ALLOC_VIS 10878 * Allocate VIs for current PCI function. 10879 */ 10880 #define MC_CMD_ALLOC_VIS 0x8b 10881 #undef MC_CMD_0x8b_PRIVILEGE_CTG 10882 10883 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10884 10885 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 10886 #define MC_CMD_ALLOC_VIS_IN_LEN 8 10887 /* The minimum number of VIs that is acceptable */ 10888 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 10889 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 10890 /* The maximum number of VIs that would be useful */ 10891 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 10892 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4 10893 10894 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 10895 * Use extended version in new code. 10896 */ 10897 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 10898 /* The number of VIs allocated on this function */ 10899 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 10900 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 10901 /* The base absolute VI number allocated to this function. Required to 10902 * correctly interpret wakeup events. 10903 */ 10904 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 10905 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4 10906 10907 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 10908 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 10909 /* The number of VIs allocated on this function */ 10910 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 10911 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 10912 /* The base absolute VI number allocated to this function. Required to 10913 * correctly interpret wakeup events. 10914 */ 10915 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 10916 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 10917 /* Function's port vi_shift value (always 0 on Huntington) */ 10918 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 10919 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 10920 10921 10922 /***********************************/ 10923 /* MC_CMD_FREE_VIS 10924 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 10925 * but not freed. 10926 */ 10927 #define MC_CMD_FREE_VIS 0x8c 10928 #undef MC_CMD_0x8c_PRIVILEGE_CTG 10929 10930 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10931 10932 /* MC_CMD_FREE_VIS_IN msgrequest */ 10933 #define MC_CMD_FREE_VIS_IN_LEN 0 10934 10935 /* MC_CMD_FREE_VIS_OUT msgresponse */ 10936 #define MC_CMD_FREE_VIS_OUT_LEN 0 10937 10938 10939 /***********************************/ 10940 /* MC_CMD_GET_SRIOV_CFG 10941 * Get SRIOV config for this PF. 10942 */ 10943 #define MC_CMD_GET_SRIOV_CFG 0xba 10944 #undef MC_CMD_0xba_PRIVILEGE_CTG 10945 10946 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10947 10948 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 10949 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 10950 10951 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 10952 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 10953 /* Number of VFs currently enabled. */ 10954 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 10955 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 10956 /* Max number of VFs before sriov stride and offset may need to be changed. */ 10957 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 10958 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 10959 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 10960 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 10961 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8 10962 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 10963 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 10964 /* RID offset of first VF from PF. */ 10965 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 10966 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 10967 /* RID offset of each subsequent VF from the previous. */ 10968 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 10969 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 10970 10971 10972 /***********************************/ 10973 /* MC_CMD_SET_SRIOV_CFG 10974 * Set SRIOV config for this PF. 10975 */ 10976 #define MC_CMD_SET_SRIOV_CFG 0xbb 10977 #undef MC_CMD_0xbb_PRIVILEGE_CTG 10978 10979 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10980 10981 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 10982 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 10983 /* Number of VFs currently enabled. */ 10984 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 10985 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 10986 /* Max number of VFs before sriov stride and offset may need to be changed. */ 10987 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 10988 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 10989 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 10990 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 10991 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8 10992 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 10993 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 10994 /* RID offset of first VF from PF, or 0 for no change, or 10995 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 10996 */ 10997 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 10998 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 10999 /* RID offset of each subsequent VF from the previous, 0 for no change, or 11000 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 11001 */ 11002 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 11003 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 11004 11005 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 11006 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 11007 11008 11009 /***********************************/ 11010 /* MC_CMD_GET_VI_ALLOC_INFO 11011 * Get information about number of VI's and base VI number allocated to this 11012 * function. 11013 */ 11014 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 11015 #undef MC_CMD_0x8d_PRIVILEGE_CTG 11016 11017 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11018 11019 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 11020 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 11021 11022 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 11023 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 11024 /* The number of VIs allocated on this function */ 11025 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 11026 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 11027 /* The base absolute VI number allocated to this function. Required to 11028 * correctly interpret wakeup events. 11029 */ 11030 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 11031 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 11032 /* Function's port vi_shift value (always 0 on Huntington) */ 11033 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 11034 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 11035 11036 11037 /***********************************/ 11038 /* MC_CMD_DUMP_VI_STATE 11039 * For CmdClient use. Dump pertinent information on a specific absolute VI. 11040 */ 11041 #define MC_CMD_DUMP_VI_STATE 0x8e 11042 #undef MC_CMD_0x8e_PRIVILEGE_CTG 11043 11044 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11045 11046 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 11047 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 11048 /* The VI number to query. */ 11049 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 11050 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 11051 11052 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 11053 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 11054 /* The PF part of the function owning this VI. */ 11055 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 11056 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 11057 /* The VF part of the function owning this VI. */ 11058 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 11059 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 11060 /* Base of VIs allocated to this function. */ 11061 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 11062 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 11063 /* Count of VIs allocated to the owner function. */ 11064 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 11065 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 11066 /* Base interrupt vector allocated to this function. */ 11067 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 11068 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 11069 /* Number of interrupt vectors allocated to this function. */ 11070 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 11071 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 11072 /* Raw evq ptr table data. */ 11073 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 11074 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 11075 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 11076 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 11077 /* Raw evq timer table data. */ 11078 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 11079 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 11080 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 11081 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 11082 /* Combined metadata field. */ 11083 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 11084 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 11085 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28 11086 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 11087 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 11088 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28 11089 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 11090 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 11091 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28 11092 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 11093 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 11094 /* TXDPCPU raw table data for queue. */ 11095 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 11096 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 11097 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 11098 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 11099 /* TXDPCPU raw table data for queue. */ 11100 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 11101 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 11102 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 11103 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 11104 /* TXDPCPU raw table data for queue. */ 11105 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 11106 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 11107 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 11108 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 11109 /* Combined metadata field. */ 11110 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 11111 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 11112 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 11113 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 11114 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56 11115 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 11116 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 11117 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56 11118 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 11119 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 11120 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56 11121 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 11122 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 11123 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56 11124 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 11125 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 11126 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56 11127 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 11128 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 11129 /* RXDPCPU raw table data for queue. */ 11130 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 11131 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 11132 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 11133 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 11134 /* RXDPCPU raw table data for queue. */ 11135 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 11136 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 11137 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 11138 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 11139 /* Reserved, currently 0. */ 11140 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 11141 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 11142 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 11143 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 11144 /* Combined metadata field. */ 11145 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 11146 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 11147 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 11148 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 11149 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88 11150 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 11151 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 11152 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88 11153 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 11154 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 11155 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88 11156 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 11157 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 11158 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88 11159 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 11160 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 11161 11162 11163 /***********************************/ 11164 /* MC_CMD_ALLOC_PIOBUF 11165 * Allocate a push I/O buffer for later use with a tx queue. 11166 */ 11167 #define MC_CMD_ALLOC_PIOBUF 0x8f 11168 #undef MC_CMD_0x8f_PRIVILEGE_CTG 11169 11170 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11171 11172 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 11173 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 11174 11175 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 11176 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 11177 /* Handle for allocated push I/O buffer. */ 11178 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 11179 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 11180 11181 11182 /***********************************/ 11183 /* MC_CMD_FREE_PIOBUF 11184 * Free a push I/O buffer. 11185 */ 11186 #define MC_CMD_FREE_PIOBUF 0x90 11187 #undef MC_CMD_0x90_PRIVILEGE_CTG 11188 11189 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11190 11191 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 11192 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 11193 /* Handle for allocated push I/O buffer. */ 11194 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 11195 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 11196 11197 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 11198 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 11199 11200 11201 /***********************************/ 11202 /* MC_CMD_GET_VI_TLP_PROCESSING 11203 * Get TLP steering and ordering information for a VI. 11204 */ 11205 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 11206 #undef MC_CMD_0xb0_PRIVILEGE_CTG 11207 11208 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11209 11210 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 11211 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 11212 /* VI number to get information for. */ 11213 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 11214 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 11215 11216 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 11217 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 11218 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 11219 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 11220 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 11221 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 11222 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 11223 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 11224 /* Use Relaxed ordering model for TLPs on this VI. */ 11225 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 11226 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 11227 /* Use ID based ordering for TLPs on this VI. */ 11228 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 11229 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 11230 /* Set no snoop bit for TLPs on this VI. */ 11231 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 11232 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 11233 /* Enable TPH for TLPs on this VI. */ 11234 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 11235 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 11236 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 11237 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 11238 11239 11240 /***********************************/ 11241 /* MC_CMD_SET_VI_TLP_PROCESSING 11242 * Set TLP steering and ordering information for a VI. 11243 */ 11244 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 11245 #undef MC_CMD_0xb1_PRIVILEGE_CTG 11246 11247 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11248 11249 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 11250 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 11251 /* VI number to set information for. */ 11252 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 11253 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 11254 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 11255 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 11256 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 11257 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 11258 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 11259 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 11260 /* Use Relaxed ordering model for TLPs on this VI. */ 11261 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 11262 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 11263 /* Use ID based ordering for TLPs on this VI. */ 11264 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 11265 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 11266 /* Set the no snoop bit for TLPs on this VI. */ 11267 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 11268 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 11269 /* Enable TPH for TLPs on this VI. */ 11270 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 11271 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 11272 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 11273 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 11274 11275 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 11276 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 11277 11278 11279 /***********************************/ 11280 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 11281 * Get global PCIe steering and transaction processing configuration. 11282 */ 11283 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 11284 #undef MC_CMD_0xbc_PRIVILEGE_CTG 11285 11286 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11287 11288 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 11289 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 11290 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 11291 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 11292 /* enum: MISC. */ 11293 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 11294 /* enum: IDO. */ 11295 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 11296 /* enum: RO. */ 11297 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 11298 /* enum: TPH Type. */ 11299 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 11300 11301 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 11302 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 11303 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 11304 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 11305 /* Enum values, see field(s): */ 11306 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 11307 /* Amalgamated TLP info word. */ 11308 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 11309 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 11310 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4 11311 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 11312 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 11313 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4 11314 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 11315 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 11316 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4 11317 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 11318 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 11319 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4 11320 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 11321 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 11322 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4 11323 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 11324 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 11325 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4 11326 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 11327 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 11328 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4 11329 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 11330 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 11331 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4 11332 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 11333 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 11334 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4 11335 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 11336 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 11337 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4 11338 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 11339 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 11340 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4 11341 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 11342 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 11343 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4 11344 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 11345 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 11346 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4 11347 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 11348 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 11349 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4 11350 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 11351 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 11352 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4 11353 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 11354 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 11355 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4 11356 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 11357 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 11358 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4 11359 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 11360 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 11361 11362 11363 /***********************************/ 11364 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 11365 * Set global PCIe steering and transaction processing configuration. 11366 */ 11367 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 11368 #undef MC_CMD_0xbd_PRIVILEGE_CTG 11369 11370 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11371 11372 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 11373 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 11374 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 11375 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 11376 /* Enum values, see field(s): */ 11377 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 11378 /* Amalgamated TLP info word. */ 11379 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 11380 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 11381 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4 11382 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 11383 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 11384 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4 11385 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 11386 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 11387 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4 11388 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 11389 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 11390 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4 11391 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 11392 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 11393 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4 11394 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 11395 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 11396 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4 11397 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 11398 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 11399 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4 11400 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 11401 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 11402 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4 11403 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 11404 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 11405 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4 11406 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 11407 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 11408 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4 11409 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 11410 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 11411 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4 11412 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 11413 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 11414 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4 11415 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 11416 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 11417 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4 11418 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 11419 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 11420 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4 11421 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 11422 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 11423 11424 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 11425 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 11426 11427 11428 /***********************************/ 11429 /* MC_CMD_SATELLITE_DOWNLOAD 11430 * Download a new set of images to the satellite CPUs from the host. 11431 */ 11432 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 11433 #undef MC_CMD_0x91_PRIVILEGE_CTG 11434 11435 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11436 11437 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 11438 * are subtle, and so downloads must proceed in a number of phases. 11439 * 11440 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 11441 * 11442 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 11443 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 11444 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 11445 * download may be aborted using CHUNK_ID_ABORT. 11446 * 11447 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 11448 * similar to PHASE_IMEMS. 11449 * 11450 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 11451 * 11452 * After any error (a requested abort is not considered to be an error) the 11453 * sequence must be restarted from PHASE_RESET. 11454 */ 11455 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 11456 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 11457 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 1020 11458 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 11459 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4) 11460 /* Download phase. (Note: the IDLE phase is used internally and is never valid 11461 * in a command from the host.) 11462 */ 11463 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 11464 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 11465 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 11466 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 11467 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 11468 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 11469 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 11470 /* Target for download. (These match the blob numbers defined in 11471 * mc_flash_layout.h.) 11472 */ 11473 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 11474 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 11475 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11476 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 11477 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11478 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 11479 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11480 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 11481 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11482 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 11483 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11484 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 11485 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11486 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 11487 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11488 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 11489 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11490 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 11491 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11492 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 11493 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11494 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 11495 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11496 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 11497 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 11498 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 11499 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 11500 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 11501 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 11502 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 11503 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 11504 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 11505 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 11506 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 11507 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 11508 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 11509 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 11510 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 11511 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 11512 /* enum: Last chunk, containing checksum rather than data */ 11513 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 11514 /* enum: Abort download of this item */ 11515 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 11516 /* Length of this chunk in bytes */ 11517 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 11518 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 11519 /* Data for this chunk */ 11520 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 11521 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 11522 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 11523 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 11524 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM_MCDI2 251 11525 11526 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 11527 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 11528 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 11529 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 11530 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 11531 /* Extra status information */ 11532 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 11533 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 11534 /* enum: Code download OK, completed. */ 11535 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 11536 /* enum: Code download aborted as requested. */ 11537 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 11538 /* enum: Code download OK so far, send next chunk. */ 11539 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 11540 /* enum: Download phases out of sequence */ 11541 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 11542 /* enum: Bad target for this phase */ 11543 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 11544 /* enum: Chunk ID out of sequence */ 11545 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 11546 /* enum: Chunk length zero or too large */ 11547 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 11548 /* enum: Checksum was incorrect */ 11549 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 11550 11551 11552 /***********************************/ 11553 /* MC_CMD_GET_CAPABILITIES 11554 * Get device capabilities. 11555 * 11556 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 11557 * reference inherent device capabilities as opposed to current NVRAM config. 11558 */ 11559 #define MC_CMD_GET_CAPABILITIES 0xbe 11560 #undef MC_CMD_0xbe_PRIVILEGE_CTG 11561 11562 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11563 11564 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 11565 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 11566 11567 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 11568 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 11569 /* First word of flags. */ 11570 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 11571 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4 11572 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0 11573 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 11574 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 11575 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0 11576 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 11577 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 11578 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0 11579 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 11580 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 11581 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 11582 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 11583 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 11584 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0 11585 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 11586 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 11587 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0 11588 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 11589 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 11590 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0 11591 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 11592 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 11593 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 11594 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 11595 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 11596 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 11597 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 11598 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11599 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 11600 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 11601 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 11602 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0 11603 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 11604 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 11605 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0 11606 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 11607 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 11608 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 11609 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 11610 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 11611 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0 11612 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 11613 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 11614 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0 11615 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 11616 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 11617 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0 11618 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 11619 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 11620 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0 11621 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 11622 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 11623 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0 11624 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 11625 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 11626 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0 11627 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 11628 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 11629 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0 11630 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 11631 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 11632 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0 11633 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 11634 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 11635 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0 11636 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 11637 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 11638 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0 11639 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 11640 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 11641 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0 11642 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 11643 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 11644 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0 11645 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 11646 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 11647 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0 11648 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 11649 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 11650 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 11651 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 11652 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 11653 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0 11654 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 11655 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 11656 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0 11657 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 11658 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 11659 /* RxDPCPU firmware id. */ 11660 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 11661 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 11662 /* enum: Standard RXDP firmware */ 11663 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 11664 /* enum: Low latency RXDP firmware */ 11665 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 11666 /* enum: Packed stream RXDP firmware */ 11667 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 11668 /* enum: Rules engine RXDP firmware */ 11669 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5 11670 /* enum: DPDK RXDP firmware */ 11671 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6 11672 /* enum: BIST RXDP firmware */ 11673 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 11674 /* enum: RXDP Test firmware image 1 */ 11675 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 11676 /* enum: RXDP Test firmware image 2 */ 11677 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 11678 /* enum: RXDP Test firmware image 3 */ 11679 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 11680 /* enum: RXDP Test firmware image 4 */ 11681 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 11682 /* enum: RXDP Test firmware image 5 */ 11683 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 11684 /* enum: RXDP Test firmware image 6 */ 11685 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 11686 /* enum: RXDP Test firmware image 7 */ 11687 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 11688 /* enum: RXDP Test firmware image 8 */ 11689 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 11690 /* enum: RXDP Test firmware image 9 */ 11691 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 11692 /* enum: RXDP Test firmware image 10 */ 11693 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c 11694 /* TxDPCPU firmware id. */ 11695 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 11696 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 11697 /* enum: Standard TXDP firmware */ 11698 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 11699 /* enum: Low latency TXDP firmware */ 11700 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 11701 /* enum: High packet rate TXDP firmware */ 11702 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 11703 /* enum: Rules engine TXDP firmware */ 11704 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5 11705 /* enum: DPDK TXDP firmware */ 11706 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6 11707 /* enum: BIST TXDP firmware */ 11708 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 11709 /* enum: TXDP Test firmware image 1 */ 11710 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 11711 /* enum: TXDP Test firmware image 2 */ 11712 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 11713 /* enum: TXDP CSR bus test firmware */ 11714 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 11715 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 11716 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 11717 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8 11718 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 11719 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 11720 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8 11721 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 11722 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 11723 /* enum: reserved value - do not use (may indicate alternative interpretation 11724 * of REV field in future) 11725 */ 11726 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 11727 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 11728 * development only) 11729 */ 11730 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 11731 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 11732 */ 11733 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 11734 /* enum: RX PD firmware with approximately Siena-compatible behaviour 11735 * (Huntington development only) 11736 */ 11737 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 11738 /* enum: Full featured RX PD production firmware */ 11739 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 11740 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11741 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 11742 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 11743 * (Huntington development only) 11744 */ 11745 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11746 /* enum: Low latency RX PD production firmware */ 11747 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 11748 /* enum: Packed stream RX PD production firmware */ 11749 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 11750 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 11751 * tests (Medford development only) 11752 */ 11753 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 11754 /* enum: Rules engine RX PD production firmware */ 11755 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 11756 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11757 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9 11758 /* enum: DPDK RX PD production firmware */ 11759 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa 11760 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11761 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11762 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 11763 * encapsulations (Medford development only) 11764 */ 11765 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 11766 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 11767 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 11768 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10 11769 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 11770 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 11771 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10 11772 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 11773 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 11774 /* enum: reserved value - do not use (may indicate alternative interpretation 11775 * of REV field in future) 11776 */ 11777 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 11778 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 11779 * development only) 11780 */ 11781 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 11782 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 11783 */ 11784 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 11785 /* enum: TX PD firmware with approximately Siena-compatible behaviour 11786 * (Huntington development only) 11787 */ 11788 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 11789 /* enum: Full featured TX PD production firmware */ 11790 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 11791 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11792 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 11793 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 11794 * (Huntington development only) 11795 */ 11796 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11797 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 11798 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 11799 * tests (Medford development only) 11800 */ 11801 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 11802 /* enum: Rules engine TX PD production firmware */ 11803 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 11804 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11805 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9 11806 /* enum: DPDK TX PD production firmware */ 11807 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa 11808 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11809 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11810 /* Hardware capabilities of NIC */ 11811 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 11812 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4 11813 /* Licensed capabilities */ 11814 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 11815 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4 11816 11817 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 11818 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 11819 11820 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 11821 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 11822 /* First word of flags. */ 11823 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 11824 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4 11825 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0 11826 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 11827 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 11828 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0 11829 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 11830 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 11831 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0 11832 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 11833 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 11834 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 11835 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 11836 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 11837 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0 11838 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 11839 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 11840 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0 11841 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 11842 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 11843 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0 11844 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 11845 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 11846 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 11847 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 11848 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 11849 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 11850 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 11851 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11852 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 11853 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 11854 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 11855 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0 11856 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 11857 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 11858 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0 11859 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 11860 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 11861 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 11862 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 11863 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 11864 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0 11865 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 11866 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 11867 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0 11868 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 11869 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 11870 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0 11871 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 11872 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 11873 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0 11874 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 11875 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 11876 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0 11877 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 11878 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 11879 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0 11880 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 11881 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 11882 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0 11883 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 11884 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 11885 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0 11886 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 11887 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 11888 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0 11889 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 11890 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 11891 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0 11892 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 11893 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 11894 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0 11895 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 11896 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 11897 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0 11898 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 11899 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 11900 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0 11901 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 11902 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 11903 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 11904 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 11905 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 11906 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0 11907 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 11908 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 11909 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0 11910 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 11911 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 11912 /* RxDPCPU firmware id. */ 11913 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 11914 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 11915 /* enum: Standard RXDP firmware */ 11916 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 11917 /* enum: Low latency RXDP firmware */ 11918 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 11919 /* enum: Packed stream RXDP firmware */ 11920 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 11921 /* enum: Rules engine RXDP firmware */ 11922 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5 11923 /* enum: DPDK RXDP firmware */ 11924 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6 11925 /* enum: BIST RXDP firmware */ 11926 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 11927 /* enum: RXDP Test firmware image 1 */ 11928 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 11929 /* enum: RXDP Test firmware image 2 */ 11930 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 11931 /* enum: RXDP Test firmware image 3 */ 11932 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 11933 /* enum: RXDP Test firmware image 4 */ 11934 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 11935 /* enum: RXDP Test firmware image 5 */ 11936 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 11937 /* enum: RXDP Test firmware image 6 */ 11938 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 11939 /* enum: RXDP Test firmware image 7 */ 11940 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 11941 /* enum: RXDP Test firmware image 8 */ 11942 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 11943 /* enum: RXDP Test firmware image 9 */ 11944 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 11945 /* enum: RXDP Test firmware image 10 */ 11946 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c 11947 /* TxDPCPU firmware id. */ 11948 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 11949 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 11950 /* enum: Standard TXDP firmware */ 11951 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 11952 /* enum: Low latency TXDP firmware */ 11953 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 11954 /* enum: High packet rate TXDP firmware */ 11955 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 11956 /* enum: Rules engine TXDP firmware */ 11957 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5 11958 /* enum: DPDK TXDP firmware */ 11959 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6 11960 /* enum: BIST TXDP firmware */ 11961 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 11962 /* enum: TXDP Test firmware image 1 */ 11963 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 11964 /* enum: TXDP Test firmware image 2 */ 11965 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 11966 /* enum: TXDP CSR bus test firmware */ 11967 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 11968 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 11969 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 11970 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8 11971 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 11972 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 11973 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8 11974 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 11975 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 11976 /* enum: reserved value - do not use (may indicate alternative interpretation 11977 * of REV field in future) 11978 */ 11979 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 11980 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 11981 * development only) 11982 */ 11983 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 11984 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 11985 */ 11986 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 11987 /* enum: RX PD firmware with approximately Siena-compatible behaviour 11988 * (Huntington development only) 11989 */ 11990 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 11991 /* enum: Full featured RX PD production firmware */ 11992 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 11993 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11994 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 11995 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 11996 * (Huntington development only) 11997 */ 11998 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11999 /* enum: Low latency RX PD production firmware */ 12000 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 12001 /* enum: Packed stream RX PD production firmware */ 12002 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 12003 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 12004 * tests (Medford development only) 12005 */ 12006 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 12007 /* enum: Rules engine RX PD production firmware */ 12008 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 12009 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12010 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9 12011 /* enum: DPDK RX PD production firmware */ 12012 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa 12013 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12014 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12015 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 12016 * encapsulations (Medford development only) 12017 */ 12018 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 12019 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 12020 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 12021 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10 12022 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 12023 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 12024 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10 12025 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 12026 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 12027 /* enum: reserved value - do not use (may indicate alternative interpretation 12028 * of REV field in future) 12029 */ 12030 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 12031 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 12032 * development only) 12033 */ 12034 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 12035 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 12036 */ 12037 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 12038 /* enum: TX PD firmware with approximately Siena-compatible behaviour 12039 * (Huntington development only) 12040 */ 12041 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 12042 /* enum: Full featured TX PD production firmware */ 12043 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 12044 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 12045 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 12046 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 12047 * (Huntington development only) 12048 */ 12049 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 12050 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 12051 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 12052 * tests (Medford development only) 12053 */ 12054 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 12055 /* enum: Rules engine TX PD production firmware */ 12056 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 12057 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12058 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9 12059 /* enum: DPDK TX PD production firmware */ 12060 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa 12061 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12062 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12063 /* Hardware capabilities of NIC */ 12064 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 12065 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4 12066 /* Licensed capabilities */ 12067 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 12068 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4 12069 /* Second word of flags. Not present on older firmware (check the length). */ 12070 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 12071 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4 12072 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20 12073 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 12074 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 12075 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20 12076 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 12077 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 12078 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20 12079 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 12080 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 12081 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20 12082 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 12083 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 12084 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20 12085 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 12086 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 12087 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20 12088 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 12089 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 12090 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 12091 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 12092 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 12093 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 12094 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 12095 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 12096 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20 12097 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 12098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 12099 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20 12100 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 12101 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 12102 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20 12103 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 12104 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 12105 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20 12106 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 12107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 12108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20 12109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 12110 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 12111 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 12112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 12113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 12114 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20 12115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 12116 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 12117 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20 12118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 12119 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 12120 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20 12121 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15 12122 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1 12123 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20 12124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16 12125 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1 12126 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20 12127 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17 12128 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1 12129 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 12130 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 12131 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 12132 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20 12133 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19 12134 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1 12135 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20 12136 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20 12137 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1 12138 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 12139 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 12140 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 12141 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 12142 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 12143 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 12144 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20 12145 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22 12146 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1 12147 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 12148 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 12149 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 12150 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20 12151 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24 12152 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1 12153 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20 12154 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25 12155 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1 12156 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 12157 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 12158 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 12159 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 12160 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 12161 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 12162 #define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20 12163 #define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28 12164 #define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1 12165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20 12166 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29 12167 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1 12168 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20 12169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30 12170 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1 12171 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 12172 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 12173 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 12174 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 12175 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 12176 */ 12177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 12178 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 12179 /* One byte per PF containing the number of the external port assigned to this 12180 * PF, indexed by PF number. Special values indicate that a PF is either not 12181 * present or not assigned. 12182 */ 12183 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 12184 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 12185 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 12186 /* enum: The caller is not permitted to access information on this PF. */ 12187 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 12188 /* enum: PF does not exist. */ 12189 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 12190 /* enum: PF does exist but is not assigned to any external port. */ 12191 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 12192 /* enum: This value indicates that PF is assigned, but it cannot be expressed 12193 * in this field. It is intended for a possible future situation where a more 12194 * complex scheme of PFs to ports mapping is being used. The future driver 12195 * should look for a new field supporting the new scheme. The current/old 12196 * driver should treat this value as PF_NOT_ASSIGNED. 12197 */ 12198 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 12199 /* One byte per PF containing the number of its VFs, indexed by PF number. A 12200 * special value indicates that a PF is not present. 12201 */ 12202 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 12203 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 12204 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 12205 /* enum: The caller is not permitted to access information on this PF. */ 12206 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 12207 /* enum: PF does not exist. */ 12208 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 12209 /* Number of VIs available for each external port */ 12210 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 12211 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 12212 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 12213 /* Size of RX descriptor cache expressed as binary logarithm The actual size 12214 * equals (2 ^ RX_DESC_CACHE_SIZE) 12215 */ 12216 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 12217 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 12218 /* Size of TX descriptor cache expressed as binary logarithm The actual size 12219 * equals (2 ^ TX_DESC_CACHE_SIZE) 12220 */ 12221 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 12222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 12223 /* Total number of available PIO buffers */ 12224 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 12225 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 12226 /* Size of a single PIO buffer */ 12227 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 12228 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 12229 12230 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 12231 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 12232 /* First word of flags. */ 12233 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 12234 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4 12235 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0 12236 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 12237 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 12238 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0 12239 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 12240 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 12241 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0 12242 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 12243 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 12244 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 12245 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 12246 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 12247 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0 12248 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 12249 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 12250 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0 12251 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 12252 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 12253 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0 12254 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 12255 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 12256 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 12257 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 12258 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 12259 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 12260 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 12261 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 12262 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 12263 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 12264 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 12265 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0 12266 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 12267 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 12268 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0 12269 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 12270 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 12271 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 12272 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 12273 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 12274 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0 12275 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 12276 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 12277 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0 12278 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 12279 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 12280 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0 12281 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 12282 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 12283 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0 12284 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 12285 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 12286 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0 12287 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 12288 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 12289 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0 12290 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 12291 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 12292 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0 12293 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 12294 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 12295 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0 12296 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 12297 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 12298 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0 12299 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 12300 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 12301 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0 12302 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 12303 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 12304 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0 12305 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 12306 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 12307 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0 12308 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 12309 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 12310 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0 12311 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 12312 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 12313 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 12314 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 12315 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 12316 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0 12317 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 12318 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 12319 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0 12320 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 12321 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 12322 /* RxDPCPU firmware id. */ 12323 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 12324 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 12325 /* enum: Standard RXDP firmware */ 12326 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 12327 /* enum: Low latency RXDP firmware */ 12328 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 12329 /* enum: Packed stream RXDP firmware */ 12330 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 12331 /* enum: Rules engine RXDP firmware */ 12332 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5 12333 /* enum: DPDK RXDP firmware */ 12334 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6 12335 /* enum: BIST RXDP firmware */ 12336 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 12337 /* enum: RXDP Test firmware image 1 */ 12338 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 12339 /* enum: RXDP Test firmware image 2 */ 12340 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 12341 /* enum: RXDP Test firmware image 3 */ 12342 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 12343 /* enum: RXDP Test firmware image 4 */ 12344 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 12345 /* enum: RXDP Test firmware image 5 */ 12346 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 12347 /* enum: RXDP Test firmware image 6 */ 12348 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 12349 /* enum: RXDP Test firmware image 7 */ 12350 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 12351 /* enum: RXDP Test firmware image 8 */ 12352 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 12353 /* enum: RXDP Test firmware image 9 */ 12354 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 12355 /* enum: RXDP Test firmware image 10 */ 12356 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c 12357 /* TxDPCPU firmware id. */ 12358 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 12359 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 12360 /* enum: Standard TXDP firmware */ 12361 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 12362 /* enum: Low latency TXDP firmware */ 12363 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 12364 /* enum: High packet rate TXDP firmware */ 12365 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 12366 /* enum: Rules engine TXDP firmware */ 12367 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5 12368 /* enum: DPDK TXDP firmware */ 12369 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6 12370 /* enum: BIST TXDP firmware */ 12371 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 12372 /* enum: TXDP Test firmware image 1 */ 12373 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 12374 /* enum: TXDP Test firmware image 2 */ 12375 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 12376 /* enum: TXDP CSR bus test firmware */ 12377 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 12378 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 12379 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 12380 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8 12381 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 12382 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 12383 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8 12384 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 12385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 12386 /* enum: reserved value - do not use (may indicate alternative interpretation 12387 * of REV field in future) 12388 */ 12389 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 12390 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 12391 * development only) 12392 */ 12393 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 12394 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 12395 */ 12396 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 12397 /* enum: RX PD firmware with approximately Siena-compatible behaviour 12398 * (Huntington development only) 12399 */ 12400 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 12401 /* enum: Full featured RX PD production firmware */ 12402 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 12403 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 12404 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 12405 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 12406 * (Huntington development only) 12407 */ 12408 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 12409 /* enum: Low latency RX PD production firmware */ 12410 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 12411 /* enum: Packed stream RX PD production firmware */ 12412 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 12413 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 12414 * tests (Medford development only) 12415 */ 12416 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 12417 /* enum: Rules engine RX PD production firmware */ 12418 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 12419 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12420 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9 12421 /* enum: DPDK RX PD production firmware */ 12422 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa 12423 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12424 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12425 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 12426 * encapsulations (Medford development only) 12427 */ 12428 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 12429 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 12430 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 12431 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10 12432 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 12433 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 12434 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10 12435 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 12436 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 12437 /* enum: reserved value - do not use (may indicate alternative interpretation 12438 * of REV field in future) 12439 */ 12440 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 12441 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 12442 * development only) 12443 */ 12444 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 12445 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 12446 */ 12447 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 12448 /* enum: TX PD firmware with approximately Siena-compatible behaviour 12449 * (Huntington development only) 12450 */ 12451 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 12452 /* enum: Full featured TX PD production firmware */ 12453 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 12454 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 12455 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 12456 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 12457 * (Huntington development only) 12458 */ 12459 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 12460 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 12461 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 12462 * tests (Medford development only) 12463 */ 12464 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 12465 /* enum: Rules engine TX PD production firmware */ 12466 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 12467 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12468 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9 12469 /* enum: DPDK TX PD production firmware */ 12470 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa 12471 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12472 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12473 /* Hardware capabilities of NIC */ 12474 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 12475 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4 12476 /* Licensed capabilities */ 12477 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 12478 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4 12479 /* Second word of flags. Not present on older firmware (check the length). */ 12480 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 12481 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4 12482 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20 12483 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 12484 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 12485 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20 12486 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 12487 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 12488 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20 12489 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 12490 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 12491 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20 12492 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 12493 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 12494 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20 12495 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 12496 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 12497 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20 12498 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 12499 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 12500 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 12501 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 12502 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 12503 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 12504 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 12505 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 12506 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20 12507 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 12508 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 12509 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20 12510 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 12511 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 12512 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20 12513 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 12514 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 12515 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20 12516 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 12517 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 12518 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20 12519 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 12520 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 12521 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 12522 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 12523 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 12524 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20 12525 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 12526 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 12527 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20 12528 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 12529 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 12530 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20 12531 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15 12532 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1 12533 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20 12534 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16 12535 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1 12536 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20 12537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17 12538 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1 12539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 12540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 12541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 12542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20 12543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19 12544 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1 12545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20 12546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20 12547 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1 12548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 12549 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 12550 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 12551 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 12552 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 12553 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 12554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20 12555 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22 12556 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1 12557 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 12558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 12559 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 12560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20 12561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24 12562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1 12563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20 12564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25 12565 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1 12566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 12567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 12568 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 12569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 12570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 12571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 12572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20 12573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28 12574 #define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1 12575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20 12576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29 12577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1 12578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20 12579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30 12580 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1 12581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 12582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 12583 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 12584 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 12585 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 12586 */ 12587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 12588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 12589 /* One byte per PF containing the number of the external port assigned to this 12590 * PF, indexed by PF number. Special values indicate that a PF is either not 12591 * present or not assigned. 12592 */ 12593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 12594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 12595 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 12596 /* enum: The caller is not permitted to access information on this PF. */ 12597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 12598 /* enum: PF does not exist. */ 12599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 12600 /* enum: PF does exist but is not assigned to any external port. */ 12601 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 12602 /* enum: This value indicates that PF is assigned, but it cannot be expressed 12603 * in this field. It is intended for a possible future situation where a more 12604 * complex scheme of PFs to ports mapping is being used. The future driver 12605 * should look for a new field supporting the new scheme. The current/old 12606 * driver should treat this value as PF_NOT_ASSIGNED. 12607 */ 12608 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 12609 /* One byte per PF containing the number of its VFs, indexed by PF number. A 12610 * special value indicates that a PF is not present. 12611 */ 12612 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 12613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 12614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 12615 /* enum: The caller is not permitted to access information on this PF. */ 12616 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 12617 /* enum: PF does not exist. */ 12618 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 12619 /* Number of VIs available for each external port */ 12620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 12621 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 12622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 12623 /* Size of RX descriptor cache expressed as binary logarithm The actual size 12624 * equals (2 ^ RX_DESC_CACHE_SIZE) 12625 */ 12626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 12627 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 12628 /* Size of TX descriptor cache expressed as binary logarithm The actual size 12629 * equals (2 ^ TX_DESC_CACHE_SIZE) 12630 */ 12631 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 12632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 12633 /* Total number of available PIO buffers */ 12634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 12635 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 12636 /* Size of a single PIO buffer */ 12637 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 12638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 12639 /* On chips later than Medford the amount of address space assigned to each VI 12640 * is configurable. This is a global setting that the driver must query to 12641 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 12642 * with 8k VI windows. 12643 */ 12644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 12645 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 12646 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 12647 * CTPIO is not mapped. 12648 */ 12649 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 12650 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 12651 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 12652 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 12653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 12654 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 12655 * (SF-115995-SW) in the present configuration of firmware and port mode. 12656 */ 12657 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 12658 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 12659 /* Number of buffers per adapter that can be used for VFIFO Stuffing 12660 * (SF-115995-SW) in the present configuration of firmware and port mode. 12661 */ 12662 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 12663 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 12664 12665 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */ 12666 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78 12667 /* First word of flags. */ 12668 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0 12669 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4 12670 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0 12671 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3 12672 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1 12673 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0 12674 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4 12675 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1 12676 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0 12677 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5 12678 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1 12679 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 12680 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 12681 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 12682 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0 12683 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7 12684 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 12685 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0 12686 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8 12687 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 12688 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0 12689 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9 12690 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1 12691 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 12692 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 12693 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 12694 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 12695 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 12696 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 12697 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 12698 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 12699 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 12700 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0 12701 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13 12702 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 12703 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0 12704 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14 12705 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1 12706 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 12707 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 12708 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 12709 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0 12710 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16 12711 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1 12712 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0 12713 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17 12714 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1 12715 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0 12716 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18 12717 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1 12718 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0 12719 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19 12720 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1 12721 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0 12722 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20 12723 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1 12724 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0 12725 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21 12726 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1 12727 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0 12728 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22 12729 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1 12730 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0 12731 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23 12732 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1 12733 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0 12734 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24 12735 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1 12736 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0 12737 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25 12738 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1 12739 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0 12740 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26 12741 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1 12742 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0 12743 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27 12744 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 12745 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0 12746 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28 12747 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1 12748 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 12749 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 12750 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 12751 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0 12752 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30 12753 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1 12754 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0 12755 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31 12756 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1 12757 /* RxDPCPU firmware id. */ 12758 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4 12759 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2 12760 /* enum: Standard RXDP firmware */ 12761 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0 12762 /* enum: Low latency RXDP firmware */ 12763 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1 12764 /* enum: Packed stream RXDP firmware */ 12765 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2 12766 /* enum: Rules engine RXDP firmware */ 12767 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5 12768 /* enum: DPDK RXDP firmware */ 12769 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6 12770 /* enum: BIST RXDP firmware */ 12771 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a 12772 /* enum: RXDP Test firmware image 1 */ 12773 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 12774 /* enum: RXDP Test firmware image 2 */ 12775 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 12776 /* enum: RXDP Test firmware image 3 */ 12777 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 12778 /* enum: RXDP Test firmware image 4 */ 12779 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 12780 /* enum: RXDP Test firmware image 5 */ 12781 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105 12782 /* enum: RXDP Test firmware image 6 */ 12783 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 12784 /* enum: RXDP Test firmware image 7 */ 12785 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 12786 /* enum: RXDP Test firmware image 8 */ 12787 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 12788 /* enum: RXDP Test firmware image 9 */ 12789 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 12790 /* enum: RXDP Test firmware image 10 */ 12791 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c 12792 /* TxDPCPU firmware id. */ 12793 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6 12794 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2 12795 /* enum: Standard TXDP firmware */ 12796 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0 12797 /* enum: Low latency TXDP firmware */ 12798 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1 12799 /* enum: High packet rate TXDP firmware */ 12800 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3 12801 /* enum: Rules engine TXDP firmware */ 12802 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5 12803 /* enum: DPDK TXDP firmware */ 12804 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6 12805 /* enum: BIST TXDP firmware */ 12806 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d 12807 /* enum: TXDP Test firmware image 1 */ 12808 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 12809 /* enum: TXDP Test firmware image 2 */ 12810 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 12811 /* enum: TXDP CSR bus test firmware */ 12812 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103 12813 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8 12814 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2 12815 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8 12816 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0 12817 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12 12818 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8 12819 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12 12820 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 12821 /* enum: reserved value - do not use (may indicate alternative interpretation 12822 * of REV field in future) 12823 */ 12824 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0 12825 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 12826 * development only) 12827 */ 12828 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 12829 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 12830 */ 12831 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 12832 /* enum: RX PD firmware with approximately Siena-compatible behaviour 12833 * (Huntington development only) 12834 */ 12835 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 12836 /* enum: Full featured RX PD production firmware */ 12837 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 12838 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 12839 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3 12840 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 12841 * (Huntington development only) 12842 */ 12843 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 12844 /* enum: Low latency RX PD production firmware */ 12845 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 12846 /* enum: Packed stream RX PD production firmware */ 12847 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 12848 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 12849 * tests (Medford development only) 12850 */ 12851 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 12852 /* enum: Rules engine RX PD production firmware */ 12853 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 12854 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12855 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9 12856 /* enum: DPDK RX PD production firmware */ 12857 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa 12858 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12859 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12860 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 12861 * encapsulations (Medford development only) 12862 */ 12863 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 12864 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10 12865 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2 12866 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10 12867 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0 12868 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12 12869 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10 12870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12 12871 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 12872 /* enum: reserved value - do not use (may indicate alternative interpretation 12873 * of REV field in future) 12874 */ 12875 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0 12876 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 12877 * development only) 12878 */ 12879 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 12880 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 12881 */ 12882 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 12883 /* enum: TX PD firmware with approximately Siena-compatible behaviour 12884 * (Huntington development only) 12885 */ 12886 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 12887 /* enum: Full featured TX PD production firmware */ 12888 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 12889 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 12890 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3 12891 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 12892 * (Huntington development only) 12893 */ 12894 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 12895 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 12896 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 12897 * tests (Medford development only) 12898 */ 12899 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 12900 /* enum: Rules engine TX PD production firmware */ 12901 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 12902 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 12903 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9 12904 /* enum: DPDK TX PD production firmware */ 12905 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa 12906 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 12907 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 12908 /* Hardware capabilities of NIC */ 12909 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12 12910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4 12911 /* Licensed capabilities */ 12912 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16 12913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4 12914 /* Second word of flags. Not present on older firmware (check the length). */ 12915 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20 12916 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4 12917 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20 12918 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0 12919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1 12920 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20 12921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1 12922 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1 12923 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20 12924 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2 12925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1 12926 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20 12927 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3 12928 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1 12929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20 12930 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4 12931 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1 12932 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20 12933 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5 12934 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 12935 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 12936 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 12937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 12938 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 12939 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 12940 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 12941 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20 12942 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7 12943 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1 12944 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20 12945 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8 12946 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 12947 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20 12948 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9 12949 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1 12950 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20 12951 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10 12952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1 12953 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20 12954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11 12955 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1 12956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 12957 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 12958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 12959 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20 12960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13 12961 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1 12962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20 12963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14 12964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1 12965 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20 12966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15 12967 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1 12968 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20 12969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16 12970 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1 12971 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20 12972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17 12973 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1 12974 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 12975 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 12976 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 12977 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20 12978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19 12979 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1 12980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20 12981 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20 12982 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1 12983 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 12984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 12985 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 12986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 12987 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 12988 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 12989 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20 12990 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22 12991 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1 12992 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 12993 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 12994 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 12995 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20 12996 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24 12997 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1 12998 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20 12999 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25 13000 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1 13001 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 13002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 13003 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 13004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 13005 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 13006 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 13007 #define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20 13008 #define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28 13009 #define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1 13010 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20 13011 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29 13012 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1 13013 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20 13014 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30 13015 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1 13016 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 13017 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 13018 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 13019 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 13020 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 13021 */ 13022 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 13023 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 13024 /* One byte per PF containing the number of the external port assigned to this 13025 * PF, indexed by PF number. Special values indicate that a PF is either not 13026 * present or not assigned. 13027 */ 13028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 13029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 13030 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 13031 /* enum: The caller is not permitted to access information on this PF. */ 13032 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff 13033 /* enum: PF does not exist. */ 13034 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe 13035 /* enum: PF does exist but is not assigned to any external port. */ 13036 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd 13037 /* enum: This value indicates that PF is assigned, but it cannot be expressed 13038 * in this field. It is intended for a possible future situation where a more 13039 * complex scheme of PFs to ports mapping is being used. The future driver 13040 * should look for a new field supporting the new scheme. The current/old 13041 * driver should treat this value as PF_NOT_ASSIGNED. 13042 */ 13043 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 13044 /* One byte per PF containing the number of its VFs, indexed by PF number. A 13045 * special value indicates that a PF is not present. 13046 */ 13047 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42 13048 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1 13049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16 13050 /* enum: The caller is not permitted to access information on this PF. */ 13051 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 13052 /* enum: PF does not exist. */ 13053 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 13054 /* Number of VIs available for each external port */ 13055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 13056 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 13057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 13058 /* Size of RX descriptor cache expressed as binary logarithm The actual size 13059 * equals (2 ^ RX_DESC_CACHE_SIZE) 13060 */ 13061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66 13062 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1 13063 /* Size of TX descriptor cache expressed as binary logarithm The actual size 13064 * equals (2 ^ TX_DESC_CACHE_SIZE) 13065 */ 13066 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67 13067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1 13068 /* Total number of available PIO buffers */ 13069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68 13070 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2 13071 /* Size of a single PIO buffer */ 13072 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70 13073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2 13074 /* On chips later than Medford the amount of address space assigned to each VI 13075 * is configurable. This is a global setting that the driver must query to 13076 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 13077 * with 8k VI windows. 13078 */ 13079 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72 13080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1 13081 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 13082 * CTPIO is not mapped. 13083 */ 13084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0 13085 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1 13087 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2 13089 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 13090 * (SF-115995-SW) in the present configuration of firmware and port mode. 13091 */ 13092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 13093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 13094 /* Number of buffers per adapter that can be used for VFIFO Stuffing 13095 * (SF-115995-SW) in the present configuration of firmware and port mode. 13096 */ 13097 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 13098 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 13099 /* Entry count in the MAC stats array, including the final GENERATION_END 13100 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 13101 * hold at least this many 64-bit stats values, if they wish to receive all 13102 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 13103 * stats array returned will be truncated. 13104 */ 13105 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76 13106 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2 13107 13108 /* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */ 13109 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84 13110 /* First word of flags. */ 13111 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0 13112 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4 13113 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0 13114 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3 13115 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1 13116 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0 13117 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4 13118 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1 13119 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0 13120 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5 13121 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1 13122 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 13123 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 13124 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 13125 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0 13126 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7 13127 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 13128 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0 13129 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8 13130 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 13131 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0 13132 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9 13133 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1 13134 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 13135 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 13136 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 13137 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 13138 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 13139 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 13140 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 13141 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 13142 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 13143 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0 13144 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13 13145 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 13146 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0 13147 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14 13148 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1 13149 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 13150 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 13151 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 13152 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0 13153 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16 13154 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1 13155 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0 13156 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17 13157 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1 13158 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0 13159 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18 13160 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1 13161 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0 13162 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19 13163 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1 13164 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0 13165 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20 13166 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1 13167 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0 13168 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21 13169 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1 13170 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0 13171 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22 13172 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1 13173 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0 13174 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23 13175 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1 13176 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0 13177 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24 13178 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1 13179 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0 13180 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25 13181 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1 13182 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0 13183 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26 13184 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1 13185 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0 13186 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27 13187 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 13188 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0 13189 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28 13190 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1 13191 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 13192 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 13193 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 13194 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0 13195 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30 13196 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1 13197 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0 13198 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31 13199 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1 13200 /* RxDPCPU firmware id. */ 13201 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4 13202 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2 13203 /* enum: Standard RXDP firmware */ 13204 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0 13205 /* enum: Low latency RXDP firmware */ 13206 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1 13207 /* enum: Packed stream RXDP firmware */ 13208 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2 13209 /* enum: Rules engine RXDP firmware */ 13210 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5 13211 /* enum: DPDK RXDP firmware */ 13212 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6 13213 /* enum: BIST RXDP firmware */ 13214 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a 13215 /* enum: RXDP Test firmware image 1 */ 13216 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 13217 /* enum: RXDP Test firmware image 2 */ 13218 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 13219 /* enum: RXDP Test firmware image 3 */ 13220 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 13221 /* enum: RXDP Test firmware image 4 */ 13222 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 13223 /* enum: RXDP Test firmware image 5 */ 13224 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105 13225 /* enum: RXDP Test firmware image 6 */ 13226 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 13227 /* enum: RXDP Test firmware image 7 */ 13228 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 13229 /* enum: RXDP Test firmware image 8 */ 13230 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 13231 /* enum: RXDP Test firmware image 9 */ 13232 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 13233 /* enum: RXDP Test firmware image 10 */ 13234 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c 13235 /* TxDPCPU firmware id. */ 13236 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6 13237 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2 13238 /* enum: Standard TXDP firmware */ 13239 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0 13240 /* enum: Low latency TXDP firmware */ 13241 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1 13242 /* enum: High packet rate TXDP firmware */ 13243 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3 13244 /* enum: Rules engine TXDP firmware */ 13245 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5 13246 /* enum: DPDK TXDP firmware */ 13247 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6 13248 /* enum: BIST TXDP firmware */ 13249 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d 13250 /* enum: TXDP Test firmware image 1 */ 13251 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 13252 /* enum: TXDP Test firmware image 2 */ 13253 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 13254 /* enum: TXDP CSR bus test firmware */ 13255 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103 13256 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8 13257 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2 13258 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8 13259 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0 13260 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12 13261 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8 13262 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12 13263 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 13264 /* enum: reserved value - do not use (may indicate alternative interpretation 13265 * of REV field in future) 13266 */ 13267 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0 13268 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 13269 * development only) 13270 */ 13271 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 13272 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 13273 */ 13274 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 13275 /* enum: RX PD firmware with approximately Siena-compatible behaviour 13276 * (Huntington development only) 13277 */ 13278 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 13279 /* enum: Full featured RX PD production firmware */ 13280 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 13281 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 13282 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3 13283 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 13284 * (Huntington development only) 13285 */ 13286 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 13287 /* enum: Low latency RX PD production firmware */ 13288 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 13289 /* enum: Packed stream RX PD production firmware */ 13290 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 13291 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 13292 * tests (Medford development only) 13293 */ 13294 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 13295 /* enum: Rules engine RX PD production firmware */ 13296 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 13297 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 13298 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9 13299 /* enum: DPDK RX PD production firmware */ 13300 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa 13301 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 13302 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 13303 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 13304 * encapsulations (Medford development only) 13305 */ 13306 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 13307 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10 13308 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2 13309 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10 13310 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0 13311 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12 13312 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10 13313 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12 13314 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 13315 /* enum: reserved value - do not use (may indicate alternative interpretation 13316 * of REV field in future) 13317 */ 13318 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0 13319 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 13320 * development only) 13321 */ 13322 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 13323 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 13324 */ 13325 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 13326 /* enum: TX PD firmware with approximately Siena-compatible behaviour 13327 * (Huntington development only) 13328 */ 13329 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 13330 /* enum: Full featured TX PD production firmware */ 13331 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 13332 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 13333 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3 13334 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 13335 * (Huntington development only) 13336 */ 13337 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 13338 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 13339 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 13340 * tests (Medford development only) 13341 */ 13342 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 13343 /* enum: Rules engine TX PD production firmware */ 13344 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 13345 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 13346 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9 13347 /* enum: DPDK TX PD production firmware */ 13348 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa 13349 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 13350 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 13351 /* Hardware capabilities of NIC */ 13352 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12 13353 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4 13354 /* Licensed capabilities */ 13355 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16 13356 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4 13357 /* Second word of flags. Not present on older firmware (check the length). */ 13358 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20 13359 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4 13360 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20 13361 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0 13362 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1 13363 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20 13364 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1 13365 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1 13366 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20 13367 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2 13368 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1 13369 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20 13370 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3 13371 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1 13372 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20 13373 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4 13374 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1 13375 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20 13376 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5 13377 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 13378 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 13379 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 13380 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 13381 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 13382 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 13383 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 13384 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20 13385 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7 13386 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1 13387 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20 13388 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8 13389 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 13390 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20 13391 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9 13392 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1 13393 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20 13394 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10 13395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1 13396 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20 13397 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11 13398 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1 13399 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 13400 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 13401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 13402 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20 13403 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13 13404 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1 13405 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20 13406 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14 13407 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1 13408 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20 13409 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15 13410 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1 13411 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20 13412 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16 13413 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1 13414 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20 13415 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17 13416 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1 13417 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 13418 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 13419 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 13420 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20 13421 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19 13422 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1 13423 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20 13424 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20 13425 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1 13426 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 13427 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 13428 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 13429 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 13430 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 13431 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 13432 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20 13433 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22 13434 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1 13435 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 13436 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 13437 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 13438 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20 13439 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24 13440 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1 13441 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20 13442 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25 13443 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1 13444 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 13445 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 13446 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 13447 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 13448 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 13449 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 13450 #define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20 13451 #define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28 13452 #define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1 13453 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20 13454 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29 13455 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1 13456 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20 13457 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30 13458 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1 13459 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 13460 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 13461 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 13462 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 13463 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 13464 */ 13465 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 13466 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 13467 /* One byte per PF containing the number of the external port assigned to this 13468 * PF, indexed by PF number. Special values indicate that a PF is either not 13469 * present or not assigned. 13470 */ 13471 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 13472 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 13473 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 13474 /* enum: The caller is not permitted to access information on this PF. */ 13475 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff 13476 /* enum: PF does not exist. */ 13477 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe 13478 /* enum: PF does exist but is not assigned to any external port. */ 13479 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd 13480 /* enum: This value indicates that PF is assigned, but it cannot be expressed 13481 * in this field. It is intended for a possible future situation where a more 13482 * complex scheme of PFs to ports mapping is being used. The future driver 13483 * should look for a new field supporting the new scheme. The current/old 13484 * driver should treat this value as PF_NOT_ASSIGNED. 13485 */ 13486 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 13487 /* One byte per PF containing the number of its VFs, indexed by PF number. A 13488 * special value indicates that a PF is not present. 13489 */ 13490 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42 13491 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1 13492 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16 13493 /* enum: The caller is not permitted to access information on this PF. */ 13494 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */ 13495 /* enum: PF does not exist. */ 13496 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */ 13497 /* Number of VIs available for each external port */ 13498 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58 13499 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2 13500 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4 13501 /* Size of RX descriptor cache expressed as binary logarithm The actual size 13502 * equals (2 ^ RX_DESC_CACHE_SIZE) 13503 */ 13504 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66 13505 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1 13506 /* Size of TX descriptor cache expressed as binary logarithm The actual size 13507 * equals (2 ^ TX_DESC_CACHE_SIZE) 13508 */ 13509 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67 13510 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1 13511 /* Total number of available PIO buffers */ 13512 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68 13513 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2 13514 /* Size of a single PIO buffer */ 13515 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70 13516 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2 13517 /* On chips later than Medford the amount of address space assigned to each VI 13518 * is configurable. This is a global setting that the driver must query to 13519 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 13520 * with 8k VI windows. 13521 */ 13522 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72 13523 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1 13524 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 13525 * CTPIO is not mapped. 13526 */ 13527 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0 13528 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13529 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1 13530 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13531 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2 13532 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 13533 * (SF-115995-SW) in the present configuration of firmware and port mode. 13534 */ 13535 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 13536 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 13537 /* Number of buffers per adapter that can be used for VFIFO Stuffing 13538 * (SF-115995-SW) in the present configuration of firmware and port mode. 13539 */ 13540 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 13541 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 13542 /* Entry count in the MAC stats array, including the final GENERATION_END 13543 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 13544 * hold at least this many 64-bit stats values, if they wish to receive all 13545 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 13546 * stats array returned will be truncated. 13547 */ 13548 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76 13549 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2 13550 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 13551 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 13552 */ 13553 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80 13554 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4 13555 13556 /* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */ 13557 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148 13558 /* First word of flags. */ 13559 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0 13560 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4 13561 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0 13562 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3 13563 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1 13564 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0 13565 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4 13566 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1 13567 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0 13568 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5 13569 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1 13570 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 13571 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 13572 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 13573 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0 13574 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7 13575 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 13576 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0 13577 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8 13578 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 13579 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0 13580 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9 13581 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1 13582 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 13583 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 13584 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 13585 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 13586 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 13587 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 13588 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 13589 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 13590 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 13591 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0 13592 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13 13593 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 13594 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0 13595 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14 13596 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1 13597 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 13598 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 13599 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 13600 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0 13601 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16 13602 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1 13603 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0 13604 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17 13605 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1 13606 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0 13607 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18 13608 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1 13609 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0 13610 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19 13611 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1 13612 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0 13613 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20 13614 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1 13615 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0 13616 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21 13617 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1 13618 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0 13619 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22 13620 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1 13621 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0 13622 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23 13623 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1 13624 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0 13625 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24 13626 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1 13627 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0 13628 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25 13629 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1 13630 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0 13631 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26 13632 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1 13633 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0 13634 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27 13635 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 13636 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0 13637 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28 13638 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1 13639 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 13640 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 13641 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 13642 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0 13643 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30 13644 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1 13645 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0 13646 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31 13647 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1 13648 /* RxDPCPU firmware id. */ 13649 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4 13650 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2 13651 /* enum: Standard RXDP firmware */ 13652 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0 13653 /* enum: Low latency RXDP firmware */ 13654 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1 13655 /* enum: Packed stream RXDP firmware */ 13656 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2 13657 /* enum: Rules engine RXDP firmware */ 13658 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5 13659 /* enum: DPDK RXDP firmware */ 13660 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6 13661 /* enum: BIST RXDP firmware */ 13662 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a 13663 /* enum: RXDP Test firmware image 1 */ 13664 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 13665 /* enum: RXDP Test firmware image 2 */ 13666 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 13667 /* enum: RXDP Test firmware image 3 */ 13668 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 13669 /* enum: RXDP Test firmware image 4 */ 13670 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 13671 /* enum: RXDP Test firmware image 5 */ 13672 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105 13673 /* enum: RXDP Test firmware image 6 */ 13674 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 13675 /* enum: RXDP Test firmware image 7 */ 13676 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 13677 /* enum: RXDP Test firmware image 8 */ 13678 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 13679 /* enum: RXDP Test firmware image 9 */ 13680 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 13681 /* enum: RXDP Test firmware image 10 */ 13682 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c 13683 /* TxDPCPU firmware id. */ 13684 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6 13685 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2 13686 /* enum: Standard TXDP firmware */ 13687 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0 13688 /* enum: Low latency TXDP firmware */ 13689 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1 13690 /* enum: High packet rate TXDP firmware */ 13691 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3 13692 /* enum: Rules engine TXDP firmware */ 13693 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5 13694 /* enum: DPDK TXDP firmware */ 13695 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6 13696 /* enum: BIST TXDP firmware */ 13697 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d 13698 /* enum: TXDP Test firmware image 1 */ 13699 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 13700 /* enum: TXDP Test firmware image 2 */ 13701 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 13702 /* enum: TXDP CSR bus test firmware */ 13703 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103 13704 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8 13705 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2 13706 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8 13707 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0 13708 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12 13709 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8 13710 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12 13711 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 13712 /* enum: reserved value - do not use (may indicate alternative interpretation 13713 * of REV field in future) 13714 */ 13715 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0 13716 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 13717 * development only) 13718 */ 13719 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 13720 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 13721 */ 13722 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 13723 /* enum: RX PD firmware with approximately Siena-compatible behaviour 13724 * (Huntington development only) 13725 */ 13726 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 13727 /* enum: Full featured RX PD production firmware */ 13728 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 13729 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 13730 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3 13731 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 13732 * (Huntington development only) 13733 */ 13734 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 13735 /* enum: Low latency RX PD production firmware */ 13736 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 13737 /* enum: Packed stream RX PD production firmware */ 13738 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 13739 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 13740 * tests (Medford development only) 13741 */ 13742 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 13743 /* enum: Rules engine RX PD production firmware */ 13744 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 13745 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 13746 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9 13747 /* enum: DPDK RX PD production firmware */ 13748 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa 13749 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 13750 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 13751 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 13752 * encapsulations (Medford development only) 13753 */ 13754 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 13755 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10 13756 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2 13757 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10 13758 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0 13759 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12 13760 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10 13761 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12 13762 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 13763 /* enum: reserved value - do not use (may indicate alternative interpretation 13764 * of REV field in future) 13765 */ 13766 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0 13767 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 13768 * development only) 13769 */ 13770 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 13771 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 13772 */ 13773 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 13774 /* enum: TX PD firmware with approximately Siena-compatible behaviour 13775 * (Huntington development only) 13776 */ 13777 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 13778 /* enum: Full featured TX PD production firmware */ 13779 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 13780 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 13781 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3 13782 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 13783 * (Huntington development only) 13784 */ 13785 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 13786 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 13787 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 13788 * tests (Medford development only) 13789 */ 13790 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 13791 /* enum: Rules engine TX PD production firmware */ 13792 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 13793 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 13794 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9 13795 /* enum: DPDK TX PD production firmware */ 13796 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa 13797 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 13798 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 13799 /* Hardware capabilities of NIC */ 13800 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12 13801 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4 13802 /* Licensed capabilities */ 13803 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16 13804 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4 13805 /* Second word of flags. Not present on older firmware (check the length). */ 13806 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20 13807 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4 13808 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20 13809 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0 13810 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1 13811 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20 13812 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1 13813 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1 13814 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20 13815 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2 13816 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1 13817 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20 13818 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3 13819 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1 13820 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20 13821 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4 13822 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1 13823 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20 13824 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5 13825 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 13826 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 13827 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 13828 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 13829 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 13830 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 13831 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 13832 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20 13833 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7 13834 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1 13835 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20 13836 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8 13837 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 13838 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20 13839 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9 13840 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1 13841 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20 13842 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10 13843 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1 13844 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20 13845 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11 13846 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1 13847 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 13848 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 13849 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 13850 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20 13851 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13 13852 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1 13853 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20 13854 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14 13855 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1 13856 #define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20 13857 #define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15 13858 #define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1 13859 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20 13860 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16 13861 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1 13862 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20 13863 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17 13864 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1 13865 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 13866 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 13867 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 13868 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20 13869 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19 13870 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1 13871 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20 13872 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20 13873 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1 13874 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 13875 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 13876 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 13877 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 13878 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 13879 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 13880 #define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20 13881 #define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22 13882 #define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1 13883 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 13884 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 13885 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 13886 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20 13887 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24 13888 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1 13889 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20 13890 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25 13891 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1 13892 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 13893 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 13894 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 13895 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 13896 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 13897 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 13898 #define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20 13899 #define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28 13900 #define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1 13901 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20 13902 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29 13903 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1 13904 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20 13905 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30 13906 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1 13907 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 13908 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 13909 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 13910 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 13911 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 13912 */ 13913 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 13914 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 13915 /* One byte per PF containing the number of the external port assigned to this 13916 * PF, indexed by PF number. Special values indicate that a PF is either not 13917 * present or not assigned. 13918 */ 13919 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 13920 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 13921 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 13922 /* enum: The caller is not permitted to access information on this PF. */ 13923 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff 13924 /* enum: PF does not exist. */ 13925 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe 13926 /* enum: PF does exist but is not assigned to any external port. */ 13927 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd 13928 /* enum: This value indicates that PF is assigned, but it cannot be expressed 13929 * in this field. It is intended for a possible future situation where a more 13930 * complex scheme of PFs to ports mapping is being used. The future driver 13931 * should look for a new field supporting the new scheme. The current/old 13932 * driver should treat this value as PF_NOT_ASSIGNED. 13933 */ 13934 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 13935 /* One byte per PF containing the number of its VFs, indexed by PF number. A 13936 * special value indicates that a PF is not present. 13937 */ 13938 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42 13939 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1 13940 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16 13941 /* enum: The caller is not permitted to access information on this PF. */ 13942 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */ 13943 /* enum: PF does not exist. */ 13944 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */ 13945 /* Number of VIs available for each external port */ 13946 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58 13947 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2 13948 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4 13949 /* Size of RX descriptor cache expressed as binary logarithm The actual size 13950 * equals (2 ^ RX_DESC_CACHE_SIZE) 13951 */ 13952 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66 13953 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1 13954 /* Size of TX descriptor cache expressed as binary logarithm The actual size 13955 * equals (2 ^ TX_DESC_CACHE_SIZE) 13956 */ 13957 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67 13958 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1 13959 /* Total number of available PIO buffers */ 13960 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68 13961 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2 13962 /* Size of a single PIO buffer */ 13963 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70 13964 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2 13965 /* On chips later than Medford the amount of address space assigned to each VI 13966 * is configurable. This is a global setting that the driver must query to 13967 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 13968 * with 8k VI windows. 13969 */ 13970 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72 13971 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1 13972 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 13973 * CTPIO is not mapped. 13974 */ 13975 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0 13976 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13977 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1 13978 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 13979 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2 13980 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 13981 * (SF-115995-SW) in the present configuration of firmware and port mode. 13982 */ 13983 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 13984 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 13985 /* Number of buffers per adapter that can be used for VFIFO Stuffing 13986 * (SF-115995-SW) in the present configuration of firmware and port mode. 13987 */ 13988 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 13989 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 13990 /* Entry count in the MAC stats array, including the final GENERATION_END 13991 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 13992 * hold at least this many 64-bit stats values, if they wish to receive all 13993 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 13994 * stats array returned will be truncated. 13995 */ 13996 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76 13997 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2 13998 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 13999 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 14000 */ 14001 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80 14002 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4 14003 /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 14004 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 14005 * they create an RX queue. Due to hardware limitations, only a small number of 14006 * different buffer sizes may be available concurrently. Nonzero entries in 14007 * this array are the sizes of buffers which the system guarantees will be 14008 * available for use. If the list is empty, there are no limitations on 14009 * concurrent buffer sizes. 14010 */ 14011 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 14012 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 14013 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 14014 14015 /* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */ 14016 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152 14017 /* First word of flags. */ 14018 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0 14019 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4 14020 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0 14021 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3 14022 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1 14023 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0 14024 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4 14025 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1 14026 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0 14027 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5 14028 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1 14029 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 14030 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 14031 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 14032 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0 14033 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7 14034 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 14035 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0 14036 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8 14037 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 14038 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0 14039 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9 14040 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1 14041 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 14042 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 14043 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 14044 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 14045 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 14046 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 14047 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 14048 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 14049 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 14050 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0 14051 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13 14052 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 14053 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0 14054 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14 14055 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1 14056 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 14057 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 14058 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 14059 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0 14060 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16 14061 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1 14062 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0 14063 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17 14064 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1 14065 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0 14066 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18 14067 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1 14068 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0 14069 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19 14070 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1 14071 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0 14072 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20 14073 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1 14074 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0 14075 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21 14076 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1 14077 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0 14078 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22 14079 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1 14080 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0 14081 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23 14082 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1 14083 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0 14084 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24 14085 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1 14086 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0 14087 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25 14088 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1 14089 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0 14090 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26 14091 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1 14092 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0 14093 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27 14094 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 14095 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0 14096 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28 14097 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1 14098 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 14099 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 14100 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 14101 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0 14102 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30 14103 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1 14104 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0 14105 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31 14106 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1 14107 /* RxDPCPU firmware id. */ 14108 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4 14109 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2 14110 /* enum: Standard RXDP firmware */ 14111 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0 14112 /* enum: Low latency RXDP firmware */ 14113 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1 14114 /* enum: Packed stream RXDP firmware */ 14115 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2 14116 /* enum: Rules engine RXDP firmware */ 14117 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5 14118 /* enum: DPDK RXDP firmware */ 14119 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6 14120 /* enum: BIST RXDP firmware */ 14121 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a 14122 /* enum: RXDP Test firmware image 1 */ 14123 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 14124 /* enum: RXDP Test firmware image 2 */ 14125 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 14126 /* enum: RXDP Test firmware image 3 */ 14127 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 14128 /* enum: RXDP Test firmware image 4 */ 14129 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 14130 /* enum: RXDP Test firmware image 5 */ 14131 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105 14132 /* enum: RXDP Test firmware image 6 */ 14133 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 14134 /* enum: RXDP Test firmware image 7 */ 14135 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 14136 /* enum: RXDP Test firmware image 8 */ 14137 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 14138 /* enum: RXDP Test firmware image 9 */ 14139 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 14140 /* enum: RXDP Test firmware image 10 */ 14141 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c 14142 /* TxDPCPU firmware id. */ 14143 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6 14144 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2 14145 /* enum: Standard TXDP firmware */ 14146 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0 14147 /* enum: Low latency TXDP firmware */ 14148 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1 14149 /* enum: High packet rate TXDP firmware */ 14150 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3 14151 /* enum: Rules engine TXDP firmware */ 14152 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5 14153 /* enum: DPDK TXDP firmware */ 14154 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6 14155 /* enum: BIST TXDP firmware */ 14156 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d 14157 /* enum: TXDP Test firmware image 1 */ 14158 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 14159 /* enum: TXDP Test firmware image 2 */ 14160 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 14161 /* enum: TXDP CSR bus test firmware */ 14162 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103 14163 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8 14164 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2 14165 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8 14166 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0 14167 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12 14168 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8 14169 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12 14170 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 14171 /* enum: reserved value - do not use (may indicate alternative interpretation 14172 * of REV field in future) 14173 */ 14174 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0 14175 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 14176 * development only) 14177 */ 14178 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 14179 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 14180 */ 14181 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 14182 /* enum: RX PD firmware with approximately Siena-compatible behaviour 14183 * (Huntington development only) 14184 */ 14185 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 14186 /* enum: Full featured RX PD production firmware */ 14187 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 14188 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 14189 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3 14190 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 14191 * (Huntington development only) 14192 */ 14193 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 14194 /* enum: Low latency RX PD production firmware */ 14195 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 14196 /* enum: Packed stream RX PD production firmware */ 14197 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 14198 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 14199 * tests (Medford development only) 14200 */ 14201 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 14202 /* enum: Rules engine RX PD production firmware */ 14203 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 14204 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 14205 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9 14206 /* enum: DPDK RX PD production firmware */ 14207 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa 14208 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 14209 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 14210 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 14211 * encapsulations (Medford development only) 14212 */ 14213 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 14214 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10 14215 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2 14216 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10 14217 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0 14218 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12 14219 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10 14220 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12 14221 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 14222 /* enum: reserved value - do not use (may indicate alternative interpretation 14223 * of REV field in future) 14224 */ 14225 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0 14226 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 14227 * development only) 14228 */ 14229 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 14230 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 14231 */ 14232 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 14233 /* enum: TX PD firmware with approximately Siena-compatible behaviour 14234 * (Huntington development only) 14235 */ 14236 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 14237 /* enum: Full featured TX PD production firmware */ 14238 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 14239 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 14240 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3 14241 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 14242 * (Huntington development only) 14243 */ 14244 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 14245 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 14246 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 14247 * tests (Medford development only) 14248 */ 14249 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 14250 /* enum: Rules engine TX PD production firmware */ 14251 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 14252 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 14253 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9 14254 /* enum: DPDK TX PD production firmware */ 14255 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa 14256 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 14257 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 14258 /* Hardware capabilities of NIC */ 14259 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12 14260 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4 14261 /* Licensed capabilities */ 14262 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16 14263 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4 14264 /* Second word of flags. Not present on older firmware (check the length). */ 14265 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20 14266 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4 14267 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20 14268 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0 14269 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1 14270 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20 14271 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1 14272 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1 14273 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20 14274 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2 14275 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1 14276 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20 14277 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3 14278 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1 14279 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20 14280 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4 14281 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1 14282 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20 14283 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5 14284 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 14285 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 14286 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 14287 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 14288 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 14289 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 14290 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 14291 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20 14292 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7 14293 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1 14294 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20 14295 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8 14296 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 14297 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20 14298 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9 14299 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1 14300 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20 14301 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10 14302 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1 14303 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20 14304 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11 14305 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1 14306 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 14307 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 14308 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 14309 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20 14310 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13 14311 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1 14312 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20 14313 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14 14314 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1 14315 #define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20 14316 #define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15 14317 #define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1 14318 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20 14319 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16 14320 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1 14321 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20 14322 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17 14323 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1 14324 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 14325 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 14326 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 14327 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20 14328 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19 14329 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1 14330 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20 14331 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20 14332 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1 14333 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 14334 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 14335 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 14336 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 14337 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 14338 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 14339 #define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20 14340 #define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22 14341 #define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1 14342 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 14343 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 14344 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 14345 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20 14346 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24 14347 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1 14348 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20 14349 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25 14350 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1 14351 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 14352 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 14353 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 14354 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 14355 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 14356 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 14357 #define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20 14358 #define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28 14359 #define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1 14360 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20 14361 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29 14362 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1 14363 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20 14364 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30 14365 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1 14366 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 14367 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 14368 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 14369 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 14370 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 14371 */ 14372 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 14373 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 14374 /* One byte per PF containing the number of the external port assigned to this 14375 * PF, indexed by PF number. Special values indicate that a PF is either not 14376 * present or not assigned. 14377 */ 14378 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 14379 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 14380 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 14381 /* enum: The caller is not permitted to access information on this PF. */ 14382 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff 14383 /* enum: PF does not exist. */ 14384 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe 14385 /* enum: PF does exist but is not assigned to any external port. */ 14386 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd 14387 /* enum: This value indicates that PF is assigned, but it cannot be expressed 14388 * in this field. It is intended for a possible future situation where a more 14389 * complex scheme of PFs to ports mapping is being used. The future driver 14390 * should look for a new field supporting the new scheme. The current/old 14391 * driver should treat this value as PF_NOT_ASSIGNED. 14392 */ 14393 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 14394 /* One byte per PF containing the number of its VFs, indexed by PF number. A 14395 * special value indicates that a PF is not present. 14396 */ 14397 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42 14398 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1 14399 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16 14400 /* enum: The caller is not permitted to access information on this PF. */ 14401 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */ 14402 /* enum: PF does not exist. */ 14403 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */ 14404 /* Number of VIs available for each external port */ 14405 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58 14406 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2 14407 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4 14408 /* Size of RX descriptor cache expressed as binary logarithm The actual size 14409 * equals (2 ^ RX_DESC_CACHE_SIZE) 14410 */ 14411 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66 14412 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1 14413 /* Size of TX descriptor cache expressed as binary logarithm The actual size 14414 * equals (2 ^ TX_DESC_CACHE_SIZE) 14415 */ 14416 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67 14417 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1 14418 /* Total number of available PIO buffers */ 14419 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68 14420 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2 14421 /* Size of a single PIO buffer */ 14422 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70 14423 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2 14424 /* On chips later than Medford the amount of address space assigned to each VI 14425 * is configurable. This is a global setting that the driver must query to 14426 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 14427 * with 8k VI windows. 14428 */ 14429 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72 14430 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1 14431 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 14432 * CTPIO is not mapped. 14433 */ 14434 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0 14435 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 14436 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1 14437 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 14438 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2 14439 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 14440 * (SF-115995-SW) in the present configuration of firmware and port mode. 14441 */ 14442 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 14443 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 14444 /* Number of buffers per adapter that can be used for VFIFO Stuffing 14445 * (SF-115995-SW) in the present configuration of firmware and port mode. 14446 */ 14447 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 14448 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 14449 /* Entry count in the MAC stats array, including the final GENERATION_END 14450 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 14451 * hold at least this many 64-bit stats values, if they wish to receive all 14452 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 14453 * stats array returned will be truncated. 14454 */ 14455 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76 14456 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2 14457 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 14458 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 14459 */ 14460 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80 14461 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4 14462 /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 14463 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 14464 * they create an RX queue. Due to hardware limitations, only a small number of 14465 * different buffer sizes may be available concurrently. Nonzero entries in 14466 * this array are the sizes of buffers which the system guarantees will be 14467 * available for use. If the list is empty, there are no limitations on 14468 * concurrent buffer sizes. 14469 */ 14470 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 14471 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 14472 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 14473 /* Third word of flags. Not present on older firmware (check the length). */ 14474 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148 14475 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4 14476 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148 14477 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0 14478 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1 14479 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148 14480 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1 14481 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1 14482 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148 14483 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2 14484 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1 14485 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148 14486 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3 14487 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1 14488 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148 14489 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4 14490 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1 14491 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148 14492 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5 14493 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1 14494 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148 14495 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6 14496 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1 14497 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148 14498 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7 14499 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1 14500 14501 /* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */ 14502 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160 14503 /* First word of flags. */ 14504 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0 14505 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4 14506 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0 14507 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3 14508 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1 14509 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0 14510 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4 14511 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1 14512 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0 14513 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5 14514 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1 14515 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 14516 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 14517 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 14518 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0 14519 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7 14520 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 14521 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0 14522 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8 14523 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 14524 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0 14525 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9 14526 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1 14527 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 14528 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 14529 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 14530 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 14531 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 14532 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 14533 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 14534 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 14535 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 14536 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0 14537 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13 14538 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 14539 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0 14540 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14 14541 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1 14542 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 14543 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 14544 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 14545 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0 14546 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16 14547 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1 14548 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0 14549 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17 14550 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1 14551 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0 14552 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18 14553 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1 14554 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0 14555 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19 14556 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1 14557 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0 14558 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20 14559 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1 14560 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0 14561 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21 14562 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1 14563 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0 14564 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22 14565 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1 14566 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0 14567 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23 14568 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1 14569 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0 14570 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24 14571 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1 14572 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0 14573 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25 14574 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1 14575 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0 14576 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26 14577 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1 14578 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0 14579 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27 14580 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 14581 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0 14582 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28 14583 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1 14584 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 14585 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 14586 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 14587 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0 14588 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30 14589 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1 14590 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0 14591 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31 14592 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1 14593 /* RxDPCPU firmware id. */ 14594 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4 14595 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2 14596 /* enum: Standard RXDP firmware */ 14597 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0 14598 /* enum: Low latency RXDP firmware */ 14599 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1 14600 /* enum: Packed stream RXDP firmware */ 14601 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2 14602 /* enum: Rules engine RXDP firmware */ 14603 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5 14604 /* enum: DPDK RXDP firmware */ 14605 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6 14606 /* enum: BIST RXDP firmware */ 14607 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a 14608 /* enum: RXDP Test firmware image 1 */ 14609 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 14610 /* enum: RXDP Test firmware image 2 */ 14611 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 14612 /* enum: RXDP Test firmware image 3 */ 14613 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 14614 /* enum: RXDP Test firmware image 4 */ 14615 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 14616 /* enum: RXDP Test firmware image 5 */ 14617 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105 14618 /* enum: RXDP Test firmware image 6 */ 14619 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 14620 /* enum: RXDP Test firmware image 7 */ 14621 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 14622 /* enum: RXDP Test firmware image 8 */ 14623 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 14624 /* enum: RXDP Test firmware image 9 */ 14625 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 14626 /* enum: RXDP Test firmware image 10 */ 14627 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c 14628 /* TxDPCPU firmware id. */ 14629 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6 14630 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2 14631 /* enum: Standard TXDP firmware */ 14632 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0 14633 /* enum: Low latency TXDP firmware */ 14634 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1 14635 /* enum: High packet rate TXDP firmware */ 14636 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3 14637 /* enum: Rules engine TXDP firmware */ 14638 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5 14639 /* enum: DPDK TXDP firmware */ 14640 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6 14641 /* enum: BIST TXDP firmware */ 14642 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d 14643 /* enum: TXDP Test firmware image 1 */ 14644 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 14645 /* enum: TXDP Test firmware image 2 */ 14646 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 14647 /* enum: TXDP CSR bus test firmware */ 14648 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103 14649 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8 14650 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2 14651 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8 14652 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0 14653 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12 14654 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8 14655 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12 14656 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 14657 /* enum: reserved value - do not use (may indicate alternative interpretation 14658 * of REV field in future) 14659 */ 14660 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0 14661 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 14662 * development only) 14663 */ 14664 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 14665 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 14666 */ 14667 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 14668 /* enum: RX PD firmware with approximately Siena-compatible behaviour 14669 * (Huntington development only) 14670 */ 14671 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 14672 /* enum: Full featured RX PD production firmware */ 14673 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 14674 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 14675 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3 14676 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 14677 * (Huntington development only) 14678 */ 14679 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 14680 /* enum: Low latency RX PD production firmware */ 14681 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 14682 /* enum: Packed stream RX PD production firmware */ 14683 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 14684 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 14685 * tests (Medford development only) 14686 */ 14687 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 14688 /* enum: Rules engine RX PD production firmware */ 14689 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 14690 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 14691 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9 14692 /* enum: DPDK RX PD production firmware */ 14693 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa 14694 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 14695 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 14696 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 14697 * encapsulations (Medford development only) 14698 */ 14699 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 14700 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10 14701 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2 14702 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10 14703 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0 14704 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12 14705 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10 14706 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12 14707 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 14708 /* enum: reserved value - do not use (may indicate alternative interpretation 14709 * of REV field in future) 14710 */ 14711 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0 14712 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 14713 * development only) 14714 */ 14715 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 14716 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 14717 */ 14718 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 14719 /* enum: TX PD firmware with approximately Siena-compatible behaviour 14720 * (Huntington development only) 14721 */ 14722 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 14723 /* enum: Full featured TX PD production firmware */ 14724 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 14725 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 14726 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3 14727 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 14728 * (Huntington development only) 14729 */ 14730 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 14731 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 14732 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 14733 * tests (Medford development only) 14734 */ 14735 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 14736 /* enum: Rules engine TX PD production firmware */ 14737 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 14738 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 14739 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9 14740 /* enum: DPDK TX PD production firmware */ 14741 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa 14742 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 14743 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 14744 /* Hardware capabilities of NIC */ 14745 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12 14746 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4 14747 /* Licensed capabilities */ 14748 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16 14749 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4 14750 /* Second word of flags. Not present on older firmware (check the length). */ 14751 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20 14752 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4 14753 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20 14754 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0 14755 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1 14756 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20 14757 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1 14758 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1 14759 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20 14760 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2 14761 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1 14762 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20 14763 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3 14764 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1 14765 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20 14766 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4 14767 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1 14768 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20 14769 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5 14770 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 14771 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 14772 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 14773 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 14774 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 14775 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 14776 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 14777 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20 14778 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7 14779 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1 14780 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20 14781 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8 14782 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 14783 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20 14784 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9 14785 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1 14786 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20 14787 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10 14788 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1 14789 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20 14790 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11 14791 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1 14792 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 14793 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 14794 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 14795 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20 14796 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13 14797 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1 14798 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20 14799 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14 14800 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1 14801 #define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20 14802 #define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15 14803 #define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1 14804 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20 14805 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16 14806 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1 14807 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20 14808 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17 14809 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1 14810 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 14811 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 14812 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 14813 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20 14814 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19 14815 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1 14816 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20 14817 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20 14818 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1 14819 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 14820 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 14821 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 14822 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 14823 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 14824 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 14825 #define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20 14826 #define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22 14827 #define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1 14828 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 14829 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 14830 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 14831 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20 14832 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24 14833 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1 14834 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20 14835 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25 14836 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1 14837 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 14838 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 14839 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 14840 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 14841 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 14842 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 14843 #define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20 14844 #define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28 14845 #define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1 14846 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20 14847 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29 14848 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1 14849 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20 14850 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30 14851 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1 14852 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 14853 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 14854 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 14855 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 14856 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 14857 */ 14858 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 14859 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 14860 /* One byte per PF containing the number of the external port assigned to this 14861 * PF, indexed by PF number. Special values indicate that a PF is either not 14862 * present or not assigned. 14863 */ 14864 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 14865 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 14866 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 14867 /* enum: The caller is not permitted to access information on this PF. */ 14868 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff 14869 /* enum: PF does not exist. */ 14870 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe 14871 /* enum: PF does exist but is not assigned to any external port. */ 14872 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd 14873 /* enum: This value indicates that PF is assigned, but it cannot be expressed 14874 * in this field. It is intended for a possible future situation where a more 14875 * complex scheme of PFs to ports mapping is being used. The future driver 14876 * should look for a new field supporting the new scheme. The current/old 14877 * driver should treat this value as PF_NOT_ASSIGNED. 14878 */ 14879 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 14880 /* One byte per PF containing the number of its VFs, indexed by PF number. A 14881 * special value indicates that a PF is not present. 14882 */ 14883 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42 14884 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1 14885 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16 14886 /* enum: The caller is not permitted to access information on this PF. */ 14887 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */ 14888 /* enum: PF does not exist. */ 14889 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */ 14890 /* Number of VIs available for each external port */ 14891 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58 14892 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2 14893 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4 14894 /* Size of RX descriptor cache expressed as binary logarithm The actual size 14895 * equals (2 ^ RX_DESC_CACHE_SIZE) 14896 */ 14897 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66 14898 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1 14899 /* Size of TX descriptor cache expressed as binary logarithm The actual size 14900 * equals (2 ^ TX_DESC_CACHE_SIZE) 14901 */ 14902 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67 14903 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1 14904 /* Total number of available PIO buffers */ 14905 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68 14906 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2 14907 /* Size of a single PIO buffer */ 14908 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70 14909 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2 14910 /* On chips later than Medford the amount of address space assigned to each VI 14911 * is configurable. This is a global setting that the driver must query to 14912 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 14913 * with 8k VI windows. 14914 */ 14915 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72 14916 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1 14917 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 14918 * CTPIO is not mapped. 14919 */ 14920 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0 14921 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 14922 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1 14923 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 14924 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2 14925 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 14926 * (SF-115995-SW) in the present configuration of firmware and port mode. 14927 */ 14928 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 14929 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 14930 /* Number of buffers per adapter that can be used for VFIFO Stuffing 14931 * (SF-115995-SW) in the present configuration of firmware and port mode. 14932 */ 14933 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 14934 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 14935 /* Entry count in the MAC stats array, including the final GENERATION_END 14936 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 14937 * hold at least this many 64-bit stats values, if they wish to receive all 14938 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 14939 * stats array returned will be truncated. 14940 */ 14941 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76 14942 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2 14943 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 14944 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 14945 */ 14946 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80 14947 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4 14948 /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 14949 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 14950 * they create an RX queue. Due to hardware limitations, only a small number of 14951 * different buffer sizes may be available concurrently. Nonzero entries in 14952 * this array are the sizes of buffers which the system guarantees will be 14953 * available for use. If the list is empty, there are no limitations on 14954 * concurrent buffer sizes. 14955 */ 14956 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 14957 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 14958 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 14959 /* Third word of flags. Not present on older firmware (check the length). */ 14960 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148 14961 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4 14962 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148 14963 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0 14964 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1 14965 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148 14966 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1 14967 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1 14968 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148 14969 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2 14970 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1 14971 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148 14972 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3 14973 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1 14974 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148 14975 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4 14976 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1 14977 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148 14978 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5 14979 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1 14980 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148 14981 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6 14982 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1 14983 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148 14984 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7 14985 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1 14986 /* These bits are reserved for communicating test-specific capabilities to 14987 * host-side test software. All production drivers should treat this field as 14988 * opaque. 14989 */ 14990 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152 14991 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8 14992 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152 14993 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156 14994 14995 /* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */ 14996 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184 14997 /* First word of flags. */ 14998 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0 14999 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4 15000 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0 15001 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3 15002 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1 15003 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0 15004 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4 15005 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1 15006 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0 15007 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5 15008 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1 15009 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0 15010 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 15011 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 15012 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0 15013 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7 15014 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 15015 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0 15016 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8 15017 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 15018 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0 15019 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9 15020 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1 15021 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0 15022 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 15023 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 15024 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0 15025 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 15026 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 15027 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0 15028 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 15029 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 15030 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0 15031 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13 15032 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 15033 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0 15034 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14 15035 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1 15036 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0 15037 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 15038 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 15039 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0 15040 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16 15041 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1 15042 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0 15043 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17 15044 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1 15045 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0 15046 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18 15047 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1 15048 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0 15049 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19 15050 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1 15051 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0 15052 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20 15053 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1 15054 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0 15055 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21 15056 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1 15057 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0 15058 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22 15059 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1 15060 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0 15061 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23 15062 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1 15063 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0 15064 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24 15065 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1 15066 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0 15067 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25 15068 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1 15069 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0 15070 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26 15071 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1 15072 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0 15073 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27 15074 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 15075 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0 15076 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28 15077 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1 15078 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0 15079 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 15080 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 15081 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0 15082 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30 15083 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1 15084 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0 15085 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31 15086 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1 15087 /* RxDPCPU firmware id. */ 15088 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4 15089 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2 15090 /* enum: Standard RXDP firmware */ 15091 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0 15092 /* enum: Low latency RXDP firmware */ 15093 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1 15094 /* enum: Packed stream RXDP firmware */ 15095 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2 15096 /* enum: Rules engine RXDP firmware */ 15097 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5 15098 /* enum: DPDK RXDP firmware */ 15099 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6 15100 /* enum: BIST RXDP firmware */ 15101 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a 15102 /* enum: RXDP Test firmware image 1 */ 15103 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 15104 /* enum: RXDP Test firmware image 2 */ 15105 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 15106 /* enum: RXDP Test firmware image 3 */ 15107 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 15108 /* enum: RXDP Test firmware image 4 */ 15109 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 15110 /* enum: RXDP Test firmware image 5 */ 15111 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105 15112 /* enum: RXDP Test firmware image 6 */ 15113 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 15114 /* enum: RXDP Test firmware image 7 */ 15115 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 15116 /* enum: RXDP Test firmware image 8 */ 15117 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 15118 /* enum: RXDP Test firmware image 9 */ 15119 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 15120 /* enum: RXDP Test firmware image 10 */ 15121 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c 15122 /* TxDPCPU firmware id. */ 15123 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6 15124 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2 15125 /* enum: Standard TXDP firmware */ 15126 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0 15127 /* enum: Low latency TXDP firmware */ 15128 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1 15129 /* enum: High packet rate TXDP firmware */ 15130 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3 15131 /* enum: Rules engine TXDP firmware */ 15132 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5 15133 /* enum: DPDK TXDP firmware */ 15134 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6 15135 /* enum: BIST TXDP firmware */ 15136 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d 15137 /* enum: TXDP Test firmware image 1 */ 15138 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 15139 /* enum: TXDP Test firmware image 2 */ 15140 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 15141 /* enum: TXDP CSR bus test firmware */ 15142 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103 15143 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8 15144 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2 15145 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8 15146 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0 15147 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12 15148 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8 15149 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12 15150 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 15151 /* enum: reserved value - do not use (may indicate alternative interpretation 15152 * of REV field in future) 15153 */ 15154 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0 15155 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 15156 * development only) 15157 */ 15158 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 15159 /* enum: RX PD firmware for telemetry prototyping (Medford2 development only) 15160 */ 15161 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 15162 /* enum: RX PD firmware with approximately Siena-compatible behaviour 15163 * (Huntington development only) 15164 */ 15165 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 15166 /* enum: Full featured RX PD production firmware */ 15167 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 15168 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 15169 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3 15170 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 15171 * (Huntington development only) 15172 */ 15173 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 15174 /* enum: Low latency RX PD production firmware */ 15175 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 15176 /* enum: Packed stream RX PD production firmware */ 15177 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 15178 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 15179 * tests (Medford development only) 15180 */ 15181 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 15182 /* enum: Rules engine RX PD production firmware */ 15183 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 15184 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 15185 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9 15186 /* enum: DPDK RX PD production firmware */ 15187 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa 15188 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 15189 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 15190 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 15191 * encapsulations (Medford development only) 15192 */ 15193 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 15194 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10 15195 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2 15196 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10 15197 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0 15198 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12 15199 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10 15200 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12 15201 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 15202 /* enum: reserved value - do not use (may indicate alternative interpretation 15203 * of REV field in future) 15204 */ 15205 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0 15206 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 15207 * development only) 15208 */ 15209 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 15210 /* enum: TX PD firmware for telemetry prototyping (Medford2 development only) 15211 */ 15212 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1 15213 /* enum: TX PD firmware with approximately Siena-compatible behaviour 15214 * (Huntington development only) 15215 */ 15216 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 15217 /* enum: Full featured TX PD production firmware */ 15218 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 15219 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 15220 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3 15221 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 15222 * (Huntington development only) 15223 */ 15224 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 15225 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 15226 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 15227 * tests (Medford development only) 15228 */ 15229 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 15230 /* enum: Rules engine TX PD production firmware */ 15231 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 15232 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 15233 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9 15234 /* enum: DPDK TX PD production firmware */ 15235 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa 15236 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 15237 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 15238 /* Hardware capabilities of NIC */ 15239 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12 15240 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4 15241 /* Licensed capabilities */ 15242 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16 15243 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4 15244 /* Second word of flags. Not present on older firmware (check the length). */ 15245 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20 15246 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4 15247 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20 15248 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0 15249 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1 15250 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20 15251 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1 15252 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1 15253 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20 15254 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2 15255 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1 15256 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20 15257 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3 15258 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1 15259 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20 15260 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4 15261 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1 15262 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20 15263 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5 15264 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 15265 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20 15266 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 15267 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 15268 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20 15269 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7 15270 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1 15271 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20 15272 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7 15273 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1 15274 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20 15275 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8 15276 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 15277 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20 15278 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9 15279 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1 15280 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20 15281 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10 15282 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1 15283 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20 15284 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11 15285 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1 15286 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20 15287 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 15288 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 15289 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20 15290 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13 15291 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1 15292 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20 15293 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14 15294 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1 15295 #define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20 15296 #define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15 15297 #define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1 15298 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20 15299 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16 15300 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1 15301 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20 15302 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17 15303 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1 15304 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20 15305 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 15306 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 15307 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20 15308 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19 15309 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1 15310 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20 15311 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20 15312 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1 15313 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20 15314 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 15315 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 15316 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20 15317 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 15318 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 15319 #define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20 15320 #define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22 15321 #define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1 15322 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20 15323 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 15324 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 15325 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20 15326 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24 15327 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1 15328 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20 15329 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25 15330 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1 15331 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20 15332 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26 15333 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1 15334 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20 15335 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27 15336 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1 15337 #define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20 15338 #define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28 15339 #define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1 15340 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20 15341 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29 15342 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1 15343 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20 15344 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30 15345 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1 15346 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20 15347 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31 15348 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1 15349 /* Number of FATSOv2 contexts per datapath supported by this NIC (when 15350 * TX_TSO_V2 == 1). Not present on older firmware (check the length). 15351 */ 15352 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 15353 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 15354 /* One byte per PF containing the number of the external port assigned to this 15355 * PF, indexed by PF number. Special values indicate that a PF is either not 15356 * present or not assigned. 15357 */ 15358 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 15359 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 15360 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 15361 /* enum: The caller is not permitted to access information on this PF. */ 15362 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff 15363 /* enum: PF does not exist. */ 15364 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe 15365 /* enum: PF does exist but is not assigned to any external port. */ 15366 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd 15367 /* enum: This value indicates that PF is assigned, but it cannot be expressed 15368 * in this field. It is intended for a possible future situation where a more 15369 * complex scheme of PFs to ports mapping is being used. The future driver 15370 * should look for a new field supporting the new scheme. The current/old 15371 * driver should treat this value as PF_NOT_ASSIGNED. 15372 */ 15373 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 15374 /* One byte per PF containing the number of its VFs, indexed by PF number. A 15375 * special value indicates that a PF is not present. 15376 */ 15377 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42 15378 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1 15379 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16 15380 /* enum: The caller is not permitted to access information on this PF. */ 15381 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */ 15382 /* enum: PF does not exist. */ 15383 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */ 15384 /* Number of VIs available for each external port */ 15385 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58 15386 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2 15387 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4 15388 /* Size of RX descriptor cache expressed as binary logarithm The actual size 15389 * equals (2 ^ RX_DESC_CACHE_SIZE) 15390 */ 15391 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66 15392 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1 15393 /* Size of TX descriptor cache expressed as binary logarithm The actual size 15394 * equals (2 ^ TX_DESC_CACHE_SIZE) 15395 */ 15396 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67 15397 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1 15398 /* Total number of available PIO buffers */ 15399 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68 15400 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2 15401 /* Size of a single PIO buffer */ 15402 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70 15403 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2 15404 /* On chips later than Medford the amount of address space assigned to each VI 15405 * is configurable. This is a global setting that the driver must query to 15406 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 15407 * with 8k VI windows. 15408 */ 15409 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72 15410 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1 15411 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 15412 * CTPIO is not mapped. 15413 */ 15414 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0 15415 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 15416 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1 15417 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 15418 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2 15419 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 15420 * (SF-115995-SW) in the present configuration of firmware and port mode. 15421 */ 15422 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 15423 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 15424 /* Number of buffers per adapter that can be used for VFIFO Stuffing 15425 * (SF-115995-SW) in the present configuration of firmware and port mode. 15426 */ 15427 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 15428 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 15429 /* Entry count in the MAC stats array, including the final GENERATION_END 15430 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 15431 * hold at least this many 64-bit stats values, if they wish to receive all 15432 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 15433 * stats array returned will be truncated. 15434 */ 15435 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76 15436 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2 15437 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 15438 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 15439 */ 15440 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80 15441 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4 15442 /* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in 15443 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when 15444 * they create an RX queue. Due to hardware limitations, only a small number of 15445 * different buffer sizes may be available concurrently. Nonzero entries in 15446 * this array are the sizes of buffers which the system guarantees will be 15447 * available for use. If the list is empty, there are no limitations on 15448 * concurrent buffer sizes. 15449 */ 15450 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84 15451 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4 15452 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16 15453 /* Third word of flags. Not present on older firmware (check the length). */ 15454 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148 15455 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4 15456 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148 15457 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0 15458 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1 15459 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148 15460 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1 15461 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1 15462 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148 15463 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2 15464 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1 15465 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148 15466 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3 15467 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1 15468 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148 15469 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4 15470 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1 15471 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148 15472 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5 15473 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1 15474 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148 15475 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6 15476 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1 15477 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148 15478 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7 15479 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1 15480 /* These bits are reserved for communicating test-specific capabilities to 15481 * host-side test software. All production drivers should treat this field as 15482 * opaque. 15483 */ 15484 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152 15485 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8 15486 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152 15487 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156 15488 /* The minimum size (in table entries) of indirection table to be allocated 15489 * from the pool for an RSS context. Note that the table size used must be a 15490 * power of 2. 15491 */ 15492 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160 15493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4 15494 /* The maximum size (in table entries) of indirection table to be allocated 15495 * from the pool for an RSS context. Note that the table size used must be a 15496 * power of 2. 15497 */ 15498 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164 15499 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4 15500 /* The maximum number of queues that can be used by an RSS context in exclusive 15501 * mode. In exclusive mode the context has a configurable indirection table and 15502 * a configurable RSS key. 15503 */ 15504 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168 15505 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4 15506 /* The maximum number of queues that can be used by an RSS context in even- 15507 * spreading mode. In even-spreading mode the context has no indirection table 15508 * but it does have a configurable RSS key. 15509 */ 15510 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172 15511 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4 15512 /* The total number of RSS contexts supported. Note that the number of 15513 * available contexts using indirection tables is also limited by the 15514 * availability of indirection table space allocated from a common pool. 15515 */ 15516 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176 15517 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4 15518 /* The total amount of indirection table space that can be shared between RSS 15519 * contexts. 15520 */ 15521 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180 15522 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4 15523 15524 15525 /***********************************/ 15526 /* MC_CMD_V2_EXTN 15527 * Encapsulation for a v2 extended command 15528 */ 15529 #define MC_CMD_V2_EXTN 0x7f 15530 15531 /* MC_CMD_V2_EXTN_IN msgrequest */ 15532 #define MC_CMD_V2_EXTN_IN_LEN 4 15533 /* the extended command number */ 15534 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 15535 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 15536 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 15537 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 15538 /* the actual length of the encapsulated command (which is not in the v1 15539 * header) 15540 */ 15541 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 15542 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 15543 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 15544 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2 15545 /* Type of command/response */ 15546 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28 15547 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4 15548 /* enum: MCDI command directed to or response originating from the MC. */ 15549 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0 15550 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type 15551 * are not defined. 15552 */ 15553 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 15554 15555 15556 /***********************************/ 15557 /* MC_CMD_TCM_BUCKET_ALLOC 15558 * Allocate a pacer bucket (for qau rp or a snapper test) 15559 */ 15560 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 15561 #undef MC_CMD_0xb2_PRIVILEGE_CTG 15562 15563 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15564 15565 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 15566 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 15567 15568 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 15569 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 15570 /* the bucket id */ 15571 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 15572 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 15573 15574 15575 /***********************************/ 15576 /* MC_CMD_TCM_BUCKET_FREE 15577 * Free a pacer bucket 15578 */ 15579 #define MC_CMD_TCM_BUCKET_FREE 0xb3 15580 #undef MC_CMD_0xb3_PRIVILEGE_CTG 15581 15582 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15583 15584 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 15585 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 15586 /* the bucket id */ 15587 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 15588 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 15589 15590 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 15591 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 15592 15593 15594 /***********************************/ 15595 /* MC_CMD_TCM_BUCKET_INIT 15596 * Initialise pacer bucket with a given rate 15597 */ 15598 #define MC_CMD_TCM_BUCKET_INIT 0xb4 15599 #undef MC_CMD_0xb4_PRIVILEGE_CTG 15600 15601 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15602 15603 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 15604 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 15605 /* the bucket id */ 15606 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 15607 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 15608 /* the rate in mbps */ 15609 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 15610 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 15611 15612 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 15613 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 15614 /* the bucket id */ 15615 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 15616 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 15617 /* the rate in mbps */ 15618 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 15619 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 15620 /* the desired maximum fill level */ 15621 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 15622 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 15623 15624 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 15625 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 15626 15627 15628 /***********************************/ 15629 /* MC_CMD_TCM_TXQ_INIT 15630 * Initialise txq in pacer with given options or set options 15631 */ 15632 #define MC_CMD_TCM_TXQ_INIT 0xb5 15633 #undef MC_CMD_0xb5_PRIVILEGE_CTG 15634 15635 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15636 15637 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 15638 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 15639 /* the txq id */ 15640 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 15641 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 15642 /* the static priority associated with the txq */ 15643 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 15644 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 15645 /* bitmask of the priority queues this txq is inserted into when inserted. */ 15646 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 15647 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 15648 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 8 15649 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 15650 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 15651 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 8 15652 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 15653 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 15654 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 8 15655 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 15656 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 15657 /* the reaction point (RP) bucket */ 15658 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 15659 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 15660 /* an already reserved bucket (typically set to bucket associated with outer 15661 * vswitch) 15662 */ 15663 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 15664 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 15665 /* an already reserved bucket (typically set to bucket associated with inner 15666 * vswitch) 15667 */ 15668 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 15669 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 15670 /* the min bucket (typically for ETS/minimum bandwidth) */ 15671 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 15672 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 15673 15674 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 15675 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 15676 /* the txq id */ 15677 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 15678 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 15679 /* the static priority associated with the txq */ 15680 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 15681 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 15682 /* bitmask of the priority queues this txq is inserted into when inserted. */ 15683 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 15684 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 15685 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 8 15686 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 15687 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 15688 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 8 15689 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 15690 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 15691 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 8 15692 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 15693 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 15694 /* the reaction point (RP) bucket */ 15695 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 15696 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 15697 /* an already reserved bucket (typically set to bucket associated with outer 15698 * vswitch) 15699 */ 15700 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 15701 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 15702 /* an already reserved bucket (typically set to bucket associated with inner 15703 * vswitch) 15704 */ 15705 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 15706 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 15707 /* the min bucket (typically for ETS/minimum bandwidth) */ 15708 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 15709 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 15710 /* the static priority associated with the txq */ 15711 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 15712 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 15713 15714 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 15715 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 15716 15717 15718 /***********************************/ 15719 /* MC_CMD_LINK_PIOBUF 15720 * Link a push I/O buffer to a TxQ 15721 */ 15722 #define MC_CMD_LINK_PIOBUF 0x92 15723 #undef MC_CMD_0x92_PRIVILEGE_CTG 15724 15725 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 15726 15727 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 15728 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 15729 /* Handle for allocated push I/O buffer. */ 15730 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 15731 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 15732 /* Function Local Instance (VI) number. */ 15733 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 15734 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 15735 15736 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 15737 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 15738 15739 15740 /***********************************/ 15741 /* MC_CMD_UNLINK_PIOBUF 15742 * Unlink a push I/O buffer from a TxQ 15743 */ 15744 #define MC_CMD_UNLINK_PIOBUF 0x93 15745 #undef MC_CMD_0x93_PRIVILEGE_CTG 15746 15747 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 15748 15749 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 15750 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 15751 /* Function Local Instance (VI) number. */ 15752 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 15753 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 15754 15755 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 15756 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 15757 15758 15759 /***********************************/ 15760 /* MC_CMD_VSWITCH_ALLOC 15761 * allocate and initialise a v-switch. 15762 */ 15763 #define MC_CMD_VSWITCH_ALLOC 0x94 15764 #undef MC_CMD_0x94_PRIVILEGE_CTG 15765 15766 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15767 15768 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 15769 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 15770 /* The port to connect to the v-switch's upstream port. */ 15771 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 15772 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 15773 /* The type of v-switch to create. */ 15774 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 15775 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4 15776 /* enum: VLAN */ 15777 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 15778 /* enum: VEB */ 15779 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 15780 /* enum: VEPA (obsolete) */ 15781 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 15782 /* enum: MUX */ 15783 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 15784 /* enum: Snapper specific; semantics TBD */ 15785 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 15786 /* Flags controlling v-port creation */ 15787 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 15788 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4 15789 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8 15790 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 15791 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 15792 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 15793 * this must be one or greated, and the attached v-ports must have exactly this 15794 * number of tags. For other v-switch types, this must be zero of greater, and 15795 * is an upper limit on the number of VLAN tags for attached v-ports. An error 15796 * will be returned if existing configuration means we can't support attached 15797 * v-ports with this number of tags. 15798 */ 15799 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 15800 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 15801 15802 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 15803 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 15804 15805 15806 /***********************************/ 15807 /* MC_CMD_VSWITCH_FREE 15808 * de-allocate a v-switch. 15809 */ 15810 #define MC_CMD_VSWITCH_FREE 0x95 15811 #undef MC_CMD_0x95_PRIVILEGE_CTG 15812 15813 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15814 15815 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 15816 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 15817 /* The port to which the v-switch is connected. */ 15818 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 15819 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4 15820 15821 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 15822 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 15823 15824 15825 /***********************************/ 15826 /* MC_CMD_VSWITCH_QUERY 15827 * read some config of v-switch. For now this command is an empty placeholder. 15828 * It may be used to check if a v-switch is connected to a given EVB port (if 15829 * not, then the command returns ENOENT). 15830 */ 15831 #define MC_CMD_VSWITCH_QUERY 0x63 15832 #undef MC_CMD_0x63_PRIVILEGE_CTG 15833 15834 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15835 15836 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 15837 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 15838 /* The port to which the v-switch is connected. */ 15839 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 15840 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 15841 15842 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 15843 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 15844 15845 15846 /***********************************/ 15847 /* MC_CMD_VPORT_ALLOC 15848 * allocate a v-port. 15849 */ 15850 #define MC_CMD_VPORT_ALLOC 0x96 15851 #undef MC_CMD_0x96_PRIVILEGE_CTG 15852 15853 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15854 15855 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 15856 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 15857 /* The port to which the v-switch is connected. */ 15858 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 15859 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 15860 /* The type of the new v-port. */ 15861 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 15862 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4 15863 /* enum: VLAN (obsolete) */ 15864 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 15865 /* enum: VEB (obsolete) */ 15866 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 15867 /* enum: VEPA (obsolete) */ 15868 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 15869 /* enum: A normal v-port receives packets which match a specified MAC and/or 15870 * VLAN. 15871 */ 15872 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 15873 /* enum: An expansion v-port packets traffic which don't match any other 15874 * v-port. 15875 */ 15876 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 15877 /* enum: An test v-port receives packets which match any filters installed by 15878 * its downstream components. 15879 */ 15880 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 15881 /* Flags controlling v-port creation */ 15882 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 15883 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4 15884 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8 15885 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 15886 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 15887 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8 15888 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 15889 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 15890 /* The number of VLAN tags to insert/remove. An error will be returned if 15891 * incompatible with the number of VLAN tags specified for the upstream 15892 * v-switch. 15893 */ 15894 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 15895 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 15896 /* The actual VLAN tags to insert/remove */ 15897 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 15898 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4 15899 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16 15900 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 15901 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 15902 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16 15903 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 15904 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 15905 15906 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 15907 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 15908 /* The handle of the new v-port */ 15909 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 15910 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 15911 15912 15913 /***********************************/ 15914 /* MC_CMD_VPORT_FREE 15915 * de-allocate a v-port. 15916 */ 15917 #define MC_CMD_VPORT_FREE 0x97 15918 #undef MC_CMD_0x97_PRIVILEGE_CTG 15919 15920 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15921 15922 /* MC_CMD_VPORT_FREE_IN msgrequest */ 15923 #define MC_CMD_VPORT_FREE_IN_LEN 4 15924 /* The handle of the v-port */ 15925 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 15926 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4 15927 15928 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 15929 #define MC_CMD_VPORT_FREE_OUT_LEN 0 15930 15931 15932 /***********************************/ 15933 /* MC_CMD_VADAPTOR_ALLOC 15934 * allocate a v-adaptor. 15935 */ 15936 #define MC_CMD_VADAPTOR_ALLOC 0x98 15937 #undef MC_CMD_0x98_PRIVILEGE_CTG 15938 15939 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15940 15941 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 15942 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 15943 /* The port to connect to the v-adaptor's port. */ 15944 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 15945 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 15946 /* Flags controlling v-adaptor creation */ 15947 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 15948 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4 15949 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8 15950 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 15951 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 15952 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8 15953 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 15954 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 15955 /* The number of VLAN tags to strip on receive */ 15956 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 15957 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4 15958 /* The number of VLAN tags to transparently insert/remove. */ 15959 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 15960 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 15961 /* The actual VLAN tags to insert/remove */ 15962 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 15963 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4 15964 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20 15965 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 15966 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 15967 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20 15968 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 15969 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 15970 /* The MAC address to assign to this v-adaptor */ 15971 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 15972 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 15973 /* enum: Derive the MAC address from the upstream port */ 15974 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 15975 15976 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 15977 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 15978 15979 15980 /***********************************/ 15981 /* MC_CMD_VADAPTOR_FREE 15982 * de-allocate a v-adaptor. 15983 */ 15984 #define MC_CMD_VADAPTOR_FREE 0x99 15985 #undef MC_CMD_0x99_PRIVILEGE_CTG 15986 15987 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15988 15989 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 15990 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 15991 /* The port to which the v-adaptor is connected. */ 15992 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 15993 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4 15994 15995 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 15996 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 15997 15998 15999 /***********************************/ 16000 /* MC_CMD_VADAPTOR_SET_MAC 16001 * assign a new MAC address to a v-adaptor. 16002 */ 16003 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 16004 #undef MC_CMD_0x5d_PRIVILEGE_CTG 16005 16006 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16007 16008 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 16009 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 16010 /* The port to which the v-adaptor is connected. */ 16011 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 16012 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 16013 /* The new MAC address to assign to this v-adaptor */ 16014 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 16015 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 16016 16017 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 16018 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 16019 16020 16021 /***********************************/ 16022 /* MC_CMD_VADAPTOR_GET_MAC 16023 * read the MAC address assigned to a v-adaptor. 16024 */ 16025 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 16026 #undef MC_CMD_0x5e_PRIVILEGE_CTG 16027 16028 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16029 16030 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 16031 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 16032 /* The port to which the v-adaptor is connected. */ 16033 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 16034 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 16035 16036 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 16037 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 16038 /* The MAC address assigned to this v-adaptor */ 16039 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 16040 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 16041 16042 16043 /***********************************/ 16044 /* MC_CMD_VADAPTOR_QUERY 16045 * read some config of v-adaptor. 16046 */ 16047 #define MC_CMD_VADAPTOR_QUERY 0x61 16048 #undef MC_CMD_0x61_PRIVILEGE_CTG 16049 16050 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16051 16052 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 16053 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 16054 /* The port to which the v-adaptor is connected. */ 16055 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 16056 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 16057 16058 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 16059 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 16060 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 16061 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 16062 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4 16063 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 16064 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 16065 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4 16066 /* The number of VLAN tags that may still be added */ 16067 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 16068 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 16069 16070 16071 /***********************************/ 16072 /* MC_CMD_EVB_PORT_ASSIGN 16073 * assign a port to a PCI function. 16074 */ 16075 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 16076 #undef MC_CMD_0x9a_PRIVILEGE_CTG 16077 16078 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16079 16080 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 16081 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 16082 /* The port to assign. */ 16083 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 16084 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4 16085 /* The target function to modify. */ 16086 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 16087 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4 16088 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4 16089 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 16090 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 16091 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4 16092 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 16093 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 16094 16095 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 16096 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 16097 16098 16099 /***********************************/ 16100 /* MC_CMD_RDWR_A64_REGIONS 16101 * Assign the 64 bit region addresses. 16102 */ 16103 #define MC_CMD_RDWR_A64_REGIONS 0x9b 16104 #undef MC_CMD_0x9b_PRIVILEGE_CTG 16105 16106 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16107 16108 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 16109 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 16110 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 16111 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 16112 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 16113 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 16114 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 16115 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 16116 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 16117 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 16118 /* Write enable bits 0-3, set to write, clear to read. */ 16119 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 16120 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 16121 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 16122 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 16123 16124 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 16125 * regardless of state of write bits in the request. 16126 */ 16127 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 16128 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 16129 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 16130 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 16131 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 16132 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 16133 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 16134 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 16135 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 16136 16137 16138 /***********************************/ 16139 /* MC_CMD_ONLOAD_STACK_ALLOC 16140 * Allocate an Onload stack ID. 16141 */ 16142 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 16143 #undef MC_CMD_0x9c_PRIVILEGE_CTG 16144 16145 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 16146 16147 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 16148 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 16149 /* The handle of the owning upstream port */ 16150 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 16151 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 16152 16153 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 16154 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 16155 /* The handle of the new Onload stack */ 16156 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 16157 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 16158 16159 16160 /***********************************/ 16161 /* MC_CMD_ONLOAD_STACK_FREE 16162 * Free an Onload stack ID. 16163 */ 16164 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 16165 #undef MC_CMD_0x9d_PRIVILEGE_CTG 16166 16167 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 16168 16169 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 16170 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 16171 /* The handle of the Onload stack */ 16172 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 16173 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 16174 16175 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 16176 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 16177 16178 16179 /***********************************/ 16180 /* MC_CMD_RSS_CONTEXT_ALLOC 16181 * Allocate an RSS context. 16182 */ 16183 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 16184 #undef MC_CMD_0x9e_PRIVILEGE_CTG 16185 16186 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16187 16188 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 16189 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 16190 /* The handle of the owning upstream port */ 16191 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 16192 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 16193 /* The type of context to allocate */ 16194 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 16195 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4 16196 /* enum: Allocate a context for exclusive use. The key and indirection table 16197 * must be explicitly configured. 16198 */ 16199 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 16200 /* enum: Allocate a context for shared use; this will spread across a range of 16201 * queues, but the key and indirection table are pre-configured and may not be 16202 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 16203 */ 16204 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 16205 /* enum: Allocate a context to spread evenly across an arbitrary number of 16206 * queues. No indirection table space is allocated for this context. (EF100 and 16207 * later) 16208 */ 16209 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2 16210 /* Number of queues spanned by this context. For exclusive contexts this must 16211 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where 16212 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if 16213 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in 16214 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even- 16215 * spreading contexts this must be in the range 1 to 16216 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note 16217 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still 16218 * be useful as a way of obtaining the Toeplitz hash. 16219 */ 16220 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 16221 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4 16222 16223 /* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */ 16224 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16 16225 /* The handle of the owning upstream port */ 16226 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0 16227 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4 16228 /* The type of context to allocate */ 16229 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4 16230 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4 16231 /* enum: Allocate a context for exclusive use. The key and indirection table 16232 * must be explicitly configured. 16233 */ 16234 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0 16235 /* enum: Allocate a context for shared use; this will spread across a range of 16236 * queues, but the key and indirection table are pre-configured and may not be 16237 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 16238 */ 16239 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1 16240 /* enum: Allocate a context to spread evenly across an arbitrary number of 16241 * queues. No indirection table space is allocated for this context. (EF100 and 16242 * later) 16243 */ 16244 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2 16245 /* Number of queues spanned by this context. For exclusive contexts this must 16246 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where 16247 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if 16248 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in 16249 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even- 16250 * spreading contexts this must be in the range 1 to 16251 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note 16252 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still 16253 * be useful as a way of obtaining the Toeplitz hash. 16254 */ 16255 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8 16256 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4 16257 /* Size of indirection table to be allocated to this context from the pool. 16258 * Must be a power of 2. The minimum and maximum table size can be queried 16259 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in 16260 * the common pool to allocate the requested table size, due to allocating 16261 * table space to other RSS contexts, then the command will fail with 16262 * MC_CMD_ERR_ENOSPC. 16263 */ 16264 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12 16265 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4 16266 16267 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 16268 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 16269 /* The handle of the new RSS context. This should be considered opaque to the 16270 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 16271 * handle. 16272 */ 16273 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 16274 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4 16275 /* enum: guaranteed invalid RSS context handle value */ 16276 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 16277 16278 16279 /***********************************/ 16280 /* MC_CMD_RSS_CONTEXT_FREE 16281 * Free an RSS context. 16282 */ 16283 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 16284 #undef MC_CMD_0x9f_PRIVILEGE_CTG 16285 16286 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16287 16288 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 16289 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 16290 /* The handle of the RSS context */ 16291 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 16292 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4 16293 16294 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 16295 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 16296 16297 16298 /***********************************/ 16299 /* MC_CMD_RSS_CONTEXT_SET_KEY 16300 * Set the Toeplitz hash key for an RSS context. 16301 */ 16302 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 16303 #undef MC_CMD_0xa0_PRIVILEGE_CTG 16304 16305 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16306 16307 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 16308 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 16309 /* The handle of the RSS context */ 16310 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 16311 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4 16312 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 16313 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 16314 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 16315 16316 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 16317 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 16318 16319 16320 /***********************************/ 16321 /* MC_CMD_RSS_CONTEXT_GET_KEY 16322 * Get the Toeplitz hash key for an RSS context. 16323 */ 16324 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 16325 #undef MC_CMD_0xa1_PRIVILEGE_CTG 16326 16327 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16328 16329 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 16330 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 16331 /* The handle of the RSS context */ 16332 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 16333 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4 16334 16335 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 16336 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 16337 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 16338 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 16339 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 16340 16341 16342 /***********************************/ 16343 /* MC_CMD_RSS_CONTEXT_SET_TABLE 16344 * Set the indirection table for an RSS context. This command should only be 16345 * used with indirection tables containing 128 entries, which is the default 16346 * when the RSS context is allocated without specifying a table size. 16347 */ 16348 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 16349 #undef MC_CMD_0xa2_PRIVILEGE_CTG 16350 16351 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16352 16353 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 16354 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 16355 /* The handle of the RSS context */ 16356 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 16357 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 16358 /* The 128-byte indirection table (1 byte per entry) */ 16359 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 16360 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 16361 16362 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 16363 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 16364 16365 16366 /***********************************/ 16367 /* MC_CMD_RSS_CONTEXT_GET_TABLE 16368 * Get the indirection table for an RSS context. This command should only be 16369 * used with indirection tables containing 128 entries, which is the default 16370 * when the RSS context is allocated without specifying a table size. 16371 */ 16372 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 16373 #undef MC_CMD_0xa3_PRIVILEGE_CTG 16374 16375 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16376 16377 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 16378 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 16379 /* The handle of the RSS context */ 16380 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 16381 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 16382 16383 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 16384 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 16385 /* The 128-byte indirection table (1 byte per entry) */ 16386 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 16387 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 16388 16389 16390 /***********************************/ 16391 /* MC_CMD_RSS_CONTEXT_WRITE_TABLE 16392 * Write a portion of a selectable-size indirection table for an RSS context. 16393 * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the 16394 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES. 16395 */ 16396 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e 16397 #undef MC_CMD_0x13e_PRIVILEGE_CTG 16398 16399 #define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16400 16401 /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */ 16402 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8 16403 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252 16404 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020 16405 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num)) 16406 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4) 16407 /* The handle of the RSS context */ 16408 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0 16409 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4 16410 /* An array of index-value pairs to be written to the table. Structure is 16411 * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY. 16412 */ 16413 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4 16414 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4 16415 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1 16416 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62 16417 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254 16418 16419 /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */ 16420 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0 16421 16422 /* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */ 16423 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4 16424 /* The index of the table entry to be written. */ 16425 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0 16426 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2 16427 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0 16428 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16 16429 /* The value to write into the table entry. */ 16430 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2 16431 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2 16432 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16 16433 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16 16434 16435 16436 /***********************************/ 16437 /* MC_CMD_RSS_CONTEXT_READ_TABLE 16438 * Read a portion of a selectable-size indirection table for an RSS context. 16439 * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the 16440 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES. 16441 */ 16442 #define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f 16443 #undef MC_CMD_0x13f_PRIVILEGE_CTG 16444 16445 #define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16446 16447 /* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */ 16448 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6 16449 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252 16450 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020 16451 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num)) 16452 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2) 16453 /* The handle of the RSS context */ 16454 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0 16455 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4 16456 /* An array containing the indices of the entries to be read. */ 16457 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4 16458 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2 16459 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1 16460 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124 16461 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508 16462 16463 /* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */ 16464 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2 16465 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252 16466 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020 16467 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num)) 16468 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2) 16469 /* A buffer containing the requested entries read from the table. */ 16470 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0 16471 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2 16472 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1 16473 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126 16474 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510 16475 16476 16477 /***********************************/ 16478 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 16479 * Set various control flags for an RSS context. 16480 */ 16481 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 16482 #undef MC_CMD_0xe1_PRIVILEGE_CTG 16483 16484 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16485 16486 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 16487 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 16488 /* The handle of the RSS context */ 16489 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 16490 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 16491 /* Hash control flags. The _EN bits are always supported, but new modes are 16492 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 16493 * in this case, the MODE fields may be set to non-zero values, and will take 16494 * effect regardless of the settings of the _EN flags. See the RSS_MODE 16495 * structure for the meaning of the mode bits. Drivers must check the 16496 * capability before trying to set any _MODE fields, as older firmware will 16497 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 16498 * the case where all the _MODE flags are zero, the _EN flags take effect, 16499 * providing backward compatibility for existing drivers. (Setting all _MODE 16500 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 16501 * particular packet type.) 16502 */ 16503 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 16504 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4 16505 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4 16506 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 16507 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 16508 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4 16509 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 16510 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 16511 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4 16512 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 16513 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 16514 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4 16515 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 16516 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 16517 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4 16518 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 16519 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 16520 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4 16521 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 16522 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 16523 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4 16524 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 16525 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 16526 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4 16527 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 16528 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 16529 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4 16530 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 16531 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 16532 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4 16533 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 16534 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 16535 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4 16536 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 16537 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 16538 16539 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 16540 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 16541 16542 16543 /***********************************/ 16544 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 16545 * Get various control flags for an RSS context. 16546 */ 16547 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 16548 #undef MC_CMD_0xe2_PRIVILEGE_CTG 16549 16550 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16551 16552 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 16553 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 16554 /* The handle of the RSS context */ 16555 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 16556 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 16557 16558 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 16559 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 16560 /* Hash control flags. If all _MODE bits are zero (which will always be true 16561 * for older firmware which does not report the ADDITIONAL_RSS_MODES 16562 * capability), the _EN bits report the state. If any _MODE bits are non-zero 16563 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 16564 * then the _EN bits should be disregarded, although the _MODE flags are 16565 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 16566 * context and in the case where the _EN flags were used in the SET. This 16567 * provides backward compatibility: old drivers will not be attempting to 16568 * derive any meaning from the _MODE bits (and can never set them to any value 16569 * not representable by the _EN bits); new drivers can always determine the 16570 * mode by looking only at the _MODE bits; the value returned by a GET can 16571 * always be used for a SET regardless of old/new driver vs. old/new firmware. 16572 */ 16573 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 16574 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4 16575 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4 16576 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 16577 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 16578 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4 16579 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 16580 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 16581 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4 16582 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 16583 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 16584 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4 16585 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 16586 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 16587 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4 16588 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 16589 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 16590 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4 16591 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 16592 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 16593 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4 16594 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 16595 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 16596 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4 16597 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 16598 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 16599 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4 16600 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 16601 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 16602 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4 16603 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 16604 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 16605 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4 16606 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 16607 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 16608 16609 16610 /***********************************/ 16611 /* MC_CMD_DOT1P_MAPPING_ALLOC 16612 * Allocate a .1p mapping. 16613 */ 16614 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 16615 #undef MC_CMD_0xa4_PRIVILEGE_CTG 16616 16617 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16618 16619 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 16620 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 16621 /* The handle of the owning upstream port */ 16622 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 16623 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 16624 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 16625 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 16626 * referenced RSS contexts must span no more than this number. 16627 */ 16628 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 16629 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 16630 16631 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 16632 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 16633 /* The handle of the new .1p mapping. This should be considered opaque to the 16634 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 16635 * handle. 16636 */ 16637 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 16638 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 16639 /* enum: guaranteed invalid .1p mapping handle value */ 16640 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 16641 16642 16643 /***********************************/ 16644 /* MC_CMD_DOT1P_MAPPING_FREE 16645 * Free a .1p mapping. 16646 */ 16647 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 16648 #undef MC_CMD_0xa5_PRIVILEGE_CTG 16649 16650 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16651 16652 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 16653 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 16654 /* The handle of the .1p mapping */ 16655 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 16656 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 16657 16658 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 16659 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 16660 16661 16662 /***********************************/ 16663 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 16664 * Set the mapping table for a .1p mapping. 16665 */ 16666 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 16667 #undef MC_CMD_0xa6_PRIVILEGE_CTG 16668 16669 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16670 16671 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 16672 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 16673 /* The handle of the .1p mapping */ 16674 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 16675 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 16676 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 16677 * handle) 16678 */ 16679 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 16680 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 16681 16682 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 16683 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 16684 16685 16686 /***********************************/ 16687 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 16688 * Get the mapping table for a .1p mapping. 16689 */ 16690 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 16691 #undef MC_CMD_0xa7_PRIVILEGE_CTG 16692 16693 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16694 16695 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 16696 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 16697 /* The handle of the .1p mapping */ 16698 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 16699 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 16700 16701 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 16702 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 16703 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 16704 * handle) 16705 */ 16706 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 16707 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 16708 16709 16710 /***********************************/ 16711 /* MC_CMD_GET_VECTOR_CFG 16712 * Get Interrupt Vector config for this PF. 16713 */ 16714 #define MC_CMD_GET_VECTOR_CFG 0xbf 16715 #undef MC_CMD_0xbf_PRIVILEGE_CTG 16716 16717 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16718 16719 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 16720 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 16721 16722 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 16723 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 16724 /* Base absolute interrupt vector number. */ 16725 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 16726 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 16727 /* Number of interrupt vectors allocate to this PF. */ 16728 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 16729 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 16730 /* Number of interrupt vectors to allocate per VF. */ 16731 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 16732 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 16733 16734 16735 /***********************************/ 16736 /* MC_CMD_SET_VECTOR_CFG 16737 * Set Interrupt Vector config for this PF. 16738 */ 16739 #define MC_CMD_SET_VECTOR_CFG 0xc0 16740 #undef MC_CMD_0xc0_PRIVILEGE_CTG 16741 16742 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16743 16744 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 16745 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 16746 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 16747 * let the system find a suitable base. 16748 */ 16749 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 16750 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 16751 /* Number of interrupt vectors allocate to this PF. */ 16752 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 16753 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 16754 /* Number of interrupt vectors to allocate per VF. */ 16755 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 16756 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 16757 16758 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 16759 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 16760 16761 16762 /***********************************/ 16763 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 16764 * Add a MAC address to a v-port 16765 */ 16766 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 16767 #undef MC_CMD_0xa8_PRIVILEGE_CTG 16768 16769 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16770 16771 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 16772 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 16773 /* The handle of the v-port */ 16774 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 16775 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4 16776 /* MAC address to add */ 16777 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 16778 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 16779 16780 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 16781 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 16782 16783 16784 /***********************************/ 16785 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 16786 * Delete a MAC address from a v-port 16787 */ 16788 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 16789 #undef MC_CMD_0xa9_PRIVILEGE_CTG 16790 16791 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16792 16793 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 16794 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 16795 /* The handle of the v-port */ 16796 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 16797 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4 16798 /* MAC address to add */ 16799 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 16800 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 16801 16802 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 16803 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 16804 16805 16806 /***********************************/ 16807 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 16808 * Delete a MAC address from a v-port 16809 */ 16810 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 16811 #undef MC_CMD_0xaa_PRIVILEGE_CTG 16812 16813 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16814 16815 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 16816 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 16817 /* The handle of the v-port */ 16818 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 16819 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4 16820 16821 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 16822 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 16823 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 16824 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018 16825 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 16826 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6) 16827 /* The number of MAC addresses returned */ 16828 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 16829 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4 16830 /* Array of MAC addresses */ 16831 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 16832 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 16833 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 16834 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 16835 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 169 16836 16837 16838 /***********************************/ 16839 /* MC_CMD_VPORT_RECONFIGURE 16840 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 16841 * has already been passed to another function (v-port's user), then that 16842 * function will be reset before applying the changes. 16843 */ 16844 #define MC_CMD_VPORT_RECONFIGURE 0xeb 16845 #undef MC_CMD_0xeb_PRIVILEGE_CTG 16846 16847 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16848 16849 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 16850 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 16851 /* The handle of the v-port */ 16852 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 16853 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4 16854 /* Flags requesting what should be changed. */ 16855 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 16856 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4 16857 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4 16858 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 16859 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 16860 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4 16861 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 16862 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 16863 /* The number of VLAN tags to insert/remove. An error will be returned if 16864 * incompatible with the number of VLAN tags specified for the upstream 16865 * v-switch. 16866 */ 16867 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 16868 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4 16869 /* The actual VLAN tags to insert/remove */ 16870 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 16871 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4 16872 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12 16873 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 16874 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 16875 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12 16876 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 16877 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 16878 /* The number of MAC addresses to add */ 16879 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 16880 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4 16881 /* MAC addresses to add */ 16882 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 16883 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 16884 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 16885 16886 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 16887 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 16888 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 16889 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4 16890 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0 16891 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 16892 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 16893 16894 16895 /***********************************/ 16896 /* MC_CMD_EVB_PORT_QUERY 16897 * read some config of v-port. 16898 */ 16899 #define MC_CMD_EVB_PORT_QUERY 0x62 16900 #undef MC_CMD_0x62_PRIVILEGE_CTG 16901 16902 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16903 16904 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 16905 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 16906 /* The handle of the v-port */ 16907 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 16908 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 16909 16910 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 16911 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 16912 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 16913 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 16914 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 16915 /* The number of VLAN tags that may be used on a v-adaptor connected to this 16916 * EVB port. 16917 */ 16918 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 16919 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 16920 16921 16922 /***********************************/ 16923 /* MC_CMD_DUMP_BUFTBL_ENTRIES 16924 * Dump buffer table entries, mainly for command client debug use. Dumps 16925 * absolute entries, and does not use chunk handles. All entries must be in 16926 * range, and used for q page mapping, Although the latter restriction may be 16927 * lifted in future. 16928 */ 16929 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 16930 #undef MC_CMD_0xab_PRIVILEGE_CTG 16931 16932 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 16933 16934 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 16935 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 16936 /* Index of the first buffer table entry. */ 16937 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 16938 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 16939 /* Number of buffer table entries to dump. */ 16940 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 16941 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 16942 16943 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 16944 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 16945 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 16946 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX_MCDI2 1020 16947 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 16948 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12) 16949 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 16950 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 16951 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 16952 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 16953 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 16954 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM_MCDI2 85 16955 16956 16957 /***********************************/ 16958 /* MC_CMD_SET_RXDP_CONFIG 16959 * Set global RXDP configuration settings 16960 */ 16961 #define MC_CMD_SET_RXDP_CONFIG 0xc1 16962 #undef MC_CMD_0xc1_PRIVILEGE_CTG 16963 16964 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16965 16966 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 16967 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 16968 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 16969 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 16970 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0 16971 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 16972 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 16973 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0 16974 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 16975 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 16976 /* enum: pad to 64 bytes */ 16977 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 16978 /* enum: pad to 128 bytes (Medford only) */ 16979 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 16980 /* enum: pad to 256 bytes (Medford only) */ 16981 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 16982 16983 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 16984 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 16985 16986 16987 /***********************************/ 16988 /* MC_CMD_GET_RXDP_CONFIG 16989 * Get global RXDP configuration settings 16990 */ 16991 #define MC_CMD_GET_RXDP_CONFIG 0xc2 16992 #undef MC_CMD_0xc2_PRIVILEGE_CTG 16993 16994 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16995 16996 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 16997 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 16998 16999 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 17000 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 17001 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 17002 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 17003 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0 17004 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 17005 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 17006 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0 17007 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 17008 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 17009 /* Enum values, see field(s): */ 17010 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 17011 17012 17013 /***********************************/ 17014 /* MC_CMD_GET_CLOCK 17015 * Return the system and PDCPU clock frequencies. 17016 */ 17017 #define MC_CMD_GET_CLOCK 0xac 17018 #undef MC_CMD_0xac_PRIVILEGE_CTG 17019 17020 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17021 17022 /* MC_CMD_GET_CLOCK_IN msgrequest */ 17023 #define MC_CMD_GET_CLOCK_IN_LEN 0 17024 17025 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 17026 #define MC_CMD_GET_CLOCK_OUT_LEN 8 17027 /* System frequency, MHz */ 17028 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 17029 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4 17030 /* DPCPU frequency, MHz */ 17031 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 17032 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 17033 17034 17035 /***********************************/ 17036 /* MC_CMD_SET_CLOCK 17037 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 17038 */ 17039 #define MC_CMD_SET_CLOCK 0xad 17040 #undef MC_CMD_0xad_PRIVILEGE_CTG 17041 17042 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17043 17044 /* MC_CMD_SET_CLOCK_IN msgrequest */ 17045 #define MC_CMD_SET_CLOCK_IN_LEN 28 17046 /* Requested frequency in MHz for system clock domain */ 17047 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 17048 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 17049 /* enum: Leave the system clock domain frequency unchanged */ 17050 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 17051 /* Requested frequency in MHz for inter-core clock domain */ 17052 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 17053 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 17054 /* enum: Leave the inter-core clock domain frequency unchanged */ 17055 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 17056 /* Requested frequency in MHz for DPCPU clock domain */ 17057 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 17058 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 17059 /* enum: Leave the DPCPU clock domain frequency unchanged */ 17060 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 17061 /* Requested frequency in MHz for PCS clock domain */ 17062 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 17063 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 17064 /* enum: Leave the PCS clock domain frequency unchanged */ 17065 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 17066 /* Requested frequency in MHz for MC clock domain */ 17067 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 17068 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 17069 /* enum: Leave the MC clock domain frequency unchanged */ 17070 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 17071 /* Requested frequency in MHz for rmon clock domain */ 17072 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 17073 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 17074 /* enum: Leave the rmon clock domain frequency unchanged */ 17075 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 17076 /* Requested frequency in MHz for vswitch clock domain */ 17077 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 17078 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 17079 /* enum: Leave the vswitch clock domain frequency unchanged */ 17080 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 17081 17082 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 17083 #define MC_CMD_SET_CLOCK_OUT_LEN 28 17084 /* Resulting system frequency in MHz */ 17085 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 17086 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 17087 /* enum: The system clock domain doesn't exist */ 17088 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 17089 /* Resulting inter-core frequency in MHz */ 17090 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 17091 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 17092 /* enum: The inter-core clock domain doesn't exist / isn't used */ 17093 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 17094 /* Resulting DPCPU frequency in MHz */ 17095 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 17096 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 17097 /* enum: The dpcpu clock domain doesn't exist */ 17098 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 17099 /* Resulting PCS frequency in MHz */ 17100 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 17101 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 17102 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 17103 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 17104 /* Resulting MC frequency in MHz */ 17105 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 17106 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 17107 /* enum: The MC clock domain doesn't exist / isn't controlled */ 17108 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 17109 /* Resulting rmon frequency in MHz */ 17110 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 17111 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 17112 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 17113 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 17114 /* Resulting vswitch frequency in MHz */ 17115 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 17116 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 17117 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 17118 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 17119 17120 17121 /***********************************/ 17122 /* MC_CMD_DPCPU_RPC 17123 * Send an arbitrary DPCPU message. 17124 */ 17125 #define MC_CMD_DPCPU_RPC 0xae 17126 #undef MC_CMD_0xae_PRIVILEGE_CTG 17127 17128 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17129 17130 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 17131 #define MC_CMD_DPCPU_RPC_IN_LEN 36 17132 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 17133 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 17134 /* enum: RxDPCPU0 */ 17135 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 17136 /* enum: TxDPCPU0 */ 17137 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 17138 /* enum: TxDPCPU1 */ 17139 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 17140 /* enum: RxDPCPU1 (Medford only) */ 17141 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 17142 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 17143 * DPCPU_RX0) 17144 */ 17145 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 17146 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 17147 * DPCPU_TX0) 17148 */ 17149 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 17150 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 17151 * initialised to zero 17152 */ 17153 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 17154 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 17155 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4 17156 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 17157 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 17158 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 17159 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 17160 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 17161 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 17162 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 17163 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 17164 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 17165 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 17166 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 17167 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4 17168 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 17169 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 17170 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4 17171 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 17172 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 17173 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4 17174 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 17175 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 17176 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4 17177 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 17178 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 17179 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4 17180 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 17181 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 17182 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 17183 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 17184 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 17185 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 17186 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 17187 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4 17188 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 17189 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 17190 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4 17191 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 17192 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 17193 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4 17194 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 17195 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 17196 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4 17197 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 17198 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 17199 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 17200 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 17201 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 17202 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4 17203 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 17204 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 17205 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 17206 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 17207 /* Register data to write. Only valid in write/write-read. */ 17208 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 17209 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 17210 /* Register address. */ 17211 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 17212 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 17213 17214 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 17215 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 17216 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 17217 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 17218 /* DATA */ 17219 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 17220 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 17221 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4 17222 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 17223 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 17224 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4 17225 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 17226 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 17227 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 17228 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 17229 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 17230 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 17231 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 17232 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 17233 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 17234 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 17235 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 17236 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 17237 17238 17239 /***********************************/ 17240 /* MC_CMD_TRIGGER_INTERRUPT 17241 * Trigger an interrupt by prodding the BIU. 17242 */ 17243 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 17244 #undef MC_CMD_0xe3_PRIVILEGE_CTG 17245 17246 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17247 17248 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 17249 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 17250 /* Interrupt level relative to base for function. */ 17251 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 17252 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4 17253 17254 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 17255 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 17256 17257 17258 /***********************************/ 17259 /* MC_CMD_SHMBOOT_OP 17260 * Special operations to support (for now) shmboot. 17261 */ 17262 #define MC_CMD_SHMBOOT_OP 0xe6 17263 #undef MC_CMD_0xe6_PRIVILEGE_CTG 17264 17265 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17266 17267 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 17268 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 17269 /* Identifies the operation to perform */ 17270 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 17271 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 17272 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 17273 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 17274 17275 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 17276 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 17277 17278 17279 /***********************************/ 17280 /* MC_CMD_CAP_BLK_READ 17281 * Read multiple 64bit words from capture block memory 17282 */ 17283 #define MC_CMD_CAP_BLK_READ 0xe7 17284 #undef MC_CMD_0xe7_PRIVILEGE_CTG 17285 17286 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17287 17288 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 17289 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 17290 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 17291 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 17292 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 17293 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 17294 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 17295 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 17296 17297 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 17298 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 17299 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 17300 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX_MCDI2 1016 17301 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 17302 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8) 17303 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 17304 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 17305 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 17306 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 17307 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 17308 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 17309 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127 17310 17311 17312 /***********************************/ 17313 /* MC_CMD_DUMP_DO 17314 * Take a dump of the DUT state 17315 */ 17316 #define MC_CMD_DUMP_DO 0xe8 17317 #undef MC_CMD_0xe8_PRIVILEGE_CTG 17318 17319 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17320 17321 /* MC_CMD_DUMP_DO_IN msgrequest */ 17322 #define MC_CMD_DUMP_DO_IN_LEN 52 17323 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 17324 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4 17325 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 17326 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4 17327 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 17328 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 17329 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 17330 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 17331 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 17332 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 17333 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 17334 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 17335 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 17336 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 17337 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 17338 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 17339 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 17340 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 17341 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 17342 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 17343 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 17344 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 17345 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 17346 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 17347 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 17348 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 17349 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 17350 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 17351 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 17352 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 17353 /* enum: The uart port this command was received over (if using a uart 17354 * transport) 17355 */ 17356 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 17357 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 17358 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 17359 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 17360 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4 17361 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 17362 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 17363 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 17364 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 17365 /* Enum values, see field(s): */ 17366 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 17367 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 17368 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 17369 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 17370 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 17371 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 17372 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 17373 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 17374 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 17375 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 17376 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 17377 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 17378 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 17379 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 17380 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 17381 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 17382 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 17383 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 17384 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 17385 17386 /* MC_CMD_DUMP_DO_OUT msgresponse */ 17387 #define MC_CMD_DUMP_DO_OUT_LEN 4 17388 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 17389 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 17390 17391 17392 /***********************************/ 17393 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 17394 * Configure unsolicited dumps 17395 */ 17396 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 17397 #undef MC_CMD_0xe9_PRIVILEGE_CTG 17398 17399 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17400 17401 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 17402 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 17403 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 17404 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4 17405 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 17406 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4 17407 /* Enum values, see field(s): */ 17408 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 17409 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 17410 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 17411 /* Enum values, see field(s): */ 17412 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 17413 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 17414 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 17415 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 17416 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 17417 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 17418 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 17419 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 17420 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 17421 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 17422 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 17423 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 17424 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 17425 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 17426 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 17427 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 17428 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 17429 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 17430 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 17431 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 17432 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4 17433 /* Enum values, see field(s): */ 17434 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 17435 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 17436 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 17437 /* Enum values, see field(s): */ 17438 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 17439 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 17440 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 17441 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 17442 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 17443 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 17444 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 17445 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 17446 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 17447 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 17448 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 17449 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 17450 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 17451 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 17452 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 17453 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 17454 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 17455 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 17456 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 17457 17458 17459 /***********************************/ 17460 /* MC_CMD_SET_PSU 17461 * Adjusts power supply parameters. This is a warranty-voiding operation. 17462 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 17463 * the parameter is out of range. 17464 */ 17465 #define MC_CMD_SET_PSU 0xea 17466 #undef MC_CMD_0xea_PRIVILEGE_CTG 17467 17468 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17469 17470 /* MC_CMD_SET_PSU_IN msgrequest */ 17471 #define MC_CMD_SET_PSU_IN_LEN 12 17472 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 17473 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4 17474 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 17475 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 17476 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4 17477 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 17478 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 17479 /* desired value, eg voltage in mV */ 17480 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 17481 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4 17482 17483 /* MC_CMD_SET_PSU_OUT msgresponse */ 17484 #define MC_CMD_SET_PSU_OUT_LEN 0 17485 17486 17487 /***********************************/ 17488 /* MC_CMD_GET_FUNCTION_INFO 17489 * Get function information. PF and VF number. 17490 */ 17491 #define MC_CMD_GET_FUNCTION_INFO 0xec 17492 #undef MC_CMD_0xec_PRIVILEGE_CTG 17493 17494 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17495 17496 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 17497 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 17498 17499 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 17500 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 17501 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 17502 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4 17503 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 17504 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 17505 17506 17507 /***********************************/ 17508 /* MC_CMD_ENABLE_OFFLINE_BIST 17509 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 17510 * mode, calling function gets exclusive MCDI ownership. The only way out is 17511 * reboot. 17512 */ 17513 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 17514 #undef MC_CMD_0xed_PRIVILEGE_CTG 17515 17516 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17517 17518 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 17519 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 17520 17521 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 17522 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 17523 17524 17525 /***********************************/ 17526 /* MC_CMD_UART_SEND_DATA 17527 * Send checksummed[sic] block of data over the uart. Response is a placeholder 17528 * should we wish to make this reliable; currently requests are fire-and- 17529 * forget. 17530 */ 17531 #define MC_CMD_UART_SEND_DATA 0xee 17532 #undef MC_CMD_0xee_PRIVILEGE_CTG 17533 17534 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17535 17536 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 17537 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 17538 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 17539 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX_MCDI2 1020 17540 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 17541 #define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1) 17542 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 17543 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 17544 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 17545 /* Offset at which to write the data */ 17546 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 17547 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 17548 /* Length of data */ 17549 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 17550 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 17551 /* Reserved for future use */ 17552 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 17553 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 17554 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 17555 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 17556 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 17557 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 17558 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM_MCDI2 1004 17559 17560 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 17561 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 17562 17563 17564 /***********************************/ 17565 /* MC_CMD_UART_RECV_DATA 17566 * Request checksummed[sic] block of data over the uart. Only a placeholder, 17567 * subject to change and not currently implemented. 17568 */ 17569 #define MC_CMD_UART_RECV_DATA 0xef 17570 #undef MC_CMD_0xef_PRIVILEGE_CTG 17571 17572 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17573 17574 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 17575 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 17576 /* CRC32 over OFFSET, LENGTH, RESERVED */ 17577 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 17578 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 17579 /* Offset from which to read the data */ 17580 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 17581 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 17582 /* Length of data */ 17583 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 17584 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 17585 /* Reserved for future use */ 17586 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 17587 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 17588 17589 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 17590 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 17591 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 17592 #define MC_CMD_UART_RECV_DATA_IN_LENMAX_MCDI2 1020 17593 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 17594 #define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1) 17595 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 17596 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 17597 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 17598 /* Offset at which to write the data */ 17599 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 17600 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 17601 /* Length of data */ 17602 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 17603 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 17604 /* Reserved for future use */ 17605 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 17606 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 17607 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 17608 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 17609 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 17610 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 17611 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM_MCDI2 1004 17612 17613 17614 /***********************************/ 17615 /* MC_CMD_READ_FUSES 17616 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 17617 */ 17618 #define MC_CMD_READ_FUSES 0xf0 17619 #undef MC_CMD_0xf0_PRIVILEGE_CTG 17620 17621 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 17622 17623 /* MC_CMD_READ_FUSES_IN msgrequest */ 17624 #define MC_CMD_READ_FUSES_IN_LEN 8 17625 /* Offset in OTP to read */ 17626 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 17627 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 17628 /* Length of data to read in bytes */ 17629 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 17630 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 17631 17632 /* MC_CMD_READ_FUSES_OUT msgresponse */ 17633 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 17634 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 17635 #define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020 17636 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 17637 #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1) 17638 /* Length of returned OTP data in bytes */ 17639 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 17640 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 17641 /* Returned data */ 17642 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 17643 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 17644 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 17645 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 17646 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 1016 17647 17648 17649 /***********************************/ 17650 /* MC_CMD_KR_TUNE 17651 * Get or set KR Serdes RXEQ and TX Driver settings 17652 */ 17653 #define MC_CMD_KR_TUNE 0xf1 17654 #undef MC_CMD_0xf1_PRIVILEGE_CTG 17655 17656 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17657 17658 /* MC_CMD_KR_TUNE_IN msgrequest */ 17659 #define MC_CMD_KR_TUNE_IN_LENMIN 4 17660 #define MC_CMD_KR_TUNE_IN_LENMAX 252 17661 #define MC_CMD_KR_TUNE_IN_LENMAX_MCDI2 1020 17662 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 17663 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4) 17664 /* Requested operation */ 17665 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 17666 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 17667 /* enum: Get current RXEQ settings */ 17668 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 17669 /* enum: Override RXEQ settings */ 17670 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 17671 /* enum: Get current TX Driver settings */ 17672 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 17673 /* enum: Override TX Driver settings */ 17674 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 17675 /* enum: Force KR Serdes reset / recalibration */ 17676 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 17677 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 17678 * signal. 17679 */ 17680 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 17681 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 17682 * caller should call this command repeatedly after starting eye plot, until no 17683 * more data is returned. 17684 */ 17685 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 17686 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 17687 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 17688 /* enum: Start/stop link training frames */ 17689 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8 17690 /* enum: Issue KR link training command (control training coefficients) */ 17691 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9 17692 /* Align the arguments to 32 bits */ 17693 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 17694 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 17695 /* Arguments specific to the operation */ 17696 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 17697 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 17698 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 17699 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 17700 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM_MCDI2 254 17701 17702 /* MC_CMD_KR_TUNE_OUT msgresponse */ 17703 #define MC_CMD_KR_TUNE_OUT_LEN 0 17704 17705 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 17706 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 17707 /* Requested operation */ 17708 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 17709 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 17710 /* Align the arguments to 32 bits */ 17711 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 17712 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 17713 17714 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 17715 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 17716 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 17717 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020 17718 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 17719 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 17720 /* RXEQ Parameter */ 17721 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 17722 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 17723 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 17724 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 17725 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 17726 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0 17727 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 17728 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 17729 /* enum: Attenuation (0-15, Huntington) */ 17730 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 17731 /* enum: CTLE Boost (0-15, Huntington) */ 17732 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 17733 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 17734 * positive, Medford - 0-31) 17735 */ 17736 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 17737 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 17738 * positive, Medford - 0-31) 17739 */ 17740 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 17741 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 17742 * positive, Medford - 0-16) 17743 */ 17744 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 17745 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 17746 * positive, Medford - 0-16) 17747 */ 17748 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 17749 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 17750 * positive, Medford - 0-16) 17751 */ 17752 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 17753 /* enum: Edge DFE DLEV (0-128 for Medford) */ 17754 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 17755 /* enum: Variable Gain Amplifier (0-15, Medford) */ 17756 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 17757 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 17758 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 17759 /* enum: CTLE EQ Resistor (0-7, Medford) */ 17760 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 17761 /* enum: CTLE gain (0-31, Medford2) */ 17762 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb 17763 /* enum: CTLE pole (0-31, Medford2) */ 17764 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc 17765 /* enum: CTLE peaking (0-31, Medford2) */ 17766 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd 17767 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */ 17768 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe 17769 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */ 17770 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf 17771 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */ 17772 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10 17773 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */ 17774 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11 17775 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */ 17776 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12 17777 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */ 17778 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13 17779 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */ 17780 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14 17781 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */ 17782 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15 17783 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */ 17784 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16 17785 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */ 17786 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17 17787 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */ 17788 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18 17789 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */ 17790 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19 17791 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */ 17792 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a 17793 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */ 17794 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b 17795 /* enum: Negative h1 polarity data sampler offset calibration code, even path 17796 * (Medford2 - 6 bit signed (-29 - +29))) 17797 */ 17798 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c 17799 /* enum: Negative h1 polarity data sampler offset calibration code, odd path 17800 * (Medford2 - 6 bit signed (-29 - +29))) 17801 */ 17802 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d 17803 /* enum: Positive h1 polarity data sampler offset calibration code, even path 17804 * (Medford2 - 6 bit signed (-29 - +29))) 17805 */ 17806 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e 17807 /* enum: Positive h1 polarity data sampler offset calibration code, odd path 17808 * (Medford2 - 6 bit signed (-29 - +29))) 17809 */ 17810 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f 17811 /* enum: CDR calibration loop code (Medford2) */ 17812 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20 17813 /* enum: CDR integral loop code (Medford2) */ 17814 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21 17815 /* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4 17816 * stages, 2 bits per stage) 17817 */ 17818 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22 17819 /* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31)) 17820 */ 17821 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23 17822 /* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15)) 17823 */ 17824 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24 17825 /* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15)) 17826 */ 17827 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25 17828 /* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15)) 17829 */ 17830 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26 17831 /* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15)) 17832 */ 17833 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27 17834 /* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4 17835 * stages, 2 bits per stage) 17836 */ 17837 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28 17838 /* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31)) 17839 */ 17840 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29 17841 /* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15)) 17842 */ 17843 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a 17844 /* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15)) 17845 */ 17846 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b 17847 /* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15)) 17848 */ 17849 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c 17850 /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15)) 17851 */ 17852 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d 17853 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0 17854 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 17855 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 17856 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 17857 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 17858 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 17859 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 17860 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 17861 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0 17862 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 17863 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 17864 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0 17865 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 17866 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 17867 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0 17868 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 17869 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 17870 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0 17871 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 17872 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 17873 17874 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 17875 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 17876 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 17877 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020 17878 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 17879 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4) 17880 /* Requested operation */ 17881 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 17882 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 17883 /* Align the arguments to 32 bits */ 17884 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 17885 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 17886 /* RXEQ Parameter */ 17887 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 17888 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 17889 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 17890 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 17891 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254 17892 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4 17893 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 17894 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 17895 /* Enum values, see field(s): */ 17896 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 17897 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4 17898 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 17899 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 17900 /* Enum values, see field(s): */ 17901 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 17902 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4 17903 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 17904 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 17905 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4 17906 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 17907 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 17908 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4 17909 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 17910 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 17911 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4 17912 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 17913 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 17914 17915 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 17916 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 17917 17918 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 17919 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 17920 /* Requested operation */ 17921 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 17922 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 17923 /* Align the arguments to 32 bits */ 17924 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 17925 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 17926 17927 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 17928 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 17929 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 17930 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020 17931 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 17932 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 17933 /* TXEQ Parameter */ 17934 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 17935 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 17936 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 17937 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 17938 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 17939 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0 17940 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 17941 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 17942 /* enum: TX Amplitude (Huntington, Medford, Medford2) */ 17943 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 17944 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 17945 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 17946 /* enum: De-Emphasis Tap1 Fine */ 17947 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 17948 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 17949 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 17950 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 17951 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 17952 /* enum: Pre-Emphasis Magnitude (Huntington) */ 17953 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 17954 /* enum: Pre-Emphasis Fine (Huntington) */ 17955 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 17956 /* enum: TX Slew Rate Coarse control (Huntington) */ 17957 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 17958 /* enum: TX Slew Rate Fine control (Huntington) */ 17959 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 17960 /* enum: TX Termination Impedance control (Huntington) */ 17961 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 17962 /* enum: TX Amplitude Fine control (Medford) */ 17963 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 17964 /* enum: Pre-cursor Tap (Medford, Medford2) */ 17965 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 17966 /* enum: Post-cursor Tap (Medford, Medford2) */ 17967 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 17968 /* enum: TX Amplitude (Retimer Lineside) */ 17969 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd 17970 /* enum: Pre-cursor Tap (Retimer Lineside) */ 17971 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe 17972 /* enum: Post-cursor Tap (Retimer Lineside) */ 17973 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf 17974 /* enum: TX Amplitude (Retimer Hostside) */ 17975 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10 17976 /* enum: Pre-cursor Tap (Retimer Hostside) */ 17977 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11 17978 /* enum: Post-cursor Tap (Retimer Hostside) */ 17979 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12 17980 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0 17981 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 17982 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 17983 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 17984 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 17985 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 17986 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 17987 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 17988 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0 17989 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 17990 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 17991 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0 17992 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 17993 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 17994 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0 17995 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 17996 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 17997 17998 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 17999 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 18000 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 18001 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX_MCDI2 1020 18002 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 18003 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4) 18004 /* Requested operation */ 18005 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 18006 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 18007 /* Align the arguments to 32 bits */ 18008 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 18009 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 18010 /* TXEQ Parameter */ 18011 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 18012 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 18013 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 18014 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 18015 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254 18016 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4 18017 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 18018 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 18019 /* Enum values, see field(s): */ 18020 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 18021 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4 18022 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 18023 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 18024 /* Enum values, see field(s): */ 18025 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 18026 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4 18027 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 18028 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 18029 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4 18030 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 18031 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 18032 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4 18033 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 18034 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 18035 18036 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 18037 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 18038 18039 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 18040 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 18041 /* Requested operation */ 18042 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 18043 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 18044 /* Align the arguments to 32 bits */ 18045 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 18046 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 18047 18048 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 18049 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 18050 18051 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 18052 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 18053 /* Requested operation */ 18054 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 18055 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 18056 /* Align the arguments to 32 bits */ 18057 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 18058 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 18059 /* Port-relative lane to scan eye on */ 18060 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 18061 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 18062 18063 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */ 18064 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12 18065 /* Requested operation */ 18066 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0 18067 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1 18068 /* Align the arguments to 32 bits */ 18069 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1 18070 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3 18071 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4 18072 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4 18073 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4 18074 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0 18075 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8 18076 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4 18077 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31 18078 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1 18079 /* Scan duration / cycle count */ 18080 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8 18081 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4 18082 18083 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 18084 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 18085 18086 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 18087 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 18088 /* Requested operation */ 18089 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 18090 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 18091 /* Align the arguments to 32 bits */ 18092 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 18093 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 18094 18095 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 18096 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 18097 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 18098 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020 18099 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 18100 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2) 18101 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 18102 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 18103 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 18104 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 18105 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510 18106 18107 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 18108 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 18109 /* Requested operation */ 18110 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 18111 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 18112 /* Align the arguments to 32 bits */ 18113 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 18114 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 18115 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 18116 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4 18117 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4 18118 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0 18119 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8 18120 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4 18121 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31 18122 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1 18123 18124 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 18125 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 18126 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 18127 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4 18128 18129 /* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */ 18130 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8 18131 /* Requested operation */ 18132 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0 18133 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1 18134 /* Align the arguments to 32 bits */ 18135 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1 18136 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3 18137 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4 18138 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4 18139 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */ 18140 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */ 18141 18142 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */ 18143 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28 18144 /* Requested operation */ 18145 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0 18146 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1 18147 /* Align the arguments to 32 bits */ 18148 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1 18149 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3 18150 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4 18151 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4 18152 /* Set INITIALIZE state */ 18153 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8 18154 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4 18155 /* Set PRESET state */ 18156 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12 18157 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4 18158 /* C(-1) request */ 18159 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16 18160 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4 18161 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */ 18162 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */ 18163 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */ 18164 /* C(0) request */ 18165 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20 18166 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4 18167 /* Enum values, see field(s): */ 18168 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 18169 /* C(+1) request */ 18170 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24 18171 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4 18172 /* Enum values, see field(s): */ 18173 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 18174 18175 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */ 18176 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24 18177 /* C(-1) status */ 18178 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0 18179 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4 18180 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */ 18181 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */ 18182 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */ 18183 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */ 18184 /* C(0) status */ 18185 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4 18186 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4 18187 /* Enum values, see field(s): */ 18188 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 18189 /* C(+1) status */ 18190 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8 18191 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4 18192 /* Enum values, see field(s): */ 18193 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 18194 /* C(-1) value */ 18195 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12 18196 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4 18197 /* C(0) value */ 18198 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16 18199 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4 18200 /* C(+1) status */ 18201 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20 18202 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4 18203 18204 18205 /***********************************/ 18206 /* MC_CMD_PCIE_TUNE 18207 * Get or set PCIE Serdes RXEQ and TX Driver settings 18208 */ 18209 #define MC_CMD_PCIE_TUNE 0xf2 18210 #undef MC_CMD_0xf2_PRIVILEGE_CTG 18211 18212 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18213 18214 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 18215 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 18216 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 18217 #define MC_CMD_PCIE_TUNE_IN_LENMAX_MCDI2 1020 18218 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 18219 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4) 18220 /* Requested operation */ 18221 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 18222 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 18223 /* enum: Get current RXEQ settings */ 18224 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 18225 /* enum: Override RXEQ settings */ 18226 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 18227 /* enum: Get current TX Driver settings */ 18228 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 18229 /* enum: Override TX Driver settings */ 18230 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 18231 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 18232 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 18233 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 18234 * caller should call this command repeatedly after starting eye plot, until no 18235 * more data is returned. 18236 */ 18237 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 18238 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 18239 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 18240 /* Align the arguments to 32 bits */ 18241 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 18242 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 18243 /* Arguments specific to the operation */ 18244 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 18245 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 18246 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 18247 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 18248 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM_MCDI2 254 18249 18250 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 18251 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 18252 18253 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 18254 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 18255 /* Requested operation */ 18256 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 18257 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 18258 /* Align the arguments to 32 bits */ 18259 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 18260 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 18261 18262 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 18263 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 18264 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 18265 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020 18266 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 18267 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 18268 /* RXEQ Parameter */ 18269 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 18270 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 18271 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 18272 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 18273 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 18274 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0 18275 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 18276 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 18277 /* enum: Attenuation (0-15) */ 18278 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 18279 /* enum: CTLE Boost (0-15) */ 18280 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 18281 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 18282 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 18283 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 18284 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 18285 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 18286 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 18287 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 18288 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 18289 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 18290 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 18291 /* enum: DFE DLev */ 18292 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 18293 /* enum: Figure of Merit */ 18294 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 18295 /* enum: CTLE EQ Capacitor (HF Gain) */ 18296 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 18297 /* enum: CTLE EQ Resistor (DC Gain) */ 18298 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 18299 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0 18300 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 18301 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 18302 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 18303 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 18304 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 18305 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 18306 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 18307 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 18308 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 18309 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 18310 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 18311 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 18312 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 18313 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 18314 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 18315 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 18316 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 18317 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 18318 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 18319 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0 18320 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 18321 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 18322 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0 18323 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 18324 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 18325 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0 18326 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 18327 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 18328 18329 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 18330 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 18331 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 18332 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020 18333 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 18334 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4) 18335 /* Requested operation */ 18336 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 18337 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 18338 /* Align the arguments to 32 bits */ 18339 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 18340 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 18341 /* RXEQ Parameter */ 18342 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 18343 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 18344 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 18345 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 18346 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254 18347 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4 18348 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 18349 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 18350 /* Enum values, see field(s): */ 18351 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 18352 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4 18353 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 18354 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 18355 /* Enum values, see field(s): */ 18356 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 18357 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4 18358 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 18359 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 18360 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4 18361 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 18362 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 18363 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4 18364 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 18365 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 18366 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4 18367 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 18368 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 18369 18370 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 18371 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 18372 18373 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 18374 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 18375 /* Requested operation */ 18376 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 18377 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 18378 /* Align the arguments to 32 bits */ 18379 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 18380 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 18381 18382 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 18383 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 18384 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 18385 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020 18386 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 18387 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4) 18388 /* RXEQ Parameter */ 18389 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 18390 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 18391 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 18392 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 18393 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255 18394 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0 18395 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 18396 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 18397 /* enum: TxMargin (PIPE) */ 18398 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 18399 /* enum: TxSwing (PIPE) */ 18400 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 18401 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 18402 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 18403 /* enum: De-emphasis coefficient C(0) (PIPE) */ 18404 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 18405 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 18406 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 18407 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0 18408 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 18409 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 18410 /* Enum values, see field(s): */ 18411 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 18412 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0 18413 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 18414 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 18415 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0 18416 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 18417 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 18418 18419 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 18420 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 18421 /* Requested operation */ 18422 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 18423 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 18424 /* Align the arguments to 32 bits */ 18425 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 18426 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 18427 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 18428 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 18429 18430 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 18431 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 18432 18433 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 18434 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 18435 /* Requested operation */ 18436 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 18437 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 18438 /* Align the arguments to 32 bits */ 18439 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 18440 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 18441 18442 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 18443 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 18444 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 18445 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020 18446 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 18447 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2) 18448 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 18449 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 18450 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 18451 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 18452 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510 18453 18454 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 18455 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 18456 18457 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 18458 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 18459 18460 18461 /***********************************/ 18462 /* MC_CMD_LICENSING 18463 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 18464 * - not used for V3 licensing 18465 */ 18466 #define MC_CMD_LICENSING 0xf3 18467 #undef MC_CMD_0xf3_PRIVILEGE_CTG 18468 18469 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18470 18471 /* MC_CMD_LICENSING_IN msgrequest */ 18472 #define MC_CMD_LICENSING_IN_LEN 4 18473 /* identifies the type of operation requested */ 18474 #define MC_CMD_LICENSING_IN_OP_OFST 0 18475 #define MC_CMD_LICENSING_IN_OP_LEN 4 18476 /* enum: re-read and apply licenses after a license key partition update; note 18477 * that this operation returns a zero-length response 18478 */ 18479 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 18480 /* enum: report counts of installed licenses */ 18481 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 18482 18483 /* MC_CMD_LICENSING_OUT msgresponse */ 18484 #define MC_CMD_LICENSING_OUT_LEN 28 18485 /* count of application keys which are valid */ 18486 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 18487 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4 18488 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 18489 * MC_CMD_FC_OP_LICENSE) 18490 */ 18491 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 18492 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4 18493 /* count of application keys which are invalid due to being blacklisted */ 18494 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 18495 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4 18496 /* count of application keys which are invalid due to being unverifiable */ 18497 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 18498 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4 18499 /* count of application keys which are invalid due to being for the wrong node 18500 */ 18501 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 18502 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4 18503 /* licensing state (for diagnostics; the exact meaning of the bits in this 18504 * field are private to the firmware) 18505 */ 18506 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 18507 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4 18508 /* licensing subsystem self-test report (for manftest) */ 18509 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 18510 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4 18511 /* enum: licensing subsystem self-test failed */ 18512 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 18513 /* enum: licensing subsystem self-test passed */ 18514 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 18515 18516 18517 /***********************************/ 18518 /* MC_CMD_LICENSING_V3 18519 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 18520 * - V3 licensing (Medford) 18521 */ 18522 #define MC_CMD_LICENSING_V3 0xd0 18523 #undef MC_CMD_0xd0_PRIVILEGE_CTG 18524 18525 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18526 18527 /* MC_CMD_LICENSING_V3_IN msgrequest */ 18528 #define MC_CMD_LICENSING_V3_IN_LEN 4 18529 /* identifies the type of operation requested */ 18530 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 18531 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4 18532 /* enum: re-read and apply licenses after a license key partition update; note 18533 * that this operation returns a zero-length response 18534 */ 18535 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 18536 /* enum: report counts of installed licenses Returns EAGAIN if license 18537 * processing (updating) has been started but not yet completed. 18538 */ 18539 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 18540 18541 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 18542 #define MC_CMD_LICENSING_V3_OUT_LEN 88 18543 /* count of keys which are valid */ 18544 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 18545 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4 18546 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 18547 * MC_CMD_FC_OP_LICENSE) 18548 */ 18549 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 18550 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4 18551 /* count of keys which are invalid due to being unverifiable */ 18552 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 18553 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4 18554 /* count of keys which are invalid due to being for the wrong node */ 18555 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 18556 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4 18557 /* licensing state (for diagnostics; the exact meaning of the bits in this 18558 * field are private to the firmware) 18559 */ 18560 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 18561 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4 18562 /* licensing subsystem self-test report (for manftest) */ 18563 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 18564 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4 18565 /* enum: licensing subsystem self-test failed */ 18566 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 18567 /* enum: licensing subsystem self-test passed */ 18568 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 18569 /* bitmask of licensed applications */ 18570 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 18571 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 18572 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 18573 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 18574 /* reserved for future use */ 18575 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 18576 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 18577 /* bitmask of licensed features */ 18578 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 18579 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 18580 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 18581 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 18582 /* reserved for future use */ 18583 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 18584 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 18585 18586 18587 /***********************************/ 18588 /* MC_CMD_LICENSING_GET_ID_V3 18589 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 18590 * partition - V3 licensing (Medford) 18591 */ 18592 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 18593 #undef MC_CMD_0xd1_PRIVILEGE_CTG 18594 18595 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18596 18597 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 18598 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 18599 18600 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 18601 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 18602 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 18603 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020 18604 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 18605 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1) 18606 /* type of license (eg 3) */ 18607 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 18608 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 18609 /* length of the license ID (in bytes) */ 18610 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 18611 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 18612 /* the unique license ID of the adapter */ 18613 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 18614 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 18615 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 18616 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 18617 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 1012 18618 18619 18620 /***********************************/ 18621 /* MC_CMD_MC2MC_PROXY 18622 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 18623 * This will fail on a single-core system. 18624 */ 18625 #define MC_CMD_MC2MC_PROXY 0xf4 18626 #undef MC_CMD_0xf4_PRIVILEGE_CTG 18627 18628 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18629 18630 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 18631 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 18632 18633 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 18634 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 18635 18636 18637 /***********************************/ 18638 /* MC_CMD_GET_LICENSED_APP_STATE 18639 * Query the state of an individual licensed application. (Note that the actual 18640 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 18641 * or a reboot of the MC.) Not used for V3 licensing 18642 */ 18643 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 18644 #undef MC_CMD_0xf5_PRIVILEGE_CTG 18645 18646 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18647 18648 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 18649 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 18650 /* application ID to query (LICENSED_APP_ID_xxx) */ 18651 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 18652 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4 18653 18654 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 18655 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 18656 /* state of this application */ 18657 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 18658 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4 18659 /* enum: no (or invalid) license is present for the application */ 18660 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 18661 /* enum: a valid license is present for the application */ 18662 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 18663 18664 18665 /***********************************/ 18666 /* MC_CMD_GET_LICENSED_V3_APP_STATE 18667 * Query the state of an individual licensed application. (Note that the actual 18668 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 18669 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 18670 */ 18671 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 18672 #undef MC_CMD_0xd2_PRIVILEGE_CTG 18673 18674 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18675 18676 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 18677 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 18678 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 18679 * mask 18680 */ 18681 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 18682 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 18683 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 18684 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 18685 18686 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 18687 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 18688 /* state of this application */ 18689 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 18690 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 18691 /* enum: no (or invalid) license is present for the application */ 18692 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 18693 /* enum: a valid license is present for the application */ 18694 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 18695 18696 18697 /***********************************/ 18698 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 18699 * Query the state of an one or more licensed features. (Note that the actual 18700 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 18701 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 18702 */ 18703 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 18704 #undef MC_CMD_0xd3_PRIVILEGE_CTG 18705 18706 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18707 18708 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 18709 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 18710 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 18711 * more bits set 18712 */ 18713 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 18714 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 18715 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 18716 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 18717 18718 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 18719 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 18720 /* states of these features - bit set for licensed, clear for not licensed */ 18721 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 18722 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 18723 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 18724 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 18725 18726 18727 /***********************************/ 18728 /* MC_CMD_LICENSED_APP_OP 18729 * Perform an action for an individual licensed application - not used for V3 18730 * licensing. 18731 */ 18732 #define MC_CMD_LICENSED_APP_OP 0xf6 18733 #undef MC_CMD_0xf6_PRIVILEGE_CTG 18734 18735 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18736 18737 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 18738 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 18739 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 18740 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020 18741 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 18742 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4) 18743 /* application ID */ 18744 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 18745 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 18746 /* the type of operation requested */ 18747 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 18748 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 18749 /* enum: validate application */ 18750 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 18751 /* enum: mask application */ 18752 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 18753 /* arguments specific to this particular operation */ 18754 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 18755 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 18756 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 18757 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 18758 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 253 18759 18760 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 18761 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 18762 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 18763 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020 18764 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 18765 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4) 18766 /* result specific to this particular operation */ 18767 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 18768 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 18769 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 18770 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 18771 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 255 18772 18773 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 18774 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 18775 /* application ID */ 18776 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 18777 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 18778 /* the type of operation requested */ 18779 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 18780 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 18781 /* validation challenge */ 18782 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 18783 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 18784 18785 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 18786 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 18787 /* feature expiry (time_t) */ 18788 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 18789 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 18790 /* validation response */ 18791 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 18792 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 18793 18794 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 18795 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 18796 /* application ID */ 18797 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 18798 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 18799 /* the type of operation requested */ 18800 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 18801 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 18802 /* flag */ 18803 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 18804 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 18805 18806 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 18807 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 18808 18809 18810 /***********************************/ 18811 /* MC_CMD_LICENSED_V3_VALIDATE_APP 18812 * Perform validation for an individual licensed application - V3 licensing 18813 * (Medford) 18814 */ 18815 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 18816 #undef MC_CMD_0xd4_PRIVILEGE_CTG 18817 18818 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18819 18820 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 18821 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 18822 /* challenge for validation (384 bits) */ 18823 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 18824 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 18825 /* application ID expressed as a single bit mask */ 18826 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 18827 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 18828 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 18829 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 18830 18831 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 18832 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 18833 /* validation response to challenge in the form of ECDSA signature consisting 18834 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 18835 * SHA-384 digest of a message constructed from the concatenation of the input 18836 * message and the remaining fields of this output message, e.g. challenge[48 18837 * bytes] ... expiry_time[4 bytes] ... 18838 */ 18839 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 18840 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 18841 /* application expiry time */ 18842 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 18843 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 18844 /* application expiry units */ 18845 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 18846 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 18847 /* enum: expiry units are accounting units */ 18848 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 18849 /* enum: expiry units are calendar days */ 18850 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 18851 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 18852 * value for a given NIC regardless which function is calling, effectively this 18853 * is PF0 base MAC address) 18854 */ 18855 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 18856 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 18857 /* MAC address of v-adaptor associated with the client. If no such v-adapator 18858 * exists, then the field is filled with 0xFF. 18859 */ 18860 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 18861 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 18862 18863 18864 /***********************************/ 18865 /* MC_CMD_LICENSED_V3_MASK_FEATURES 18866 * Mask features - V3 licensing (Medford) 18867 */ 18868 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 18869 #undef MC_CMD_0xd5_PRIVILEGE_CTG 18870 18871 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18872 18873 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 18874 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 18875 /* mask to be applied to features to be changed */ 18876 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 18877 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 18878 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 18879 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 18880 /* whether to turn on or turn off the masked features */ 18881 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 18882 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 18883 /* enum: turn the features off */ 18884 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 18885 /* enum: turn the features back on */ 18886 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 18887 18888 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 18889 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 18890 18891 18892 /***********************************/ 18893 /* MC_CMD_LICENSING_V3_TEMPORARY 18894 * Perform operations to support installation of a single temporary license in 18895 * the adapter, in addition to those found in the licensing partition. See 18896 * SF-116124-SW for an overview of how this could be used. The license is 18897 * stored in MC persistent data and so will survive a MC reboot, but will be 18898 * erased when the adapter is power cycled 18899 */ 18900 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 18901 #undef MC_CMD_0xd6_PRIVILEGE_CTG 18902 18903 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18904 18905 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 18906 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 18907 /* operation code */ 18908 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 18909 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 18910 /* enum: install a new license, overwriting any existing temporary license. 18911 * This is an asynchronous operation owing to the time taken to validate an 18912 * ECDSA license 18913 */ 18914 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 18915 /* enum: clear the license immediately rather than waiting for the next power 18916 * cycle 18917 */ 18918 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 18919 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 18920 * operation 18921 */ 18922 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 18923 18924 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 18925 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 18926 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 18927 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 18928 /* ECDSA license and signature */ 18929 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 18930 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 18931 18932 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 18933 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 18934 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 18935 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 18936 18937 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 18938 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 18939 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 18940 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 18941 18942 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 18943 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 18944 /* status code */ 18945 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 18946 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 18947 /* enum: finished validating and installing license */ 18948 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 18949 /* enum: license validation and installation in progress */ 18950 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 18951 /* enum: licensing error. More specific error messages are not provided to 18952 * avoid exposing details of the licensing system to the client 18953 */ 18954 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 18955 /* bitmask of licensed features */ 18956 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 18957 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 18958 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 18959 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 18960 18961 18962 /***********************************/ 18963 /* MC_CMD_SET_PORT_SNIFF_CONFIG 18964 * Configure RX port sniffing for the physical port associated with the calling 18965 * function. Only a privileged function may change the port sniffing 18966 * configuration. A copy of all traffic delivered to the host (non-promiscuous 18967 * mode) or all traffic arriving at the port (promiscuous mode) may be 18968 * delivered to a specific queue, or a set of queues with RSS. 18969 */ 18970 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 18971 #undef MC_CMD_0xf7_PRIVILEGE_CTG 18972 18973 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18974 18975 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 18976 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 18977 /* configuration flags */ 18978 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 18979 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 18980 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0 18981 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 18982 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 18983 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0 18984 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 18985 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 18986 /* receive queue handle (for RSS mode, this is the base queue) */ 18987 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 18988 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 18989 /* receive mode */ 18990 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 18991 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 18992 /* enum: receive to just the specified queue */ 18993 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 18994 /* enum: receive to multiple queues using RSS context */ 18995 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 18996 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 18997 * that these handles should be considered opaque to the host, although a value 18998 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 18999 */ 19000 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 19001 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 19002 19003 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 19004 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 19005 19006 19007 /***********************************/ 19008 /* MC_CMD_GET_PORT_SNIFF_CONFIG 19009 * Obtain the current RX port sniffing configuration for the physical port 19010 * associated with the calling function. Only a privileged function may read 19011 * the configuration. 19012 */ 19013 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 19014 #undef MC_CMD_0xf8_PRIVILEGE_CTG 19015 19016 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19017 19018 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 19019 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 19020 19021 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 19022 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 19023 /* configuration flags */ 19024 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 19025 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 19026 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0 19027 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 19028 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 19029 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0 19030 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 19031 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 19032 /* receiving queue handle (for RSS mode, this is the base queue) */ 19033 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 19034 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 19035 /* receive mode */ 19036 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 19037 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 19038 /* enum: receiving to just the specified queue */ 19039 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 19040 /* enum: receiving to multiple queues using RSS context */ 19041 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 19042 /* RSS context (for RX_MODE_RSS) */ 19043 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 19044 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 19045 19046 19047 /***********************************/ 19048 /* MC_CMD_SET_PARSER_DISP_CONFIG 19049 * Change configuration related to the parser-dispatcher subsystem. 19050 */ 19051 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 19052 #undef MC_CMD_0xf9_PRIVILEGE_CTG 19053 19054 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19055 19056 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 19057 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 19058 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 19059 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020 19060 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 19061 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4) 19062 /* the type of configuration setting to change */ 19063 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 19064 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 19065 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 19066 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 19067 */ 19068 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 19069 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 19070 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 19071 * boolean.) 19072 */ 19073 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 19074 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 19075 * on the type of configuration setting being changed 19076 */ 19077 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 19078 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 19079 /* new value: the details depend on the type of configuration setting being 19080 * changed 19081 */ 19082 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 19083 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 19084 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 19085 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 19086 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 253 19087 19088 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 19089 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 19090 19091 19092 /***********************************/ 19093 /* MC_CMD_GET_PARSER_DISP_CONFIG 19094 * Read configuration related to the parser-dispatcher subsystem. 19095 */ 19096 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 19097 #undef MC_CMD_0xfa_PRIVILEGE_CTG 19098 19099 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19100 19101 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 19102 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 19103 /* the type of configuration setting to read */ 19104 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 19105 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 19106 /* Enum values, see field(s): */ 19107 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 19108 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 19109 * the type of configuration setting being read 19110 */ 19111 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 19112 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 19113 19114 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 19115 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 19116 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 19117 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020 19118 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 19119 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4) 19120 /* current value: the details depend on the type of configuration setting being 19121 * read 19122 */ 19123 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 19124 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 19125 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 19126 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 19127 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 255 19128 19129 19130 /***********************************/ 19131 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 19132 * Configure TX port sniffing for the physical port associated with the calling 19133 * function. Only a privileged function may change the port sniffing 19134 * configuration. A copy of all traffic transmitted through the port may be 19135 * delivered to a specific queue, or a set of queues with RSS. Note that these 19136 * packets are delivered with transmit timestamps in the packet prefix, not 19137 * receive timestamps, so it is likely that the queue(s) will need to be 19138 * dedicated as TX sniff receivers. 19139 */ 19140 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 19141 #undef MC_CMD_0xfb_PRIVILEGE_CTG 19142 19143 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19144 19145 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 19146 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 19147 /* configuration flags */ 19148 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 19149 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 19150 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0 19151 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 19152 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 19153 /* receive queue handle (for RSS mode, this is the base queue) */ 19154 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 19155 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 19156 /* receive mode */ 19157 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 19158 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 19159 /* enum: receive to just the specified queue */ 19160 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 19161 /* enum: receive to multiple queues using RSS context */ 19162 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 19163 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 19164 * that these handles should be considered opaque to the host, although a value 19165 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 19166 */ 19167 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 19168 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 19169 19170 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 19171 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 19172 19173 19174 /***********************************/ 19175 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 19176 * Obtain the current TX port sniffing configuration for the physical port 19177 * associated with the calling function. Only a privileged function may read 19178 * the configuration. 19179 */ 19180 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 19181 #undef MC_CMD_0xfc_PRIVILEGE_CTG 19182 19183 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19184 19185 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 19186 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 19187 19188 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 19189 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 19190 /* configuration flags */ 19191 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 19192 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 19193 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0 19194 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 19195 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 19196 /* receiving queue handle (for RSS mode, this is the base queue) */ 19197 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 19198 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 19199 /* receive mode */ 19200 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 19201 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 19202 /* enum: receiving to just the specified queue */ 19203 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 19204 /* enum: receiving to multiple queues using RSS context */ 19205 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 19206 /* RSS context (for RX_MODE_RSS) */ 19207 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 19208 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 19209 19210 19211 /***********************************/ 19212 /* MC_CMD_RMON_STATS_RX_ERRORS 19213 * Per queue rx error stats. 19214 */ 19215 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 19216 #undef MC_CMD_0xfe_PRIVILEGE_CTG 19217 19218 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19219 19220 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 19221 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 19222 /* The rx queue to get stats for. */ 19223 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 19224 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 19225 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 19226 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 19227 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4 19228 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 19229 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 19230 19231 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 19232 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 19233 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 19234 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 19235 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 19236 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 19237 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 19238 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 19239 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 19240 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 19241 19242 19243 /***********************************/ 19244 /* MC_CMD_GET_PCIE_RESOURCE_INFO 19245 * Find out about available PCIE resources 19246 */ 19247 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 19248 #undef MC_CMD_0xfd_PRIVILEGE_CTG 19249 19250 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19251 19252 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 19253 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 19254 19255 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 19256 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 19257 /* The maximum number of PFs the device can expose */ 19258 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 19259 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 19260 /* The maximum number of VFs the device can expose in total */ 19261 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 19262 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 19263 /* The maximum number of MSI-X vectors the device can provide in total */ 19264 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 19265 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 19266 /* the number of MSI-X vectors the device will allocate by default to each PF 19267 */ 19268 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 19269 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 19270 /* the number of MSI-X vectors the device will allocate by default to each VF 19271 */ 19272 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 19273 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 19274 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 19275 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 19276 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 19277 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 19278 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 19279 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 19280 19281 19282 /***********************************/ 19283 /* MC_CMD_GET_PORT_MODES 19284 * Find out about available port modes 19285 */ 19286 #define MC_CMD_GET_PORT_MODES 0xff 19287 #undef MC_CMD_0xff_PRIVILEGE_CTG 19288 19289 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19290 19291 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 19292 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 19293 19294 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 19295 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 19296 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) 19297 * that are supported for customer use in production firmware. 19298 */ 19299 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 19300 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 19301 /* Default (canonical) board mode */ 19302 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 19303 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 19304 /* Current board mode */ 19305 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 19306 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 19307 19308 /* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */ 19309 #define MC_CMD_GET_PORT_MODES_OUT_V2_LEN 16 19310 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) 19311 * that are supported for customer use in production firmware. 19312 */ 19313 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0 19314 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4 19315 /* Default (canonical) board mode */ 19316 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4 19317 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4 19318 /* Current board mode */ 19319 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 8 19320 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4 19321 /* Bitmask of engineering port modes available on the board (indexed by 19322 * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that 19323 * contains all modes implemented in firmware for a particular board. Modes 19324 * listed in MODES are considered production modes and should be exposed in 19325 * userland tools. Modes listed in in ENGINEERING_MODES, but not in MODES 19326 * should be considered hidden (not to be exposed in userland tools) and for 19327 * engineering use only. There are no other semantic differences and any mode 19328 * listed in either MODES or ENGINEERING_MODES can be set on the board. 19329 */ 19330 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 12 19331 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4 19332 19333 19334 /***********************************/ 19335 /* MC_CMD_OVERRIDE_PORT_MODE 19336 * Override flash config port mode for subsequent MC reboot(s). Override data 19337 * is stored in the presistent data section of DMEM and activated on next MC 19338 * warm reboot. A cold reboot resets the override. It is assumed that a 19339 * sufficient number of PFs are available and that port mapping is valid for 19340 * the new port mode, as the override does not affect PF configuration. 19341 */ 19342 #define MC_CMD_OVERRIDE_PORT_MODE 0x137 19343 #undef MC_CMD_0x137_PRIVILEGE_CTG 19344 19345 #define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19346 19347 /* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */ 19348 #define MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8 19349 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0 19350 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4 19351 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0 19352 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0 19353 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1 19354 /* New mode (TLV_PORT_MODE_*) to set, if override enabled */ 19355 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4 19356 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4 19357 19358 /* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */ 19359 #define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0 19360 19361 19362 /***********************************/ 19363 /* MC_CMD_READ_ATB 19364 * Sample voltages on the ATB 19365 */ 19366 #define MC_CMD_READ_ATB 0x100 19367 #undef MC_CMD_0x100_PRIVILEGE_CTG 19368 19369 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19370 19371 /* MC_CMD_READ_ATB_IN msgrequest */ 19372 #define MC_CMD_READ_ATB_IN_LEN 16 19373 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 19374 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 19375 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 19376 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 19377 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 19378 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 19379 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 19380 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 19381 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 19382 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 19383 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 19384 19385 /* MC_CMD_READ_ATB_OUT msgresponse */ 19386 #define MC_CMD_READ_ATB_OUT_LEN 4 19387 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 19388 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 19389 19390 19391 /***********************************/ 19392 /* MC_CMD_GET_WORKAROUNDS 19393 * Read the list of all implemented and all currently enabled workarounds. The 19394 * enums here must correspond with those in MC_CMD_WORKAROUND. 19395 */ 19396 #define MC_CMD_GET_WORKAROUNDS 0x59 19397 #undef MC_CMD_0x59_PRIVILEGE_CTG 19398 19399 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19400 19401 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 19402 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 19403 /* Each workaround is represented by a single bit according to the enums below. 19404 */ 19405 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 19406 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4 19407 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 19408 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4 19409 /* enum: Bug 17230 work around. */ 19410 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 19411 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 19412 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 19413 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 19414 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 19415 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 19416 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 19417 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 19418 * - before adding code that queries this workaround, remember that there's 19419 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 19420 * and will hence (incorrectly) report that the bug doesn't exist. 19421 */ 19422 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 19423 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 19424 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 19425 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 19426 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 19427 19428 19429 /***********************************/ 19430 /* MC_CMD_PRIVILEGE_MASK 19431 * Read/set privileges of an arbitrary PCIe function 19432 */ 19433 #define MC_CMD_PRIVILEGE_MASK 0x5a 19434 #undef MC_CMD_0x5a_PRIVILEGE_CTG 19435 19436 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19437 19438 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 19439 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 19440 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 19441 * 1,3 = 0x00030001 19442 */ 19443 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 19444 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4 19445 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0 19446 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 19447 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 19448 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0 19449 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 19450 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 19451 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 19452 /* New privilege mask to be set. The mask will only be changed if the MSB is 19453 * set to 1. 19454 */ 19455 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 19456 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4 19457 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 19458 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 19459 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 19460 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 19461 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 19462 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 19463 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 19464 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 19465 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 19466 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 19467 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 19468 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 19469 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 19470 * adress. 19471 */ 19472 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 19473 /* enum: Privilege that allows a Function to change the MAC address configured 19474 * in its associated vAdapter/vPort. 19475 */ 19476 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 19477 /* enum: Privilege that allows a Function to install filters that specify VLANs 19478 * that are not in the permit list for the associated vPort. This privilege is 19479 * primarily to support ESX where vPorts are created that restrict traffic to 19480 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 19481 */ 19482 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 19483 /* enum: Privilege for insecure commands. Commands that belong to this group 19484 * are not permitted on secure adapters regardless of the privilege mask. 19485 */ 19486 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000 19487 /* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for 19488 * administrator-level operations that are not allowed from the local host once 19489 * an adapter has Bound to a remote ServerLock Controller (see doxbox 19490 * SF-117064-DG for background). 19491 */ 19492 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000 19493 /* enum: Set this bit to indicate that a new privilege mask is to be set, 19494 * otherwise the command will only read the existing mask. 19495 */ 19496 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 19497 19498 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 19499 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 19500 /* For an admin function, always all the privileges are reported. */ 19501 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 19502 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 19503 19504 19505 /***********************************/ 19506 /* MC_CMD_LINK_STATE_MODE 19507 * Read/set link state mode of a VF 19508 */ 19509 #define MC_CMD_LINK_STATE_MODE 0x5c 19510 #undef MC_CMD_0x5c_PRIVILEGE_CTG 19511 19512 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19513 19514 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 19515 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 19516 /* The target function to have its link state mode read or set, must be a VF 19517 * e.g. VF 1,3 = 0x00030001 19518 */ 19519 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 19520 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4 19521 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0 19522 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 19523 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 19524 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0 19525 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 19526 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 19527 /* New link state mode to be set */ 19528 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 19529 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4 19530 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 19531 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 19532 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 19533 /* enum: Use this value to just read the existing setting without modifying it. 19534 */ 19535 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 19536 19537 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 19538 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 19539 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 19540 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 19541 19542 19543 /***********************************/ 19544 /* MC_CMD_GET_SNAPSHOT_LENGTH 19545 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 19546 * parameter to MC_CMD_INIT_RXQ. 19547 */ 19548 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 19549 #undef MC_CMD_0x101_PRIVILEGE_CTG 19550 19551 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 19552 19553 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 19554 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 19555 19556 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 19557 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 19558 /* Minimum acceptable snapshot length. */ 19559 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 19560 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 19561 /* Maximum acceptable snapshot length. */ 19562 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 19563 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 19564 19565 19566 /***********************************/ 19567 /* MC_CMD_FUSE_DIAGS 19568 * Additional fuse diagnostics 19569 */ 19570 #define MC_CMD_FUSE_DIAGS 0x102 19571 #undef MC_CMD_0x102_PRIVILEGE_CTG 19572 19573 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19574 19575 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 19576 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 19577 19578 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 19579 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 19580 /* Total number of mismatched bits between pairs in area 0 */ 19581 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 19582 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 19583 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 19584 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 19585 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 19586 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 19587 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 19588 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 19589 /* Checksum of data after logical OR of pairs in area 0 */ 19590 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 19591 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 19592 /* Total number of mismatched bits between pairs in area 1 */ 19593 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 19594 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 19595 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 19596 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 19597 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 19598 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 19599 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 19600 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 19601 /* Checksum of data after logical OR of pairs in area 1 */ 19602 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 19603 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 19604 /* Total number of mismatched bits between pairs in area 2 */ 19605 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 19606 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 19607 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 19608 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 19609 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 19610 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 19611 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 19612 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 19613 /* Checksum of data after logical OR of pairs in area 2 */ 19614 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 19615 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 19616 19617 19618 /***********************************/ 19619 /* MC_CMD_PRIVILEGE_MODIFY 19620 * Modify the privileges of a set of PCIe functions. Note that this operation 19621 * only effects non-admin functions unless the admin privilege itself is 19622 * included in one of the masks provided. 19623 */ 19624 #define MC_CMD_PRIVILEGE_MODIFY 0x60 19625 #undef MC_CMD_0x60_PRIVILEGE_CTG 19626 19627 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19628 19629 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 19630 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 19631 /* The groups of functions to have their privilege masks modified. */ 19632 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 19633 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 19634 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 19635 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 19636 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 19637 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 19638 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 19639 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 19640 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 19641 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 19642 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 19643 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4 19644 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 19645 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 19646 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4 19647 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 19648 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 19649 /* Privileges to be added to the target functions. For privilege definitions 19650 * refer to the command MC_CMD_PRIVILEGE_MASK 19651 */ 19652 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 19653 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 19654 /* Privileges to be removed from the target functions. For privilege 19655 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 19656 */ 19657 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 19658 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 19659 19660 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 19661 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 19662 19663 19664 /***********************************/ 19665 /* MC_CMD_XPM_READ_BYTES 19666 * Read XPM memory 19667 */ 19668 #define MC_CMD_XPM_READ_BYTES 0x103 19669 #undef MC_CMD_0x103_PRIVILEGE_CTG 19670 19671 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19672 19673 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 19674 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 19675 /* Start address (byte) */ 19676 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 19677 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 19678 /* Count (bytes) */ 19679 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 19680 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 19681 19682 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 19683 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 19684 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 19685 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX_MCDI2 1020 19686 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 19687 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1) 19688 /* Data */ 19689 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 19690 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 19691 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 19692 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 19693 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM_MCDI2 1020 19694 19695 19696 /***********************************/ 19697 /* MC_CMD_XPM_WRITE_BYTES 19698 * Write XPM memory 19699 */ 19700 #define MC_CMD_XPM_WRITE_BYTES 0x104 19701 #undef MC_CMD_0x104_PRIVILEGE_CTG 19702 19703 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19704 19705 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 19706 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 19707 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 19708 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX_MCDI2 1020 19709 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 19710 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1) 19711 /* Start address (byte) */ 19712 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 19713 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 19714 /* Count (bytes) */ 19715 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 19716 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 19717 /* Data */ 19718 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 19719 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 19720 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 19721 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 19722 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM_MCDI2 1012 19723 19724 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 19725 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 19726 19727 19728 /***********************************/ 19729 /* MC_CMD_XPM_READ_SECTOR 19730 * Read XPM sector 19731 */ 19732 #define MC_CMD_XPM_READ_SECTOR 0x105 19733 #undef MC_CMD_0x105_PRIVILEGE_CTG 19734 19735 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19736 19737 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 19738 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 19739 /* Sector index */ 19740 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 19741 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 19742 /* Sector size */ 19743 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 19744 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 19745 19746 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 19747 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 19748 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 19749 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX_MCDI2 36 19750 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 19751 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1) 19752 /* Sector type */ 19753 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 19754 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 19755 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 19756 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 19757 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 19758 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 19759 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 19760 /* Sector data */ 19761 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 19762 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 19763 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 19764 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 19765 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM_MCDI2 32 19766 19767 19768 /***********************************/ 19769 /* MC_CMD_XPM_WRITE_SECTOR 19770 * Write XPM sector 19771 */ 19772 #define MC_CMD_XPM_WRITE_SECTOR 0x106 19773 #undef MC_CMD_0x106_PRIVILEGE_CTG 19774 19775 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19776 19777 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 19778 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 19779 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 19780 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX_MCDI2 44 19781 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 19782 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1) 19783 /* If writing fails due to an uncorrectable error, try up to RETRIES following 19784 * sectors (or until no more space available). If 0, only one write attempt is 19785 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 19786 * mechanism. 19787 */ 19788 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 19789 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 19790 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 19791 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 19792 /* Sector type */ 19793 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 19794 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 19795 /* Enum values, see field(s): */ 19796 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 19797 /* Sector size */ 19798 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 19799 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 19800 /* Sector data */ 19801 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 19802 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 19803 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 19804 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 19805 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM_MCDI2 32 19806 19807 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 19808 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 19809 /* New sector index */ 19810 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 19811 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 19812 19813 19814 /***********************************/ 19815 /* MC_CMD_XPM_INVALIDATE_SECTOR 19816 * Invalidate XPM sector 19817 */ 19818 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 19819 #undef MC_CMD_0x107_PRIVILEGE_CTG 19820 19821 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19822 19823 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 19824 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 19825 /* Sector index */ 19826 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 19827 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 19828 19829 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 19830 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 19831 19832 19833 /***********************************/ 19834 /* MC_CMD_XPM_BLANK_CHECK 19835 * Blank-check XPM memory and report bad locations 19836 */ 19837 #define MC_CMD_XPM_BLANK_CHECK 0x108 19838 #undef MC_CMD_0x108_PRIVILEGE_CTG 19839 19840 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19841 19842 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 19843 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 19844 /* Start address (byte) */ 19845 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 19846 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 19847 /* Count (bytes) */ 19848 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 19849 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 19850 19851 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 19852 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 19853 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 19854 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX_MCDI2 1020 19855 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 19856 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2) 19857 /* Total number of bad (non-blank) locations */ 19858 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 19859 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 19860 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 19861 * into MCDI response) 19862 */ 19863 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 19864 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 19865 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 19866 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 19867 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM_MCDI2 508 19868 19869 19870 /***********************************/ 19871 /* MC_CMD_XPM_REPAIR 19872 * Blank-check and repair XPM memory 19873 */ 19874 #define MC_CMD_XPM_REPAIR 0x109 19875 #undef MC_CMD_0x109_PRIVILEGE_CTG 19876 19877 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19878 19879 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 19880 #define MC_CMD_XPM_REPAIR_IN_LEN 8 19881 /* Start address (byte) */ 19882 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 19883 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 19884 /* Count (bytes) */ 19885 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 19886 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 19887 19888 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 19889 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 19890 19891 19892 /***********************************/ 19893 /* MC_CMD_XPM_DECODER_TEST 19894 * Test XPM memory address decoders for gross manufacturing defects. Can only 19895 * be performed on an unprogrammed part. 19896 */ 19897 #define MC_CMD_XPM_DECODER_TEST 0x10a 19898 #undef MC_CMD_0x10a_PRIVILEGE_CTG 19899 19900 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19901 19902 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 19903 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 19904 19905 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 19906 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 19907 19908 19909 /***********************************/ 19910 /* MC_CMD_XPM_WRITE_TEST 19911 * XPM memory write test. Test XPM write logic for gross manufacturing defects 19912 * by writing to a dedicated test row. There are 16 locations in the test row 19913 * and the test can only be performed on locations that have not been 19914 * previously used (i.e. can be run at most 16 times). The test will pick the 19915 * first available location to use, or fail with ENOSPC if none left. 19916 */ 19917 #define MC_CMD_XPM_WRITE_TEST 0x10b 19918 #undef MC_CMD_0x10b_PRIVILEGE_CTG 19919 19920 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 19921 19922 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 19923 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 19924 19925 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 19926 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 19927 19928 19929 /***********************************/ 19930 /* MC_CMD_EXEC_SIGNED 19931 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 19932 * and if correct begin execution from the start of IMEM. The caller supplies a 19933 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 19934 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 19935 * to match flash booting. The command will respond with EINVAL if the CMAC 19936 * does match, otherwise it will respond with success before it jumps to IMEM. 19937 */ 19938 #define MC_CMD_EXEC_SIGNED 0x10c 19939 #undef MC_CMD_0x10c_PRIVILEGE_CTG 19940 19941 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19942 19943 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 19944 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 19945 /* the length of code to include in the CMAC */ 19946 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 19947 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 19948 /* the length of date to include in the CMAC */ 19949 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 19950 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 19951 /* the XPM sector containing the key to use */ 19952 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 19953 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 19954 /* the expected CMAC value */ 19955 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 19956 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 19957 19958 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 19959 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 19960 19961 19962 /***********************************/ 19963 /* MC_CMD_PREPARE_SIGNED 19964 * Prepare to upload a signed image. This will scrub the specified length of 19965 * the data region, which must be at least as large as the DATALEN supplied to 19966 * MC_CMD_EXEC_SIGNED. 19967 */ 19968 #define MC_CMD_PREPARE_SIGNED 0x10d 19969 #undef MC_CMD_0x10d_PRIVILEGE_CTG 19970 19971 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 19972 19973 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 19974 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 19975 /* the length of data area to clear */ 19976 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 19977 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 19978 19979 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 19980 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 19981 19982 19983 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 19984 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 19985 /* UDP port (the standard ports are named below but any port may be used) */ 19986 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 19987 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 19988 /* enum: the IANA allocated UDP port for VXLAN */ 19989 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 19990 /* enum: the IANA allocated UDP port for Geneve */ 19991 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 19992 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 19993 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 19994 /* tunnel encapsulation protocol (only those named below are supported) */ 19995 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 19996 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 19997 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 19998 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 19999 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 20000 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 20001 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 20002 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 20003 20004 20005 /***********************************/ 20006 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 20007 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 20008 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 20009 * encapsulation PDUs and filter them using the tunnel encapsulation filter 20010 * chain rather than the standard filter chain. Note that this command can 20011 * cause all functions to see a reset. (Available on Medford only.) 20012 */ 20013 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 20014 #undef MC_CMD_0x117_PRIVILEGE_CTG 20015 20016 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20017 20018 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 20019 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 20020 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 20021 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68 20022 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 20023 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4) 20024 /* Flags */ 20025 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 20026 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 20027 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0 20028 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 20029 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 20030 /* The number of entries in the ENTRIES array */ 20031 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 20032 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 20033 /* Entries defining the UDP port to protocol mapping, each laid out as a 20034 * TUNNEL_ENCAP_UDP_PORT_ENTRY 20035 */ 20036 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 20037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 20038 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 20039 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 20040 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 16 20041 20042 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 20043 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 20044 /* Flags */ 20045 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 20046 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 20047 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0 20048 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 20049 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 20050 20051 20052 /***********************************/ 20053 /* MC_CMD_RX_BALANCING 20054 * Configure a port upconverter to distribute the packets on both RX engines. 20055 * Packets are distributed based on a table with the destination vFIFO. The 20056 * index of the table is a hash of source and destination of IPV4 and VLAN 20057 * priority. 20058 */ 20059 #define MC_CMD_RX_BALANCING 0x118 20060 #undef MC_CMD_0x118_PRIVILEGE_CTG 20061 20062 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20063 20064 /* MC_CMD_RX_BALANCING_IN msgrequest */ 20065 #define MC_CMD_RX_BALANCING_IN_LEN 16 20066 /* The RX port whose upconverter table will be modified */ 20067 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 20068 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 20069 /* The VLAN priority associated to the table index and vFIFO */ 20070 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 20071 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 20072 /* The resulting bit of SRC^DST for indexing the table */ 20073 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 20074 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 20075 /* The RX engine to which the vFIFO in the table entry will point to */ 20076 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 20077 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 20078 20079 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 20080 #define MC_CMD_RX_BALANCING_OUT_LEN 0 20081 20082 20083 /***********************************/ 20084 /* MC_CMD_NVRAM_PRIVATE_APPEND 20085 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 20086 * if the tag is already present. 20087 */ 20088 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 20089 #undef MC_CMD_0x11c_PRIVILEGE_CTG 20090 20091 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20092 20093 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 20094 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 20095 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 20096 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX_MCDI2 1020 20097 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 20098 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1) 20099 /* The tag to be appended */ 20100 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 20101 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 20102 /* The length of the data */ 20103 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 20104 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 20105 /* The data to be contained in the TLV structure */ 20106 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 20107 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 20108 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 20109 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 20110 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM_MCDI2 1012 20111 20112 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 20113 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 20114 20115 20116 /***********************************/ 20117 /* MC_CMD_XPM_VERIFY_CONTENTS 20118 * Verify that the contents of the XPM memory is correct (Medford only). This 20119 * is used during manufacture to check that the XPM memory has been programmed 20120 * correctly at ATE. 20121 */ 20122 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 20123 #undef MC_CMD_0x11b_PRIVILEGE_CTG 20124 20125 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 20126 20127 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 20128 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 20129 /* Data type to be checked */ 20130 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 20131 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 20132 20133 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 20134 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 20135 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 20136 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX_MCDI2 1020 20137 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 20138 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1) 20139 /* Number of sectors found (test builds only) */ 20140 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 20141 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 20142 /* Number of bytes found (test builds only) */ 20143 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 20144 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 20145 /* Length of signature */ 20146 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 20147 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 20148 /* Signature */ 20149 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 20150 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 20151 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 20152 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 20153 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM_MCDI2 1008 20154 20155 20156 /***********************************/ 20157 /* MC_CMD_SET_EVQ_TMR 20158 * Update the timer load, timer reload and timer mode values for a given EVQ. 20159 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 20160 * be rounded up to the granularity supported by the hardware, then truncated 20161 * to the range supported by the hardware. The resulting value after the 20162 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 20163 * and TMR_RELOAD_ACT_NS). 20164 */ 20165 #define MC_CMD_SET_EVQ_TMR 0x120 20166 #undef MC_CMD_0x120_PRIVILEGE_CTG 20167 20168 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20169 20170 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 20171 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 20172 /* Function-relative queue instance */ 20173 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 20174 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4 20175 /* Requested value for timer load (in nanoseconds) */ 20176 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 20177 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4 20178 /* Requested value for timer reload (in nanoseconds) */ 20179 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 20180 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4 20181 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 20182 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 20183 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4 20184 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 20185 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 20186 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 20187 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 20188 20189 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 20190 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 20191 /* Actual value for timer load (in nanoseconds) */ 20192 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 20193 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4 20194 /* Actual value for timer reload (in nanoseconds) */ 20195 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 20196 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 20197 20198 20199 /***********************************/ 20200 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 20201 * Query properties about the event queue timers. 20202 */ 20203 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 20204 #undef MC_CMD_0x122_PRIVILEGE_CTG 20205 20206 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20207 20208 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 20209 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 20210 20211 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 20212 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 20213 /* Reserved for future use. */ 20214 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 20215 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4 20216 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 20217 * nanoseconds) for each increment of the timer load/reload count. The 20218 * requested duration of a timer is this value multiplied by the timer 20219 * load/reload count. 20220 */ 20221 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 20222 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4 20223 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 20224 * allowed for timer load/reload counts. 20225 */ 20226 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 20227 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4 20228 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 20229 * multiple of this step size will be rounded in an implementation defined 20230 * manner. 20231 */ 20232 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 20233 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4 20234 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 20235 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 20236 */ 20237 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 20238 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4 20239 /* Timer durations requested via MCDI that are not a multiple of this step size 20240 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 20241 */ 20242 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 20243 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4 20244 /* For timers updated using the bug35388 workaround, this is the time interval 20245 * (in nanoseconds) for each increment of the timer load/reload count. The 20246 * requested duration of a timer is this value multiplied by the timer 20247 * load/reload count. This field is only meaningful if the bug35388 workaround 20248 * is enabled. 20249 */ 20250 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 20251 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4 20252 /* For timers updated using the bug35388 workaround, this is the maximum value 20253 * allowed for timer load/reload counts. This field is only meaningful if the 20254 * bug35388 workaround is enabled. 20255 */ 20256 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 20257 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4 20258 /* For timers updated using the bug35388 workaround, timer load/reload counts 20259 * not a multiple of this step size will be rounded in an implementation 20260 * defined manner. This field is only meaningful if the bug35388 workaround is 20261 * enabled. 20262 */ 20263 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 20264 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 20265 20266 20267 /***********************************/ 20268 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 20269 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 20270 * non used switch buffers. 20271 */ 20272 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 20273 #undef MC_CMD_0x11d_PRIVILEGE_CTG 20274 20275 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20276 20277 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 20278 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 20279 /* Desired instance. Must be set to a specific instance, which is a function 20280 * local queue index. 20281 */ 20282 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 20283 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 20284 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 20285 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 20286 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 20287 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 20288 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 20289 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 20290 /* Number of buffers to reserve for the common pool */ 20291 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 20292 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 20293 /* TX datapath to which the Common Pool is connected to. */ 20294 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 20295 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 20296 /* enum: Extracts information from function */ 20297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 20298 /* Network port or RX Engine to which the common pool connects. */ 20299 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 20300 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 20301 /* enum: Extracts information from function */ 20302 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 20303 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 20304 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 20305 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 20306 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 20307 /* enum: To enable Switch loopback with Rx engine 0 */ 20308 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 20309 /* enum: To enable Switch loopback with Rx engine 1 */ 20310 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 20311 20312 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 20313 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 20314 /* ID of the common pool allocated */ 20315 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 20316 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 20317 20318 20319 /***********************************/ 20320 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 20321 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 20322 * previously allocated common pools. 20323 */ 20324 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 20325 #undef MC_CMD_0x11e_PRIVILEGE_CTG 20326 20327 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20328 20329 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 20330 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 20331 /* Common pool previously allocated to which the new vFIFO will be associated 20332 */ 20333 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 20334 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 20335 /* Port or RX engine to associate the vFIFO egress */ 20336 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 20337 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 20338 /* enum: Extracts information from common pool */ 20339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 20340 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 20341 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 20342 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 20343 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 20344 /* enum: To enable Switch loopback with Rx engine 0 */ 20345 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 20346 /* enum: To enable Switch loopback with Rx engine 1 */ 20347 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 20348 /* Minimum number of buffers that the pool must have */ 20349 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 20350 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 20351 /* enum: Do not check the space available */ 20352 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 20353 /* Will the vFIFO be used as TX_vFIFO_ULL */ 20354 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 20355 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 20356 /* Network priority of the vFIFO,if applicable */ 20357 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 20358 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 20359 /* enum: Search for the lowest unused priority */ 20360 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 20361 20362 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 20363 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 20364 /* Short vFIFO ID */ 20365 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 20366 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 20367 /* Network priority of the vFIFO */ 20368 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 20369 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 20370 20371 20372 /***********************************/ 20373 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 20374 * This interface clears the configuration of the given vFIFO and leaves it 20375 * ready to be re-used. 20376 */ 20377 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 20378 #undef MC_CMD_0x11f_PRIVILEGE_CTG 20379 20380 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20381 20382 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 20383 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 20384 /* Short vFIFO ID */ 20385 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 20386 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 20387 20388 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 20389 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 20390 20391 20392 /***********************************/ 20393 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 20394 * This interface clears the configuration of the given common pool and leaves 20395 * it ready to be re-used. 20396 */ 20397 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 20398 #undef MC_CMD_0x121_PRIVILEGE_CTG 20399 20400 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20401 20402 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 20403 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 20404 /* Common pool ID given when pool allocated */ 20405 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 20406 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 20407 20408 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 20409 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 20410 20411 20412 /***********************************/ 20413 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 20414 * This interface allows the host to find out how many common pool buffers are 20415 * not yet assigned. 20416 */ 20417 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 20418 #undef MC_CMD_0x124_PRIVILEGE_CTG 20419 20420 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20421 20422 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 20423 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 20424 20425 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 20426 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 20427 /* Available buffers for the ENG to NET vFIFOs. */ 20428 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 20429 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 20430 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 20431 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 20432 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 20433 20434 20435 /***********************************/ 20436 /* MC_CMD_SUC_VERSION 20437 * Get the version of the SUC 20438 */ 20439 #define MC_CMD_SUC_VERSION 0x134 20440 #undef MC_CMD_0x134_PRIVILEGE_CTG 20441 20442 #define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20443 20444 /* MC_CMD_SUC_VERSION_IN msgrequest */ 20445 #define MC_CMD_SUC_VERSION_IN_LEN 0 20446 20447 /* MC_CMD_SUC_VERSION_OUT msgresponse */ 20448 #define MC_CMD_SUC_VERSION_OUT_LEN 24 20449 /* The SUC firmware version as four numbers - a.b.c.d */ 20450 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0 20451 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4 20452 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4 20453 /* The date, in seconds since the Unix epoch, when the firmware image was 20454 * built. 20455 */ 20456 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16 20457 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4 20458 /* The ID of the SUC chip. This is specific to the platform but typically 20459 * indicates family, memory sizes etc. See SF-116728-SW for further details. 20460 */ 20461 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20 20462 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4 20463 20464 /* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot 20465 * loader. 20466 */ 20467 #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4 20468 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0 20469 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4 20470 /* enum: Requests the SUC boot version. */ 20471 #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b 20472 20473 /* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */ 20474 #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4 20475 /* The SUC boot version */ 20476 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0 20477 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4 20478 20479 20480 /***********************************/ 20481 /* MC_CMD_GET_RX_PREFIX_ID 20482 * This command is part of the mechanism for configuring the format of the RX 20483 * packet prefix. It takes as input a bitmask of the fields the host would like 20484 * to be in the prefix. If the hardware supports RX prefixes with that 20485 * combination of fields, then this command returns a list of prefix-ids, 20486 * opaque identifiers suitable for use in the RX_PREFIX_ID field of a 20487 * MC_CMD_INIT_RXQ_V5_IN message. If the combination of fields is not 20488 * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids 20489 * due to resource constraints, returns ENOSPC. 20490 */ 20491 #define MC_CMD_GET_RX_PREFIX_ID 0x13b 20492 #undef MC_CMD_0x13b_PRIVILEGE_CTG 20493 20494 #define MC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20495 20496 /* MC_CMD_GET_RX_PREFIX_ID_IN msgrequest */ 20497 #define MC_CMD_GET_RX_PREFIX_ID_IN_LEN 8 20498 /* Field bitmask. */ 20499 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0 20500 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8 20501 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0 20502 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4 20503 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0 20504 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0 20505 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1 20506 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0 20507 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1 20508 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1 20509 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0 20510 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2 20511 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1 20512 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0 20513 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3 20514 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1 20515 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0 20516 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4 20517 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1 20518 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0 20519 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5 20520 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1 20521 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0 20522 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6 20523 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1 20524 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0 20525 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7 20526 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1 20527 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0 20528 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8 20529 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1 20530 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0 20531 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9 20532 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1 20533 20534 /* MC_CMD_GET_RX_PREFIX_ID_OUT msgresponse */ 20535 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMIN 8 20536 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX 252 20537 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020 20538 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num)) 20539 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4) 20540 /* Number of prefix-ids returned */ 20541 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0 20542 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4 20543 /* Opaque prefix identifiers which can be passed into MC_CMD_INIT_RXQ_V5 or 20544 * MC_CMD_QUERY_PREFIX_ID 20545 */ 20546 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4 20547 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4 20548 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1 20549 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM 62 20550 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MAXNUM_MCDI2 254 20551 20552 /* RX_PREFIX_FIELD_INFO structuredef: Information about a single RX prefix 20553 * field 20554 */ 20555 #define RX_PREFIX_FIELD_INFO_LEN 4 20556 /* The offset of the field from the start of the prefix, in bits */ 20557 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0 20558 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LEN 2 20559 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0 20560 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_WIDTH 16 20561 /* The width of the field, in bits */ 20562 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_OFST 2 20563 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1 20564 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LBN 16 20565 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_WIDTH 8 20566 /* The type of the field. These enum values are in the same order as the fields 20567 * in the MC_CMD_GET_RX_PREFIX_ID_IN bitmask 20568 */ 20569 #define RX_PREFIX_FIELD_INFO_TYPE_OFST 3 20570 #define RX_PREFIX_FIELD_INFO_TYPE_LEN 1 20571 #define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */ 20572 #define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */ 20573 #define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */ 20574 #define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */ 20575 #define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */ 20576 #define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */ 20577 #define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */ 20578 #define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */ 20579 #define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */ 20580 #define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */ 20581 #define RX_PREFIX_FIELD_INFO_TYPE_LBN 24 20582 #define RX_PREFIX_FIELD_INFO_TYPE_WIDTH 8 20583 20584 /* RX_PREFIX_FIXED_RESPONSE structuredef: Information about an RX prefix in 20585 * which every field has a fixed offset and width 20586 */ 20587 #define RX_PREFIX_FIXED_RESPONSE_LENMIN 4 20588 #define RX_PREFIX_FIXED_RESPONSE_LENMAX 252 20589 #define RX_PREFIX_FIXED_RESPONSE_LENMAX_MCDI2 1020 20590 #define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num)) 20591 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4) 20592 /* Length of the RX prefix in bytes */ 20593 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0 20594 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1 20595 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0 20596 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_WIDTH 8 20597 /* Number of fields present in the prefix */ 20598 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1 20599 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1 20600 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LBN 8 20601 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_WIDTH 8 20602 #define RX_PREFIX_FIXED_RESPONSE_RESERVED_OFST 2 20603 #define RX_PREFIX_FIXED_RESPONSE_RESERVED_LEN 2 20604 #define RX_PREFIX_FIXED_RESPONSE_RESERVED_LBN 16 20605 #define RX_PREFIX_FIXED_RESPONSE_RESERVED_WIDTH 16 20606 /* Array of RX_PREFIX_FIELD_INFO structures, of length FIELD_COUNT */ 20607 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4 20608 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4 20609 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0 20610 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM 62 20611 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MAXNUM_MCDI2 254 20612 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LBN 32 20613 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_WIDTH 32 20614 20615 20616 /***********************************/ 20617 /* MC_CMD_QUERY_RX_PREFIX_ID 20618 * This command takes an RX prefix id (obtained from MC_CMD_GET_RX_PREFIX_ID) 20619 * and returns a description of the RX prefix of packets delievered to an RXQ 20620 * created with that prefix id 20621 */ 20622 #define MC_CMD_QUERY_RX_PREFIX_ID 0x13c 20623 #undef MC_CMD_0x13c_PRIVILEGE_CTG 20624 20625 #define MC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20626 20627 /* MC_CMD_QUERY_RX_PREFIX_ID_IN msgrequest */ 20628 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4 20629 /* Prefix id to query */ 20630 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0 20631 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4 20632 20633 /* MC_CMD_QUERY_RX_PREFIX_ID_OUT msgresponse */ 20634 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4 20635 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX 252 20636 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMAX_MCDI2 1020 20637 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num)) 20638 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1) 20639 /* An enum describing the structure of this response. */ 20640 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0 20641 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1 20642 /* enum: The response is of format RX_PREFIX_FIXED_RESPONSE */ 20643 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0 20644 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1 20645 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_LEN 3 20646 /* The response. Its format is as defined by the RESPONSE_TYPE value */ 20647 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4 20648 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1 20649 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0 20650 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM 248 20651 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MAXNUM_MCDI2 1016 20652 20653 20654 /***********************************/ 20655 /* MC_CMD_BUNDLE 20656 * A command to perform various bundle-related operations on insecure cards. 20657 */ 20658 #define MC_CMD_BUNDLE 0x13d 20659 #undef MC_CMD_0x13d_PRIVILEGE_CTG 20660 20661 #define MC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE 20662 20663 /* MC_CMD_BUNDLE_IN msgrequest */ 20664 #define MC_CMD_BUNDLE_IN_LEN 4 20665 /* Sub-command code */ 20666 #define MC_CMD_BUNDLE_IN_OP_OFST 0 20667 #define MC_CMD_BUNDLE_IN_OP_LEN 4 20668 /* enum: Get the current host access mode set on component partitions. */ 20669 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0 20670 /* enum: Set the host access mode set on component partitions. */ 20671 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1 20672 20673 /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN msgrequest: Retrieve the current 20674 * access mode on component partitions such as MC_FIRMWARE, SUC_FIRMWARE and 20675 * EXPANSION_UEFI. This command only works on engineering (insecure) cards. On 20676 * secure adapters, this command returns MC_CMD_ERR_EPERM. 20677 */ 20678 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4 20679 /* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */ 20680 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0 20681 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4 20682 20683 /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT msgresponse: Returns the access 20684 * control mode. 20685 */ 20686 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4 20687 /* Access mode of component partitions. */ 20688 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0 20689 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4 20690 /* enum: Component partitions are read-only from the host. */ 20691 #define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0 20692 /* enum: Component partitions can read read-from written-to by the host. */ 20693 #define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1 20694 20695 /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN msgrequest: The component 20696 * partitions such as MC_FIRMWARE, SUC_FIRMWARE, EXPANSION_UEFI are set as 20697 * read-only on firmware built with bundle support. This command marks these 20698 * partitions as read/writeable. The access status set by this command does not 20699 * persist across MC reboots. This command only works on engineering (insecure) 20700 * cards. On secure adapters, this command returns MC_CMD_ERR_EPERM. 20701 */ 20702 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_LEN 8 20703 /* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */ 20704 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0 20705 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4 20706 /* Access mode of component partitions. */ 20707 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4 20708 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4 20709 /* Enum values, see field(s): */ 20710 /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT/ACCESS_MODE */ 20711 20712 /* MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT msgresponse */ 20713 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0 20714 20715 20716 /***********************************/ 20717 /* MC_CMD_GET_VPD 20718 * Read all VPD starting from a given address 20719 */ 20720 #define MC_CMD_GET_VPD 0x165 20721 #undef MC_CMD_0x165_PRIVILEGE_CTG 20722 20723 #define MC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20724 20725 /* MC_CMD_GET_VPD_IN msgresponse */ 20726 #define MC_CMD_GET_VPD_IN_LEN 4 20727 /* VPD address to start from. In case VPD is longer than MCDI buffer 20728 * (unlikely), user can make multiple calls with different starting addresses. 20729 */ 20730 #define MC_CMD_GET_VPD_IN_ADDR_OFST 0 20731 #define MC_CMD_GET_VPD_IN_ADDR_LEN 4 20732 20733 /* MC_CMD_GET_VPD_OUT msgresponse */ 20734 #define MC_CMD_GET_VPD_OUT_LENMIN 0 20735 #define MC_CMD_GET_VPD_OUT_LENMAX 252 20736 #define MC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020 20737 #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num)) 20738 #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1) 20739 /* VPD data returned. */ 20740 #define MC_CMD_GET_VPD_OUT_DATA_OFST 0 20741 #define MC_CMD_GET_VPD_OUT_DATA_LEN 1 20742 #define MC_CMD_GET_VPD_OUT_DATA_MINNUM 0 20743 #define MC_CMD_GET_VPD_OUT_DATA_MAXNUM 252 20744 #define MC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1020 20745 20746 20747 /***********************************/ 20748 /* MC_CMD_GET_NCSI_INFO 20749 * Provide information about the NC-SI stack 20750 */ 20751 #define MC_CMD_GET_NCSI_INFO 0x167 20752 #undef MC_CMD_0x167_PRIVILEGE_CTG 20753 20754 #define MC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20755 20756 /* MC_CMD_GET_NCSI_INFO_IN msgrequest */ 20757 #define MC_CMD_GET_NCSI_INFO_IN_LEN 8 20758 /* Operation to be performed */ 20759 #define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0 20760 #define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4 20761 /* enum: Information on the link settings. */ 20762 #define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0 20763 /* enum: Statistics associated with the channel */ 20764 #define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1 20765 /* The NC-SI channel on which the operation is to be performed */ 20766 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4 20767 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4 20768 20769 /* MC_CMD_GET_NCSI_INFO_LINK_OUT msgresponse */ 20770 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_LEN 12 20771 /* Settings as received from BMC. */ 20772 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0 20773 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4 20774 /* Advertised capabilities applied to channel. */ 20775 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4 20776 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4 20777 /* General status */ 20778 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8 20779 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4 20780 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_OFST 8 20781 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0 20782 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2 20783 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_OFST 8 20784 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2 20785 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1 20786 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_OFST 8 20787 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3 20788 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1 20789 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_OFST 8 20790 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4 20791 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1 20792 20793 /* MC_CMD_GET_NCSI_INFO_STATISTICS_OUT msgresponse */ 20794 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_LEN 28 20795 /* The number of NC-SI commands received. */ 20796 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0 20797 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4 20798 /* The number of NC-SI commands dropped. */ 20799 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4 20800 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4 20801 /* The number of invalid NC-SI commands received. */ 20802 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_OFST 8 20803 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4 20804 /* The number of checksum errors seen. */ 20805 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_OFST 12 20806 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4 20807 /* The number of NC-SI requests received. */ 20808 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_OFST 16 20809 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4 20810 /* The number of NC-SI responses sent (includes AENs) */ 20811 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_OFST 20 20812 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4 20813 /* The number of NC-SI AENs sent */ 20814 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24 20815 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4 20816 20817 20818 /* CLOCK_INFO structuredef: Information about a single hardware clock */ 20819 #define CLOCK_INFO_LEN 28 20820 /* Enumeration that uniquely identifies the clock */ 20821 #define CLOCK_INFO_CLOCK_ID_OFST 0 20822 #define CLOCK_INFO_CLOCK_ID_LEN 2 20823 /* enum: The Riverhead CMC (card MC) */ 20824 #define CLOCK_INFO_CLOCK_CMC 0x0 20825 /* enum: The Riverhead NMC (network MC) */ 20826 #define CLOCK_INFO_CLOCK_NMC 0x1 20827 /* enum: The Riverhead SDNET slice main logic */ 20828 #define CLOCK_INFO_CLOCK_SDNET 0x2 20829 /* enum: The Riverhead SDNET LUT */ 20830 #define CLOCK_INFO_CLOCK_SDNET_LUT 0x3 20831 /* enum: The Riverhead SDNET control logic */ 20832 #define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4 20833 /* enum: The Riverhead Streaming SubSystem */ 20834 #define CLOCK_INFO_CLOCK_SSS 0x5 20835 /* enum: The Riverhead network MAC and associated CSR registers */ 20836 #define CLOCK_INFO_CLOCK_MAC 0x6 20837 #define CLOCK_INFO_CLOCK_ID_LBN 0 20838 #define CLOCK_INFO_CLOCK_ID_WIDTH 16 20839 /* Assorted flags */ 20840 #define CLOCK_INFO_FLAGS_OFST 2 20841 #define CLOCK_INFO_FLAGS_LEN 2 20842 #define CLOCK_INFO_SETTABLE_OFST 2 20843 #define CLOCK_INFO_SETTABLE_LBN 0 20844 #define CLOCK_INFO_SETTABLE_WIDTH 1 20845 #define CLOCK_INFO_FLAGS_LBN 16 20846 #define CLOCK_INFO_FLAGS_WIDTH 16 20847 /* The frequency in HZ */ 20848 #define CLOCK_INFO_FREQUENCY_OFST 4 20849 #define CLOCK_INFO_FREQUENCY_LEN 8 20850 #define CLOCK_INFO_FREQUENCY_LO_OFST 4 20851 #define CLOCK_INFO_FREQUENCY_HI_OFST 8 20852 #define CLOCK_INFO_FREQUENCY_LBN 32 20853 #define CLOCK_INFO_FREQUENCY_WIDTH 64 20854 /* Human-readable ASCII name for clock, with NUL termination */ 20855 #define CLOCK_INFO_NAME_OFST 12 20856 #define CLOCK_INFO_NAME_LEN 1 20857 #define CLOCK_INFO_NAME_NUM 16 20858 #define CLOCK_INFO_NAME_LBN 96 20859 #define CLOCK_INFO_NAME_WIDTH 8 20860 20861 20862 /***********************************/ 20863 /* MC_CMD_GET_CLOCKS_INFO 20864 * Get information about the device clocks 20865 */ 20866 #define MC_CMD_GET_CLOCKS_INFO 0x166 20867 #undef MC_CMD_0x166_PRIVILEGE_CTG 20868 20869 #define MC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20870 20871 /* MC_CMD_GET_CLOCKS_INFO_IN msgrequest */ 20872 #define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0 20873 20874 /* MC_CMD_GET_CLOCKS_INFO_OUT msgresponse */ 20875 #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0 20876 #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX 252 20877 #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMAX_MCDI2 1008 20878 #define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num)) 20879 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28) 20880 /* An array of CLOCK_INFO structures. */ 20881 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0 20882 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_LEN 28 20883 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0 20884 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9 20885 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36 20886 20887 20888 /***********************************/ 20889 /* MC_CMD_VNIC_ENCAP_RULE_ADD 20890 * Add a rule for detecting encapsulations in the VNIC stage. Currently this only affects checksum validation in VNIC RX - on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. only apply to the current driver. If a rule matches, then the packet is considered to have the corresponding encapsulation type, and the inner packet is parsed. It is up to the driver to ensure that overlapping rules are not inserted. (If a packet would match multiple rules, a random one of them will be used.) A rule with the exact same match criteria may not be inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are supported, use MC_CMD_GET_PARSER_DISP_INFO with OP OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported combinations. Each driver may only have a limited set of active rules - returns ENOSPC if the caller's table is full. 20891 */ 20892 #define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d 20893 #undef MC_CMD_0x16d_PRIVILEGE_CTG 20894 20895 #define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20896 20897 /* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */ 20898 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36 20899 /* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */ 20900 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0 20901 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4 20902 /* Any non-zero bits other than the ones named below or an unsupported 20903 * combination will cause the NIC to return EOPNOTSUPP. In the future more 20904 * flags may be added. 20905 */ 20906 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4 20907 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4 20908 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4 20909 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0 20910 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1 20911 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4 20912 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1 20913 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1 20914 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4 20915 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2 20916 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1 20917 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4 20918 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3 20919 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1 20920 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4 20921 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4 20922 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1 20923 /* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order. 20924 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used. 20925 */ 20926 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8 20927 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2 20928 /* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order. 20929 * (Deprecated) 20930 */ 20931 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80 20932 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12 20933 /* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */ 20934 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10 20935 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2 20936 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10 20937 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0 20938 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12 20939 /* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the 20940 * case of IPv4, the IP should be in the first 4 bytes and all other bytes 20941 * should be zero. 20942 */ 20943 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12 20944 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16 20945 /* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */ 20946 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28 20947 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1 20948 /* Actions that should be applied to packets match the rule. */ 20949 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29 20950 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1 20951 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29 20952 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0 20953 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1 20954 /* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */ 20955 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30 20956 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2 20957 /* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */ 20958 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32 20959 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4 20960 20961 /* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */ 20962 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4 20963 /* Handle to inserted rule. Used for removing the rule. */ 20964 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0 20965 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4 20966 20967 20968 /***********************************/ 20969 /* MC_CMD_VNIC_ENCAP_RULE_REMOVE 20970 * Remove a VNIC encapsulation rule. Packets which would have previously matched the rule will then be considered as unencapsulated. Returns EALREADY if the input HANDLE doesn't correspond to an existing rule. 20971 */ 20972 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e 20973 #undef MC_CMD_0x16e_PRIVILEGE_CTG 20974 20975 #define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 20976 20977 /* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */ 20978 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4 20979 /* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */ 20980 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0 20981 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4 20982 20983 /* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */ 20984 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0 20985 20986 /* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are 20987 * defined in SF-120734-TC with more information in SF-122717-TC. 20988 */ 20989 #define FUNCTION_PERSONALITY_LEN 4 20990 #define FUNCTION_PERSONALITY_ID_OFST 0 20991 #define FUNCTION_PERSONALITY_ID_LEN 4 20992 /* enum: Function has no assigned personality */ 20993 #define FUNCTION_PERSONALITY_NULL 0x0 20994 /* enum: Function has an EF100-style function control window and VI windows 20995 * with both EF100 and vDPA doorbells. 20996 */ 20997 #define FUNCTION_PERSONALITY_EF100 0x1 20998 /* enum: Function has virtio net device configuration registers and doorbells 20999 * for virtio queue pairs. 21000 */ 21001 #define FUNCTION_PERSONALITY_VIRTIO_NET 0x2 21002 /* enum: Function has virtio block device configuration registers and a 21003 * doorbell for a single virtqueue. 21004 */ 21005 #define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3 21006 /* enum: Function is a Xilinx acceleration device - management function */ 21007 #define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4 21008 /* enum: Function is a Xilinx acceleration device - user function */ 21009 #define FUNCTION_PERSONALITY_ACCEL_USR 0x5 21010 #define FUNCTION_PERSONALITY_ID_LBN 0 21011 #define FUNCTION_PERSONALITY_ID_WIDTH 32 21012 21013 21014 /***********************************/ 21015 /* MC_CMD_VIRTIO_GET_FEATURES 21016 * Get a list of the virtio features supported by the device. 21017 */ 21018 #define MC_CMD_VIRTIO_GET_FEATURES 0x168 21019 #undef MC_CMD_0x168_PRIVILEGE_CTG 21020 21021 #define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21022 21023 /* MC_CMD_VIRTIO_GET_FEATURES_IN msgrequest */ 21024 #define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4 21025 /* Type of device to get features for. Matches the device id as defined by the 21026 * virtio spec. 21027 */ 21028 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0 21029 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4 21030 /* enum: Reserved. Do not use. */ 21031 #define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0 21032 /* enum: Net device. */ 21033 #define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1 21034 /* enum: Block device. */ 21035 #define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2 21036 21037 /* MC_CMD_VIRTIO_GET_FEATURES_OUT msgresponse */ 21038 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_LEN 8 21039 /* Features supported by the device. The result is a bitfield in the format of 21040 * the feature bits of the specified device type as defined in the virtIO 1.1 21041 * specification ( https://docs.oasis- 21042 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf ) 21043 */ 21044 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0 21045 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8 21046 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0 21047 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4 21048 21049 21050 /***********************************/ 21051 /* MC_CMD_VIRTIO_TEST_FEATURES 21052 * Query whether a given set of features is supported. Fails with ENOSUP if the 21053 * driver requests a feature the device doesn't support. Fails with EINVAL if 21054 * the driver fails to request a feature which the device requires. 21055 */ 21056 #define MC_CMD_VIRTIO_TEST_FEATURES 0x169 21057 #undef MC_CMD_0x169_PRIVILEGE_CTG 21058 21059 #define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21060 21061 /* MC_CMD_VIRTIO_TEST_FEATURES_IN msgrequest */ 21062 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_LEN 16 21063 /* Type of device to test features for. Matches the device id as defined by the 21064 * virtio spec. 21065 */ 21066 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0 21067 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4 21068 /* Enum values, see field(s): */ 21069 /* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */ 21070 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4 21071 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4 21072 /* Features requested. Same format as the returned value from 21073 * MC_CMD_VIRTIO_GET_FEATURES. 21074 */ 21075 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8 21076 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8 21077 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8 21078 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12 21079 21080 /* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */ 21081 #define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0 21082 21083 21084 /***********************************/ 21085 /* MC_CMD_VIRTIO_INIT_QUEUE 21086 * Create a virtio virtqueue. Fails with EALREADY if the queue already exists. 21087 * Fails with ENOSUP if a feature is requested that isn't supported. Fails with 21088 * EINVAL if a required feature isn't requested, or any other parameter is 21089 * invalid. 21090 */ 21091 #define MC_CMD_VIRTIO_INIT_QUEUE 0x16a 21092 #undef MC_CMD_0x16a_PRIVILEGE_CTG 21093 21094 #define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21095 21096 /* MC_CMD_VIRTIO_INIT_QUEUE_REQ msgrequest */ 21097 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_LEN 68 21098 /* Type of virtqueue to create. A network rxq and a txq can exist at the same 21099 * time on a single VI. 21100 */ 21101 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0 21102 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1 21103 /* enum: A network device receive queue */ 21104 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0 21105 /* enum: A network device transmit queue */ 21106 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1 21107 /* enum: A block device request queue */ 21108 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2 21109 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1 21110 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1 21111 /* If the calling function is a PF and this field is not VF_NULL, create the 21112 * queue on the specified child VF instead of on the PF. 21113 */ 21114 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_OFST 2 21115 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_LEN 2 21116 /* enum: No VF, create queue on the PF. */ 21117 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff 21118 /* Desired instance. This is the function-local index of the associated VI, not 21119 * the virtqueue number as counted by the virtqueue spec. 21120 */ 21121 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4 21122 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4 21123 /* Queue size, in entries. Must be a power of two. */ 21124 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_OFST 8 21125 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4 21126 /* Flags */ 21127 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_OFST 12 21128 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4 21129 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_OFST 12 21130 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0 21131 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1 21132 /* Address of the descriptor table in the virtqueue. */ 21133 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16 21134 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8 21135 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16 21136 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20 21137 /* Address of the available ring in the virtqueue. */ 21138 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24 21139 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8 21140 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24 21141 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28 21142 /* Address of the used ring in the virtqueue. */ 21143 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32 21144 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8 21145 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32 21146 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36 21147 /* PASID to use on PCIe transactions involving this queue. Ignored if the 21148 * USE_PASID flag is not set. 21149 */ 21150 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_OFST 40 21151 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4 21152 /* Which MSIX vector to use for this virtqueue, or NO_VECTOR if MSIX should not 21153 * be used. 21154 */ 21155 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_OFST 44 21156 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_LEN 2 21157 /* enum: Do not enable interrupts for this virtqueue */ 21158 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff 21159 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_OFST 46 21160 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_LEN 2 21161 /* Virtio features to apply to this queue. Same format as the in the virtio 21162 * spec and in the return from MC_CMD_VIRTIO_GET_FEATURES. Must be a subset of 21163 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per- 21164 * queue because with vDPA multiple queues on the same function can be passed 21165 * through to different virtual hosts as independent devices. 21166 */ 21167 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48 21168 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8 21169 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48 21170 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52 21171 /* Enum values, see field(s): */ 21172 /* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */ 21173 /* The inital producer index for this queue's used ring. If this queue is being 21174 * created to be migrated into, this should be the FINAL_PIDX value returned by 21175 * MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from. Otherwise, it 21176 * should be zero. 21177 */ 21178 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_OFST 56 21179 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4 21180 /* The inital consumer index for this queue's available ring. If this queue is 21181 * being created to be migrated into, this should be the FINAL_CIDX value 21182 * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from. 21183 * Otherwise, it should be zero. 21184 */ 21185 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_OFST 60 21186 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4 21187 /* A MAE_MPORT_SELECTOR defining which mport this queue should be associated 21188 * with. Use MAE_MPORT_SELECTOR_ASSIGNED to request the default mport for the 21189 * function this queue is being created on. 21190 */ 21191 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_OFST 64 21192 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4 21193 21194 /* MC_CMD_VIRTIO_INIT_QUEUE_RESP msgresponse */ 21195 #define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0 21196 21197 21198 /***********************************/ 21199 /* MC_CMD_VIRTIO_FINI_QUEUE 21200 * Destroy a virtio virtqueue 21201 */ 21202 #define MC_CMD_VIRTIO_FINI_QUEUE 0x16b 21203 #undef MC_CMD_0x16b_PRIVILEGE_CTG 21204 21205 #define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21206 21207 /* MC_CMD_VIRTIO_FINI_QUEUE_REQ msgrequest */ 21208 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_LEN 8 21209 /* Type of virtqueue to destroy. */ 21210 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0 21211 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1 21212 /* Enum values, see field(s): */ 21213 /* MC_CMD_VIRTIO_INIT_QUEUE/MC_CMD_VIRTIO_INIT_QUEUE_REQ/QUEUE_TYPE */ 21214 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1 21215 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1 21216 /* If the calling function is a PF and this field is not VF_NULL, destroy the 21217 * queue on the specified child VF instead of on the PF. 21218 */ 21219 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_OFST 2 21220 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_LEN 2 21221 /* enum: No VF, destroy the queue on the PF. */ 21222 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff 21223 /* Instance to destroy */ 21224 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4 21225 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4 21226 21227 /* MC_CMD_VIRTIO_FINI_QUEUE_RESP msgresponse */ 21228 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_LEN 8 21229 /* The producer index of the used ring when the queue was stopped. */ 21230 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0 21231 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4 21232 /* The consumer index of the available ring when the queue was stopped. */ 21233 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4 21234 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4 21235 21236 21237 /***********************************/ 21238 /* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 21239 * Get the offset in the BAR of the doorbells for a VI. Doesn't require the 21240 * queue(s) to be allocated. 21241 */ 21242 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c 21243 #undef MC_CMD_0x16c_PRIVILEGE_CTG 21244 21245 #define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 21246 21247 /* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ msgrequest */ 21248 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_LEN 8 21249 /* Type of device to get information for. Matches the device id as defined by 21250 * the virtio spec. 21251 */ 21252 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0 21253 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1 21254 /* Enum values, see field(s): */ 21255 /* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */ 21256 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1 21257 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1 21258 /* If the calling function is a PF and this field is not VF_NULL, query the VI 21259 * on the specified child VF instead of on the PF. 21260 */ 21261 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_OFST 2 21262 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_LEN 2 21263 /* enum: No VF, query the PF. */ 21264 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff 21265 /* VI instance to query */ 21266 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4 21267 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4 21268 21269 /* MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP msgresponse */ 21270 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_LEN 8 21271 /* Offset of RX doorbell in BAR */ 21272 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0 21273 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4 21274 /* Offset of TX doorbell in BAR */ 21275 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4 21276 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4 21277 21278 /* MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP msgresponse */ 21279 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4 21280 /* Offset of request doorbell in BAR */ 21281 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0 21282 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4 21283 21284 /* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID 21285 * (interface/PF/VF tuple) 21286 */ 21287 #define PCIE_FUNCTION_LEN 8 21288 /* PCIe PF function number */ 21289 #define PCIE_FUNCTION_PF_OFST 0 21290 #define PCIE_FUNCTION_PF_LEN 2 21291 /* enum: Wildcard value representing any available function (e.g in resource 21292 * allocation requests) 21293 */ 21294 #define PCIE_FUNCTION_PF_ANY 0xfffe 21295 /* enum: Value representing invalid (null) function */ 21296 #define PCIE_FUNCTION_PF_NULL 0xffff 21297 #define PCIE_FUNCTION_PF_LBN 0 21298 #define PCIE_FUNCTION_PF_WIDTH 16 21299 /* PCIe VF Function number (PF relative) */ 21300 #define PCIE_FUNCTION_VF_OFST 2 21301 #define PCIE_FUNCTION_VF_LEN 2 21302 /* enum: Wildcard value representing any available function (e.g in resource 21303 * allocation requests) 21304 */ 21305 #define PCIE_FUNCTION_VF_ANY 0xfffe 21306 /* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF == 21307 * PF_NULL) 21308 */ 21309 #define PCIE_FUNCTION_VF_NULL 0xffff 21310 #define PCIE_FUNCTION_VF_LBN 16 21311 #define PCIE_FUNCTION_VF_WIDTH 16 21312 /* PCIe interface of the function */ 21313 #define PCIE_FUNCTION_INTF_OFST 4 21314 #define PCIE_FUNCTION_INTF_LEN 4 21315 /* enum: Host PCIe interface */ 21316 #define PCIE_FUNCTION_INTF_HOST 0x0 21317 /* enum: Application Processor interface */ 21318 #define PCIE_FUNCTION_INTF_AP 0x1 21319 #define PCIE_FUNCTION_INTF_LBN 32 21320 #define PCIE_FUNCTION_INTF_WIDTH 32 21321 21322 21323 /***********************************/ 21324 /* MC_CMD_DESC_PROXY_FUNC_CREATE 21325 * Descriptor proxy functions are abstract devices that forward all request 21326 * submitted to the host PCIe function (descriptors submitted to Virtio or 21327 * EF100 queues) to be handled on another function (most commonly on the 21328 * embedded Application Processor), via EF100 descriptor proxy, memory-to- 21329 * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk 21330 * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy 21331 * function on the host and assigns a user-defined label. The actual function 21332 * configuration is not persisted until the caller configures it with 21333 * MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN and commits with 21334 * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN. 21335 */ 21336 #define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172 21337 #undef MC_CMD_0x172_PRIVILEGE_CTG 21338 21339 #define MC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21340 21341 /* MC_CMD_DESC_PROXY_FUNC_CREATE_IN msgrequest */ 21342 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LEN 52 21343 /* PCIe Function ID to allocate (as struct PCIE_FUNCTION). Set to 21344 * {PF_ANY,VF_ANY,interface} for "any available function" Set to 21345 * {PF_ANY,VF_NULL,interface} for "any available PF" 21346 */ 21347 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0 21348 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8 21349 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0 21350 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4 21351 /* The personality to set. The meanings of the personalities are defined in 21352 * SF-120734-TC with more information in SF-122717-TC. At present, we only 21353 * support proxying for VIRTIO_BLK 21354 */ 21355 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_OFST 8 21356 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4 21357 /* Enum values, see field(s): */ 21358 /* FUNCTION_PERSONALITY/ID */ 21359 /* User-defined label (zero-terminated ASCII string) to uniquely identify the 21360 * function 21361 */ 21362 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_OFST 12 21363 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_LEN 40 21364 21365 /* MC_CMD_DESC_PROXY_FUNC_CREATE_OUT msgresponse */ 21366 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_LEN 12 21367 /* Handle to the descriptor proxy function */ 21368 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0 21369 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4 21370 /* Allocated function ID (as struct PCIE_FUNCTION) */ 21371 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4 21372 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8 21373 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4 21374 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8 21375 21376 21377 /***********************************/ 21378 /* MC_CMD_DESC_PROXY_FUNC_DESTROY 21379 * Remove an existing descriptor proxy function. Underlying function 21380 * personality and configuration reverts back to factory default. Function 21381 * configuration is committed immediately to specified store and any function 21382 * ownership is released. 21383 */ 21384 #define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173 21385 #undef MC_CMD_0x173_PRIVILEGE_CTG 21386 21387 #define MC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21388 21389 /* MC_CMD_DESC_PROXY_FUNC_DESTROY_IN msgrequest */ 21390 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LEN 44 21391 /* User-defined label (zero-terminated ASCII string) to uniquely identify the 21392 * function 21393 */ 21394 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0 21395 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_LEN 40 21396 /* Store from which to remove function configuration */ 21397 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_OFST 40 21398 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4 21399 /* Enum values, see field(s): */ 21400 /* MC_CMD_DESC_PROXY_FUNC_COMMIT/MC_CMD_DESC_PROXY_FUNC_COMMIT_IN/STORE */ 21401 21402 /* MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT msgresponse */ 21403 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0 21404 21405 /* VIRTIO_BLK_CONFIG structuredef: Virtio block device configuration. See 21406 * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature 21407 * bits. See Virtio specification v1.1, Section 5.2.4 (struct 21408 * virtio_blk_config) for definition of remaining configuration fields 21409 */ 21410 #define VIRTIO_BLK_CONFIG_LEN 68 21411 /* Virtio block device features to advertise, per Virtio 1.1, 5.2.3 and 6 */ 21412 #define VIRTIO_BLK_CONFIG_FEATURES_OFST 0 21413 #define VIRTIO_BLK_CONFIG_FEATURES_LEN 8 21414 #define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0 21415 #define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4 21416 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0 21417 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0 21418 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1 21419 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0 21420 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1 21421 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1 21422 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0 21423 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_LBN 2 21424 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1 21425 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0 21426 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4 21427 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1 21428 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0 21429 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_LBN 5 21430 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1 21431 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0 21432 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_LBN 6 21433 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1 21434 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0 21435 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_LBN 7 21436 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1 21437 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0 21438 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_LBN 9 21439 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1 21440 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0 21441 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_LBN 10 21442 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1 21443 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0 21444 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_LBN 11 21445 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1 21446 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0 21447 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_LBN 12 21448 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1 21449 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0 21450 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_LBN 13 21451 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1 21452 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0 21453 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_LBN 14 21454 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1 21455 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0 21456 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_LBN 28 21457 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1 21458 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0 21459 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_LBN 29 21460 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1 21461 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0 21462 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_LBN 32 21463 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1 21464 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0 21465 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_LBN 33 21466 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1 21467 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0 21468 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_LBN 34 21469 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1 21470 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0 21471 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_LBN 35 21472 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1 21473 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0 21474 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_LBN 36 21475 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1 21476 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0 21477 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_LBN 37 21478 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1 21479 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0 21480 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_LBN 38 21481 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1 21482 #define VIRTIO_BLK_CONFIG_FEATURES_LBN 0 21483 #define VIRTIO_BLK_CONFIG_FEATURES_WIDTH 64 21484 /* The capacity of the device (expressed in 512-byte sectors) */ 21485 #define VIRTIO_BLK_CONFIG_CAPACITY_OFST 8 21486 #define VIRTIO_BLK_CONFIG_CAPACITY_LEN 8 21487 #define VIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8 21488 #define VIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12 21489 #define VIRTIO_BLK_CONFIG_CAPACITY_LBN 64 21490 #define VIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64 21491 /* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is 21492 * set. 21493 */ 21494 #define VIRTIO_BLK_CONFIG_SIZE_MAX_OFST 16 21495 #define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4 21496 #define VIRTIO_BLK_CONFIG_SIZE_MAX_LBN 128 21497 #define VIRTIO_BLK_CONFIG_SIZE_MAX_WIDTH 32 21498 /* Maximum number of segments in a request. Only valid when 21499 * VIRTIO_BLK_F_SEG_MAX is set. 21500 */ 21501 #define VIRTIO_BLK_CONFIG_SEG_MAX_OFST 20 21502 #define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4 21503 #define VIRTIO_BLK_CONFIG_SEG_MAX_LBN 160 21504 #define VIRTIO_BLK_CONFIG_SEG_MAX_WIDTH 32 21505 /* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is 21506 * set. 21507 */ 21508 #define VIRTIO_BLK_CONFIG_CYLINDERS_OFST 24 21509 #define VIRTIO_BLK_CONFIG_CYLINDERS_LEN 2 21510 #define VIRTIO_BLK_CONFIG_CYLINDERS_LBN 192 21511 #define VIRTIO_BLK_CONFIG_CYLINDERS_WIDTH 16 21512 /* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set. 21513 */ 21514 #define VIRTIO_BLK_CONFIG_HEADS_OFST 26 21515 #define VIRTIO_BLK_CONFIG_HEADS_LEN 1 21516 #define VIRTIO_BLK_CONFIG_HEADS_LBN 208 21517 #define VIRTIO_BLK_CONFIG_HEADS_WIDTH 8 21518 /* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set. 21519 */ 21520 #define VIRTIO_BLK_CONFIG_SECTORS_OFST 27 21521 #define VIRTIO_BLK_CONFIG_SECTORS_LEN 1 21522 #define VIRTIO_BLK_CONFIG_SECTORS_LBN 216 21523 #define VIRTIO_BLK_CONFIG_SECTORS_WIDTH 8 21524 /* Block size of disk. Only valid when VIRTIO_BLK_F_BLK_SIZE is set. */ 21525 #define VIRTIO_BLK_CONFIG_BLK_SIZE_OFST 28 21526 #define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4 21527 #define VIRTIO_BLK_CONFIG_BLK_SIZE_LBN 224 21528 #define VIRTIO_BLK_CONFIG_BLK_SIZE_WIDTH 32 21529 /* Block topology - number of logical blocks per physical block (log2). Only 21530 * valid when VIRTIO_BLK_F_TOPOLOGY is set. 21531 */ 21532 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_OFST 32 21533 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1 21534 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LBN 256 21535 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_WIDTH 8 21536 /* Block topology - offset of first aligned logical block. Only valid when 21537 * VIRTIO_BLK_F_TOPOLOGY is set. 21538 */ 21539 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_OFST 33 21540 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1 21541 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LBN 264 21542 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_WIDTH 8 21543 /* Block topology - suggested minimum I/O size in blocks. Only valid when 21544 * VIRTIO_BLK_F_TOPOLOGY is set. 21545 */ 21546 #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_OFST 34 21547 #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LEN 2 21548 #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_LBN 272 21549 #define VIRTIO_BLK_CONFIG_MIN_IO_SIZE_WIDTH 16 21550 /* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid 21551 * when VIRTIO_BLK_F_TOPOLOGY is set. 21552 */ 21553 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_OFST 36 21554 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4 21555 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LBN 288 21556 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_WIDTH 32 21557 /* Unused, set to zero. Note that virtio_blk_config.writeback is volatile and 21558 * not carried in config data. 21559 */ 21560 #define VIRTIO_BLK_CONFIG_UNUSED0_OFST 40 21561 #define VIRTIO_BLK_CONFIG_UNUSED0_LEN 2 21562 #define VIRTIO_BLK_CONFIG_UNUSED0_LBN 320 21563 #define VIRTIO_BLK_CONFIG_UNUSED0_WIDTH 16 21564 /* Number of queues. Only valid if the VIRTIO_BLK_F_MQ feature is negotiated. 21565 */ 21566 #define VIRTIO_BLK_CONFIG_NUM_QUEUES_OFST 42 21567 #define VIRTIO_BLK_CONFIG_NUM_QUEUES_LEN 2 21568 #define VIRTIO_BLK_CONFIG_NUM_QUEUES_LBN 336 21569 #define VIRTIO_BLK_CONFIG_NUM_QUEUES_WIDTH 16 21570 /* Maximum discard sectors size, in 512-byte units. Only valid if 21571 * VIRTIO_BLK_F_DISCARD is set. 21572 */ 21573 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_OFST 44 21574 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4 21575 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LBN 352 21576 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_WIDTH 32 21577 /* Maximum discard segment number. Only valid if VIRTIO_BLK_F_DISCARD is set. 21578 */ 21579 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_OFST 48 21580 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4 21581 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LBN 384 21582 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_WIDTH 32 21583 /* Discard sector alignment, in 512-byte units. Only valid if 21584 * VIRTIO_BLK_F_DISCARD is set. 21585 */ 21586 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_OFST 52 21587 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4 21588 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LBN 416 21589 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_WIDTH 32 21590 /* Maximum write zeroes sectors size, in 512-byte units. Only valid if 21591 * VIRTIO_BLK_F_WRITE_ZEROES is set. 21592 */ 21593 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_OFST 56 21594 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4 21595 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LBN 448 21596 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_WIDTH 32 21597 /* Maximum write zeroes segment number. Only valid if VIRTIO_BLK_F_WRITE_ZEROES 21598 * is set. 21599 */ 21600 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_OFST 60 21601 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4 21602 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LBN 480 21603 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_WIDTH 32 21604 /* Write zeroes request can result in deallocating one or more sectors. Only 21605 * valid if VIRTIO_BLK_F_WRITE_ZEROES is set. 21606 */ 21607 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_OFST 64 21608 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1 21609 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LBN 512 21610 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_WIDTH 8 21611 /* Unused, set to zero. */ 21612 #define VIRTIO_BLK_CONFIG_UNUSED1_OFST 65 21613 #define VIRTIO_BLK_CONFIG_UNUSED1_LEN 3 21614 #define VIRTIO_BLK_CONFIG_UNUSED1_LBN 520 21615 #define VIRTIO_BLK_CONFIG_UNUSED1_WIDTH 24 21616 21617 21618 /***********************************/ 21619 /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 21620 * Set configuration for an existing descriptor proxy function. Configuration 21621 * data must match function personality. The actual function configuration is 21622 * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN 21623 */ 21624 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174 21625 #undef MC_CMD_0x174_PRIVILEGE_CTG 21626 21627 #define MC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21628 21629 /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN msgrequest */ 21630 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMIN 20 21631 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX 252 21632 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX_MCDI2 1020 21633 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num)) 21634 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1) 21635 /* Handle to descriptor proxy function (as returned by 21636 * MC_CMD_DESC_PROXY_FUNC_OPEN) 21637 */ 21638 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0 21639 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4 21640 /* Reserved for future extension, set to zero. */ 21641 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4 21642 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_LEN 16 21643 /* Configuration data. Format of configuration data is determined implicitly 21644 * from function personality referred to by HANDLE. Currently, only supported 21645 * format is VIRTIO_BLK_CONFIG. 21646 */ 21647 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_OFST 20 21648 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1 21649 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0 21650 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM 232 21651 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM_MCDI2 1000 21652 21653 /* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT msgresponse */ 21654 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0 21655 21656 21657 /***********************************/ 21658 /* MC_CMD_DESC_PROXY_FUNC_COMMIT 21659 * Commit function configuration to non-volatile or volatile store. Once 21660 * configuration is applied to hardware (which may happen immediately or on 21661 * next function/device reset) a DESC_PROXY_FUNC_CONFIG_SET MCDI event will be 21662 * delivered to callers MCDI event queue. 21663 */ 21664 #define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175 21665 #undef MC_CMD_0x175_PRIVILEGE_CTG 21666 21667 #define MC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21668 21669 /* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN msgrequest */ 21670 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_LEN 8 21671 /* Handle to descriptor proxy function (as returned by 21672 * MC_CMD_DESC_PROXY_FUNC_OPEN) 21673 */ 21674 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0 21675 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4 21676 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4 21677 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4 21678 /* enum: Store into non-volatile (dynamic) config */ 21679 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0 21680 /* enum: Store into volatile (ephemeral) config */ 21681 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1 21682 21683 /* MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT msgresponse */ 21684 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4 21685 /* Generation count to be delivered in an event once configuration becomes live 21686 */ 21687 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0 21688 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4 21689 21690 21691 /***********************************/ 21692 /* MC_CMD_DESC_PROXY_FUNC_OPEN 21693 * Retrieve a handle for an existing descriptor proxy function. Returns an 21694 * integer handle, valid until function is deallocated, MC rebooted or power- 21695 * cycle. Returns ENODEV if no function with given label exists. 21696 */ 21697 #define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176 21698 #undef MC_CMD_0x176_PRIVILEGE_CTG 21699 21700 #define MC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21701 21702 /* MC_CMD_DESC_PROXY_FUNC_OPEN_IN msgrequest */ 21703 #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LEN 40 21704 /* User-defined label (zero-terminated ASCII string) to uniquely identify the 21705 * function 21706 */ 21707 #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0 21708 #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_LEN 40 21709 21710 /* MC_CMD_DESC_PROXY_FUNC_OPEN_OUT msgresponse */ 21711 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMIN 40 21712 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX 252 21713 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX_MCDI2 1020 21714 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num)) 21715 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1) 21716 /* Handle to the descriptor proxy function */ 21717 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0 21718 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4 21719 /* PCIe Function ID (as struct PCIE_FUNCTION) */ 21720 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4 21721 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8 21722 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4 21723 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8 21724 /* Function personality */ 21725 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12 21726 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4 21727 /* Enum values, see field(s): */ 21728 /* FUNCTION_PERSONALITY/ID */ 21729 /* Function configuration state */ 21730 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_OFST 16 21731 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4 21732 /* enum: Function configuration is visible to the host (live) */ 21733 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0 21734 /* enum: Function configuration is pending reset */ 21735 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1 21736 /* Generation count to be delivered in an event once the configuration becomes 21737 * live (if status is "pending") 21738 */ 21739 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_OFST 20 21740 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4 21741 /* Reserved for future extension, set to zero. */ 21742 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_OFST 24 21743 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_LEN 16 21744 /* Configuration data corresponding to function personality. Currently, only 21745 * supported format is VIRTIO_BLK_CONFIG 21746 */ 21747 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_OFST 40 21748 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1 21749 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0 21750 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM 212 21751 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM_MCDI2 980 21752 21753 21754 /***********************************/ 21755 /* MC_CMD_DESC_PROXY_FUNC_CLOSE 21756 * Releases a handle for an open descriptor proxy function. If proxying was 21757 * enabled on the device, the caller is expected to gracefully stop it using 21758 * MC_CMD_DESC_PROXY_FUNC_DISABLE prior to calling this function. Closing an 21759 * active device without disabling proxying will result in forced close, which 21760 * will put the device into a failed state and signal the host driver of the 21761 * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side) 21762 */ 21763 #define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1 21764 #undef MC_CMD_0x1a1_PRIVILEGE_CTG 21765 21766 #define MC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21767 21768 /* MC_CMD_DESC_PROXY_FUNC_CLOSE_IN msgrequest */ 21769 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4 21770 /* Handle to the descriptor proxy function */ 21771 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0 21772 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4 21773 21774 /* MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT msgresponse */ 21775 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0 21776 21777 /* DESC_PROXY_FUNC_MAP structuredef */ 21778 #define DESC_PROXY_FUNC_MAP_LEN 52 21779 /* PCIe function ID (as struct PCIE_FUNCTION) */ 21780 #define DESC_PROXY_FUNC_MAP_FUNC_OFST 0 21781 #define DESC_PROXY_FUNC_MAP_FUNC_LEN 8 21782 #define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0 21783 #define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4 21784 #define DESC_PROXY_FUNC_MAP_FUNC_LBN 0 21785 #define DESC_PROXY_FUNC_MAP_FUNC_WIDTH 64 21786 /* Function personality */ 21787 #define DESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8 21788 #define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4 21789 /* Enum values, see field(s): */ 21790 /* FUNCTION_PERSONALITY/ID */ 21791 #define DESC_PROXY_FUNC_MAP_PERSONALITY_LBN 64 21792 #define DESC_PROXY_FUNC_MAP_PERSONALITY_WIDTH 32 21793 /* User-defined label (zero-terminated ASCII string) to uniquely identify the 21794 * function 21795 */ 21796 #define DESC_PROXY_FUNC_MAP_LABEL_OFST 12 21797 #define DESC_PROXY_FUNC_MAP_LABEL_LEN 40 21798 #define DESC_PROXY_FUNC_MAP_LABEL_LBN 96 21799 #define DESC_PROXY_FUNC_MAP_LABEL_WIDTH 320 21800 21801 21802 /***********************************/ 21803 /* MC_CMD_DESC_PROXY_FUNC_ENUM 21804 * Enumerate existing descriptor proxy functions 21805 */ 21806 #define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177 21807 #undef MC_CMD_0x177_PRIVILEGE_CTG 21808 21809 #define MC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21810 21811 /* MC_CMD_DESC_PROXY_FUNC_ENUM_IN msgrequest */ 21812 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4 21813 /* Starting index, set to 0 on first request. See 21814 * MC_CMD_DESC_PROXY_FUNC_ENUM_OUT/FLAGS. 21815 */ 21816 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0 21817 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4 21818 21819 /* MC_CMD_DESC_PROXY_FUNC_ENUM_OUT msgresponse */ 21820 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4 21821 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX 212 21822 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX_MCDI2 992 21823 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num)) 21824 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52) 21825 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0 21826 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4 21827 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0 21828 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0 21829 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1 21830 /* Function map, as array of DESC_PROXY_FUNC_MAP */ 21831 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4 21832 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_LEN 52 21833 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0 21834 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4 21835 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM_MCDI2 19 21836 21837 21838 /***********************************/ 21839 /* MC_CMD_DESC_PROXY_FUNC_ENABLE 21840 * Enable descriptor proxying for function into target event queue. Returns VI 21841 * allocation info for the proxy source function, so that the caller can map 21842 * absolute VI IDs from descriptor proxy events back to the originating 21843 * function. 21844 */ 21845 #define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178 21846 #undef MC_CMD_0x178_PRIVILEGE_CTG 21847 21848 #define MC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21849 21850 /* MC_CMD_DESC_PROXY_FUNC_ENABLE_IN msgrequest */ 21851 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_LEN 8 21852 /* Handle to descriptor proxy function (as returned by 21853 * MC_CMD_DESC_PROXY_FUNC_OPEN) 21854 */ 21855 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0 21856 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4 21857 /* Descriptor proxy sink queue (caller function relative). Must be extended 21858 * width event queue 21859 */ 21860 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4 21861 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4 21862 21863 /* MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT msgresponse */ 21864 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_LEN 8 21865 /* The number of VIs allocated on the function */ 21866 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0 21867 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4 21868 /* The base absolute VI number allocated to the function. */ 21869 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4 21870 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4 21871 21872 21873 /***********************************/ 21874 /* MC_CMD_DESC_PROXY_FUNC_DISABLE 21875 * Disable descriptor proxying for function 21876 */ 21877 #define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179 21878 #undef MC_CMD_0x179_PRIVILEGE_CTG 21879 21880 #define MC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21881 21882 /* MC_CMD_DESC_PROXY_FUNC_DISABLE_IN msgrequest */ 21883 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4 21884 /* Handle to descriptor proxy function (as returned by 21885 * MC_CMD_DESC_PROXY_FUNC_OPEN) 21886 */ 21887 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0 21888 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4 21889 21890 /* MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT msgresponse */ 21891 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0 21892 21893 21894 /***********************************/ 21895 /* MC_CMD_GET_ADDR_SPC_ID 21896 * Get Address space identifier for use in mem2mem descriptors for a given 21897 * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem 21898 * descriptors. 21899 */ 21900 #define MC_CMD_GET_ADDR_SPC_ID 0x1a0 21901 #undef MC_CMD_0x1a0_PRIVILEGE_CTG 21902 21903 #define MC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 21904 21905 /* MC_CMD_GET_ADDR_SPC_ID_IN msgrequest */ 21906 #define MC_CMD_GET_ADDR_SPC_ID_IN_LEN 16 21907 /* Resource type to get ADDR_SPC_ID for */ 21908 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0 21909 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4 21910 /* enum: Address space ID for host/AP memory DMA over the same interface this 21911 * MCDI was called on 21912 */ 21913 #define MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0 21914 /* enum: Address space ID for host/AP memory DMA via PCI interface and function 21915 * specified by FUNC 21916 */ 21917 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1 21918 /* enum: Address space ID for host/AP memory DMA via PCI interface and function 21919 * specified by FUNC with PASID value specified by PASID 21920 */ 21921 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2 21922 /* enum: Address space ID for host/AP memory DMA via PCI interface and function 21923 * specified by FUNC with PASID value of relative VI specified by VI 21924 */ 21925 #define MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3 21926 /* enum: Address space ID for host/AP memory DMA via PCI interface, function 21927 * and PASID value of absolute VI specified by VI 21928 */ 21929 #define MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4 21930 /* enum: Address space ID for host memory DMA via PCI interface and function of 21931 * descriptor proxy function specified by HANDLE 21932 */ 21933 #define MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5 21934 /* enum: Address space ID for DMA to/from MC memory */ 21935 #define MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6 21936 /* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR) 21937 */ 21938 #define MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7 21939 /* PCIe Function ID (as struct PCIE_FUNCTION). Only valid if TYPE is PCI_FUNC, 21940 * PCI_FUNC_PASID or REL_VI. 21941 */ 21942 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4 21943 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8 21944 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4 21945 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8 21946 /* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */ 21947 #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12 21948 #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4 21949 /* Relative or absolute VI number. Only valid if TYPE is REL_VI or ABS_VI */ 21950 #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_OFST 12 21951 #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4 21952 /* Descriptor proxy function handle. Only valid if TYPE is DESC_PROXY_HANDLE. 21953 */ 21954 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4 21955 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4 21956 21957 /* MC_CMD_GET_ADDR_SPC_ID_OUT msgresponse */ 21958 #define MC_CMD_GET_ADDR_SPC_ID_OUT_LEN 8 21959 /* Address Space ID for the requested target. Only the lower 36 bits are valid 21960 * in the current SmartNIC implementation. 21961 */ 21962 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0 21963 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8 21964 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0 21965 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4 21966 21967 21968 #endif /* MCDI_PCOL_H */ 21969