1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/types.h> 4 #include <linux/clk.h> 5 #include <linux/platform_device.h> 6 #include <linux/pm_runtime.h> 7 #include <linux/acpi.h> 8 #include <linux/of_mdio.h> 9 #include <linux/etherdevice.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 13 #include <net/tcp.h> 14 #include <net/ip6_checksum.h> 15 16 #define NETSEC_REG_SOFT_RST 0x104 17 #define NETSEC_REG_COM_INIT 0x120 18 19 #define NETSEC_REG_TOP_STATUS 0x200 20 #define NETSEC_IRQ_RX BIT(1) 21 #define NETSEC_IRQ_TX BIT(0) 22 23 #define NETSEC_REG_TOP_INTEN 0x204 24 #define NETSEC_REG_INTEN_SET 0x234 25 #define NETSEC_REG_INTEN_CLR 0x238 26 27 #define NETSEC_REG_NRM_TX_STATUS 0x400 28 #define NETSEC_REG_NRM_TX_INTEN 0x404 29 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428 30 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 31 #define NRM_TX_ST_NTOWNR BIT(17) 32 #define NRM_TX_ST_TR_ERR BIT(16) 33 #define NRM_TX_ST_TXDONE BIT(15) 34 #define NRM_TX_ST_TMREXP BIT(14) 35 36 #define NETSEC_REG_NRM_RX_STATUS 0x440 37 #define NETSEC_REG_NRM_RX_INTEN 0x444 38 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468 39 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 40 #define NRM_RX_ST_RC_ERR BIT(16) 41 #define NRM_RX_ST_PKTCNT BIT(15) 42 #define NRM_RX_ST_TMREXP BIT(14) 43 44 #define NETSEC_REG_PKT_CMD_BUF 0xd0 45 46 #define NETSEC_REG_CLK_EN 0x100 47 48 #define NETSEC_REG_PKT_CTRL 0x140 49 50 #define NETSEC_REG_DMA_TMR_CTRL 0x20c 51 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c 52 #define NETSEC_REG_F_TAIKI_VER 0x230 53 #define NETSEC_REG_DMA_HM_CTRL 0x214 54 #define NETSEC_REG_DMA_MH_CTRL 0x220 55 #define NETSEC_REG_ADDR_DIS_CORE 0x218 56 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 57 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 58 59 #define NETSEC_REG_NRM_TX_PKTCNT 0x410 60 61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 63 64 #define NETSEC_REG_NRM_TX_TMR 0x41c 65 66 #define NETSEC_REG_NRM_RX_PKTCNT 0x454 67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 68 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 69 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 70 71 #define NETSEC_REG_NRM_RX_TMR 0x45c 72 73 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 74 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 75 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 76 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 77 78 #define NETSEC_REG_NRM_TX_CONFIG 0x430 79 #define NETSEC_REG_NRM_RX_CONFIG 0x470 80 81 #define MAC_REG_STATUS 0x1024 82 #define MAC_REG_DATA 0x11c0 83 #define MAC_REG_CMD 0x11c4 84 #define MAC_REG_FLOW_TH 0x11cc 85 #define MAC_REG_INTF_SEL 0x11d4 86 #define MAC_REG_DESC_INIT 0x11fc 87 #define MAC_REG_DESC_SOFT_RST 0x1204 88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 89 90 #define GMAC_REG_MCR 0x0000 91 #define GMAC_REG_MFFR 0x0004 92 #define GMAC_REG_GAR 0x0010 93 #define GMAC_REG_GDR 0x0014 94 #define GMAC_REG_FCR 0x0018 95 #define GMAC_REG_BMR 0x1000 96 #define GMAC_REG_RDLAR 0x100c 97 #define GMAC_REG_TDLAR 0x1010 98 #define GMAC_REG_OMR 0x1018 99 100 #define MHZ(n) ((n) * 1000 * 1000) 101 102 #define NETSEC_TX_SHIFT_OWN_FIELD 31 103 #define NETSEC_TX_SHIFT_LD_FIELD 30 104 #define NETSEC_TX_SHIFT_DRID_FIELD 24 105 #define NETSEC_TX_SHIFT_PT_FIELD 21 106 #define NETSEC_TX_SHIFT_TDRID_FIELD 16 107 #define NETSEC_TX_SHIFT_CC_FIELD 15 108 #define NETSEC_TX_SHIFT_FS_FIELD 9 109 #define NETSEC_TX_LAST 8 110 #define NETSEC_TX_SHIFT_CO 7 111 #define NETSEC_TX_SHIFT_SO 6 112 #define NETSEC_TX_SHIFT_TRS_FIELD 4 113 114 #define NETSEC_RX_PKT_OWN_FIELD 31 115 #define NETSEC_RX_PKT_LD_FIELD 30 116 #define NETSEC_RX_PKT_SDRID_FIELD 24 117 #define NETSEC_RX_PKT_FR_FIELD 23 118 #define NETSEC_RX_PKT_ER_FIELD 21 119 #define NETSEC_RX_PKT_ERR_FIELD 16 120 #define NETSEC_RX_PKT_TDRID_FIELD 12 121 #define NETSEC_RX_PKT_FS_FIELD 9 122 #define NETSEC_RX_PKT_LS_FIELD 8 123 #define NETSEC_RX_PKT_CO_FIELD 6 124 125 #define NETSEC_RX_PKT_ERR_MASK 3 126 127 #define NETSEC_MAX_TX_PKT_LEN 1518 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 129 130 #define NETSEC_RING_GMAC 15 131 #define NETSEC_RING_MAX 2 132 133 #define NETSEC_TCP_SEG_LEN_MAX 1460 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 135 136 #define NETSEC_RX_CKSUM_NOTAVAIL 0 137 #define NETSEC_RX_CKSUM_OK 1 138 #define NETSEC_RX_CKSUM_NG 2 139 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 141 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 142 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 145 146 #define NETSEC_INT_PKTCNT_MAX 2047 147 148 #define NETSEC_FLOW_START_TH_MAX 95 149 #define NETSEC_FLOW_STOP_TH_MAX 95 150 #define NETSEC_FLOW_PAUSE_TIME_MIN 5 151 152 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 153 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 160 161 #define NETSEC_CLK_EN_REG_DOM_G BIT(5) 162 #define NETSEC_CLK_EN_REG_DOM_C BIT(1) 163 #define NETSEC_CLK_EN_REG_DOM_D BIT(0) 164 165 #define NETSEC_COM_INIT_REG_DB BIT(2) 166 #define NETSEC_COM_INIT_REG_CLS BIT(1) 167 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 168 NETSEC_COM_INIT_REG_DB) 169 170 #define NETSEC_SOFT_RST_REG_RESET 0 171 #define NETSEC_SOFT_RST_REG_RUN BIT(31) 172 173 #define NETSEC_DMA_CTRL_REG_STOP 1 174 #define MH_CTRL__MODE_TRANS BIT(20) 175 176 #define NETSEC_GMAC_CMD_ST_READ 0 177 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 178 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 179 180 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 181 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181 182 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001 183 184 #define NETSEC_GMAC_OMR_REG_ST BIT(13) 185 #define NETSEC_GMAC_OMR_REG_SR BIT(1) 186 187 #define NETSEC_GMAC_MCR_REG_IBN BIT(30) 188 #define NETSEC_GMAC_MCR_REG_CST BIT(25) 189 #define NETSEC_GMAC_MCR_REG_JE BIT(20) 190 #define NETSEC_MCR_PS BIT(15) 191 #define NETSEC_GMAC_MCR_REG_FES BIT(14) 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 194 195 #define NETSEC_FCR_RFE BIT(2) 196 #define NETSEC_FCR_TFE BIT(1) 197 198 #define NETSEC_GMAC_GAR_REG_GW BIT(1) 199 #define NETSEC_GMAC_GAR_REG_GB BIT(0) 200 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 203 #define GMAC_REG_SHIFT_CR_GAR 2 204 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 211 212 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 213 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 214 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 216 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 219 #define NETSEC_REG_DESC_TMR_MODE 4 220 #define NETSEC_REG_DESC_ENDIAN 0 221 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 223 #define NETSEC_MAC_DESC_INIT_REG_INIT 1 224 225 #define NETSEC_EEPROM_MAC_ADDRESS 0x00 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 228 #define NETSEC_EEPROM_HM_ME_SIZE 0x10 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 231 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 233 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24 234 235 #define DESC_NUM 256 236 237 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 238 #define NETSEC_RX_BUF_SZ 1536 239 240 #define DESC_SZ sizeof(struct netsec_de) 241 242 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 243 244 enum ring_id { 245 NETSEC_RING_TX = 0, 246 NETSEC_RING_RX 247 }; 248 249 struct netsec_desc { 250 struct sk_buff *skb; 251 dma_addr_t dma_addr; 252 void *addr; 253 u16 len; 254 }; 255 256 struct netsec_desc_ring { 257 dma_addr_t desc_dma; 258 struct netsec_desc *desc; 259 void *vaddr; 260 u16 head, tail; 261 }; 262 263 struct netsec_priv { 264 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 265 struct ethtool_coalesce et_coalesce; 266 spinlock_t reglock; /* protect reg access */ 267 struct napi_struct napi; 268 phy_interface_t phy_interface; 269 struct net_device *ndev; 270 struct device_node *phy_np; 271 struct phy_device *phydev; 272 struct mii_bus *mii_bus; 273 void __iomem *ioaddr; 274 void __iomem *eeprom_base; 275 struct device *dev; 276 struct clk *clk; 277 u32 msg_enable; 278 u32 freq; 279 u32 phy_addr; 280 bool rx_cksum_offload_flag; 281 }; 282 283 struct netsec_de { /* Netsec Descriptor layout */ 284 u32 attr; 285 u32 data_buf_addr_up; 286 u32 data_buf_addr_lw; 287 u32 buf_len_info; 288 }; 289 290 struct netsec_tx_pkt_ctrl { 291 u16 tcp_seg_len; 292 bool tcp_seg_offload_flag; 293 bool cksum_offload_flag; 294 }; 295 296 struct netsec_rx_pkt_info { 297 int rx_cksum_result; 298 int err_code; 299 bool err_flag; 300 }; 301 302 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 303 { 304 writel(val, priv->ioaddr + reg_addr); 305 } 306 307 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 308 { 309 return readl(priv->ioaddr + reg_addr); 310 } 311 312 /************* MDIO BUS OPS FOLLOW *************/ 313 314 #define TIMEOUT_SPINS_MAC 1000 315 #define TIMEOUT_SECONDARY_MS_MAC 100 316 317 static u32 netsec_clk_type(u32 freq) 318 { 319 if (freq < MHZ(35)) 320 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 321 if (freq < MHZ(60)) 322 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 323 if (freq < MHZ(100)) 324 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 325 if (freq < MHZ(150)) 326 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 327 if (freq < MHZ(250)) 328 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 329 330 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 331 } 332 333 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 334 { 335 u32 timeout = TIMEOUT_SPINS_MAC; 336 337 while (--timeout && netsec_read(priv, addr) & mask) 338 cpu_relax(); 339 if (timeout) 340 return 0; 341 342 timeout = TIMEOUT_SECONDARY_MS_MAC; 343 while (--timeout && netsec_read(priv, addr) & mask) 344 usleep_range(1000, 2000); 345 346 if (timeout) 347 return 0; 348 349 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 350 351 return -ETIMEDOUT; 352 } 353 354 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 355 { 356 netsec_write(priv, MAC_REG_DATA, value); 357 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 358 return netsec_wait_while_busy(priv, 359 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 360 } 361 362 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 363 { 364 int ret; 365 366 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 367 ret = netsec_wait_while_busy(priv, 368 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 369 if (ret) 370 return ret; 371 372 *read = netsec_read(priv, MAC_REG_DATA); 373 374 return 0; 375 } 376 377 static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 378 u32 addr, u32 mask) 379 { 380 u32 timeout = TIMEOUT_SPINS_MAC; 381 int ret, data; 382 383 do { 384 ret = netsec_mac_read(priv, addr, &data); 385 if (ret) 386 break; 387 cpu_relax(); 388 } while (--timeout && (data & mask)); 389 390 if (timeout) 391 return 0; 392 393 timeout = TIMEOUT_SECONDARY_MS_MAC; 394 do { 395 usleep_range(1000, 2000); 396 397 ret = netsec_mac_read(priv, addr, &data); 398 if (ret) 399 break; 400 cpu_relax(); 401 } while (--timeout && (data & mask)); 402 403 if (timeout && !ret) 404 return 0; 405 406 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 407 408 return -ETIMEDOUT; 409 } 410 411 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 412 { 413 struct phy_device *phydev = priv->ndev->phydev; 414 u32 value = 0; 415 416 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 417 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 418 419 if (phydev->speed != SPEED_1000) 420 value |= NETSEC_MCR_PS; 421 422 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 423 phydev->speed == SPEED_100) 424 value |= NETSEC_GMAC_MCR_REG_FES; 425 426 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 427 428 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 429 value |= NETSEC_GMAC_MCR_REG_IBN; 430 431 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 432 return -ETIMEDOUT; 433 434 return 0; 435 } 436 437 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 438 439 static int netsec_phy_write(struct mii_bus *bus, 440 int phy_addr, int reg, u16 val) 441 { 442 int status; 443 struct netsec_priv *priv = bus->priv; 444 445 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 446 return -ETIMEDOUT; 447 if (netsec_mac_write(priv, GMAC_REG_GAR, 448 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 449 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 450 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 451 (netsec_clk_type(priv->freq) << 452 GMAC_REG_SHIFT_CR_GAR))) 453 return -ETIMEDOUT; 454 455 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 456 NETSEC_GMAC_GAR_REG_GB); 457 458 /* Developerbox implements RTL8211E PHY and there is 459 * a compatibility problem with F_GMAC4. 460 * RTL8211E expects MDC clock must be kept toggling for several 461 * clock cycle with MDIO high before entering the IDLE state. 462 * To meet this requirement, netsec driver needs to issue dummy 463 * read(e.g. read PHYID1(offset 0x2) register) right after write. 464 */ 465 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 466 467 return status; 468 } 469 470 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 471 { 472 struct netsec_priv *priv = bus->priv; 473 u32 data; 474 int ret; 475 476 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 477 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 478 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 479 (netsec_clk_type(priv->freq) << 480 GMAC_REG_SHIFT_CR_GAR))) 481 return -ETIMEDOUT; 482 483 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 484 NETSEC_GMAC_GAR_REG_GB); 485 if (ret) 486 return ret; 487 488 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 489 if (ret) 490 return ret; 491 492 return data; 493 } 494 495 /************* ETHTOOL_OPS FOLLOW *************/ 496 497 static void netsec_et_get_drvinfo(struct net_device *net_device, 498 struct ethtool_drvinfo *info) 499 { 500 strlcpy(info->driver, "netsec", sizeof(info->driver)); 501 strlcpy(info->bus_info, dev_name(net_device->dev.parent), 502 sizeof(info->bus_info)); 503 } 504 505 static int netsec_et_get_coalesce(struct net_device *net_device, 506 struct ethtool_coalesce *et_coalesce) 507 { 508 struct netsec_priv *priv = netdev_priv(net_device); 509 510 *et_coalesce = priv->et_coalesce; 511 512 return 0; 513 } 514 515 static int netsec_et_set_coalesce(struct net_device *net_device, 516 struct ethtool_coalesce *et_coalesce) 517 { 518 struct netsec_priv *priv = netdev_priv(net_device); 519 520 priv->et_coalesce = *et_coalesce; 521 522 if (priv->et_coalesce.tx_coalesce_usecs < 50) 523 priv->et_coalesce.tx_coalesce_usecs = 50; 524 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 525 priv->et_coalesce.tx_max_coalesced_frames = 1; 526 527 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 528 priv->et_coalesce.tx_max_coalesced_frames); 529 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 530 priv->et_coalesce.tx_coalesce_usecs); 531 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 532 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 533 534 if (priv->et_coalesce.rx_coalesce_usecs < 50) 535 priv->et_coalesce.rx_coalesce_usecs = 50; 536 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 537 priv->et_coalesce.rx_max_coalesced_frames = 1; 538 539 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 540 priv->et_coalesce.rx_max_coalesced_frames); 541 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 542 priv->et_coalesce.rx_coalesce_usecs); 543 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 544 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 545 546 return 0; 547 } 548 549 static u32 netsec_et_get_msglevel(struct net_device *dev) 550 { 551 struct netsec_priv *priv = netdev_priv(dev); 552 553 return priv->msg_enable; 554 } 555 556 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 557 { 558 struct netsec_priv *priv = netdev_priv(dev); 559 560 priv->msg_enable = datum; 561 } 562 563 static const struct ethtool_ops netsec_ethtool_ops = { 564 .get_drvinfo = netsec_et_get_drvinfo, 565 .get_link_ksettings = phy_ethtool_get_link_ksettings, 566 .set_link_ksettings = phy_ethtool_set_link_ksettings, 567 .get_link = ethtool_op_get_link, 568 .get_coalesce = netsec_et_get_coalesce, 569 .set_coalesce = netsec_et_set_coalesce, 570 .get_msglevel = netsec_et_get_msglevel, 571 .set_msglevel = netsec_et_set_msglevel, 572 }; 573 574 /************* NETDEV_OPS FOLLOW *************/ 575 576 577 static void netsec_set_rx_de(struct netsec_priv *priv, 578 struct netsec_desc_ring *dring, u16 idx, 579 const struct netsec_desc *desc) 580 { 581 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 582 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 583 (1 << NETSEC_RX_PKT_FS_FIELD) | 584 (1 << NETSEC_RX_PKT_LS_FIELD); 585 586 if (idx == DESC_NUM - 1) 587 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 588 589 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 590 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 591 de->buf_len_info = desc->len; 592 de->attr = attr; 593 dma_wmb(); 594 595 dring->desc[idx].dma_addr = desc->dma_addr; 596 dring->desc[idx].addr = desc->addr; 597 dring->desc[idx].len = desc->len; 598 } 599 600 static bool netsec_clean_tx_dring(struct netsec_priv *priv) 601 { 602 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 603 unsigned int pkts, bytes; 604 struct netsec_de *entry; 605 int tail = dring->tail; 606 int cnt = 0; 607 608 pkts = 0; 609 bytes = 0; 610 entry = dring->vaddr + DESC_SZ * tail; 611 612 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) && 613 cnt < DESC_NUM) { 614 struct netsec_desc *desc; 615 int eop; 616 617 desc = &dring->desc[tail]; 618 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 619 dma_rmb(); 620 621 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 622 DMA_TO_DEVICE); 623 if (eop) { 624 pkts++; 625 bytes += desc->skb->len; 626 dev_kfree_skb(desc->skb); 627 } 628 /* clean up so netsec_uninit_pkt_dring() won't free the skb 629 * again 630 */ 631 *desc = (struct netsec_desc){}; 632 633 /* entry->attr is not going to be accessed by the NIC until 634 * netsec_set_tx_de() is called. No need for a dma_wmb() here 635 */ 636 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 637 /* move tail ahead */ 638 dring->tail = (tail + 1) % DESC_NUM; 639 640 tail = dring->tail; 641 entry = dring->vaddr + DESC_SZ * tail; 642 cnt++; 643 } 644 645 if (!cnt) 646 return false; 647 648 /* reading the register clears the irq */ 649 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 650 651 priv->ndev->stats.tx_packets += cnt; 652 priv->ndev->stats.tx_bytes += bytes; 653 654 netdev_completed_queue(priv->ndev, cnt, bytes); 655 656 return true; 657 } 658 659 static void netsec_process_tx(struct netsec_priv *priv) 660 { 661 struct net_device *ndev = priv->ndev; 662 bool cleaned; 663 664 cleaned = netsec_clean_tx_dring(priv); 665 666 if (cleaned && netif_queue_stopped(ndev)) { 667 /* Make sure we update the value, anyone stopping the queue 668 * after this will read the proper consumer idx 669 */ 670 smp_wmb(); 671 netif_wake_queue(ndev); 672 } 673 } 674 675 static void *netsec_alloc_rx_data(struct netsec_priv *priv, 676 dma_addr_t *dma_handle, u16 *desc_len, 677 bool napi) 678 { 679 size_t total_len = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 680 size_t payload_len = NETSEC_RX_BUF_SZ; 681 dma_addr_t mapping; 682 void *buf; 683 684 total_len += SKB_DATA_ALIGN(payload_len + NETSEC_SKB_PAD); 685 686 buf = napi ? napi_alloc_frag(total_len) : netdev_alloc_frag(total_len); 687 if (!buf) 688 return NULL; 689 690 mapping = dma_map_single(priv->dev, buf + NETSEC_SKB_PAD, payload_len, 691 DMA_FROM_DEVICE); 692 if (unlikely(dma_mapping_error(priv->dev, mapping))) 693 goto err_out; 694 695 *dma_handle = mapping; 696 *desc_len = payload_len; 697 698 return buf; 699 700 err_out: 701 skb_free_frag(buf); 702 return NULL; 703 } 704 705 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 706 { 707 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 708 u16 idx = from; 709 710 while (num) { 711 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 712 idx++; 713 if (idx >= DESC_NUM) 714 idx = 0; 715 num--; 716 } 717 } 718 719 static int netsec_process_rx(struct netsec_priv *priv, int budget) 720 { 721 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 722 struct net_device *ndev = priv->ndev; 723 struct netsec_rx_pkt_info rx_info; 724 struct sk_buff *skb; 725 int done = 0; 726 727 while (done < budget) { 728 u16 idx = dring->tail; 729 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 730 struct netsec_desc *desc = &dring->desc[idx]; 731 u16 pkt_len, desc_len; 732 dma_addr_t dma_handle; 733 void *buf_addr; 734 u32 truesize; 735 736 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 737 /* reading the register clears the irq */ 738 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 739 break; 740 } 741 742 /* This barrier is needed to keep us from reading 743 * any other fields out of the netsec_de until we have 744 * verified the descriptor has been written back 745 */ 746 dma_rmb(); 747 done++; 748 749 pkt_len = de->buf_len_info >> 16; 750 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 751 NETSEC_RX_PKT_ERR_MASK; 752 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 753 if (rx_info.err_flag) { 754 netif_err(priv, drv, priv->ndev, 755 "%s: rx fail err(%d)\n", __func__, 756 rx_info.err_code); 757 ndev->stats.rx_dropped++; 758 dring->tail = (dring->tail + 1) % DESC_NUM; 759 /* reuse buffer page frag */ 760 netsec_rx_fill(priv, idx, 1); 761 continue; 762 } 763 rx_info.rx_cksum_result = 764 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 765 766 /* allocate a fresh buffer and map it to the hardware. 767 * This will eventually replace the old buffer in the hardware 768 */ 769 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len, 770 true); 771 if (unlikely(!buf_addr)) 772 break; 773 774 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 775 DMA_FROM_DEVICE); 776 prefetch(desc->addr); 777 778 truesize = SKB_DATA_ALIGN(desc->len + NETSEC_SKB_PAD) + 779 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 780 skb = build_skb(desc->addr, truesize); 781 if (unlikely(!skb)) { 782 /* free the newly allocated buffer, we are not going to 783 * use it 784 */ 785 dma_unmap_single(priv->dev, dma_handle, desc_len, 786 DMA_FROM_DEVICE); 787 skb_free_frag(buf_addr); 788 netif_err(priv, drv, priv->ndev, 789 "rx failed to build skb\n"); 790 break; 791 } 792 dma_unmap_single_attrs(priv->dev, desc->dma_addr, desc->len, 793 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 794 795 /* Update the descriptor with the new buffer we allocated */ 796 desc->len = desc_len; 797 desc->dma_addr = dma_handle; 798 desc->addr = buf_addr; 799 800 skb_reserve(skb, NETSEC_SKB_PAD); 801 skb_put(skb, pkt_len); 802 skb->protocol = eth_type_trans(skb, priv->ndev); 803 804 if (priv->rx_cksum_offload_flag && 805 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 806 skb->ip_summed = CHECKSUM_UNNECESSARY; 807 808 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) { 809 ndev->stats.rx_packets++; 810 ndev->stats.rx_bytes += pkt_len; 811 } 812 813 netsec_rx_fill(priv, idx, 1); 814 dring->tail = (dring->tail + 1) % DESC_NUM; 815 } 816 817 return done; 818 } 819 820 static int netsec_napi_poll(struct napi_struct *napi, int budget) 821 { 822 struct netsec_priv *priv; 823 int rx, done, todo; 824 825 priv = container_of(napi, struct netsec_priv, napi); 826 827 netsec_process_tx(priv); 828 829 todo = budget; 830 do { 831 rx = netsec_process_rx(priv, todo); 832 todo -= rx; 833 } while (rx); 834 835 done = budget - todo; 836 837 if (done < budget && napi_complete_done(napi, done)) { 838 unsigned long flags; 839 840 spin_lock_irqsave(&priv->reglock, flags); 841 netsec_write(priv, NETSEC_REG_INTEN_SET, 842 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 843 spin_unlock_irqrestore(&priv->reglock, flags); 844 } 845 846 return done; 847 } 848 849 static void netsec_set_tx_de(struct netsec_priv *priv, 850 struct netsec_desc_ring *dring, 851 const struct netsec_tx_pkt_ctrl *tx_ctrl, 852 const struct netsec_desc *desc, 853 struct sk_buff *skb) 854 { 855 int idx = dring->head; 856 struct netsec_de *de; 857 u32 attr; 858 859 de = dring->vaddr + (DESC_SZ * idx); 860 861 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 862 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 863 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 864 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 865 (1 << NETSEC_TX_LAST) | 866 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 867 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 868 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 869 if (idx == DESC_NUM - 1) 870 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 871 872 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 873 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 874 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 875 de->attr = attr; 876 dma_wmb(); 877 878 dring->desc[idx] = *desc; 879 dring->desc[idx].skb = skb; 880 881 /* move head ahead */ 882 dring->head = (dring->head + 1) % DESC_NUM; 883 } 884 885 static int netsec_desc_used(struct netsec_desc_ring *dring) 886 { 887 int used; 888 889 if (dring->head >= dring->tail) 890 used = dring->head - dring->tail; 891 else 892 used = dring->head + DESC_NUM - dring->tail; 893 894 return used; 895 } 896 897 static int netsec_check_stop_tx(struct netsec_priv *priv, int used) 898 { 899 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 900 901 /* keep tail from touching the queue */ 902 if (DESC_NUM - used < 2) { 903 netif_stop_queue(priv->ndev); 904 905 /* Make sure we read the updated value in case 906 * descriptors got freed 907 */ 908 smp_rmb(); 909 910 used = netsec_desc_used(dring); 911 if (DESC_NUM - used < 2) 912 return NETDEV_TX_BUSY; 913 914 netif_wake_queue(priv->ndev); 915 } 916 917 return 0; 918 } 919 920 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 921 struct net_device *ndev) 922 { 923 struct netsec_priv *priv = netdev_priv(ndev); 924 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 925 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 926 struct netsec_desc tx_desc; 927 u16 tso_seg_len = 0; 928 int filled; 929 930 filled = netsec_desc_used(dring); 931 if (netsec_check_stop_tx(priv, filled)) { 932 net_warn_ratelimited("%s %s Tx queue full\n", 933 dev_name(priv->dev), ndev->name); 934 return NETDEV_TX_BUSY; 935 } 936 937 if (skb->ip_summed == CHECKSUM_PARTIAL) 938 tx_ctrl.cksum_offload_flag = true; 939 940 if (skb_is_gso(skb)) 941 tso_seg_len = skb_shinfo(skb)->gso_size; 942 943 if (tso_seg_len > 0) { 944 if (skb->protocol == htons(ETH_P_IP)) { 945 ip_hdr(skb)->tot_len = 0; 946 tcp_hdr(skb)->check = 947 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 948 ip_hdr(skb)->daddr, 0); 949 } else { 950 ipv6_hdr(skb)->payload_len = 0; 951 tcp_hdr(skb)->check = 952 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 953 &ipv6_hdr(skb)->daddr, 954 0, IPPROTO_TCP, 0); 955 } 956 957 tx_ctrl.tcp_seg_offload_flag = true; 958 tx_ctrl.tcp_seg_len = tso_seg_len; 959 } 960 961 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 962 skb_headlen(skb), DMA_TO_DEVICE); 963 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 964 netif_err(priv, drv, priv->ndev, 965 "%s: DMA mapping failed\n", __func__); 966 ndev->stats.tx_dropped++; 967 dev_kfree_skb_any(skb); 968 return NETDEV_TX_OK; 969 } 970 tx_desc.addr = skb->data; 971 tx_desc.len = skb_headlen(skb); 972 973 skb_tx_timestamp(skb); 974 netdev_sent_queue(priv->ndev, skb->len); 975 976 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 977 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 978 979 return NETDEV_TX_OK; 980 } 981 982 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 983 { 984 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 985 struct netsec_desc *desc; 986 u16 idx; 987 988 if (!dring->vaddr || !dring->desc) 989 return; 990 991 for (idx = 0; idx < DESC_NUM; idx++) { 992 desc = &dring->desc[idx]; 993 if (!desc->addr) 994 continue; 995 996 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 997 id == NETSEC_RING_RX ? DMA_FROM_DEVICE : 998 DMA_TO_DEVICE); 999 if (id == NETSEC_RING_RX) 1000 skb_free_frag(desc->addr); 1001 else if (id == NETSEC_RING_TX) 1002 dev_kfree_skb(desc->skb); 1003 } 1004 1005 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 1006 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 1007 1008 dring->head = 0; 1009 dring->tail = 0; 1010 1011 if (id == NETSEC_RING_TX) 1012 netdev_reset_queue(priv->ndev); 1013 } 1014 1015 static void netsec_free_dring(struct netsec_priv *priv, int id) 1016 { 1017 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1018 1019 if (dring->vaddr) { 1020 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 1021 dring->vaddr, dring->desc_dma); 1022 dring->vaddr = NULL; 1023 } 1024 1025 kfree(dring->desc); 1026 dring->desc = NULL; 1027 } 1028 1029 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 1030 { 1031 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1032 int i; 1033 1034 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1035 &dring->desc_dma, GFP_KERNEL); 1036 if (!dring->vaddr) 1037 goto err; 1038 1039 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1040 if (!dring->desc) 1041 goto err; 1042 1043 if (id == NETSEC_RING_TX) { 1044 for (i = 0; i < DESC_NUM; i++) { 1045 struct netsec_de *de; 1046 1047 de = dring->vaddr + (DESC_SZ * i); 1048 /* de->attr is not going to be accessed by the NIC 1049 * until netsec_set_tx_de() is called. 1050 * No need for a dma_wmb() here 1051 */ 1052 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 1053 } 1054 } 1055 1056 return 0; 1057 err: 1058 netsec_free_dring(priv, id); 1059 1060 return -ENOMEM; 1061 } 1062 1063 static int netsec_setup_rx_dring(struct netsec_priv *priv) 1064 { 1065 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1066 int i; 1067 1068 for (i = 0; i < DESC_NUM; i++) { 1069 struct netsec_desc *desc = &dring->desc[i]; 1070 dma_addr_t dma_handle; 1071 void *buf; 1072 u16 len; 1073 1074 buf = netsec_alloc_rx_data(priv, &dma_handle, &len, 1075 false); 1076 if (!buf) { 1077 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1078 goto err_out; 1079 } 1080 desc->dma_addr = dma_handle; 1081 desc->addr = buf; 1082 desc->len = len; 1083 } 1084 1085 netsec_rx_fill(priv, 0, DESC_NUM); 1086 1087 return 0; 1088 1089 err_out: 1090 return -ENOMEM; 1091 } 1092 1093 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1094 u32 addr_h, u32 addr_l, u32 size) 1095 { 1096 u64 base = (u64)addr_h << 32 | addr_l; 1097 void __iomem *ucode; 1098 u32 i; 1099 1100 ucode = ioremap(base, size * sizeof(u32)); 1101 if (!ucode) 1102 return -ENOMEM; 1103 1104 for (i = 0; i < size; i++) 1105 netsec_write(priv, reg, readl(ucode + i * 4)); 1106 1107 iounmap(ucode); 1108 return 0; 1109 } 1110 1111 static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1112 { 1113 u32 addr_h, addr_l, size; 1114 int err; 1115 1116 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1117 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1118 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1119 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1120 addr_h, addr_l, size); 1121 if (err) 1122 return err; 1123 1124 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1125 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1126 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1127 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1128 addr_h, addr_l, size); 1129 if (err) 1130 return err; 1131 1132 addr_h = 0; 1133 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1134 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1135 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1136 addr_h, addr_l, size); 1137 if (err) 1138 return err; 1139 1140 return 0; 1141 } 1142 1143 static int netsec_reset_hardware(struct netsec_priv *priv, 1144 bool load_ucode) 1145 { 1146 u32 value; 1147 int err; 1148 1149 /* stop DMA engines */ 1150 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1151 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1152 NETSEC_DMA_CTRL_REG_STOP); 1153 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1154 NETSEC_DMA_CTRL_REG_STOP); 1155 1156 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1157 NETSEC_DMA_CTRL_REG_STOP) 1158 cpu_relax(); 1159 1160 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1161 NETSEC_DMA_CTRL_REG_STOP) 1162 cpu_relax(); 1163 } 1164 1165 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1166 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1167 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1168 1169 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1170 cpu_relax(); 1171 1172 /* set desc_start addr */ 1173 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1174 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1175 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1176 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1177 1178 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1179 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1180 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1181 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1182 1183 /* set normal tx dring ring config */ 1184 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1185 1 << NETSEC_REG_DESC_ENDIAN); 1186 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1187 1 << NETSEC_REG_DESC_ENDIAN); 1188 1189 if (load_ucode) { 1190 err = netsec_netdev_load_microcode(priv); 1191 if (err) { 1192 netif_err(priv, probe, priv->ndev, 1193 "%s: failed to load microcode (%d)\n", 1194 __func__, err); 1195 return err; 1196 } 1197 } 1198 1199 /* start DMA engines */ 1200 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1201 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1202 1203 usleep_range(1000, 2000); 1204 1205 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1206 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1207 netif_err(priv, probe, priv->ndev, 1208 "microengine start failed\n"); 1209 return -ENXIO; 1210 } 1211 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1212 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1213 1214 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1215 if (priv->ndev->mtu > ETH_DATA_LEN) 1216 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1217 1218 /* change to normal mode */ 1219 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1220 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1221 1222 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1223 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1224 cpu_relax(); 1225 1226 /* clear any pending EMPTY/ERR irq status */ 1227 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1228 1229 /* Disable TX & RX intr */ 1230 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1231 1232 return 0; 1233 } 1234 1235 static int netsec_start_gmac(struct netsec_priv *priv) 1236 { 1237 struct phy_device *phydev = priv->ndev->phydev; 1238 u32 value = 0; 1239 int ret; 1240 1241 if (phydev->speed != SPEED_1000) 1242 value = (NETSEC_GMAC_MCR_REG_CST | 1243 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1244 1245 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1246 return -ETIMEDOUT; 1247 if (netsec_mac_write(priv, GMAC_REG_BMR, 1248 NETSEC_GMAC_BMR_REG_RESET)) 1249 return -ETIMEDOUT; 1250 1251 /* Wait soft reset */ 1252 usleep_range(1000, 5000); 1253 1254 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1255 if (ret) 1256 return ret; 1257 if (value & NETSEC_GMAC_BMR_REG_SWR) 1258 return -EAGAIN; 1259 1260 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1261 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1262 return -ETIMEDOUT; 1263 1264 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1265 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1266 return -ETIMEDOUT; 1267 1268 if (netsec_mac_write(priv, GMAC_REG_BMR, 1269 NETSEC_GMAC_BMR_REG_COMMON)) 1270 return -ETIMEDOUT; 1271 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1272 NETSEC_GMAC_RDLAR_REG_COMMON)) 1273 return -ETIMEDOUT; 1274 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1275 NETSEC_GMAC_TDLAR_REG_COMMON)) 1276 return -ETIMEDOUT; 1277 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1278 return -ETIMEDOUT; 1279 1280 ret = netsec_mac_update_to_phy_state(priv); 1281 if (ret) 1282 return ret; 1283 1284 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1285 if (ret) 1286 return ret; 1287 1288 value |= NETSEC_GMAC_OMR_REG_SR; 1289 value |= NETSEC_GMAC_OMR_REG_ST; 1290 1291 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1292 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1293 1294 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce); 1295 1296 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1297 return -ETIMEDOUT; 1298 1299 return 0; 1300 } 1301 1302 static int netsec_stop_gmac(struct netsec_priv *priv) 1303 { 1304 u32 value; 1305 int ret; 1306 1307 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1308 if (ret) 1309 return ret; 1310 value &= ~NETSEC_GMAC_OMR_REG_SR; 1311 value &= ~NETSEC_GMAC_OMR_REG_ST; 1312 1313 /* disable all interrupts */ 1314 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1315 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1316 1317 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1318 } 1319 1320 static void netsec_phy_adjust_link(struct net_device *ndev) 1321 { 1322 struct netsec_priv *priv = netdev_priv(ndev); 1323 1324 if (ndev->phydev->link) 1325 netsec_start_gmac(priv); 1326 else 1327 netsec_stop_gmac(priv); 1328 1329 phy_print_status(ndev->phydev); 1330 } 1331 1332 static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1333 { 1334 struct netsec_priv *priv = dev_id; 1335 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1336 unsigned long flags; 1337 1338 /* Disable interrupts */ 1339 if (status & NETSEC_IRQ_TX) { 1340 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1341 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1342 } 1343 if (status & NETSEC_IRQ_RX) { 1344 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1345 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1346 } 1347 1348 spin_lock_irqsave(&priv->reglock, flags); 1349 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1350 spin_unlock_irqrestore(&priv->reglock, flags); 1351 1352 napi_schedule(&priv->napi); 1353 1354 return IRQ_HANDLED; 1355 } 1356 1357 static int netsec_netdev_open(struct net_device *ndev) 1358 { 1359 struct netsec_priv *priv = netdev_priv(ndev); 1360 int ret; 1361 1362 pm_runtime_get_sync(priv->dev); 1363 1364 ret = netsec_setup_rx_dring(priv); 1365 if (ret) { 1366 netif_err(priv, probe, priv->ndev, 1367 "%s: fail setup ring\n", __func__); 1368 goto err1; 1369 } 1370 1371 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1372 IRQF_SHARED, "netsec", priv); 1373 if (ret) { 1374 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1375 goto err2; 1376 } 1377 1378 if (dev_of_node(priv->dev)) { 1379 if (!of_phy_connect(priv->ndev, priv->phy_np, 1380 netsec_phy_adjust_link, 0, 1381 priv->phy_interface)) { 1382 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1383 ret = -ENODEV; 1384 goto err3; 1385 } 1386 } else { 1387 ret = phy_connect_direct(priv->ndev, priv->phydev, 1388 netsec_phy_adjust_link, 1389 priv->phy_interface); 1390 if (ret) { 1391 netif_err(priv, link, priv->ndev, 1392 "phy_connect_direct() failed (%d)\n", ret); 1393 goto err3; 1394 } 1395 } 1396 1397 phy_start(ndev->phydev); 1398 1399 netsec_start_gmac(priv); 1400 napi_enable(&priv->napi); 1401 netif_start_queue(ndev); 1402 1403 /* Enable TX+RX intr. */ 1404 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1405 1406 return 0; 1407 err3: 1408 free_irq(priv->ndev->irq, priv); 1409 err2: 1410 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1411 err1: 1412 pm_runtime_put_sync(priv->dev); 1413 return ret; 1414 } 1415 1416 static int netsec_netdev_stop(struct net_device *ndev) 1417 { 1418 int ret; 1419 struct netsec_priv *priv = netdev_priv(ndev); 1420 1421 netif_stop_queue(priv->ndev); 1422 dma_wmb(); 1423 1424 napi_disable(&priv->napi); 1425 1426 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1427 netsec_stop_gmac(priv); 1428 1429 free_irq(priv->ndev->irq, priv); 1430 1431 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1432 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1433 1434 phy_stop(ndev->phydev); 1435 phy_disconnect(ndev->phydev); 1436 1437 ret = netsec_reset_hardware(priv, false); 1438 1439 pm_runtime_put_sync(priv->dev); 1440 1441 return ret; 1442 } 1443 1444 static int netsec_netdev_init(struct net_device *ndev) 1445 { 1446 struct netsec_priv *priv = netdev_priv(ndev); 1447 int ret; 1448 u16 data; 1449 1450 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1451 1452 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1453 if (ret) 1454 return ret; 1455 1456 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1457 if (ret) 1458 goto err1; 1459 1460 /* set phy power down */ 1461 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR) | 1462 BMCR_PDOWN; 1463 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1464 1465 ret = netsec_reset_hardware(priv, true); 1466 if (ret) 1467 goto err2; 1468 1469 return 0; 1470 err2: 1471 netsec_free_dring(priv, NETSEC_RING_RX); 1472 err1: 1473 netsec_free_dring(priv, NETSEC_RING_TX); 1474 return ret; 1475 } 1476 1477 static void netsec_netdev_uninit(struct net_device *ndev) 1478 { 1479 struct netsec_priv *priv = netdev_priv(ndev); 1480 1481 netsec_free_dring(priv, NETSEC_RING_RX); 1482 netsec_free_dring(priv, NETSEC_RING_TX); 1483 } 1484 1485 static int netsec_netdev_set_features(struct net_device *ndev, 1486 netdev_features_t features) 1487 { 1488 struct netsec_priv *priv = netdev_priv(ndev); 1489 1490 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1491 1492 return 0; 1493 } 1494 1495 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr, 1496 int cmd) 1497 { 1498 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1499 } 1500 1501 static const struct net_device_ops netsec_netdev_ops = { 1502 .ndo_init = netsec_netdev_init, 1503 .ndo_uninit = netsec_netdev_uninit, 1504 .ndo_open = netsec_netdev_open, 1505 .ndo_stop = netsec_netdev_stop, 1506 .ndo_start_xmit = netsec_netdev_start_xmit, 1507 .ndo_set_features = netsec_netdev_set_features, 1508 .ndo_set_mac_address = eth_mac_addr, 1509 .ndo_validate_addr = eth_validate_addr, 1510 .ndo_do_ioctl = netsec_netdev_ioctl, 1511 }; 1512 1513 static int netsec_of_probe(struct platform_device *pdev, 1514 struct netsec_priv *priv, u32 *phy_addr) 1515 { 1516 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1517 if (!priv->phy_np) { 1518 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1519 return -EINVAL; 1520 } 1521 1522 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1523 1524 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1525 if (IS_ERR(priv->clk)) { 1526 dev_err(&pdev->dev, "phy_ref_clk not found\n"); 1527 return PTR_ERR(priv->clk); 1528 } 1529 priv->freq = clk_get_rate(priv->clk); 1530 1531 return 0; 1532 } 1533 1534 static int netsec_acpi_probe(struct platform_device *pdev, 1535 struct netsec_priv *priv, u32 *phy_addr) 1536 { 1537 int ret; 1538 1539 if (!IS_ENABLED(CONFIG_ACPI)) 1540 return -ENODEV; 1541 1542 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1543 if (ret) { 1544 dev_err(&pdev->dev, 1545 "missing required property 'phy-channel'\n"); 1546 return ret; 1547 } 1548 1549 ret = device_property_read_u32(&pdev->dev, 1550 "socionext,phy-clock-frequency", 1551 &priv->freq); 1552 if (ret) 1553 dev_err(&pdev->dev, 1554 "missing required property 'socionext,phy-clock-frequency'\n"); 1555 return ret; 1556 } 1557 1558 static void netsec_unregister_mdio(struct netsec_priv *priv) 1559 { 1560 struct phy_device *phydev = priv->phydev; 1561 1562 if (!dev_of_node(priv->dev) && phydev) { 1563 phy_device_remove(phydev); 1564 phy_device_free(phydev); 1565 } 1566 1567 mdiobus_unregister(priv->mii_bus); 1568 } 1569 1570 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1571 { 1572 struct mii_bus *bus; 1573 int ret; 1574 1575 bus = devm_mdiobus_alloc(priv->dev); 1576 if (!bus) 1577 return -ENOMEM; 1578 1579 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1580 bus->priv = priv; 1581 bus->name = "SNI NETSEC MDIO"; 1582 bus->read = netsec_phy_read; 1583 bus->write = netsec_phy_write; 1584 bus->parent = priv->dev; 1585 priv->mii_bus = bus; 1586 1587 if (dev_of_node(priv->dev)) { 1588 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1589 1590 mdio_node = of_get_child_by_name(parent, "mdio"); 1591 if (mdio_node) { 1592 parent = mdio_node; 1593 } else { 1594 /* older f/w doesn't populate the mdio subnode, 1595 * allow relaxed upgrade of f/w in due time. 1596 */ 1597 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1598 } 1599 1600 ret = of_mdiobus_register(bus, parent); 1601 of_node_put(mdio_node); 1602 1603 if (ret) { 1604 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1605 return ret; 1606 } 1607 } else { 1608 /* Mask out all PHYs from auto probing. */ 1609 bus->phy_mask = ~0; 1610 ret = mdiobus_register(bus); 1611 if (ret) { 1612 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1613 return ret; 1614 } 1615 1616 priv->phydev = get_phy_device(bus, phy_addr, false); 1617 if (IS_ERR(priv->phydev)) { 1618 ret = PTR_ERR(priv->phydev); 1619 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1620 priv->phydev = NULL; 1621 return -ENODEV; 1622 } 1623 1624 ret = phy_device_register(priv->phydev); 1625 if (ret) { 1626 mdiobus_unregister(bus); 1627 dev_err(priv->dev, 1628 "phy_device_register err(%d)\n", ret); 1629 } 1630 } 1631 1632 return ret; 1633 } 1634 1635 static int netsec_probe(struct platform_device *pdev) 1636 { 1637 struct resource *mmio_res, *eeprom_res, *irq_res; 1638 u8 *mac, macbuf[ETH_ALEN]; 1639 struct netsec_priv *priv; 1640 u32 hw_ver, phy_addr = 0; 1641 struct net_device *ndev; 1642 int ret; 1643 1644 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1645 if (!mmio_res) { 1646 dev_err(&pdev->dev, "No MMIO resource found.\n"); 1647 return -ENODEV; 1648 } 1649 1650 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1651 if (!eeprom_res) { 1652 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 1653 return -ENODEV; 1654 } 1655 1656 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1657 if (!irq_res) { 1658 dev_err(&pdev->dev, "No IRQ resource found.\n"); 1659 return -ENODEV; 1660 } 1661 1662 ndev = alloc_etherdev(sizeof(*priv)); 1663 if (!ndev) 1664 return -ENOMEM; 1665 1666 priv = netdev_priv(ndev); 1667 1668 spin_lock_init(&priv->reglock); 1669 SET_NETDEV_DEV(ndev, &pdev->dev); 1670 platform_set_drvdata(pdev, priv); 1671 ndev->irq = irq_res->start; 1672 priv->dev = &pdev->dev; 1673 priv->ndev = ndev; 1674 1675 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 1676 NETIF_MSG_LINK | NETIF_MSG_PROBE; 1677 1678 priv->phy_interface = device_get_phy_mode(&pdev->dev); 1679 if (priv->phy_interface < 0) { 1680 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1681 ret = -ENODEV; 1682 goto free_ndev; 1683 } 1684 1685 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 1686 resource_size(mmio_res)); 1687 if (!priv->ioaddr) { 1688 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 1689 ret = -ENXIO; 1690 goto free_ndev; 1691 } 1692 1693 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 1694 resource_size(eeprom_res)); 1695 if (!priv->eeprom_base) { 1696 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 1697 ret = -ENXIO; 1698 goto free_ndev; 1699 } 1700 1701 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf)); 1702 if (mac) 1703 ether_addr_copy(ndev->dev_addr, mac); 1704 1705 if (priv->eeprom_base && 1706 (!mac || !is_valid_ether_addr(ndev->dev_addr))) { 1707 void __iomem *macp = priv->eeprom_base + 1708 NETSEC_EEPROM_MAC_ADDRESS; 1709 1710 ndev->dev_addr[0] = readb(macp + 3); 1711 ndev->dev_addr[1] = readb(macp + 2); 1712 ndev->dev_addr[2] = readb(macp + 1); 1713 ndev->dev_addr[3] = readb(macp + 0); 1714 ndev->dev_addr[4] = readb(macp + 7); 1715 ndev->dev_addr[5] = readb(macp + 6); 1716 } 1717 1718 if (!is_valid_ether_addr(ndev->dev_addr)) { 1719 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 1720 eth_hw_addr_random(ndev); 1721 } 1722 1723 if (dev_of_node(&pdev->dev)) 1724 ret = netsec_of_probe(pdev, priv, &phy_addr); 1725 else 1726 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 1727 if (ret) 1728 goto free_ndev; 1729 1730 priv->phy_addr = phy_addr; 1731 1732 if (!priv->freq) { 1733 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 1734 ret = -ENODEV; 1735 goto free_ndev; 1736 } 1737 1738 /* default for throughput */ 1739 priv->et_coalesce.rx_coalesce_usecs = 500; 1740 priv->et_coalesce.rx_max_coalesced_frames = 8; 1741 priv->et_coalesce.tx_coalesce_usecs = 500; 1742 priv->et_coalesce.tx_max_coalesced_frames = 8; 1743 1744 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 1745 &ndev->max_mtu); 1746 if (ret < 0) 1747 ndev->max_mtu = ETH_DATA_LEN; 1748 1749 /* runtime_pm coverage just for probe, open/close also cover it */ 1750 pm_runtime_enable(&pdev->dev); 1751 pm_runtime_get_sync(&pdev->dev); 1752 1753 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 1754 /* this driver only supports F_TAIKI style NETSEC */ 1755 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 1756 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 1757 ret = -ENODEV; 1758 goto pm_disable; 1759 } 1760 1761 dev_info(&pdev->dev, "hardware revision %d.%d\n", 1762 hw_ver >> 16, hw_ver & 0xffff); 1763 1764 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT); 1765 1766 ndev->netdev_ops = &netsec_netdev_ops; 1767 ndev->ethtool_ops = &netsec_ethtool_ops; 1768 1769 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 1770 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1771 ndev->hw_features = ndev->features; 1772 1773 priv->rx_cksum_offload_flag = true; 1774 1775 ret = netsec_register_mdio(priv, phy_addr); 1776 if (ret) 1777 goto unreg_napi; 1778 1779 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 1780 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 1781 1782 ret = register_netdev(ndev); 1783 if (ret) { 1784 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 1785 goto unreg_mii; 1786 } 1787 1788 pm_runtime_put_sync(&pdev->dev); 1789 return 0; 1790 1791 unreg_mii: 1792 netsec_unregister_mdio(priv); 1793 unreg_napi: 1794 netif_napi_del(&priv->napi); 1795 pm_disable: 1796 pm_runtime_put_sync(&pdev->dev); 1797 pm_runtime_disable(&pdev->dev); 1798 free_ndev: 1799 free_netdev(ndev); 1800 dev_err(&pdev->dev, "init failed\n"); 1801 1802 return ret; 1803 } 1804 1805 static int netsec_remove(struct platform_device *pdev) 1806 { 1807 struct netsec_priv *priv = platform_get_drvdata(pdev); 1808 1809 unregister_netdev(priv->ndev); 1810 1811 netsec_unregister_mdio(priv); 1812 1813 netif_napi_del(&priv->napi); 1814 1815 pm_runtime_disable(&pdev->dev); 1816 free_netdev(priv->ndev); 1817 1818 return 0; 1819 } 1820 1821 #ifdef CONFIG_PM 1822 static int netsec_runtime_suspend(struct device *dev) 1823 { 1824 struct netsec_priv *priv = dev_get_drvdata(dev); 1825 1826 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 1827 1828 clk_disable_unprepare(priv->clk); 1829 1830 return 0; 1831 } 1832 1833 static int netsec_runtime_resume(struct device *dev) 1834 { 1835 struct netsec_priv *priv = dev_get_drvdata(dev); 1836 1837 clk_prepare_enable(priv->clk); 1838 1839 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 1840 NETSEC_CLK_EN_REG_DOM_C | 1841 NETSEC_CLK_EN_REG_DOM_G); 1842 return 0; 1843 } 1844 #endif 1845 1846 static const struct dev_pm_ops netsec_pm_ops = { 1847 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 1848 }; 1849 1850 static const struct of_device_id netsec_dt_ids[] = { 1851 { .compatible = "socionext,synquacer-netsec" }, 1852 { } 1853 }; 1854 MODULE_DEVICE_TABLE(of, netsec_dt_ids); 1855 1856 #ifdef CONFIG_ACPI 1857 static const struct acpi_device_id netsec_acpi_ids[] = { 1858 { "SCX0001" }, 1859 { } 1860 }; 1861 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 1862 #endif 1863 1864 static struct platform_driver netsec_driver = { 1865 .probe = netsec_probe, 1866 .remove = netsec_remove, 1867 .driver = { 1868 .name = "netsec", 1869 .pm = &netsec_pm_ops, 1870 .of_match_table = netsec_dt_ids, 1871 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 1872 }, 1873 }; 1874 module_platform_driver(netsec_driver); 1875 1876 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 1877 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 1878 MODULE_DESCRIPTION("NETSEC Ethernet driver"); 1879 MODULE_LICENSE("GPL"); 1880