1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_H__ 11 #define __DWMAC4_H__ 12 13 #include "common.h" 14 15 /* MAC registers */ 16 #define GMAC_CONFIG 0x00000000 17 #define GMAC_EXT_CONFIG 0x00000004 18 #define GMAC_PACKET_FILTER 0x00000008 19 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4) 20 #define GMAC_VLAN_TAG 0x00000050 21 #define GMAC_VLAN_HASH_TABLE 0x00000058 22 #define GMAC_RX_FLOW_CTRL 0x00000090 23 #define GMAC_VLAN_INCL 0x00000060 24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 25 #define GMAC_TXQ_PRTY_MAP0 0x98 26 #define GMAC_TXQ_PRTY_MAP1 0x9C 27 #define GMAC_RXQ_CTRL0 0x000000a0 28 #define GMAC_RXQ_CTRL1 0x000000a4 29 #define GMAC_RXQ_CTRL2 0x000000a8 30 #define GMAC_RXQ_CTRL3 0x000000ac 31 #define GMAC_INT_STATUS 0x000000b0 32 #define GMAC_INT_EN 0x000000b4 33 #define GMAC_1US_TIC_COUNTER 0x000000dc 34 #define GMAC_PCS_BASE 0x000000e0 35 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 36 #define GMAC_PMT 0x000000c0 37 #define GMAC_DEBUG 0x00000114 38 #define GMAC_HW_FEATURE0 0x0000011c 39 #define GMAC_HW_FEATURE1 0x00000120 40 #define GMAC_HW_FEATURE2 0x00000124 41 #define GMAC_HW_FEATURE3 0x00000128 42 #define GMAC_MDIO_ADDR 0x00000200 43 #define GMAC_MDIO_DATA 0x00000204 44 #define GMAC_ARP_ADDR 0x00000210 45 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 46 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 47 #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30) 48 #define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30) 49 #define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30) 50 #define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30) 51 52 /* RX Queues Routing */ 53 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 54 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 55 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 56 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 57 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 58 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 59 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 60 #define GMAC_RXQCTRL_UPQ_SHIFT 12 61 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 62 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 63 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 64 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 65 #define GMAC_RXQCTRL_TACPQE BIT(21) 66 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 67 68 /* MAC Packet Filtering */ 69 #define GMAC_PACKET_FILTER_PR BIT(0) 70 #define GMAC_PACKET_FILTER_HMC BIT(2) 71 #define GMAC_PACKET_FILTER_PM BIT(4) 72 #define GMAC_PACKET_FILTER_PCF BIT(7) 73 #define GMAC_PACKET_FILTER_HPF BIT(10) 74 #define GMAC_PACKET_FILTER_VTFE BIT(16) 75 #define GMAC_PACKET_FILTER_IPFE BIT(20) 76 77 #define GMAC_MAX_PERFECT_ADDRESSES 128 78 79 /* MAC VLAN */ 80 #define GMAC_VLAN_EDVLP BIT(26) 81 #define GMAC_VLAN_VTHM BIT(25) 82 #define GMAC_VLAN_DOVLTC BIT(20) 83 #define GMAC_VLAN_ESVL BIT(18) 84 #define GMAC_VLAN_ETV BIT(16) 85 #define GMAC_VLAN_VID GENMASK(15, 0) 86 #define GMAC_VLAN_VLTI BIT(20) 87 #define GMAC_VLAN_CSVL BIT(19) 88 #define GMAC_VLAN_VLC GENMASK(17, 16) 89 #define GMAC_VLAN_VLC_SHIFT 16 90 91 /* MAC RX Queue Enable */ 92 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 93 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 94 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 95 96 /* MAC Flow Control RX */ 97 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 98 99 /* RX Queues Priorities */ 100 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 101 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 102 103 /* TX Queues Priorities */ 104 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 105 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 106 107 /* MAC Flow Control TX */ 108 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 109 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 110 111 /* MAC Interrupt bitmap*/ 112 #define GMAC_INT_RGSMIIS BIT(0) 113 #define GMAC_INT_PCS_LINK BIT(1) 114 #define GMAC_INT_PCS_ANE BIT(2) 115 #define GMAC_INT_PCS_PHYIS BIT(3) 116 #define GMAC_INT_PMT_EN BIT(4) 117 #define GMAC_INT_LPI_EN BIT(5) 118 119 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 120 GMAC_INT_PCS_ANE) 121 122 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN) 123 124 enum dwmac4_irq_status { 125 time_stamp_irq = 0x00001000, 126 mmc_rx_csum_offload_irq = 0x00000800, 127 mmc_tx_irq = 0x00000400, 128 mmc_rx_irq = 0x00000200, 129 mmc_irq = 0x00000100, 130 lpi_irq = 0x00000020, 131 pmt_irq = 0x00000010, 132 }; 133 134 /* MAC PMT bitmap */ 135 enum power_event { 136 pointer_reset = 0x80000000, 137 global_unicast = 0x00000200, 138 wake_up_rx_frame = 0x00000040, 139 magic_frame = 0x00000020, 140 wake_up_frame_en = 0x00000004, 141 magic_pkt_en = 0x00000002, 142 power_down = 0x00000001, 143 }; 144 145 /* Energy Efficient Ethernet (EEE) for GMAC4 146 * 147 * LPI status, timer and control register offset 148 */ 149 #define GMAC4_LPI_CTRL_STATUS 0xd0 150 #define GMAC4_LPI_TIMER_CTRL 0xd4 151 152 /* LPI control and status defines */ 153 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ 154 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 155 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 156 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 157 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 158 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 159 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 160 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 161 162 /* MAC Debug bitmap */ 163 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 164 #define GMAC_DEBUG_TFCSTS_SHIFT 17 165 #define GMAC_DEBUG_TFCSTS_IDLE 0 166 #define GMAC_DEBUG_TFCSTS_WAIT 1 167 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 168 #define GMAC_DEBUG_TFCSTS_XFER 3 169 #define GMAC_DEBUG_TPESTS BIT(16) 170 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 171 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 172 #define GMAC_DEBUG_RPESTS BIT(0) 173 174 /* MAC config */ 175 #define GMAC_CONFIG_ARPEN BIT(31) 176 #define GMAC_CONFIG_SARC GENMASK(30, 28) 177 #define GMAC_CONFIG_SARC_SHIFT 28 178 #define GMAC_CONFIG_IPC BIT(27) 179 #define GMAC_CONFIG_2K BIT(22) 180 #define GMAC_CONFIG_ACS BIT(20) 181 #define GMAC_CONFIG_BE BIT(18) 182 #define GMAC_CONFIG_JD BIT(17) 183 #define GMAC_CONFIG_JE BIT(16) 184 #define GMAC_CONFIG_PS BIT(15) 185 #define GMAC_CONFIG_FES BIT(14) 186 #define GMAC_CONFIG_DM BIT(13) 187 #define GMAC_CONFIG_LM BIT(12) 188 #define GMAC_CONFIG_DCRS BIT(9) 189 #define GMAC_CONFIG_TE BIT(1) 190 #define GMAC_CONFIG_RE BIT(0) 191 192 /* MAC extended config */ 193 #define GMAC_CONFIG_HDSMS GENMASK(22, 20) 194 #define GMAC_CONFIG_HDSMS_SHIFT 20 195 #define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT) 196 197 /* MAC HW features0 bitmap */ 198 #define GMAC_HW_FEAT_SAVLANINS BIT(27) 199 #define GMAC_HW_FEAT_ADDMAC BIT(18) 200 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 201 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 202 #define GMAC_HW_FEAT_EEESEL BIT(13) 203 #define GMAC_HW_FEAT_TSSEL BIT(12) 204 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9) 205 #define GMAC_HW_FEAT_MMCSEL BIT(8) 206 #define GMAC_HW_FEAT_MGKSEL BIT(7) 207 #define GMAC_HW_FEAT_RWKSEL BIT(6) 208 #define GMAC_HW_FEAT_SMASEL BIT(5) 209 #define GMAC_HW_FEAT_VLHASH BIT(4) 210 #define GMAC_HW_FEAT_PCSSEL BIT(3) 211 #define GMAC_HW_FEAT_HDSEL BIT(2) 212 #define GMAC_HW_FEAT_GMIISEL BIT(1) 213 #define GMAC_HW_FEAT_MIISEL BIT(0) 214 215 /* MAC HW features1 bitmap */ 216 #define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27) 217 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) 218 #define GMAC_HW_FEAT_AVSEL BIT(20) 219 #define GMAC_HW_TSOEN BIT(18) 220 #define GMAC_HW_FEAT_SPHEN BIT(17) 221 #define GMAC_HW_ADDR64 GENMASK(15, 14) 222 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 223 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 224 225 /* MAC HW features2 bitmap */ 226 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 227 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 228 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 229 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 230 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 231 232 /* MAC HW features3 bitmap */ 233 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 234 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 235 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 236 #define GMAC_HW_FEAT_FRPSEL BIT(10) 237 #define GMAC_HW_FEAT_DVLAN BIT(5) 238 239 /* MAC HW ADDR regs */ 240 #define GMAC_HI_DCS GENMASK(18, 16) 241 #define GMAC_HI_DCS_SHIFT 16 242 #define GMAC_HI_REG_AE BIT(31) 243 244 /* L3/L4 Filters regs */ 245 #define GMAC_L4DPIM0 BIT(21) 246 #define GMAC_L4DPM0 BIT(20) 247 #define GMAC_L4SPIM0 BIT(19) 248 #define GMAC_L4SPM0 BIT(18) 249 #define GMAC_L4PEN0 BIT(16) 250 #define GMAC_L3DAIM0 BIT(5) 251 #define GMAC_L3DAM0 BIT(4) 252 #define GMAC_L3SAIM0 BIT(3) 253 #define GMAC_L3SAM0 BIT(2) 254 #define GMAC_L3PEN0 BIT(0) 255 #define GMAC_L4DP0 GENMASK(31, 16) 256 #define GMAC_L4DP0_SHIFT 16 257 #define GMAC_L4SP0 GENMASK(15, 0) 258 259 /* MTL registers */ 260 #define MTL_OPERATION_MODE 0x00000c00 261 #define MTL_FRPE BIT(15) 262 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 263 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 264 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 265 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 266 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 267 #define MTL_OPERATION_RAA BIT(2) 268 #define MTL_OPERATION_RAA_SP (0x0 << 2) 269 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 270 271 #define MTL_INT_STATUS 0x00000c20 272 #define MTL_INT_QX(x) BIT(x) 273 274 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 275 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 276 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0) 277 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0) 278 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x)) 279 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 280 281 #define MTL_CHAN_BASE_ADDR 0x00000d00 282 #define MTL_CHAN_BASE_OFFSET 0x40 283 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 284 (x * MTL_CHAN_BASE_OFFSET)) 285 286 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 287 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 288 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 289 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 290 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 291 292 #define MTL_OP_MODE_RSF BIT(5) 293 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 294 #define MTL_OP_MODE_TXQEN_AV BIT(2) 295 #define MTL_OP_MODE_TXQEN BIT(3) 296 #define MTL_OP_MODE_TSF BIT(1) 297 298 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 299 #define MTL_OP_MODE_TQS_SHIFT 16 300 301 #define MTL_OP_MODE_TTC_MASK 0x70 302 #define MTL_OP_MODE_TTC_SHIFT 4 303 304 #define MTL_OP_MODE_TTC_32 0 305 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 306 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 307 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 308 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 309 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 310 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 311 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 312 313 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 314 #define MTL_OP_MODE_RQS_SHIFT 20 315 316 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 317 #define MTL_OP_MODE_RFD_SHIFT 14 318 319 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 320 #define MTL_OP_MODE_RFA_SHIFT 8 321 322 #define MTL_OP_MODE_EHFC BIT(7) 323 324 #define MTL_OP_MODE_RTC_MASK 0x18 325 #define MTL_OP_MODE_RTC_SHIFT 3 326 327 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 328 #define MTL_OP_MODE_RTC_64 0 329 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 330 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 331 332 /* MTL ETS Control register */ 333 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 334 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 335 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \ 336 ((x) * MTL_ETS_CTRL_BASE_OFFSET)) 337 338 #define MTL_ETS_CTRL_CC BIT(3) 339 #define MTL_ETS_CTRL_AVALG BIT(2) 340 341 /* MTL Queue Quantum Weight */ 342 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 343 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 344 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \ 345 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET)) 346 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 347 348 /* MTL sendSlopeCredit register */ 349 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 350 #define MTL_SEND_SLP_CRED_OFFSET 0x40 351 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \ 352 ((x) * MTL_SEND_SLP_CRED_OFFSET)) 353 354 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 355 356 /* MTL hiCredit register */ 357 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 358 #define MTL_HIGH_CRED_OFFSET 0x40 359 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \ 360 ((x) * MTL_HIGH_CRED_OFFSET)) 361 362 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 363 364 /* MTL loCredit register */ 365 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 366 #define MTL_LOW_CRED_OFFSET 0x40 367 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \ 368 ((x) * MTL_LOW_CRED_OFFSET)) 369 370 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 371 372 /* MTL debug */ 373 #define MTL_DEBUG_TXSTSFSTS BIT(5) 374 #define MTL_DEBUG_TXFSTS BIT(4) 375 #define MTL_DEBUG_TWCSTS BIT(3) 376 377 /* MTL debug: Tx FIFO Read Controller Status */ 378 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 379 #define MTL_DEBUG_TRCSTS_SHIFT 1 380 #define MTL_DEBUG_TRCSTS_IDLE 0 381 #define MTL_DEBUG_TRCSTS_READ 1 382 #define MTL_DEBUG_TRCSTS_TXW 2 383 #define MTL_DEBUG_TRCSTS_WRITE 3 384 #define MTL_DEBUG_TXPAUSED BIT(0) 385 386 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 387 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 388 #define MTL_DEBUG_RXFSTS_SHIFT 4 389 #define MTL_DEBUG_RXFSTS_EMPTY 0 390 #define MTL_DEBUG_RXFSTS_BT 1 391 #define MTL_DEBUG_RXFSTS_AT 2 392 #define MTL_DEBUG_RXFSTS_FULL 3 393 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 394 #define MTL_DEBUG_RRCSTS_SHIFT 1 395 #define MTL_DEBUG_RRCSTS_IDLE 0 396 #define MTL_DEBUG_RRCSTS_RDATA 1 397 #define MTL_DEBUG_RRCSTS_RSTAT 2 398 #define MTL_DEBUG_RRCSTS_FLUSH 3 399 #define MTL_DEBUG_RWCSTS BIT(0) 400 401 /* MTL interrupt */ 402 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 403 #define MTL_RX_OVERFLOW_INT BIT(16) 404 405 /* Default operating mode of the MAC */ 406 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 407 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \ 408 GMAC_CONFIG_JE) 409 410 /* To dump the core regs excluding the Address Registers */ 411 #define GMAC_REG_NUM 132 412 413 /* MTL debug */ 414 #define MTL_DEBUG_TXSTSFSTS BIT(5) 415 #define MTL_DEBUG_TXFSTS BIT(4) 416 #define MTL_DEBUG_TWCSTS BIT(3) 417 418 /* MTL debug: Tx FIFO Read Controller Status */ 419 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 420 #define MTL_DEBUG_TRCSTS_SHIFT 1 421 #define MTL_DEBUG_TRCSTS_IDLE 0 422 #define MTL_DEBUG_TRCSTS_READ 1 423 #define MTL_DEBUG_TRCSTS_TXW 2 424 #define MTL_DEBUG_TRCSTS_WRITE 3 425 #define MTL_DEBUG_TXPAUSED BIT(0) 426 427 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 428 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 429 #define MTL_DEBUG_RXFSTS_SHIFT 4 430 #define MTL_DEBUG_RXFSTS_EMPTY 0 431 #define MTL_DEBUG_RXFSTS_BT 1 432 #define MTL_DEBUG_RXFSTS_AT 2 433 #define MTL_DEBUG_RXFSTS_FULL 3 434 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 435 #define MTL_DEBUG_RRCSTS_SHIFT 1 436 #define MTL_DEBUG_RRCSTS_IDLE 0 437 #define MTL_DEBUG_RRCSTS_RDATA 1 438 #define MTL_DEBUG_RRCSTS_RSTAT 2 439 #define MTL_DEBUG_RRCSTS_FLUSH 3 440 #define MTL_DEBUG_RWCSTS BIT(0) 441 442 /* SGMII/RGMII status register */ 443 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 444 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 445 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 446 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 447 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 448 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 449 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 450 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 451 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 452 /* LNKMOD */ 453 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 454 /* LNKSPEED */ 455 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 456 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 457 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 458 459 extern const struct stmmac_dma_ops dwmac4_dma_ops; 460 extern const struct stmmac_dma_ops dwmac410_dma_ops; 461 #endif /* __DWMAC4_H__ */ 462