1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This contains the functions to handle the descriptors for DesignWare databook 4 * 4.xx. 5 * 6 * Copyright (C) 2015 STMicroelectronics Ltd 7 * 8 * Author: Alexandre Torgue <alexandre.torgue@st.com> 9 */ 10 11 #include <linux/stmmac.h> 12 #include "common.h" 13 #include "dwmac4_descs.h" 14 15 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x, 16 struct dma_desc *p, 17 void __iomem *ioaddr) 18 { 19 struct net_device_stats *stats = (struct net_device_stats *)data; 20 unsigned int tdes3; 21 int ret = tx_done; 22 23 tdes3 = le32_to_cpu(p->des3); 24 25 /* Get tx owner first */ 26 if (unlikely(tdes3 & TDES3_OWN)) 27 return tx_dma_own; 28 29 /* Verify tx error by looking at the last segment. */ 30 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR))) 31 return tx_not_ls; 32 33 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) { 34 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT)) 35 x->tx_jabber++; 36 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED)) 37 x->tx_frame_flushed++; 38 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) { 39 x->tx_losscarrier++; 40 stats->tx_carrier_errors++; 41 } 42 if (unlikely(tdes3 & TDES3_NO_CARRIER)) { 43 x->tx_carrier++; 44 stats->tx_carrier_errors++; 45 } 46 if (unlikely((tdes3 & TDES3_LATE_COLLISION) || 47 (tdes3 & TDES3_EXCESSIVE_COLLISION))) 48 stats->collisions += 49 (tdes3 & TDES3_COLLISION_COUNT_MASK) 50 >> TDES3_COLLISION_COUNT_SHIFT; 51 52 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL)) 53 x->tx_deferred++; 54 55 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) 56 x->tx_underflow++; 57 58 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR)) 59 x->tx_ip_header_error++; 60 61 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR)) 62 x->tx_payload_error++; 63 64 ret = tx_err; 65 } 66 67 if (unlikely(tdes3 & TDES3_DEFERRED)) 68 x->tx_deferred++; 69 70 return ret; 71 } 72 73 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x, 74 struct dma_desc *p) 75 { 76 struct net_device_stats *stats = (struct net_device_stats *)data; 77 unsigned int rdes1 = le32_to_cpu(p->des1); 78 unsigned int rdes2 = le32_to_cpu(p->des2); 79 unsigned int rdes3 = le32_to_cpu(p->des3); 80 int message_type; 81 int ret = good_frame; 82 83 if (unlikely(rdes3 & RDES3_OWN)) 84 return dma_own; 85 86 /* Verify rx error by looking at the last segment. */ 87 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR))) 88 return discard_frame; 89 90 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) { 91 if (unlikely(rdes3 & RDES3_GIANT_PACKET)) 92 stats->rx_length_errors++; 93 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR)) 94 x->rx_gmac_overflow++; 95 96 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG)) 97 x->rx_watchdog++; 98 99 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR)) 100 x->rx_mii++; 101 102 if (unlikely(rdes3 & RDES3_CRC_ERROR)) { 103 x->rx_crc_errors++; 104 stats->rx_crc_errors++; 105 } 106 107 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR)) 108 x->dribbling_bit++; 109 110 ret = discard_frame; 111 } 112 113 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8; 114 115 if (rdes1 & RDES1_IP_HDR_ERROR) 116 x->ip_hdr_err++; 117 if (rdes1 & RDES1_IP_CSUM_BYPASSED) 118 x->ip_csum_bypassed++; 119 if (rdes1 & RDES1_IPV4_HEADER) 120 x->ipv4_pkt_rcvd++; 121 if (rdes1 & RDES1_IPV6_HEADER) 122 x->ipv6_pkt_rcvd++; 123 124 if (message_type == RDES_EXT_NO_PTP) 125 x->no_ptp_rx_msg_type_ext++; 126 else if (message_type == RDES_EXT_SYNC) 127 x->ptp_rx_msg_type_sync++; 128 else if (message_type == RDES_EXT_FOLLOW_UP) 129 x->ptp_rx_msg_type_follow_up++; 130 else if (message_type == RDES_EXT_DELAY_REQ) 131 x->ptp_rx_msg_type_delay_req++; 132 else if (message_type == RDES_EXT_DELAY_RESP) 133 x->ptp_rx_msg_type_delay_resp++; 134 else if (message_type == RDES_EXT_PDELAY_REQ) 135 x->ptp_rx_msg_type_pdelay_req++; 136 else if (message_type == RDES_EXT_PDELAY_RESP) 137 x->ptp_rx_msg_type_pdelay_resp++; 138 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP) 139 x->ptp_rx_msg_type_pdelay_follow_up++; 140 else if (message_type == RDES_PTP_ANNOUNCE) 141 x->ptp_rx_msg_type_announce++; 142 else if (message_type == RDES_PTP_MANAGEMENT) 143 x->ptp_rx_msg_type_management++; 144 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE) 145 x->ptp_rx_msg_pkt_reserved_type++; 146 147 if (rdes1 & RDES1_PTP_PACKET_TYPE) 148 x->ptp_frame_type++; 149 if (rdes1 & RDES1_PTP_VER) 150 x->ptp_ver++; 151 if (rdes1 & RDES1_TIMESTAMP_DROPPED) 152 x->timestamp_dropped++; 153 154 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) { 155 x->sa_rx_filter_fail++; 156 ret = discard_frame; 157 } 158 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) { 159 x->da_rx_filter_fail++; 160 ret = discard_frame; 161 } 162 163 if (rdes2 & RDES2_L3_FILTER_MATCH) 164 x->l3_filter_match++; 165 if (rdes2 & RDES2_L4_FILTER_MATCH) 166 x->l4_filter_match++; 167 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK) 168 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT) 169 x->l3_l4_filter_no_match++; 170 171 return ret; 172 } 173 174 static int dwmac4_rd_get_tx_len(struct dma_desc *p) 175 { 176 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK); 177 } 178 179 static int dwmac4_get_tx_owner(struct dma_desc *p) 180 { 181 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT; 182 } 183 184 static void dwmac4_set_tx_owner(struct dma_desc *p) 185 { 186 p->des3 |= cpu_to_le32(TDES3_OWN); 187 } 188 189 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic) 190 { 191 p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR); 192 193 if (!disable_rx_ic) 194 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN); 195 } 196 197 static int dwmac4_get_tx_ls(struct dma_desc *p) 198 { 199 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR) 200 >> TDES3_LAST_DESCRIPTOR_SHIFT; 201 } 202 203 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe) 204 { 205 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK); 206 } 207 208 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p) 209 { 210 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE); 211 } 212 213 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p) 214 { 215 /* Context type from W/B descriptor must be zero */ 216 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE) 217 return 0; 218 219 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */ 220 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS) 221 return 1; 222 223 return 0; 224 } 225 226 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts) 227 { 228 struct dma_desc *p = (struct dma_desc *)desc; 229 u64 ns; 230 231 ns = le32_to_cpu(p->des0); 232 /* convert high/sec time stamp value to nanosecond */ 233 ns += le32_to_cpu(p->des1) * 1000000000ULL; 234 235 *ts = ns; 236 } 237 238 static int dwmac4_rx_check_timestamp(void *desc) 239 { 240 struct dma_desc *p = (struct dma_desc *)desc; 241 unsigned int rdes0 = le32_to_cpu(p->des0); 242 unsigned int rdes1 = le32_to_cpu(p->des1); 243 unsigned int rdes3 = le32_to_cpu(p->des3); 244 u32 own, ctxt; 245 int ret = 1; 246 247 own = rdes3 & RDES3_OWN; 248 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR) 249 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT); 250 251 if (likely(!own && ctxt)) { 252 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff)) 253 /* Corrupted value */ 254 ret = -EINVAL; 255 else 256 /* A valid Timestamp is ready to be read */ 257 ret = 0; 258 } 259 260 /* Timestamp not ready */ 261 return ret; 262 } 263 264 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc, 265 u32 ats) 266 { 267 struct dma_desc *p = (struct dma_desc *)desc; 268 int ret = -EINVAL; 269 270 /* Get the status from normal w/b descriptor */ 271 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) { 272 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) { 273 int i = 0; 274 275 /* Check if timestamp is OK from context descriptor */ 276 do { 277 ret = dwmac4_rx_check_timestamp(next_desc); 278 if (ret < 0) 279 goto exit; 280 i++; 281 282 } while ((ret == 1) && (i < 10)); 283 284 if (i == 10) 285 ret = -EBUSY; 286 } 287 } 288 exit: 289 if (likely(ret == 0)) 290 return 1; 291 292 return 0; 293 } 294 295 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic, 296 int mode, int end, int bfsize) 297 { 298 dwmac4_set_rx_owner(p, disable_rx_ic); 299 } 300 301 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end) 302 { 303 p->des0 = 0; 304 p->des1 = 0; 305 p->des2 = 0; 306 p->des3 = 0; 307 } 308 309 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 310 bool csum_flag, int mode, bool tx_own, 311 bool ls, unsigned int tot_pkt_len) 312 { 313 unsigned int tdes3 = le32_to_cpu(p->des3); 314 315 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK); 316 317 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK; 318 if (is_fs) 319 tdes3 |= TDES3_FIRST_DESCRIPTOR; 320 else 321 tdes3 &= ~TDES3_FIRST_DESCRIPTOR; 322 323 if (likely(csum_flag)) 324 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT); 325 else 326 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT); 327 328 if (ls) 329 tdes3 |= TDES3_LAST_DESCRIPTOR; 330 else 331 tdes3 &= ~TDES3_LAST_DESCRIPTOR; 332 333 /* Finally set the OWN bit. Later the DMA will start! */ 334 if (tx_own) 335 tdes3 |= TDES3_OWN; 336 337 if (is_fs && tx_own) 338 /* When the own bit, for the first frame, has to be set, all 339 * descriptors for the same frame has to be set before, to 340 * avoid race condition. 341 */ 342 dma_wmb(); 343 344 p->des3 = cpu_to_le32(tdes3); 345 } 346 347 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs, 348 int len1, int len2, bool tx_own, 349 bool ls, unsigned int tcphdrlen, 350 unsigned int tcppayloadlen) 351 { 352 unsigned int tdes3 = le32_to_cpu(p->des3); 353 354 if (len1) 355 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK)); 356 357 if (len2) 358 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT) 359 & TDES2_BUFFER2_SIZE_MASK); 360 361 if (is_fs) { 362 tdes3 |= TDES3_FIRST_DESCRIPTOR | 363 TDES3_TCP_SEGMENTATION_ENABLE | 364 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) & 365 TDES3_SLOT_NUMBER_MASK) | 366 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK)); 367 } else { 368 tdes3 &= ~TDES3_FIRST_DESCRIPTOR; 369 } 370 371 if (ls) 372 tdes3 |= TDES3_LAST_DESCRIPTOR; 373 else 374 tdes3 &= ~TDES3_LAST_DESCRIPTOR; 375 376 /* Finally set the OWN bit. Later the DMA will start! */ 377 if (tx_own) 378 tdes3 |= TDES3_OWN; 379 380 if (is_fs && tx_own) 381 /* When the own bit, for the first frame, has to be set, all 382 * descriptors for the same frame has to be set before, to 383 * avoid race condition. 384 */ 385 dma_wmb(); 386 387 p->des3 = cpu_to_le32(tdes3); 388 } 389 390 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode) 391 { 392 p->des0 = 0; 393 p->des1 = 0; 394 p->des2 = 0; 395 p->des3 = 0; 396 } 397 398 static void dwmac4_rd_set_tx_ic(struct dma_desc *p) 399 { 400 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION); 401 } 402 403 static void dwmac4_display_ring(void *head, unsigned int size, bool rx) 404 { 405 struct dma_desc *p = (struct dma_desc *)head; 406 int i; 407 408 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX"); 409 410 for (i = 0; i < size; i++) { 411 pr_info("%03d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 412 i, (unsigned int)virt_to_phys(p), 413 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 414 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 415 p++; 416 } 417 } 418 419 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss) 420 { 421 p->des0 = 0; 422 p->des1 = 0; 423 p->des2 = cpu_to_le32(mss); 424 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV); 425 } 426 427 static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr) 428 { 429 *addr = le32_to_cpu(p->des0); 430 } 431 432 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr) 433 { 434 p->des0 = cpu_to_le32(addr); 435 p->des1 = 0; 436 } 437 438 static void dwmac4_clear(struct dma_desc *p) 439 { 440 p->des0 = 0; 441 p->des1 = 0; 442 p->des2 = 0; 443 p->des3 = 0; 444 } 445 446 const struct stmmac_desc_ops dwmac4_desc_ops = { 447 .tx_status = dwmac4_wrback_get_tx_status, 448 .rx_status = dwmac4_wrback_get_rx_status, 449 .get_tx_len = dwmac4_rd_get_tx_len, 450 .get_tx_owner = dwmac4_get_tx_owner, 451 .set_tx_owner = dwmac4_set_tx_owner, 452 .set_rx_owner = dwmac4_set_rx_owner, 453 .get_tx_ls = dwmac4_get_tx_ls, 454 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len, 455 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp, 456 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status, 457 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status, 458 .get_timestamp = dwmac4_get_timestamp, 459 .set_tx_ic = dwmac4_rd_set_tx_ic, 460 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc, 461 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc, 462 .release_tx_desc = dwmac4_release_tx_desc, 463 .init_rx_desc = dwmac4_rd_init_rx_desc, 464 .init_tx_desc = dwmac4_rd_init_tx_desc, 465 .display_ring = dwmac4_display_ring, 466 .set_mss = dwmac4_set_mss_ctxt, 467 .get_addr = dwmac4_get_addr, 468 .set_addr = dwmac4_set_addr, 469 .clear = dwmac4_clear, 470 }; 471 472 const struct stmmac_mode_ops dwmac4_ring_mode_ops = { }; 473