1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 DWMAC Management Counters 4 5 Copyright (C) 2011 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include "hwif.h" 14 #include "mmc.h" 15 16 /* MAC Management Counters register offset */ 17 18 #define MMC_CNTRL 0x00 /* MMC Control */ 19 #define MMC_RX_INTR 0x04 /* MMC RX Interrupt */ 20 #define MMC_TX_INTR 0x08 /* MMC TX Interrupt */ 21 #define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */ 22 #define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */ 23 #define MMC_DEFAULT_MASK 0xffffffff 24 25 /* MMC TX counter registers */ 26 27 /* Note: 28 * _GB register stands for good and bad frames 29 * _G is for good only. 30 */ 31 #define MMC_TX_OCTETCOUNT_GB 0x14 32 #define MMC_TX_FRAMECOUNT_GB 0x18 33 #define MMC_TX_BROADCASTFRAME_G 0x1c 34 #define MMC_TX_MULTICASTFRAME_G 0x20 35 #define MMC_TX_64_OCTETS_GB 0x24 36 #define MMC_TX_65_TO_127_OCTETS_GB 0x28 37 #define MMC_TX_128_TO_255_OCTETS_GB 0x2c 38 #define MMC_TX_256_TO_511_OCTETS_GB 0x30 39 #define MMC_TX_512_TO_1023_OCTETS_GB 0x34 40 #define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38 41 #define MMC_TX_UNICAST_GB 0x3c 42 #define MMC_TX_MULTICAST_GB 0x40 43 #define MMC_TX_BROADCAST_GB 0x44 44 #define MMC_TX_UNDERFLOW_ERROR 0x48 45 #define MMC_TX_SINGLECOL_G 0x4c 46 #define MMC_TX_MULTICOL_G 0x50 47 #define MMC_TX_DEFERRED 0x54 48 #define MMC_TX_LATECOL 0x58 49 #define MMC_TX_EXESSCOL 0x5c 50 #define MMC_TX_CARRIER_ERROR 0x60 51 #define MMC_TX_OCTETCOUNT_G 0x64 52 #define MMC_TX_FRAMECOUNT_G 0x68 53 #define MMC_TX_EXCESSDEF 0x6c 54 #define MMC_TX_PAUSE_FRAME 0x70 55 #define MMC_TX_VLAN_FRAME_G 0x74 56 57 /* MMC RX counter registers */ 58 #define MMC_RX_FRAMECOUNT_GB 0x80 59 #define MMC_RX_OCTETCOUNT_GB 0x84 60 #define MMC_RX_OCTETCOUNT_G 0x88 61 #define MMC_RX_BROADCASTFRAME_G 0x8c 62 #define MMC_RX_MULTICASTFRAME_G 0x90 63 #define MMC_RX_CRC_ERROR 0x94 64 #define MMC_RX_ALIGN_ERROR 0x98 65 #define MMC_RX_RUN_ERROR 0x9C 66 #define MMC_RX_JABBER_ERROR 0xA0 67 #define MMC_RX_UNDERSIZE_G 0xA4 68 #define MMC_RX_OVERSIZE_G 0xA8 69 #define MMC_RX_64_OCTETS_GB 0xAC 70 #define MMC_RX_65_TO_127_OCTETS_GB 0xb0 71 #define MMC_RX_128_TO_255_OCTETS_GB 0xb4 72 #define MMC_RX_256_TO_511_OCTETS_GB 0xb8 73 #define MMC_RX_512_TO_1023_OCTETS_GB 0xbc 74 #define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0 75 #define MMC_RX_UNICAST_G 0xc4 76 #define MMC_RX_LENGTH_ERROR 0xc8 77 #define MMC_RX_AUTOFRANGETYPE 0xcc 78 #define MMC_RX_PAUSE_FRAMES 0xd0 79 #define MMC_RX_FIFO_OVERFLOW 0xd4 80 #define MMC_RX_VLAN_FRAMES_GB 0xd8 81 #define MMC_RX_WATCHDOG_ERROR 0xdc 82 /* IPC*/ 83 #define MMC_RX_IPC_INTR_MASK 0x100 84 #define MMC_RX_IPC_INTR 0x108 85 /* IPv4*/ 86 #define MMC_RX_IPV4_GD 0x110 87 #define MMC_RX_IPV4_HDERR 0x114 88 #define MMC_RX_IPV4_NOPAY 0x118 89 #define MMC_RX_IPV4_FRAG 0x11C 90 #define MMC_RX_IPV4_UDSBL 0x120 91 92 #define MMC_RX_IPV4_GD_OCTETS 0x150 93 #define MMC_RX_IPV4_HDERR_OCTETS 0x154 94 #define MMC_RX_IPV4_NOPAY_OCTETS 0x158 95 #define MMC_RX_IPV4_FRAG_OCTETS 0x15c 96 #define MMC_RX_IPV4_UDSBL_OCTETS 0x160 97 98 /* IPV6*/ 99 #define MMC_RX_IPV6_GD_OCTETS 0x164 100 #define MMC_RX_IPV6_HDERR_OCTETS 0x168 101 #define MMC_RX_IPV6_NOPAY_OCTETS 0x16c 102 103 #define MMC_RX_IPV6_GD 0x124 104 #define MMC_RX_IPV6_HDERR 0x128 105 #define MMC_RX_IPV6_NOPAY 0x12c 106 107 /* Protocols*/ 108 #define MMC_RX_UDP_GD 0x130 109 #define MMC_RX_UDP_ERR 0x134 110 #define MMC_RX_TCP_GD 0x138 111 #define MMC_RX_TCP_ERR 0x13c 112 #define MMC_RX_ICMP_GD 0x140 113 #define MMC_RX_ICMP_ERR 0x144 114 115 #define MMC_RX_UDP_GD_OCTETS 0x170 116 #define MMC_RX_UDP_ERR_OCTETS 0x174 117 #define MMC_RX_TCP_GD_OCTETS 0x178 118 #define MMC_RX_TCP_ERR_OCTETS 0x17c 119 #define MMC_RX_ICMP_GD_OCTETS 0x180 120 #define MMC_RX_ICMP_ERR_OCTETS 0x184 121 122 /* XGMAC MMC Registers */ 123 #define MMC_XGMAC_TX_OCTET_GB 0x14 124 #define MMC_XGMAC_TX_PKT_GB 0x1c 125 #define MMC_XGMAC_TX_BROAD_PKT_G 0x24 126 #define MMC_XGMAC_TX_MULTI_PKT_G 0x2c 127 #define MMC_XGMAC_TX_64OCT_GB 0x34 128 #define MMC_XGMAC_TX_65OCT_GB 0x3c 129 #define MMC_XGMAC_TX_128OCT_GB 0x44 130 #define MMC_XGMAC_TX_256OCT_GB 0x4c 131 #define MMC_XGMAC_TX_512OCT_GB 0x54 132 #define MMC_XGMAC_TX_1024OCT_GB 0x5c 133 #define MMC_XGMAC_TX_UNI_PKT_GB 0x64 134 #define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c 135 #define MMC_XGMAC_TX_BROAD_PKT_GB 0x74 136 #define MMC_XGMAC_TX_UNDER 0x7c 137 #define MMC_XGMAC_TX_OCTET_G 0x84 138 #define MMC_XGMAC_TX_PKT_G 0x8c 139 #define MMC_XGMAC_TX_PAUSE 0x94 140 #define MMC_XGMAC_TX_VLAN_PKT_G 0x9c 141 #define MMC_XGMAC_TX_LPI_USEC 0xa4 142 #define MMC_XGMAC_TX_LPI_TRAN 0xa8 143 144 #define MMC_XGMAC_RX_PKT_GB 0x100 145 #define MMC_XGMAC_RX_OCTET_GB 0x108 146 #define MMC_XGMAC_RX_OCTET_G 0x110 147 #define MMC_XGMAC_RX_BROAD_PKT_G 0x118 148 #define MMC_XGMAC_RX_MULTI_PKT_G 0x120 149 #define MMC_XGMAC_RX_CRC_ERR 0x128 150 #define MMC_XGMAC_RX_RUNT_ERR 0x130 151 #define MMC_XGMAC_RX_JABBER_ERR 0x134 152 #define MMC_XGMAC_RX_UNDER 0x138 153 #define MMC_XGMAC_RX_OVER 0x13c 154 #define MMC_XGMAC_RX_64OCT_GB 0x140 155 #define MMC_XGMAC_RX_65OCT_GB 0x148 156 #define MMC_XGMAC_RX_128OCT_GB 0x150 157 #define MMC_XGMAC_RX_256OCT_GB 0x158 158 #define MMC_XGMAC_RX_512OCT_GB 0x160 159 #define MMC_XGMAC_RX_1024OCT_GB 0x168 160 #define MMC_XGMAC_RX_UNI_PKT_G 0x170 161 #define MMC_XGMAC_RX_LENGTH_ERR 0x178 162 #define MMC_XGMAC_RX_RANGE 0x180 163 #define MMC_XGMAC_RX_PAUSE 0x188 164 #define MMC_XGMAC_RX_FIFOOVER_PKT 0x190 165 #define MMC_XGMAC_RX_VLAN_PKT_GB 0x198 166 #define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0 167 #define MMC_XGMAC_RX_LPI_USEC 0x1a4 168 #define MMC_XGMAC_RX_LPI_TRAN 0x1a8 169 #define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac 170 #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4 171 #define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc 172 173 #define MMC_XGMAC_TX_FPE_FRAG 0x208 174 #define MMC_XGMAC_TX_HOLD_REQ 0x20c 175 #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228 176 #define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c 177 #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230 178 #define MMC_XGMAC_RX_FPE_FRAG 0x234 179 180 static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) 181 { 182 u32 value = readl(mmcaddr + MMC_CNTRL); 183 184 value |= (mode & 0x3F); 185 186 writel(value, mmcaddr + MMC_CNTRL); 187 188 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n", 189 MMC_CNTRL, value); 190 } 191 192 /* To mask all all interrupts.*/ 193 static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr) 194 { 195 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK); 196 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK); 197 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK); 198 } 199 200 /* This reads the MAC core counters (if actaully supported). 201 * by default the MMC core is programmed to reset each 202 * counter after a read. So all the field of the mmc struct 203 * have to be incremented. 204 */ 205 static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) 206 { 207 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB); 208 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB); 209 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr + 210 MMC_TX_BROADCASTFRAME_G); 211 mmc->mmc_tx_multicastframe_g += readl(mmcaddr + 212 MMC_TX_MULTICASTFRAME_G); 213 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB); 214 mmc->mmc_tx_65_to_127_octets_gb += 215 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB); 216 mmc->mmc_tx_128_to_255_octets_gb += 217 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB); 218 mmc->mmc_tx_256_to_511_octets_gb += 219 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB); 220 mmc->mmc_tx_512_to_1023_octets_gb += 221 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB); 222 mmc->mmc_tx_1024_to_max_octets_gb += 223 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB); 224 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB); 225 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB); 226 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB); 227 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR); 228 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G); 229 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G); 230 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED); 231 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL); 232 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL); 233 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR); 234 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G); 235 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G); 236 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF); 237 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME); 238 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G); 239 240 /* MMC RX counter registers */ 241 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB); 242 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB); 243 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G); 244 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr + 245 MMC_RX_BROADCASTFRAME_G); 246 mmc->mmc_rx_multicastframe_g += readl(mmcaddr + 247 MMC_RX_MULTICASTFRAME_G); 248 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR); 249 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR); 250 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR); 251 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR); 252 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G); 253 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G); 254 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB); 255 mmc->mmc_rx_65_to_127_octets_gb += 256 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB); 257 mmc->mmc_rx_128_to_255_octets_gb += 258 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB); 259 mmc->mmc_rx_256_to_511_octets_gb += 260 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB); 261 mmc->mmc_rx_512_to_1023_octets_gb += 262 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB); 263 mmc->mmc_rx_1024_to_max_octets_gb += 264 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB); 265 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G); 266 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR); 267 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE); 268 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES); 269 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW); 270 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB); 271 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR); 272 /* IPC */ 273 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK); 274 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR); 275 /* IPv4 */ 276 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD); 277 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR); 278 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY); 279 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG); 280 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL); 281 282 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS); 283 mmc->mmc_rx_ipv4_hderr_octets += 284 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS); 285 mmc->mmc_rx_ipv4_nopay_octets += 286 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS); 287 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr + 288 MMC_RX_IPV4_FRAG_OCTETS); 289 mmc->mmc_rx_ipv4_udsbl_octets += 290 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS); 291 292 /* IPV6 */ 293 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS); 294 mmc->mmc_rx_ipv6_hderr_octets += 295 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS); 296 mmc->mmc_rx_ipv6_nopay_octets += 297 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS); 298 299 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD); 300 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR); 301 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY); 302 303 /* Protocols */ 304 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD); 305 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR); 306 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD); 307 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR); 308 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD); 309 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR); 310 311 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS); 312 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS); 313 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS); 314 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS); 315 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS); 316 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS); 317 } 318 319 const struct stmmac_mmc_ops dwmac_mmc_ops = { 320 .ctrl = dwmac_mmc_ctrl, 321 .intr_all_mask = dwmac_mmc_intr_all_mask, 322 .read = dwmac_mmc_read, 323 }; 324 325 static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) 326 { 327 u32 value = readl(mmcaddr + MMC_CNTRL); 328 329 value |= (mode & 0x3F); 330 331 writel(value, mmcaddr + MMC_CNTRL); 332 } 333 334 static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr) 335 { 336 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK); 337 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK); 338 } 339 340 static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest) 341 { 342 u64 tmp = 0; 343 344 tmp += readl(addr + reg); 345 tmp += ((u64 )readl(addr + reg + 0x4)) << 32; 346 if (tmp > GENMASK(31, 0)) 347 *dest = ~0x0; 348 else 349 *dest = *dest + tmp; 350 } 351 352 /* This reads the MAC core counters (if actaully supported). 353 * by default the MMC core is programmed to reset each 354 * counter after a read. So all the field of the mmc struct 355 * have to be incremented. 356 */ 357 static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) 358 { 359 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB, 360 &mmc->mmc_tx_octetcount_gb); 361 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB, 362 &mmc->mmc_tx_framecount_gb); 363 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G, 364 &mmc->mmc_tx_broadcastframe_g); 365 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G, 366 &mmc->mmc_tx_multicastframe_g); 367 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB, 368 &mmc->mmc_tx_64_octets_gb); 369 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB, 370 &mmc->mmc_tx_65_to_127_octets_gb); 371 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB, 372 &mmc->mmc_tx_128_to_255_octets_gb); 373 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB, 374 &mmc->mmc_tx_256_to_511_octets_gb); 375 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB, 376 &mmc->mmc_tx_512_to_1023_octets_gb); 377 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB, 378 &mmc->mmc_tx_1024_to_max_octets_gb); 379 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB, 380 &mmc->mmc_tx_unicast_gb); 381 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB, 382 &mmc->mmc_tx_multicast_gb); 383 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB, 384 &mmc->mmc_tx_broadcast_gb); 385 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER, 386 &mmc->mmc_tx_underflow_error); 387 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G, 388 &mmc->mmc_tx_octetcount_g); 389 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G, 390 &mmc->mmc_tx_framecount_g); 391 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE, 392 &mmc->mmc_tx_pause_frame); 393 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G, 394 &mmc->mmc_tx_vlan_frame_g); 395 396 /* MMC RX counter registers */ 397 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB, 398 &mmc->mmc_rx_framecount_gb); 399 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB, 400 &mmc->mmc_rx_octetcount_gb); 401 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G, 402 &mmc->mmc_rx_octetcount_g); 403 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G, 404 &mmc->mmc_rx_broadcastframe_g); 405 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G, 406 &mmc->mmc_rx_multicastframe_g); 407 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR, 408 &mmc->mmc_rx_crc_error); 409 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR, 410 &mmc->mmc_rx_crc_error); 411 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR); 412 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR); 413 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER); 414 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER); 415 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB, 416 &mmc->mmc_rx_64_octets_gb); 417 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB, 418 &mmc->mmc_rx_65_to_127_octets_gb); 419 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB, 420 &mmc->mmc_rx_128_to_255_octets_gb); 421 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB, 422 &mmc->mmc_rx_256_to_511_octets_gb); 423 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB, 424 &mmc->mmc_rx_512_to_1023_octets_gb); 425 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB, 426 &mmc->mmc_rx_1024_to_max_octets_gb); 427 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G, 428 &mmc->mmc_rx_unicast_g); 429 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR, 430 &mmc->mmc_rx_length_error); 431 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE, 432 &mmc->mmc_rx_autofrangetype); 433 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE, 434 &mmc->mmc_rx_pause_frames); 435 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT, 436 &mmc->mmc_rx_fifo_overflow); 437 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB, 438 &mmc->mmc_rx_vlan_frames_gb); 439 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR); 440 441 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG); 442 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ); 443 mmc->mmc_rx_packet_assembly_err_cntr += 444 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR); 445 mmc->mmc_rx_packet_smd_err_cntr += 446 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR); 447 mmc->mmc_rx_packet_assembly_ok_cntr += 448 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK); 449 mmc->mmc_rx_fpe_fragment_cntr += 450 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG); 451 } 452 453 const struct stmmac_mmc_ops dwxgmac_mmc_ops = { 454 .ctrl = dwxgmac_mmc_ctrl, 455 .intr_all_mask = dwxgmac_mmc_intr_all_mask, 456 .read = dwxgmac_mmc_read, 457 }; 458