1fd3040b9SWells Lu // SPDX-License-Identifier: GPL-2.0
2fd3040b9SWells Lu /* Copyright Sunplus Technology Co., Ltd.
3fd3040b9SWells Lu * All rights reserved.
4fd3040b9SWells Lu */
5fd3040b9SWells Lu
6fd3040b9SWells Lu #include <linux/platform_device.h>
7fd3040b9SWells Lu #include <linux/netdevice.h>
8fd3040b9SWells Lu #include <linux/bitfield.h>
9fd3040b9SWells Lu #include <linux/of_mdio.h>
10fd3040b9SWells Lu
11fd3040b9SWells Lu #include "spl2sw_register.h"
12fd3040b9SWells Lu #include "spl2sw_define.h"
13fd3040b9SWells Lu #include "spl2sw_desc.h"
14fd3040b9SWells Lu #include "spl2sw_mac.h"
15fd3040b9SWells Lu
spl2sw_mac_hw_stop(struct spl2sw_common * comm)16fd3040b9SWells Lu void spl2sw_mac_hw_stop(struct spl2sw_common *comm)
17fd3040b9SWells Lu {
18fd3040b9SWells Lu u32 reg;
19fd3040b9SWells Lu
20fd3040b9SWells Lu if (comm->enable == 0) {
21fd3040b9SWells Lu /* Mask and clear all interrupts. */
22fd3040b9SWells Lu writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
23fd3040b9SWells Lu writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
24fd3040b9SWells Lu
25fd3040b9SWells Lu /* Disable cpu 0 and cpu 1. */
26fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
27fd3040b9SWells Lu reg |= MAC_DIS_SOC1_CPU | MAC_DIS_SOC0_CPU;
28fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
29fd3040b9SWells Lu }
30fd3040b9SWells Lu
31fd3040b9SWells Lu /* Disable LAN ports. */
32fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
33fd3040b9SWells Lu reg |= FIELD_PREP(MAC_DIS_PORT, ~comm->enable);
34fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
35fd3040b9SWells Lu }
36fd3040b9SWells Lu
spl2sw_mac_hw_start(struct spl2sw_common * comm)37fd3040b9SWells Lu void spl2sw_mac_hw_start(struct spl2sw_common *comm)
38fd3040b9SWells Lu {
39fd3040b9SWells Lu u32 reg;
40fd3040b9SWells Lu
41fd3040b9SWells Lu /* Enable cpu port 0 (6) & CRC padding (8) */
42fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
43fd3040b9SWells Lu reg &= ~MAC_DIS_SOC0_CPU;
44fd3040b9SWells Lu reg |= MAC_EN_CRC_SOC0;
45fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
46fd3040b9SWells Lu
47fd3040b9SWells Lu /* Enable port 0 & port 1 */
48fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
49fd3040b9SWells Lu reg &= FIELD_PREP(MAC_DIS_PORT, ~comm->enable) | ~MAC_DIS_PORT;
50fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
51fd3040b9SWells Lu }
52fd3040b9SWells Lu
spl2sw_mac_addr_add(struct spl2sw_mac * mac)53fd3040b9SWells Lu int spl2sw_mac_addr_add(struct spl2sw_mac *mac)
54fd3040b9SWells Lu {
55fd3040b9SWells Lu struct spl2sw_common *comm = mac->comm;
56fd3040b9SWells Lu u32 reg;
57fd3040b9SWells Lu int ret;
58fd3040b9SWells Lu
59fd3040b9SWells Lu /* Write 6-octet MAC address. */
60fd3040b9SWells Lu writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),
61fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_W_MAC_15_0);
62fd3040b9SWells Lu writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +
63fd3040b9SWells Lu (mac->mac_addr[4] << 16) + (mac->mac_addr[5] << 24),
64fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_W_MAC_47_16);
65fd3040b9SWells Lu
66fd3040b9SWells Lu /* Set learn port = cpu_port, aging = 1 */
67fd3040b9SWells Lu reg = MAC_W_CPU_PORT_0 | FIELD_PREP(MAC_W_VID, mac->vlan_id) |
68fd3040b9SWells Lu FIELD_PREP(MAC_W_AGE, 1) | MAC_W_MAC_CMD;
69fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
70fd3040b9SWells Lu
71fd3040b9SWells Lu /* Wait for completing. */
72fd3040b9SWells Lu ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true,
73fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
74fd3040b9SWells Lu if (ret) {
75fd3040b9SWells Lu netdev_err(mac->ndev, "Failed to add address to table!\n");
76fd3040b9SWells Lu return ret;
77fd3040b9SWells Lu }
78fd3040b9SWells Lu
79fd3040b9SWells Lu netdev_dbg(mac->ndev, "mac_ad0 = %08x, mac_ad = %08x%04x\n",
80fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0),
81fd3040b9SWells Lu (u32)FIELD_GET(MAC_W_MAC_47_16,
82fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)),
83fd3040b9SWells Lu (u32)FIELD_GET(MAC_W_MAC_15_0,
84fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0)));
85fd3040b9SWells Lu return 0;
86fd3040b9SWells Lu }
87fd3040b9SWells Lu
spl2sw_mac_addr_del(struct spl2sw_mac * mac)88fd3040b9SWells Lu int spl2sw_mac_addr_del(struct spl2sw_mac *mac)
89fd3040b9SWells Lu {
90fd3040b9SWells Lu struct spl2sw_common *comm = mac->comm;
91fd3040b9SWells Lu u32 reg;
92fd3040b9SWells Lu int ret;
93fd3040b9SWells Lu
94fd3040b9SWells Lu /* Write 6-octet MAC address. */
95fd3040b9SWells Lu writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),
96fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_W_MAC_15_0);
97fd3040b9SWells Lu writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +
98fd3040b9SWells Lu (mac->mac_addr[4] << 16) + (mac->mac_addr[5] << 24),
99fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_W_MAC_47_16);
100fd3040b9SWells Lu
101fd3040b9SWells Lu /* Set learn port = lan_port0 and aging = 0
102fd3040b9SWells Lu * to wipe (age) out the entry.
103fd3040b9SWells Lu */
104fd3040b9SWells Lu reg = MAC_W_LAN_PORT_0 | FIELD_PREP(MAC_W_VID, mac->vlan_id) | MAC_W_MAC_CMD;
105fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
106fd3040b9SWells Lu
107fd3040b9SWells Lu /* Wait for completing. */
108fd3040b9SWells Lu ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true,
109fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
110fd3040b9SWells Lu if (ret) {
111fd3040b9SWells Lu netdev_err(mac->ndev, "Failed to delete address from table!\n");
112fd3040b9SWells Lu return ret;
113fd3040b9SWells Lu }
114fd3040b9SWells Lu
115fd3040b9SWells Lu netdev_dbg(mac->ndev, "mac_ad0 = %08x, mac_ad = %08x%04x\n",
116fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0),
117fd3040b9SWells Lu (u32)FIELD_GET(MAC_W_MAC_47_16,
118fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)),
119fd3040b9SWells Lu (u32)FIELD_GET(MAC_W_MAC_15_0,
120fd3040b9SWells Lu readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0)));
121fd3040b9SWells Lu return 0;
122fd3040b9SWells Lu }
123fd3040b9SWells Lu
spl2sw_mac_hw_init(struct spl2sw_common * comm)124fd3040b9SWells Lu void spl2sw_mac_hw_init(struct spl2sw_common *comm)
125fd3040b9SWells Lu {
126fd3040b9SWells Lu u32 reg;
127fd3040b9SWells Lu
128fd3040b9SWells Lu /* Disable cpu0 and cpu 1 port. */
129fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
130fd3040b9SWells Lu reg |= MAC_DIS_SOC1_CPU | MAC_DIS_SOC0_CPU;
131fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
132fd3040b9SWells Lu
133fd3040b9SWells Lu /* Set base addresses of TX and RX queues. */
134fd3040b9SWells Lu writel(comm->desc_dma, comm->l2sw_reg_base + L2SW_TX_LBASE_ADDR_0);
135fd3040b9SWells Lu writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * TX_DESC_NUM,
136fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_TX_HBASE_ADDR_0);
137fd3040b9SWells Lu writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
138fd3040b9SWells Lu MAC_GUARD_DESC_NUM), comm->l2sw_reg_base + L2SW_RX_HBASE_ADDR_0);
139fd3040b9SWells Lu writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
140fd3040b9SWells Lu MAC_GUARD_DESC_NUM + RX_QUEUE0_DESC_NUM),
141fd3040b9SWells Lu comm->l2sw_reg_base + L2SW_RX_LBASE_ADDR_0);
142fd3040b9SWells Lu
143fd3040b9SWells Lu /* Fc_rls_th=0x4a, Fc_set_th=0x3a, Drop_rls_th=0x2d, Drop_set_th=0x1d */
144fd3040b9SWells Lu writel(0x4a3a2d1d, comm->l2sw_reg_base + L2SW_FL_CNTL_TH);
145fd3040b9SWells Lu
146fd3040b9SWells Lu /* Cpu_rls_th=0x4a, Cpu_set_th=0x3a, Cpu_th=0x12, Port_th=0x12 */
147fd3040b9SWells Lu writel(0x4a3a1212, comm->l2sw_reg_base + L2SW_CPU_FL_CNTL_TH);
148fd3040b9SWells Lu
149fd3040b9SWells Lu /* mtcc_lmt=0xf, Pri_th_l=6, Pri_th_h=6, weigh_8x_en=1 */
150fd3040b9SWells Lu writel(0xf6680000, comm->l2sw_reg_base + L2SW_PRI_FL_CNTL);
151fd3040b9SWells Lu
152fd3040b9SWells Lu /* High-active LED */
153fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_LED_PORT0);
154fd3040b9SWells Lu reg |= MAC_LED_ACT_HI;
155fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0);
156fd3040b9SWells Lu
157fd3040b9SWells Lu /* Disable aging of cpu port 0 & 1.
158fd3040b9SWells Lu * Disable SA learning of cpu port 0 & 1.
159fd3040b9SWells Lu * Enable UC and MC packets
160fd3040b9SWells Lu */
161fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
162fd3040b9SWells Lu reg &= ~(MAC_EN_SOC1_AGING | MAC_EN_SOC0_AGING |
163fd3040b9SWells Lu MAC_DIS_BC2CPU_P1 | MAC_DIS_BC2CPU_P0 |
164fd3040b9SWells Lu MAC_DIS_MC2CPU_P1 | MAC_DIS_MC2CPU_P0);
165fd3040b9SWells Lu reg |= MAC_DIS_LRN_SOC1 | MAC_DIS_LRN_SOC0;
166fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
167fd3040b9SWells Lu
168fd3040b9SWells Lu /* Enable RMC2CPU for port 0 & 1
169fd3040b9SWells Lu * Enable Flow control for port 0 & 1
170fd3040b9SWells Lu * Enable Back pressure for port 0 & 1
171fd3040b9SWells Lu */
172fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
173fd3040b9SWells Lu reg &= ~(MAC_DIS_RMC2CPU_P1 | MAC_DIS_RMC2CPU_P0);
174fd3040b9SWells Lu reg |= MAC_EN_FLOW_CTL_P1 | MAC_EN_FLOW_CTL_P0 |
175fd3040b9SWells Lu MAC_EN_BACK_PRESS_P1 | MAC_EN_BACK_PRESS_P0;
176fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
177fd3040b9SWells Lu
178fd3040b9SWells Lu /* Disable LAN port SA learning. */
179fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL1);
180fd3040b9SWells Lu reg |= MAC_DIS_SA_LRN_P1 | MAC_DIS_SA_LRN_P0;
181fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL1);
182fd3040b9SWells Lu
183fd3040b9SWells Lu /* Enable rmii force mode and
184fd3040b9SWells Lu * set both external phy-address to 31.
185fd3040b9SWells Lu */
186fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
187fd3040b9SWells Lu reg &= ~(MAC_EXT_PHY1_ADDR | MAC_EXT_PHY0_ADDR);
188fd3040b9SWells Lu reg |= FIELD_PREP(MAC_EXT_PHY1_ADDR, 31) | FIELD_PREP(MAC_EXT_PHY0_ADDR, 31);
189fd3040b9SWells Lu reg |= MAC_FORCE_RMII_EN_1 | MAC_FORCE_RMII_EN_0;
190fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
191fd3040b9SWells Lu
192fd3040b9SWells Lu /* Port 0: VLAN group 0
193fd3040b9SWells Lu * Port 1: VLAN group 1
194fd3040b9SWells Lu */
195fd3040b9SWells Lu reg = FIELD_PREP(MAC_P1_PVID, 1) | FIELD_PREP(MAC_P0_PVID, 0);
196fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_PVID_CONFIG0);
197fd3040b9SWells Lu
198fd3040b9SWells Lu /* VLAN group 0: cpu0 (bit3) + port0 (bit0) = 1001 = 0x9
199fd3040b9SWells Lu * VLAN group 1: cpu0 (bit3) + port1 (bit1) = 1010 = 0xa
200fd3040b9SWells Lu */
201fd3040b9SWells Lu reg = FIELD_PREP(MAC_VLAN_MEMSET_1, 0xa) | FIELD_PREP(MAC_VLAN_MEMSET_0, 9);
202fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_VLAN_MEMSET_CONFIG0);
203fd3040b9SWells Lu
204fd3040b9SWells Lu /* RMC forward: to_cpu (1)
205fd3040b9SWells Lu * LED: 60mS (1)
206fd3040b9SWells Lu * BC storm prev: 31 BC (1)
207fd3040b9SWells Lu */
208fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);
209fd3040b9SWells Lu reg &= ~(MAC_RMC_TB_FAULT_RULE | MAC_LED_FLASH_TIME | MAC_BC_STORM_PREV);
210fd3040b9SWells Lu reg |= FIELD_PREP(MAC_RMC_TB_FAULT_RULE, 1) |
211fd3040b9SWells Lu FIELD_PREP(MAC_LED_FLASH_TIME, 1) |
212fd3040b9SWells Lu FIELD_PREP(MAC_BC_STORM_PREV, 1);
213fd3040b9SWells Lu writel(reg, comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);
214fd3040b9SWells Lu
215fd3040b9SWells Lu writel(MAC_INT_MASK_DEF, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
216fd3040b9SWells Lu }
217fd3040b9SWells Lu
spl2sw_mac_rx_mode_set(struct spl2sw_mac * mac)218fd3040b9SWells Lu void spl2sw_mac_rx_mode_set(struct spl2sw_mac *mac)
219fd3040b9SWells Lu {
220fd3040b9SWells Lu struct spl2sw_common *comm = mac->comm;
221fd3040b9SWells Lu struct net_device *ndev = mac->ndev;
222fd3040b9SWells Lu u32 mask, reg, rx_mode;
223fd3040b9SWells Lu
224fd3040b9SWells Lu netdev_dbg(ndev, "ndev->flags = %08x\n", ndev->flags);
225fd3040b9SWells Lu mask = FIELD_PREP(MAC_DIS_MC2CPU, mac->lan_port) |
226fd3040b9SWells Lu FIELD_PREP(MAC_DIS_UN2CPU, mac->lan_port);
227fd3040b9SWells Lu reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
228fd3040b9SWells Lu
229fd3040b9SWells Lu if (ndev->flags & IFF_PROMISC) {
230fd3040b9SWells Lu /* Allow MC and unknown UC packets */
231fd3040b9SWells Lu rx_mode = FIELD_PREP(MAC_DIS_MC2CPU, mac->lan_port) |
232fd3040b9SWells Lu FIELD_PREP(MAC_DIS_UN2CPU, mac->lan_port);
233fd3040b9SWells Lu } else if ((!netdev_mc_empty(ndev) && (ndev->flags & IFF_MULTICAST)) ||
234fd3040b9SWells Lu (ndev->flags & IFF_ALLMULTI)) {
235fd3040b9SWells Lu /* Allow MC packets */
236fd3040b9SWells Lu rx_mode = FIELD_PREP(MAC_DIS_MC2CPU, mac->lan_port);
237fd3040b9SWells Lu } else {
238fd3040b9SWells Lu /* Disable MC and unknown UC packets */
239fd3040b9SWells Lu rx_mode = 0;
240fd3040b9SWells Lu }
241fd3040b9SWells Lu
242fd3040b9SWells Lu writel((reg & (~mask)) | ((~rx_mode) & mask), comm->l2sw_reg_base + L2SW_CPU_CNTL);
243fd3040b9SWells Lu netdev_dbg(ndev, "cpu_cntl = %08x\n", readl(comm->l2sw_reg_base + L2SW_CPU_CNTL));
244fd3040b9SWells Lu }
245fd3040b9SWells Lu
spl2sw_mac_init(struct spl2sw_common * comm)246fd3040b9SWells Lu void spl2sw_mac_init(struct spl2sw_common *comm)
247fd3040b9SWells Lu {
248fd3040b9SWells Lu u32 i;
249fd3040b9SWells Lu
250fd3040b9SWells Lu for (i = 0; i < RX_DESC_QUEUE_NUM; i++)
251fd3040b9SWells Lu comm->rx_pos[i] = 0;
252fd3040b9SWells Lu mb(); /* make sure settings are effective. */
253fd3040b9SWells Lu
254fd3040b9SWells Lu spl2sw_mac_hw_init(comm);
255fd3040b9SWells Lu }
256fd3040b9SWells Lu
spl2sw_mac_soft_reset(struct spl2sw_common * comm)257fd3040b9SWells Lu void spl2sw_mac_soft_reset(struct spl2sw_common *comm)
258fd3040b9SWells Lu {
259fd3040b9SWells Lu u32 i;
260fd3040b9SWells Lu
261fd3040b9SWells Lu spl2sw_mac_hw_stop(comm);
262fd3040b9SWells Lu
263fd3040b9SWells Lu spl2sw_rx_descs_flush(comm);
264fd3040b9SWells Lu comm->tx_pos = 0;
265fd3040b9SWells Lu comm->tx_done_pos = 0;
266fd3040b9SWells Lu comm->tx_desc_full = 0;
267fd3040b9SWells Lu
268fd3040b9SWells Lu for (i = 0; i < RX_DESC_QUEUE_NUM; i++)
269fd3040b9SWells Lu comm->rx_pos[i] = 0;
270fd3040b9SWells Lu mb(); /* make sure settings are effective. */
271fd3040b9SWells Lu
272fd3040b9SWells Lu spl2sw_mac_hw_init(comm);
273fd3040b9SWells Lu spl2sw_mac_hw_start(comm);
274fd3040b9SWells Lu }
275