1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/sys_soc.h> 29 #include <linux/dma/ti-cppi5.h> 30 #include <linux/dma/k3-udma-glue.h> 31 #include <net/switchdev.h> 32 33 #include "cpsw_ale.h" 34 #include "cpsw_sl.h" 35 #include "am65-cpsw-nuss.h" 36 #include "am65-cpsw-switchdev.h" 37 #include "k3-cppi-desc-pool.h" 38 #include "am65-cpts.h" 39 40 #define AM65_CPSW_SS_BASE 0x0 41 #define AM65_CPSW_SGMII_BASE 0x100 42 #define AM65_CPSW_XGMII_BASE 0x2100 43 #define AM65_CPSW_CPSW_NU_BASE 0x20000 44 #define AM65_CPSW_NU_PORTS_BASE 0x1000 45 #define AM65_CPSW_NU_FRAM_BASE 0x12000 46 #define AM65_CPSW_NU_STATS_BASE 0x1a000 47 #define AM65_CPSW_NU_ALE_BASE 0x1e000 48 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 49 50 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 51 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 52 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 53 54 #define AM65_CPSW_MAX_PORTS 8 55 56 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 57 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 58 59 #define AM65_CPSW_REG_CTL 0x004 60 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 61 #define AM65_CPSW_REG_PTYPE 0x018 62 63 #define AM65_CPSW_P0_REG_CTL 0x004 64 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 65 66 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 67 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 68 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 69 70 #define AM65_CPSW_PORTN_REG_SA_L 0x308 71 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 72 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 73 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 74 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 75 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 76 77 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 78 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 79 80 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 81 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 82 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 83 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 84 85 /* AM65_CPSW_P0_REG_CTL */ 86 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 87 88 /* AM65_CPSW_PORT_REG_PRI_CTL */ 89 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 90 91 /* AM65_CPSW_PN_TS_CTL register fields */ 92 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 93 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 95 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 97 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 98 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 99 100 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 101 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 102 103 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 112 113 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 114 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 115 116 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 117 118 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 119 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 120 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 122 123 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 124 /* Number of TX/RX descriptors */ 125 #define AM65_CPSW_MAX_TX_DESC 500 126 #define AM65_CPSW_MAX_RX_DESC 500 127 128 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 129 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 130 131 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 132 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 133 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 134 135 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 136 const u8 *dev_addr) 137 { 138 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 139 (dev_addr[2] << 16) | (dev_addr[3] << 24); 140 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 141 142 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 143 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 144 } 145 146 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 147 { 148 cpsw_sl_reset(port->slave.mac_sl, 100); 149 /* Max length register has to be restored after MAC SL reset */ 150 writel(AM65_CPSW_MAX_PACKET_SIZE, 151 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 152 } 153 154 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 155 { 156 common->nuss_ver = readl(common->ss_base); 157 common->cpsw_ver = readl(common->cpsw_base); 158 dev_info(common->dev, 159 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 160 common->nuss_ver, 161 common->cpsw_ver, 162 common->port_num + 1, 163 common->pdata.quirks); 164 } 165 166 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 167 __be16 proto, u16 vid) 168 { 169 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 170 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 171 u32 port_mask, unreg_mcast = 0; 172 int ret; 173 174 if (!common->is_emac_mode) 175 return 0; 176 177 if (!netif_running(ndev) || !vid) 178 return 0; 179 180 ret = pm_runtime_resume_and_get(common->dev); 181 if (ret < 0) 182 return ret; 183 184 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 185 if (!vid) 186 unreg_mcast = port_mask; 187 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 188 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 189 unreg_mcast, port_mask, 0); 190 191 pm_runtime_put(common->dev); 192 return ret; 193 } 194 195 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 196 __be16 proto, u16 vid) 197 { 198 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 199 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 200 int ret; 201 202 if (!common->is_emac_mode) 203 return 0; 204 205 if (!netif_running(ndev) || !vid) 206 return 0; 207 208 ret = pm_runtime_resume_and_get(common->dev); 209 if (ret < 0) 210 return ret; 211 212 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 213 ret = cpsw_ale_del_vlan(common->ale, vid, 214 BIT(port->port_id) | ALE_PORT_HOST); 215 216 pm_runtime_put(common->dev); 217 return ret; 218 } 219 220 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 221 bool promisc) 222 { 223 struct am65_cpsw_common *common = port->common; 224 225 if (promisc && !common->is_emac_mode) { 226 dev_dbg(common->dev, "promisc mode requested in switch mode"); 227 return; 228 } 229 230 if (promisc) { 231 /* Enable promiscuous mode */ 232 cpsw_ale_control_set(common->ale, port->port_id, 233 ALE_PORT_MACONLY_CAF, 1); 234 dev_dbg(common->dev, "promisc enabled\n"); 235 } else { 236 /* Disable promiscuous mode */ 237 cpsw_ale_control_set(common->ale, port->port_id, 238 ALE_PORT_MACONLY_CAF, 0); 239 dev_dbg(common->dev, "promisc disabled\n"); 240 } 241 } 242 243 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 244 { 245 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 246 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 247 u32 port_mask; 248 bool promisc; 249 250 promisc = !!(ndev->flags & IFF_PROMISC); 251 am65_cpsw_slave_set_promisc(port, promisc); 252 253 if (promisc) 254 return; 255 256 /* Restore allmulti on vlans if necessary */ 257 cpsw_ale_set_allmulti(common->ale, 258 ndev->flags & IFF_ALLMULTI, port->port_id); 259 260 port_mask = ALE_PORT_HOST; 261 /* Clear all mcast from ALE */ 262 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 263 264 if (!netdev_mc_empty(ndev)) { 265 struct netdev_hw_addr *ha; 266 267 /* program multicast address list into ALE register */ 268 netdev_for_each_mc_addr(ha, ndev) { 269 cpsw_ale_add_mcast(common->ale, ha->addr, 270 port_mask, 0, 0, 0); 271 } 272 } 273 } 274 275 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 276 unsigned int txqueue) 277 { 278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 279 struct am65_cpsw_tx_chn *tx_chn; 280 struct netdev_queue *netif_txq; 281 unsigned long trans_start; 282 283 netif_txq = netdev_get_tx_queue(ndev, txqueue); 284 tx_chn = &common->tx_chns[txqueue]; 285 trans_start = READ_ONCE(netif_txq->trans_start); 286 287 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 288 txqueue, 289 netif_tx_queue_stopped(netif_txq), 290 jiffies_to_msecs(jiffies - trans_start), 291 dql_avail(&netif_txq->dql), 292 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 293 294 if (netif_tx_queue_stopped(netif_txq)) { 295 /* try recover if stopped by us */ 296 txq_trans_update(netif_txq); 297 netif_tx_wake_queue(netif_txq); 298 } 299 } 300 301 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 302 struct sk_buff *skb) 303 { 304 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 305 struct cppi5_host_desc_t *desc_rx; 306 struct device *dev = common->dev; 307 u32 pkt_len = skb_tailroom(skb); 308 dma_addr_t desc_dma; 309 dma_addr_t buf_dma; 310 void *swdata; 311 312 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 313 if (!desc_rx) { 314 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 315 return -ENOMEM; 316 } 317 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 318 319 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 320 DMA_FROM_DEVICE); 321 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 322 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 323 dev_err(dev, "Failed to map rx skb buffer\n"); 324 return -EINVAL; 325 } 326 327 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 328 AM65_CPSW_NAV_PS_DATA_SIZE); 329 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 330 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 331 swdata = cppi5_hdesc_get_swdata(desc_rx); 332 *((void **)swdata) = skb; 333 334 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 335 } 336 337 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 338 { 339 struct am65_cpsw_host *host_p = am65_common_get_host(common); 340 u32 val, pri_map; 341 342 /* P0 set Receive Priority Type */ 343 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 344 345 if (common->pf_p0_rx_ptype_rrobin) { 346 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 347 /* Enet Ports fifos works in fixed priority mode only, so 348 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 349 */ 350 pri_map = 0x0; 351 } else { 352 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 353 /* restore P0_Rx_Pri_Map */ 354 pri_map = 0x76543210; 355 } 356 357 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 358 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 359 } 360 361 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 362 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 364 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 365 366 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 367 { 368 struct am65_cpsw_host *host_p = am65_common_get_host(common); 369 int port_idx, i, ret; 370 struct sk_buff *skb; 371 u32 val, port_mask; 372 373 if (common->usage_count) 374 return 0; 375 376 /* Control register */ 377 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 378 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 379 common->cpsw_base + AM65_CPSW_REG_CTL); 380 /* Max length register */ 381 writel(AM65_CPSW_MAX_PACKET_SIZE, 382 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 383 /* set base flow_id */ 384 writel(common->rx_flow_id_base, 385 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 386 /* en tx crc offload */ 387 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 388 389 am65_cpsw_nuss_set_p0_ptype(common); 390 391 /* enable statistic */ 392 val = BIT(HOST_PORT_NUM); 393 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 394 struct am65_cpsw_port *port = &common->ports[port_idx]; 395 396 if (!port->disabled) 397 val |= BIT(port->port_id); 398 } 399 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 400 401 /* disable priority elevation */ 402 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 403 404 cpsw_ale_start(common->ale); 405 406 /* limit to one RX flow only */ 407 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 408 ALE_DEFAULT_THREAD_ID, 0); 409 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 410 ALE_DEFAULT_THREAD_ENABLE, 1); 411 /* switch to vlan unaware mode */ 412 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 414 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 415 416 /* default vlan cfg: create mask based on enabled ports */ 417 port_mask = GENMASK(common->port_num, 0) & 418 ~common->disabled_ports_mask; 419 420 cpsw_ale_add_vlan(common->ale, 0, port_mask, 421 port_mask, port_mask, 422 port_mask & ~ALE_PORT_HOST); 423 424 if (common->is_emac_mode) 425 am65_cpsw_init_host_port_emac(common); 426 else 427 am65_cpsw_init_host_port_switch(common); 428 429 for (i = 0; i < common->rx_chns.descs_num; i++) { 430 skb = __netdev_alloc_skb_ip_align(NULL, 431 AM65_CPSW_MAX_PACKET_SIZE, 432 GFP_KERNEL); 433 if (!skb) { 434 dev_err(common->dev, "cannot allocate skb\n"); 435 return -ENOMEM; 436 } 437 438 ret = am65_cpsw_nuss_rx_push(common, skb); 439 if (ret < 0) { 440 dev_err(common->dev, 441 "cannot submit skb to channel rx, error %d\n", 442 ret); 443 kfree_skb(skb); 444 return ret; 445 } 446 kmemleak_not_leak(skb); 447 } 448 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 449 450 for (i = 0; i < common->tx_ch_num; i++) { 451 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 452 if (ret) 453 return ret; 454 napi_enable(&common->tx_chns[i].napi_tx); 455 } 456 457 napi_enable(&common->napi_rx); 458 if (common->rx_irq_disabled) { 459 common->rx_irq_disabled = false; 460 enable_irq(common->rx_chns.irq); 461 } 462 463 dev_dbg(common->dev, "cpsw_nuss started\n"); 464 return 0; 465 } 466 467 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 468 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 469 470 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 471 { 472 int i; 473 474 if (common->usage_count != 1) 475 return 0; 476 477 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 478 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 479 480 /* shutdown tx channels */ 481 atomic_set(&common->tdown_cnt, common->tx_ch_num); 482 /* ensure new tdown_cnt value is visible */ 483 smp_mb__after_atomic(); 484 reinit_completion(&common->tdown_complete); 485 486 for (i = 0; i < common->tx_ch_num; i++) 487 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 488 489 i = wait_for_completion_timeout(&common->tdown_complete, 490 msecs_to_jiffies(1000)); 491 if (!i) 492 dev_err(common->dev, "tx timeout\n"); 493 for (i = 0; i < common->tx_ch_num; i++) 494 napi_disable(&common->tx_chns[i].napi_tx); 495 496 for (i = 0; i < common->tx_ch_num; i++) { 497 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 498 &common->tx_chns[i], 499 am65_cpsw_nuss_tx_cleanup); 500 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 501 } 502 503 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 504 napi_disable(&common->napi_rx); 505 506 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 507 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 508 &common->rx_chns, 509 am65_cpsw_nuss_rx_cleanup, !!i); 510 511 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 512 513 cpsw_ale_stop(common->ale); 514 515 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 516 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 517 518 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 519 return 0; 520 } 521 522 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 523 { 524 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 525 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 526 int ret; 527 528 phylink_stop(port->slave.phylink); 529 530 netif_tx_stop_all_queues(ndev); 531 532 phylink_disconnect_phy(port->slave.phylink); 533 534 ret = am65_cpsw_nuss_common_stop(common); 535 if (ret) 536 return ret; 537 538 common->usage_count--; 539 pm_runtime_put(common->dev); 540 return 0; 541 } 542 543 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 544 { 545 struct am65_cpsw_port *port = arg; 546 547 if (!vdev) 548 return 0; 549 550 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 551 } 552 553 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 554 { 555 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 556 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 557 int ret, i; 558 559 ret = pm_runtime_resume_and_get(common->dev); 560 if (ret < 0) 561 return ret; 562 563 /* Notify the stack of the actual queue counts. */ 564 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 565 if (ret) { 566 dev_err(common->dev, "cannot set real number of tx queues\n"); 567 return ret; 568 } 569 570 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 571 if (ret) { 572 dev_err(common->dev, "cannot set real number of rx queues\n"); 573 return ret; 574 } 575 576 for (i = 0; i < common->tx_ch_num; i++) 577 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 578 579 ret = am65_cpsw_nuss_common_open(common); 580 if (ret) 581 return ret; 582 583 common->usage_count++; 584 585 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 586 587 if (common->is_emac_mode) 588 am65_cpsw_init_port_emac_ale(port); 589 else 590 am65_cpsw_init_port_switch_ale(port); 591 592 /* mac_sl should be configured via phy-link interface */ 593 am65_cpsw_sl_ctl_reset(port); 594 595 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 596 if (ret) 597 goto error_cleanup; 598 599 /* restore vlan configurations */ 600 vlan_for_each(ndev, cpsw_restore_vlans, port); 601 602 phylink_start(port->slave.phylink); 603 604 return 0; 605 606 error_cleanup: 607 am65_cpsw_nuss_ndo_slave_stop(ndev); 608 return ret; 609 } 610 611 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 612 { 613 struct am65_cpsw_rx_chn *rx_chn = data; 614 struct cppi5_host_desc_t *desc_rx; 615 struct sk_buff *skb; 616 dma_addr_t buf_dma; 617 u32 buf_dma_len; 618 void **swdata; 619 620 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 621 swdata = cppi5_hdesc_get_swdata(desc_rx); 622 skb = *swdata; 623 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 624 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 625 626 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 627 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 628 629 dev_kfree_skb_any(skb); 630 } 631 632 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 633 { 634 struct skb_shared_hwtstamps *ssh; 635 u64 ns; 636 637 ns = ((u64)psdata[1] << 32) | psdata[0]; 638 639 ssh = skb_hwtstamps(skb); 640 memset(ssh, 0, sizeof(*ssh)); 641 ssh->hwtstamp = ns_to_ktime(ns); 642 } 643 644 /* RX psdata[2] word format - checksum information */ 645 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 646 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 647 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 648 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 649 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 650 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 651 652 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 653 { 654 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 655 * csum information provides in psdata[2] word: 656 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 657 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 658 * bits - indicates IPv4/IPv6 packet 659 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 660 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 661 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 662 */ 663 skb_checksum_none_assert(skb); 664 665 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 666 return; 667 668 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 669 AM65_CPSW_RX_PSD_IPV4_VALID)) && 670 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 671 /* csum for fragmented packets is unsupported */ 672 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 673 skb->ip_summed = CHECKSUM_UNNECESSARY; 674 } 675 } 676 677 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 678 u32 flow_idx) 679 { 680 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 681 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 682 struct am65_cpsw_ndev_priv *ndev_priv; 683 struct am65_cpsw_ndev_stats *stats; 684 struct cppi5_host_desc_t *desc_rx; 685 struct device *dev = common->dev; 686 struct sk_buff *skb, *new_skb; 687 dma_addr_t desc_dma, buf_dma; 688 struct am65_cpsw_port *port; 689 struct net_device *ndev; 690 void **swdata; 691 u32 *psdata; 692 int ret = 0; 693 694 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 695 if (ret) { 696 if (ret != -ENODATA) 697 dev_err(dev, "RX: pop chn fail %d\n", ret); 698 return ret; 699 } 700 701 if (cppi5_desc_is_tdcm(desc_dma)) { 702 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 703 return 0; 704 } 705 706 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 707 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 708 __func__, flow_idx, &desc_dma); 709 710 swdata = cppi5_hdesc_get_swdata(desc_rx); 711 skb = *swdata; 712 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 713 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 714 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 715 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 716 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 717 port = am65_common_get_port(common, port_id); 718 ndev = port->ndev; 719 skb->dev = ndev; 720 721 psdata = cppi5_hdesc_get_psdata(desc_rx); 722 /* add RX timestamp */ 723 if (port->rx_ts_enabled) 724 am65_cpsw_nuss_rx_ts(skb, psdata); 725 csum_info = psdata[2]; 726 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 727 728 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 729 730 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 731 732 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 733 if (new_skb) { 734 ndev_priv = netdev_priv(ndev); 735 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 736 skb_put(skb, pkt_len); 737 skb->protocol = eth_type_trans(skb, ndev); 738 am65_cpsw_nuss_rx_csum(skb, csum_info); 739 napi_gro_receive(&common->napi_rx, skb); 740 741 stats = this_cpu_ptr(ndev_priv->stats); 742 743 u64_stats_update_begin(&stats->syncp); 744 stats->rx_packets++; 745 stats->rx_bytes += pkt_len; 746 u64_stats_update_end(&stats->syncp); 747 kmemleak_not_leak(new_skb); 748 } else { 749 ndev->stats.rx_dropped++; 750 new_skb = skb; 751 } 752 753 if (netif_dormant(ndev)) { 754 dev_kfree_skb_any(new_skb); 755 ndev->stats.rx_dropped++; 756 return 0; 757 } 758 759 ret = am65_cpsw_nuss_rx_push(common, new_skb); 760 if (WARN_ON(ret < 0)) { 761 dev_kfree_skb_any(new_skb); 762 ndev->stats.rx_errors++; 763 ndev->stats.rx_dropped++; 764 } 765 766 return ret; 767 } 768 769 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 770 { 771 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 772 int flow = AM65_CPSW_MAX_RX_FLOWS; 773 int cur_budget, ret; 774 int num_rx = 0; 775 776 /* process every flow */ 777 while (flow--) { 778 cur_budget = budget - num_rx; 779 780 while (cur_budget--) { 781 ret = am65_cpsw_nuss_rx_packets(common, flow); 782 if (ret) 783 break; 784 num_rx++; 785 } 786 787 if (num_rx >= budget) 788 break; 789 } 790 791 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 792 793 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 794 if (common->rx_irq_disabled) { 795 common->rx_irq_disabled = false; 796 enable_irq(common->rx_chns.irq); 797 } 798 } 799 800 return num_rx; 801 } 802 803 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 804 struct cppi5_host_desc_t *desc) 805 { 806 struct cppi5_host_desc_t *first_desc, *next_desc; 807 dma_addr_t buf_dma, next_desc_dma; 808 u32 buf_dma_len; 809 810 first_desc = desc; 811 next_desc = first_desc; 812 813 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 814 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 815 816 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 817 818 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 819 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 820 while (next_desc_dma) { 821 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 822 next_desc_dma); 823 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 824 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 825 826 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 827 DMA_TO_DEVICE); 828 829 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 830 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 831 832 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 833 } 834 835 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 836 } 837 838 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 839 { 840 struct am65_cpsw_tx_chn *tx_chn = data; 841 struct cppi5_host_desc_t *desc_tx; 842 struct sk_buff *skb; 843 void **swdata; 844 845 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 846 swdata = cppi5_hdesc_get_swdata(desc_tx); 847 skb = *(swdata); 848 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 849 850 dev_kfree_skb_any(skb); 851 } 852 853 static struct sk_buff * 854 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 855 dma_addr_t desc_dma) 856 { 857 struct am65_cpsw_ndev_priv *ndev_priv; 858 struct am65_cpsw_ndev_stats *stats; 859 struct cppi5_host_desc_t *desc_tx; 860 struct net_device *ndev; 861 struct sk_buff *skb; 862 void **swdata; 863 864 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 865 desc_dma); 866 swdata = cppi5_hdesc_get_swdata(desc_tx); 867 skb = *(swdata); 868 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 869 870 ndev = skb->dev; 871 872 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 873 874 ndev_priv = netdev_priv(ndev); 875 stats = this_cpu_ptr(ndev_priv->stats); 876 u64_stats_update_begin(&stats->syncp); 877 stats->tx_packets++; 878 stats->tx_bytes += skb->len; 879 u64_stats_update_end(&stats->syncp); 880 881 return skb; 882 } 883 884 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 885 struct netdev_queue *netif_txq) 886 { 887 if (netif_tx_queue_stopped(netif_txq)) { 888 /* Check whether the queue is stopped due to stalled 889 * tx dma, if the queue is stopped then wake the queue 890 * as we have free desc for tx 891 */ 892 __netif_tx_lock(netif_txq, smp_processor_id()); 893 if (netif_running(ndev) && 894 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 895 netif_tx_wake_queue(netif_txq); 896 897 __netif_tx_unlock(netif_txq); 898 } 899 } 900 901 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 902 int chn, unsigned int budget) 903 { 904 struct device *dev = common->dev; 905 struct am65_cpsw_tx_chn *tx_chn; 906 struct netdev_queue *netif_txq; 907 unsigned int total_bytes = 0; 908 struct net_device *ndev; 909 struct sk_buff *skb; 910 dma_addr_t desc_dma; 911 int res, num_tx = 0; 912 913 tx_chn = &common->tx_chns[chn]; 914 915 while (true) { 916 spin_lock(&tx_chn->lock); 917 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 918 spin_unlock(&tx_chn->lock); 919 if (res == -ENODATA) 920 break; 921 922 if (cppi5_desc_is_tdcm(desc_dma)) { 923 if (atomic_dec_and_test(&common->tdown_cnt)) 924 complete(&common->tdown_complete); 925 break; 926 } 927 928 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 929 total_bytes = skb->len; 930 ndev = skb->dev; 931 napi_consume_skb(skb, budget); 932 num_tx++; 933 934 netif_txq = netdev_get_tx_queue(ndev, chn); 935 936 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 937 938 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 939 } 940 941 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 942 943 return num_tx; 944 } 945 946 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 947 int chn, unsigned int budget) 948 { 949 struct device *dev = common->dev; 950 struct am65_cpsw_tx_chn *tx_chn; 951 struct netdev_queue *netif_txq; 952 unsigned int total_bytes = 0; 953 struct net_device *ndev; 954 struct sk_buff *skb; 955 dma_addr_t desc_dma; 956 int res, num_tx = 0; 957 958 tx_chn = &common->tx_chns[chn]; 959 960 while (true) { 961 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 962 if (res == -ENODATA) 963 break; 964 965 if (cppi5_desc_is_tdcm(desc_dma)) { 966 if (atomic_dec_and_test(&common->tdown_cnt)) 967 complete(&common->tdown_complete); 968 break; 969 } 970 971 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 972 973 ndev = skb->dev; 974 total_bytes += skb->len; 975 napi_consume_skb(skb, budget); 976 num_tx++; 977 } 978 979 if (!num_tx) 980 return 0; 981 982 netif_txq = netdev_get_tx_queue(ndev, chn); 983 984 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 985 986 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 987 988 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 989 990 return num_tx; 991 } 992 993 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 994 { 995 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 996 int num_tx; 997 998 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 999 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1000 else 1001 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1002 1003 if (num_tx >= budget) 1004 return budget; 1005 1006 if (napi_complete_done(napi_tx, num_tx)) 1007 enable_irq(tx_chn->irq); 1008 1009 return 0; 1010 } 1011 1012 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1013 { 1014 struct am65_cpsw_common *common = dev_id; 1015 1016 common->rx_irq_disabled = true; 1017 disable_irq_nosync(irq); 1018 napi_schedule(&common->napi_rx); 1019 1020 return IRQ_HANDLED; 1021 } 1022 1023 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1024 { 1025 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1026 1027 disable_irq_nosync(irq); 1028 napi_schedule(&tx_chn->napi_tx); 1029 1030 return IRQ_HANDLED; 1031 } 1032 1033 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1034 struct net_device *ndev) 1035 { 1036 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1037 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1038 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1039 struct device *dev = common->dev; 1040 struct am65_cpsw_tx_chn *tx_chn; 1041 struct netdev_queue *netif_txq; 1042 dma_addr_t desc_dma, buf_dma; 1043 int ret, q_idx, i; 1044 void **swdata; 1045 u32 *psdata; 1046 u32 pkt_len; 1047 1048 /* padding enabled in hw */ 1049 pkt_len = skb_headlen(skb); 1050 1051 /* SKB TX timestamp */ 1052 if (port->tx_ts_enabled) 1053 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1054 1055 q_idx = skb_get_queue_mapping(skb); 1056 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1057 1058 tx_chn = &common->tx_chns[q_idx]; 1059 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1060 1061 /* Map the linear buffer */ 1062 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1063 DMA_TO_DEVICE); 1064 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1065 dev_err(dev, "Failed to map tx skb buffer\n"); 1066 ndev->stats.tx_errors++; 1067 goto err_free_skb; 1068 } 1069 1070 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1071 if (!first_desc) { 1072 dev_dbg(dev, "Failed to allocate descriptor\n"); 1073 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1074 DMA_TO_DEVICE); 1075 goto busy_stop_q; 1076 } 1077 1078 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1079 AM65_CPSW_NAV_PS_DATA_SIZE); 1080 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1081 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1082 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1083 1084 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1085 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1086 swdata = cppi5_hdesc_get_swdata(first_desc); 1087 *(swdata) = skb; 1088 psdata = cppi5_hdesc_get_psdata(first_desc); 1089 1090 /* HW csum offload if enabled */ 1091 psdata[2] = 0; 1092 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1093 unsigned int cs_start, cs_offset; 1094 1095 cs_start = skb_transport_offset(skb); 1096 cs_offset = cs_start + skb->csum_offset; 1097 /* HW numerates bytes starting from 1 */ 1098 psdata[2] = ((cs_offset + 1) << 24) | 1099 ((cs_start + 1) << 16) | (skb->len - cs_start); 1100 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1101 } 1102 1103 if (!skb_is_nonlinear(skb)) 1104 goto done_tx; 1105 1106 dev_dbg(dev, "fragmented SKB\n"); 1107 1108 /* Handle the case where skb is fragmented in pages */ 1109 cur_desc = first_desc; 1110 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1111 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1112 u32 frag_size = skb_frag_size(frag); 1113 1114 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1115 if (!next_desc) { 1116 dev_err(dev, "Failed to allocate descriptor\n"); 1117 goto busy_free_descs; 1118 } 1119 1120 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1121 DMA_TO_DEVICE); 1122 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1123 dev_err(dev, "Failed to map tx skb page\n"); 1124 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1125 ndev->stats.tx_errors++; 1126 goto err_free_descs; 1127 } 1128 1129 cppi5_hdesc_reset_hbdesc(next_desc); 1130 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1131 cppi5_hdesc_attach_buf(next_desc, 1132 buf_dma, frag_size, buf_dma, frag_size); 1133 1134 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1135 next_desc); 1136 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1137 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1138 1139 pkt_len += frag_size; 1140 cur_desc = next_desc; 1141 } 1142 WARN_ON(pkt_len != skb->len); 1143 1144 done_tx: 1145 skb_tx_timestamp(skb); 1146 1147 /* report bql before sending packet */ 1148 netdev_tx_sent_queue(netif_txq, pkt_len); 1149 1150 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1151 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1152 if (AM65_CPSW_IS_CPSW2G(common)) { 1153 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1154 } else { 1155 spin_lock_bh(&tx_chn->lock); 1156 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1157 spin_unlock_bh(&tx_chn->lock); 1158 } 1159 if (ret) { 1160 dev_err(dev, "can't push desc %d\n", ret); 1161 /* inform bql */ 1162 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1163 ndev->stats.tx_errors++; 1164 goto err_free_descs; 1165 } 1166 1167 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1168 netif_tx_stop_queue(netif_txq); 1169 /* Barrier, so that stop_queue visible to other cpus */ 1170 smp_mb__after_atomic(); 1171 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1172 1173 /* re-check for smp */ 1174 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1175 MAX_SKB_FRAGS) { 1176 netif_tx_wake_queue(netif_txq); 1177 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1178 } 1179 } 1180 1181 return NETDEV_TX_OK; 1182 1183 err_free_descs: 1184 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1185 err_free_skb: 1186 ndev->stats.tx_dropped++; 1187 dev_kfree_skb_any(skb); 1188 return NETDEV_TX_OK; 1189 1190 busy_free_descs: 1191 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1192 busy_stop_q: 1193 netif_tx_stop_queue(netif_txq); 1194 return NETDEV_TX_BUSY; 1195 } 1196 1197 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1198 void *addr) 1199 { 1200 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1201 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1202 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1203 int ret; 1204 1205 ret = eth_prepare_mac_addr_change(ndev, addr); 1206 if (ret < 0) 1207 return ret; 1208 1209 ret = pm_runtime_resume_and_get(common->dev); 1210 if (ret < 0) 1211 return ret; 1212 1213 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1214 HOST_PORT_NUM, 0, 0); 1215 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1216 HOST_PORT_NUM, ALE_SECURE, 0); 1217 1218 am65_cpsw_port_set_sl_mac(port, addr); 1219 eth_commit_mac_addr_change(ndev, sockaddr); 1220 1221 pm_runtime_put(common->dev); 1222 1223 return 0; 1224 } 1225 1226 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1227 struct ifreq *ifr) 1228 { 1229 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1230 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1231 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1232 struct hwtstamp_config cfg; 1233 1234 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1235 return -EOPNOTSUPP; 1236 1237 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1238 return -EFAULT; 1239 1240 /* TX HW timestamp */ 1241 switch (cfg.tx_type) { 1242 case HWTSTAMP_TX_OFF: 1243 case HWTSTAMP_TX_ON: 1244 break; 1245 default: 1246 return -ERANGE; 1247 } 1248 1249 switch (cfg.rx_filter) { 1250 case HWTSTAMP_FILTER_NONE: 1251 port->rx_ts_enabled = false; 1252 break; 1253 case HWTSTAMP_FILTER_ALL: 1254 case HWTSTAMP_FILTER_SOME: 1255 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1256 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1257 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1258 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1259 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1260 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1261 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1262 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1263 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1264 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1265 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1266 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1267 case HWTSTAMP_FILTER_NTP_ALL: 1268 port->rx_ts_enabled = true; 1269 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1270 break; 1271 default: 1272 return -ERANGE; 1273 } 1274 1275 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1276 1277 /* cfg TX timestamp */ 1278 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1279 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1280 1281 ts_vlan_ltype = ETH_P_8021Q; 1282 1283 ts_ctrl_ltype2 = ETH_P_1588 | 1284 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1285 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1286 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1287 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1288 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1289 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1290 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1291 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1292 1293 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1294 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1295 1296 if (port->tx_ts_enabled) 1297 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1298 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1299 1300 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1301 writel(ts_vlan_ltype, port->port_base + 1302 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1303 writel(ts_ctrl_ltype2, port->port_base + 1304 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1305 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1306 1307 /* en/dis RX timestamp */ 1308 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1309 1310 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1311 } 1312 1313 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1314 struct ifreq *ifr) 1315 { 1316 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1317 struct hwtstamp_config cfg; 1318 1319 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1320 return -EOPNOTSUPP; 1321 1322 cfg.flags = 0; 1323 cfg.tx_type = port->tx_ts_enabled ? 1324 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1325 cfg.rx_filter = port->rx_ts_enabled ? 1326 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1327 1328 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1329 } 1330 1331 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1332 struct ifreq *req, int cmd) 1333 { 1334 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1335 1336 if (!netif_running(ndev)) 1337 return -EINVAL; 1338 1339 switch (cmd) { 1340 case SIOCSHWTSTAMP: 1341 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1342 case SIOCGHWTSTAMP: 1343 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1344 } 1345 1346 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1347 } 1348 1349 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1350 struct rtnl_link_stats64 *stats) 1351 { 1352 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1353 unsigned int start; 1354 int cpu; 1355 1356 for_each_possible_cpu(cpu) { 1357 struct am65_cpsw_ndev_stats *cpu_stats; 1358 u64 rx_packets; 1359 u64 rx_bytes; 1360 u64 tx_packets; 1361 u64 tx_bytes; 1362 1363 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1364 do { 1365 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1366 rx_packets = cpu_stats->rx_packets; 1367 rx_bytes = cpu_stats->rx_bytes; 1368 tx_packets = cpu_stats->tx_packets; 1369 tx_bytes = cpu_stats->tx_bytes; 1370 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1371 1372 stats->rx_packets += rx_packets; 1373 stats->rx_bytes += rx_bytes; 1374 stats->tx_packets += tx_packets; 1375 stats->tx_bytes += tx_bytes; 1376 } 1377 1378 stats->rx_errors = dev->stats.rx_errors; 1379 stats->rx_dropped = dev->stats.rx_dropped; 1380 stats->tx_dropped = dev->stats.tx_dropped; 1381 } 1382 1383 static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev) 1384 { 1385 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1386 1387 return &port->devlink_port; 1388 } 1389 1390 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1391 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1392 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1393 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1394 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1395 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1396 .ndo_validate_addr = eth_validate_addr, 1397 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1398 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1399 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1400 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1401 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1402 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1403 .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, 1404 }; 1405 1406 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1407 const struct phylink_link_state *state) 1408 { 1409 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1410 phylink_config); 1411 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1412 struct am65_cpsw_common *common = port->common; 1413 1414 if (common->pdata.extra_modes & BIT(state->interface)) 1415 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1416 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1417 } 1418 1419 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1420 phy_interface_t interface) 1421 { 1422 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1423 phylink_config); 1424 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1425 struct am65_cpsw_common *common = port->common; 1426 struct net_device *ndev = port->ndev; 1427 int tmo; 1428 1429 /* disable forwarding */ 1430 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1431 1432 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1433 1434 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1435 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1436 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1437 1438 cpsw_sl_ctl_reset(port->slave.mac_sl); 1439 1440 am65_cpsw_qos_link_down(ndev); 1441 netif_tx_stop_all_queues(ndev); 1442 } 1443 1444 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1445 unsigned int mode, phy_interface_t interface, int speed, 1446 int duplex, bool tx_pause, bool rx_pause) 1447 { 1448 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1449 phylink_config); 1450 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1451 struct am65_cpsw_common *common = port->common; 1452 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1453 struct net_device *ndev = port->ndev; 1454 1455 if (speed == SPEED_1000) 1456 mac_control |= CPSW_SL_CTL_GIG; 1457 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1458 /* Can be used with in band mode only */ 1459 mac_control |= CPSW_SL_CTL_EXT_EN; 1460 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1461 mac_control |= CPSW_SL_CTL_IFCTL_A; 1462 if (duplex) 1463 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1464 1465 /* rx_pause/tx_pause */ 1466 if (rx_pause) 1467 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1468 1469 if (tx_pause) 1470 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1471 1472 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1473 1474 /* enable forwarding */ 1475 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1476 1477 am65_cpsw_qos_link_up(ndev, speed); 1478 netif_tx_wake_all_queues(ndev); 1479 } 1480 1481 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1482 .validate = phylink_generic_validate, 1483 .mac_config = am65_cpsw_nuss_mac_config, 1484 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1485 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1486 }; 1487 1488 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1489 { 1490 struct am65_cpsw_common *common = port->common; 1491 1492 if (!port->disabled) 1493 return; 1494 1495 cpsw_ale_control_set(common->ale, port->port_id, 1496 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1497 1498 cpsw_sl_reset(port->slave.mac_sl, 100); 1499 cpsw_sl_ctl_reset(port->slave.mac_sl); 1500 } 1501 1502 static void am65_cpsw_nuss_free_tx_chns(void *data) 1503 { 1504 struct am65_cpsw_common *common = data; 1505 int i; 1506 1507 for (i = 0; i < common->tx_ch_num; i++) { 1508 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1509 1510 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1511 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1512 1513 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1514 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1515 1516 memset(tx_chn, 0, sizeof(*tx_chn)); 1517 } 1518 } 1519 1520 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1521 { 1522 struct device *dev = common->dev; 1523 int i; 1524 1525 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1526 1527 for (i = 0; i < common->tx_ch_num; i++) { 1528 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1529 1530 if (tx_chn->irq) 1531 devm_free_irq(dev, tx_chn->irq, tx_chn); 1532 1533 netif_napi_del(&tx_chn->napi_tx); 1534 1535 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1536 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1537 1538 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1539 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1540 1541 memset(tx_chn, 0, sizeof(*tx_chn)); 1542 } 1543 } 1544 1545 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1546 { 1547 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1548 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1549 struct device *dev = common->dev; 1550 struct k3_ring_cfg ring_cfg = { 1551 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1552 .mode = K3_RINGACC_RING_MODE_RING, 1553 .flags = 0 1554 }; 1555 u32 hdesc_size; 1556 int i, ret = 0; 1557 1558 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1559 AM65_CPSW_NAV_SW_DATA_SIZE); 1560 1561 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1562 tx_cfg.tx_cfg = ring_cfg; 1563 tx_cfg.txcq_cfg = ring_cfg; 1564 tx_cfg.tx_cfg.size = max_desc_num; 1565 tx_cfg.txcq_cfg.size = max_desc_num; 1566 1567 for (i = 0; i < common->tx_ch_num; i++) { 1568 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1569 1570 snprintf(tx_chn->tx_chn_name, 1571 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1572 1573 spin_lock_init(&tx_chn->lock); 1574 tx_chn->common = common; 1575 tx_chn->id = i; 1576 tx_chn->descs_num = max_desc_num; 1577 1578 tx_chn->tx_chn = 1579 k3_udma_glue_request_tx_chn(dev, 1580 tx_chn->tx_chn_name, 1581 &tx_cfg); 1582 if (IS_ERR(tx_chn->tx_chn)) { 1583 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1584 "Failed to request tx dma channel\n"); 1585 goto err; 1586 } 1587 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1588 1589 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1590 tx_chn->descs_num, 1591 hdesc_size, 1592 tx_chn->tx_chn_name); 1593 if (IS_ERR(tx_chn->desc_pool)) { 1594 ret = PTR_ERR(tx_chn->desc_pool); 1595 dev_err(dev, "Failed to create poll %d\n", ret); 1596 goto err; 1597 } 1598 1599 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1600 if (tx_chn->irq <= 0) { 1601 dev_err(dev, "Failed to get tx dma irq %d\n", 1602 tx_chn->irq); 1603 goto err; 1604 } 1605 1606 snprintf(tx_chn->tx_chn_name, 1607 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1608 dev_name(dev), tx_chn->id); 1609 } 1610 1611 err: 1612 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1613 if (i) { 1614 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1615 return i; 1616 } 1617 1618 return ret; 1619 } 1620 1621 static void am65_cpsw_nuss_free_rx_chns(void *data) 1622 { 1623 struct am65_cpsw_common *common = data; 1624 struct am65_cpsw_rx_chn *rx_chn; 1625 1626 rx_chn = &common->rx_chns; 1627 1628 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1629 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1630 1631 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1632 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1633 } 1634 1635 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1636 { 1637 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1638 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1639 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1640 struct device *dev = common->dev; 1641 u32 hdesc_size; 1642 u32 fdqring_id; 1643 int i, ret = 0; 1644 1645 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1646 AM65_CPSW_NAV_SW_DATA_SIZE); 1647 1648 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1649 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1650 rx_cfg.flow_id_base = common->rx_flow_id_base; 1651 1652 /* init all flows */ 1653 rx_chn->dev = dev; 1654 rx_chn->descs_num = max_desc_num; 1655 1656 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1657 if (IS_ERR(rx_chn->rx_chn)) { 1658 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1659 "Failed to request rx dma channel\n"); 1660 goto err; 1661 } 1662 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1663 1664 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1665 rx_chn->descs_num, 1666 hdesc_size, "rx"); 1667 if (IS_ERR(rx_chn->desc_pool)) { 1668 ret = PTR_ERR(rx_chn->desc_pool); 1669 dev_err(dev, "Failed to create rx poll %d\n", ret); 1670 goto err; 1671 } 1672 1673 common->rx_flow_id_base = 1674 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1675 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1676 1677 fdqring_id = K3_RINGACC_RING_ID_ANY; 1678 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1679 struct k3_ring_cfg rxring_cfg = { 1680 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1681 .mode = K3_RINGACC_RING_MODE_RING, 1682 .flags = 0, 1683 }; 1684 struct k3_ring_cfg fdqring_cfg = { 1685 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1686 .flags = K3_RINGACC_RING_SHARED, 1687 }; 1688 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1689 .rx_cfg = rxring_cfg, 1690 .rxfdq_cfg = fdqring_cfg, 1691 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1692 .src_tag_lo_sel = 1693 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1694 }; 1695 1696 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1697 rx_flow_cfg.rx_cfg.size = max_desc_num; 1698 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1699 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1700 1701 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1702 i, &rx_flow_cfg); 1703 if (ret) { 1704 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1705 goto err; 1706 } 1707 if (!i) 1708 fdqring_id = 1709 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1710 i); 1711 1712 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1713 1714 if (rx_chn->irq <= 0) { 1715 dev_err(dev, "Failed to get rx dma irq %d\n", 1716 rx_chn->irq); 1717 ret = -ENXIO; 1718 goto err; 1719 } 1720 } 1721 1722 err: 1723 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1724 if (i) { 1725 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1726 return i; 1727 } 1728 1729 return ret; 1730 } 1731 1732 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1733 { 1734 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1735 1736 host_p->common = common; 1737 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1738 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1739 1740 return 0; 1741 } 1742 1743 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1744 int slave, u8 *mac_addr) 1745 { 1746 u32 mac_lo, mac_hi, offset; 1747 struct regmap *syscon; 1748 int ret; 1749 1750 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1751 if (IS_ERR(syscon)) { 1752 if (PTR_ERR(syscon) == -ENODEV) 1753 return 0; 1754 return PTR_ERR(syscon); 1755 } 1756 1757 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1758 &offset); 1759 if (ret) 1760 return ret; 1761 1762 regmap_read(syscon, offset, &mac_lo); 1763 regmap_read(syscon, offset + 4, &mac_hi); 1764 1765 mac_addr[0] = (mac_hi >> 8) & 0xff; 1766 mac_addr[1] = mac_hi & 0xff; 1767 mac_addr[2] = (mac_lo >> 24) & 0xff; 1768 mac_addr[3] = (mac_lo >> 16) & 0xff; 1769 mac_addr[4] = (mac_lo >> 8) & 0xff; 1770 mac_addr[5] = mac_lo & 0xff; 1771 1772 return 0; 1773 } 1774 1775 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1776 { 1777 struct device *dev = common->dev; 1778 struct device_node *node; 1779 struct am65_cpts *cpts; 1780 void __iomem *reg_base; 1781 1782 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1783 return 0; 1784 1785 node = of_get_child_by_name(dev->of_node, "cpts"); 1786 if (!node) { 1787 dev_err(dev, "%s cpts not found\n", __func__); 1788 return -ENOENT; 1789 } 1790 1791 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1792 cpts = am65_cpts_create(dev, reg_base, node); 1793 if (IS_ERR(cpts)) { 1794 int ret = PTR_ERR(cpts); 1795 1796 of_node_put(node); 1797 if (ret == -EOPNOTSUPP) { 1798 dev_info(dev, "cpts disabled\n"); 1799 return 0; 1800 } 1801 1802 dev_err(dev, "cpts create err %d\n", ret); 1803 return ret; 1804 } 1805 common->cpts = cpts; 1806 /* Forbid PM runtime if CPTS is running. 1807 * K3 CPSWxG modules may completely lose context during ON->OFF 1808 * transitions depending on integration. 1809 * AM65x/J721E MCU CPSW2G: false 1810 * J721E MAIN_CPSW9G: true 1811 */ 1812 pm_runtime_forbid(dev); 1813 1814 return 0; 1815 } 1816 1817 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1818 { 1819 struct device_node *node, *port_np; 1820 struct device *dev = common->dev; 1821 int ret; 1822 1823 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1824 if (!node) 1825 return -ENOENT; 1826 1827 for_each_child_of_node(node, port_np) { 1828 struct am65_cpsw_port *port; 1829 u32 port_id; 1830 1831 /* it is not a slave port node, continue */ 1832 if (strcmp(port_np->name, "port")) 1833 continue; 1834 1835 ret = of_property_read_u32(port_np, "reg", &port_id); 1836 if (ret < 0) { 1837 dev_err(dev, "%pOF error reading port_id %d\n", 1838 port_np, ret); 1839 goto of_node_put; 1840 } 1841 1842 if (!port_id || port_id > common->port_num) { 1843 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1844 port_np, port_id, port_np->name); 1845 ret = -EINVAL; 1846 goto of_node_put; 1847 } 1848 1849 port = am65_common_get_port(common, port_id); 1850 port->port_id = port_id; 1851 port->common = common; 1852 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1853 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1854 if (common->pdata.extra_modes) 1855 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1856 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1857 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1858 port->name = of_get_property(port_np, "label", NULL); 1859 port->fetch_ram_base = 1860 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1861 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1862 1863 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1864 if (IS_ERR(port->slave.mac_sl)) { 1865 ret = PTR_ERR(port->slave.mac_sl); 1866 goto of_node_put; 1867 } 1868 1869 port->disabled = !of_device_is_available(port_np); 1870 if (port->disabled) { 1871 common->disabled_ports_mask |= BIT(port->port_id); 1872 continue; 1873 } 1874 1875 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1876 if (IS_ERR(port->slave.ifphy)) { 1877 ret = PTR_ERR(port->slave.ifphy); 1878 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1879 port_np, ret); 1880 goto of_node_put; 1881 } 1882 1883 port->slave.mac_only = 1884 of_property_read_bool(port_np, "ti,mac-only"); 1885 1886 /* get phy/link info */ 1887 port->slave.phy_node = port_np; 1888 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1889 if (ret) { 1890 dev_err(dev, "%pOF read phy-mode err %d\n", 1891 port_np, ret); 1892 goto of_node_put; 1893 } 1894 1895 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1896 if (ret) 1897 goto of_node_put; 1898 1899 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1900 if (ret) { 1901 am65_cpsw_am654_get_efuse_macid(port_np, 1902 port->port_id, 1903 port->slave.mac_addr); 1904 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1905 eth_random_addr(port->slave.mac_addr); 1906 dev_err(dev, "Use random MAC address\n"); 1907 } 1908 } 1909 } 1910 of_node_put(node); 1911 1912 /* is there at least one ext.port */ 1913 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1914 dev_err(dev, "No Ext. port are available\n"); 1915 return -ENODEV; 1916 } 1917 1918 return 0; 1919 1920 of_node_put: 1921 of_node_put(port_np); 1922 of_node_put(node); 1923 return ret; 1924 } 1925 1926 static void am65_cpsw_pcpu_stats_free(void *data) 1927 { 1928 struct am65_cpsw_ndev_stats __percpu *stats = data; 1929 1930 free_percpu(stats); 1931 } 1932 1933 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 1934 { 1935 struct am65_cpsw_port *port; 1936 int i; 1937 1938 for (i = 0; i < common->port_num; i++) { 1939 port = &common->ports[i]; 1940 if (port->slave.phylink) 1941 phylink_destroy(port->slave.phylink); 1942 } 1943 } 1944 1945 static int 1946 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 1947 { 1948 struct am65_cpsw_ndev_priv *ndev_priv; 1949 struct device *dev = common->dev; 1950 struct am65_cpsw_port *port; 1951 struct phylink *phylink; 1952 int ret; 1953 1954 port = &common->ports[port_idx]; 1955 1956 if (port->disabled) 1957 return 0; 1958 1959 /* alloc netdev */ 1960 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1961 sizeof(struct am65_cpsw_ndev_priv), 1962 AM65_CPSW_MAX_TX_QUEUES, 1963 AM65_CPSW_MAX_RX_QUEUES); 1964 if (!port->ndev) { 1965 dev_err(dev, "error allocating slave net_device %u\n", 1966 port->port_id); 1967 return -ENOMEM; 1968 } 1969 1970 ndev_priv = netdev_priv(port->ndev); 1971 ndev_priv->port = port; 1972 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1973 SET_NETDEV_DEV(port->ndev, dev); 1974 1975 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 1976 1977 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1978 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1979 port->ndev->hw_features = NETIF_F_SG | 1980 NETIF_F_RXCSUM | 1981 NETIF_F_HW_CSUM | 1982 NETIF_F_HW_TC; 1983 port->ndev->features = port->ndev->hw_features | 1984 NETIF_F_HW_VLAN_CTAG_FILTER; 1985 port->ndev->vlan_features |= NETIF_F_SG; 1986 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 1987 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1988 1989 /* Configuring Phylink */ 1990 port->slave.phylink_config.dev = &port->ndev->dev; 1991 port->slave.phylink_config.type = PHYLINK_NETDEV; 1992 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 1993 1994 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 1995 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 1996 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 1997 __set_bit(PHY_INTERFACE_MODE_RMII, 1998 port->slave.phylink_config.supported_interfaces); 1999 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2000 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2001 port->slave.phylink_config.supported_interfaces); 2002 } else { 2003 dev_err(dev, "selected phy-mode is not supported\n"); 2004 return -EOPNOTSUPP; 2005 } 2006 2007 phylink = phylink_create(&port->slave.phylink_config, 2008 of_node_to_fwnode(port->slave.phy_node), 2009 port->slave.phy_if, 2010 &am65_cpsw_phylink_mac_ops); 2011 if (IS_ERR(phylink)) 2012 return PTR_ERR(phylink); 2013 2014 port->slave.phylink = phylink; 2015 2016 /* Disable TX checksum offload by default due to HW bug */ 2017 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2018 port->ndev->features &= ~NETIF_F_HW_CSUM; 2019 2020 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2021 if (!ndev_priv->stats) 2022 return -ENOMEM; 2023 2024 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2025 ndev_priv->stats); 2026 if (ret) 2027 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2028 2029 if (!common->dma_ndev) 2030 common->dma_ndev = port->ndev; 2031 2032 return ret; 2033 } 2034 2035 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2036 { 2037 int ret; 2038 int i; 2039 2040 for (i = 0; i < common->port_num; i++) { 2041 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2042 if (ret) 2043 return ret; 2044 } 2045 2046 netif_napi_add(common->dma_ndev, &common->napi_rx, 2047 am65_cpsw_nuss_rx_poll); 2048 2049 return ret; 2050 } 2051 2052 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2053 { 2054 struct device *dev = common->dev; 2055 int i, ret = 0; 2056 2057 for (i = 0; i < common->tx_ch_num; i++) { 2058 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2059 2060 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2061 am65_cpsw_nuss_tx_poll); 2062 2063 ret = devm_request_irq(dev, tx_chn->irq, 2064 am65_cpsw_nuss_tx_irq, 2065 IRQF_TRIGGER_HIGH, 2066 tx_chn->tx_chn_name, tx_chn); 2067 if (ret) { 2068 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2069 tx_chn->id, tx_chn->irq, ret); 2070 goto err; 2071 } 2072 } 2073 2074 err: 2075 return ret; 2076 } 2077 2078 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2079 { 2080 struct am65_cpsw_port *port; 2081 int i; 2082 2083 for (i = 0; i < common->port_num; i++) { 2084 port = &common->ports[i]; 2085 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2086 unregister_netdev(port->ndev); 2087 } 2088 } 2089 2090 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2091 { 2092 int set_val = 0; 2093 int i; 2094 2095 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2096 set_val = 1; 2097 2098 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2099 2100 for (i = 1; i <= common->port_num; i++) { 2101 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2102 struct am65_cpsw_ndev_priv *priv; 2103 2104 if (!port->ndev) 2105 continue; 2106 2107 priv = am65_ndev_to_priv(port->ndev); 2108 priv->offload_fwd_mark = set_val; 2109 } 2110 } 2111 2112 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2113 { 2114 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2115 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2116 2117 return !common->is_emac_mode; 2118 } 2119 2120 return false; 2121 } 2122 2123 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2124 struct net_device *br_ndev, 2125 struct netlink_ext_ack *extack) 2126 { 2127 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2128 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2129 int err; 2130 2131 if (!common->br_members) { 2132 common->hw_bridge_dev = br_ndev; 2133 } else { 2134 /* This is adding the port to a second bridge, this is 2135 * unsupported 2136 */ 2137 if (common->hw_bridge_dev != br_ndev) 2138 return -EOPNOTSUPP; 2139 } 2140 2141 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2142 false, extack); 2143 if (err) 2144 return err; 2145 2146 common->br_members |= BIT(priv->port->port_id); 2147 2148 am65_cpsw_port_offload_fwd_mark_update(common); 2149 2150 return NOTIFY_DONE; 2151 } 2152 2153 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2154 { 2155 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2156 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2157 2158 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2159 2160 common->br_members &= ~BIT(priv->port->port_id); 2161 2162 am65_cpsw_port_offload_fwd_mark_update(common); 2163 2164 if (!common->br_members) 2165 common->hw_bridge_dev = NULL; 2166 } 2167 2168 /* netdev notifier */ 2169 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2170 unsigned long event, void *ptr) 2171 { 2172 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2173 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2174 struct netdev_notifier_changeupper_info *info; 2175 int ret = NOTIFY_DONE; 2176 2177 if (!am65_cpsw_port_dev_check(ndev)) 2178 return NOTIFY_DONE; 2179 2180 switch (event) { 2181 case NETDEV_CHANGEUPPER: 2182 info = ptr; 2183 2184 if (netif_is_bridge_master(info->upper_dev)) { 2185 if (info->linking) 2186 ret = am65_cpsw_netdevice_port_link(ndev, 2187 info->upper_dev, 2188 extack); 2189 else 2190 am65_cpsw_netdevice_port_unlink(ndev); 2191 } 2192 break; 2193 default: 2194 return NOTIFY_DONE; 2195 } 2196 2197 return notifier_from_errno(ret); 2198 } 2199 2200 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2201 { 2202 int ret = 0; 2203 2204 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2205 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2206 return 0; 2207 2208 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2209 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2210 if (ret) { 2211 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2212 return ret; 2213 } 2214 2215 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2216 if (ret) 2217 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2218 2219 return ret; 2220 } 2221 2222 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2223 { 2224 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2225 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2226 return; 2227 2228 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2229 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2230 } 2231 2232 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2233 2234 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2235 { 2236 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2237 ALE_MCAST_BLOCK_LEARN_FWD); 2238 } 2239 2240 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2241 { 2242 struct am65_cpsw_host *host = am65_common_get_host(common); 2243 2244 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2245 2246 am65_cpsw_init_stp_ale_entry(common); 2247 2248 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2249 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2250 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2251 } 2252 2253 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2254 { 2255 struct am65_cpsw_host *host = am65_common_get_host(common); 2256 2257 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2258 2259 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2260 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2261 2262 /* learning make no sense in multi-mac mode */ 2263 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2264 } 2265 2266 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2267 struct devlink_param_gset_ctx *ctx) 2268 { 2269 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2270 struct am65_cpsw_common *common = dl_priv->common; 2271 2272 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2273 2274 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2275 return -EOPNOTSUPP; 2276 2277 ctx->val.vbool = !common->is_emac_mode; 2278 2279 return 0; 2280 } 2281 2282 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2283 { 2284 struct am65_cpsw_slave_data *slave = &port->slave; 2285 struct am65_cpsw_common *common = port->common; 2286 u32 port_mask; 2287 2288 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2289 2290 if (slave->mac_only) 2291 /* enable mac-only mode on port */ 2292 cpsw_ale_control_set(common->ale, port->port_id, 2293 ALE_PORT_MACONLY, 1); 2294 2295 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2296 2297 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2298 2299 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2300 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2301 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2302 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2303 } 2304 2305 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2306 { 2307 struct am65_cpsw_slave_data *slave = &port->slave; 2308 struct am65_cpsw_common *cpsw = port->common; 2309 u32 port_mask; 2310 2311 cpsw_ale_control_set(cpsw->ale, port->port_id, 2312 ALE_PORT_NOLEARN, 0); 2313 2314 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2315 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2316 slave->port_vlan); 2317 2318 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2319 2320 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2321 port_mask, ALE_VLAN, slave->port_vlan, 2322 ALE_MCAST_FWD_2); 2323 2324 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2325 2326 cpsw_ale_control_set(cpsw->ale, port->port_id, 2327 ALE_PORT_MACONLY, 0); 2328 } 2329 2330 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2331 struct devlink_param_gset_ctx *ctx) 2332 { 2333 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2334 struct am65_cpsw_common *cpsw = dl_priv->common; 2335 bool switch_en = ctx->val.vbool; 2336 bool if_running = false; 2337 int i; 2338 2339 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2340 2341 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2342 return -EOPNOTSUPP; 2343 2344 if (switch_en == !cpsw->is_emac_mode) 2345 return 0; 2346 2347 if (!switch_en && cpsw->br_members) { 2348 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2349 return -EINVAL; 2350 } 2351 2352 rtnl_lock(); 2353 2354 cpsw->is_emac_mode = !switch_en; 2355 2356 for (i = 0; i < cpsw->port_num; i++) { 2357 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2358 2359 if (!sl_ndev || !netif_running(sl_ndev)) 2360 continue; 2361 2362 if_running = true; 2363 } 2364 2365 if (!if_running) { 2366 /* all ndevs are down */ 2367 for (i = 0; i < cpsw->port_num; i++) { 2368 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2369 struct am65_cpsw_slave_data *slave; 2370 2371 if (!sl_ndev) 2372 continue; 2373 2374 slave = am65_ndev_to_slave(sl_ndev); 2375 if (switch_en) 2376 slave->port_vlan = cpsw->default_vlan; 2377 else 2378 slave->port_vlan = 0; 2379 } 2380 2381 goto exit; 2382 } 2383 2384 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2385 /* clean up ALE table */ 2386 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2387 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2388 2389 if (switch_en) { 2390 dev_info(cpsw->dev, "Enable switch mode\n"); 2391 2392 am65_cpsw_init_host_port_switch(cpsw); 2393 2394 for (i = 0; i < cpsw->port_num; i++) { 2395 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2396 struct am65_cpsw_slave_data *slave; 2397 struct am65_cpsw_port *port; 2398 2399 if (!sl_ndev) 2400 continue; 2401 2402 port = am65_ndev_to_port(sl_ndev); 2403 slave = am65_ndev_to_slave(sl_ndev); 2404 slave->port_vlan = cpsw->default_vlan; 2405 2406 if (netif_running(sl_ndev)) 2407 am65_cpsw_init_port_switch_ale(port); 2408 } 2409 2410 } else { 2411 dev_info(cpsw->dev, "Disable switch mode\n"); 2412 2413 am65_cpsw_init_host_port_emac(cpsw); 2414 2415 for (i = 0; i < cpsw->port_num; i++) { 2416 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2417 struct am65_cpsw_port *port; 2418 2419 if (!sl_ndev) 2420 continue; 2421 2422 port = am65_ndev_to_port(sl_ndev); 2423 port->slave.port_vlan = 0; 2424 if (netif_running(sl_ndev)) 2425 am65_cpsw_init_port_emac_ale(port); 2426 } 2427 } 2428 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2429 exit: 2430 rtnl_unlock(); 2431 2432 return 0; 2433 } 2434 2435 static const struct devlink_param am65_cpsw_devlink_params[] = { 2436 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2437 DEVLINK_PARAM_TYPE_BOOL, 2438 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2439 am65_cpsw_dl_switch_mode_get, 2440 am65_cpsw_dl_switch_mode_set, NULL), 2441 }; 2442 2443 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2444 { 2445 struct devlink_port_attrs attrs = {}; 2446 struct am65_cpsw_devlink *dl_priv; 2447 struct device *dev = common->dev; 2448 struct devlink_port *dl_port; 2449 struct am65_cpsw_port *port; 2450 int ret = 0; 2451 int i; 2452 2453 common->devlink = 2454 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2455 if (!common->devlink) 2456 return -ENOMEM; 2457 2458 dl_priv = devlink_priv(common->devlink); 2459 dl_priv->common = common; 2460 2461 /* Provide devlink hook to switch mode when multiple external ports 2462 * are present NUSS switchdev driver is enabled. 2463 */ 2464 if (!AM65_CPSW_IS_CPSW2G(common) && 2465 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2466 ret = devlink_params_register(common->devlink, 2467 am65_cpsw_devlink_params, 2468 ARRAY_SIZE(am65_cpsw_devlink_params)); 2469 if (ret) { 2470 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2471 goto dl_unreg; 2472 } 2473 } 2474 2475 for (i = 1; i <= common->port_num; i++) { 2476 port = am65_common_get_port(common, i); 2477 dl_port = &port->devlink_port; 2478 2479 if (port->ndev) 2480 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2481 else 2482 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2483 attrs.phys.port_number = port->port_id; 2484 attrs.switch_id.id_len = sizeof(resource_size_t); 2485 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2486 devlink_port_attrs_set(dl_port, &attrs); 2487 2488 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2489 if (ret) { 2490 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2491 port->port_id, ret); 2492 goto dl_port_unreg; 2493 } 2494 } 2495 devlink_register(common->devlink); 2496 return ret; 2497 2498 dl_port_unreg: 2499 for (i = i - 1; i >= 1; i--) { 2500 port = am65_common_get_port(common, i); 2501 dl_port = &port->devlink_port; 2502 2503 devlink_port_unregister(dl_port); 2504 } 2505 dl_unreg: 2506 devlink_free(common->devlink); 2507 return ret; 2508 } 2509 2510 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2511 { 2512 struct devlink_port *dl_port; 2513 struct am65_cpsw_port *port; 2514 int i; 2515 2516 devlink_unregister(common->devlink); 2517 2518 for (i = 1; i <= common->port_num; i++) { 2519 port = am65_common_get_port(common, i); 2520 dl_port = &port->devlink_port; 2521 2522 devlink_port_unregister(dl_port); 2523 } 2524 2525 if (!AM65_CPSW_IS_CPSW2G(common) && 2526 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2527 devlink_params_unregister(common->devlink, 2528 am65_cpsw_devlink_params, 2529 ARRAY_SIZE(am65_cpsw_devlink_params)); 2530 2531 devlink_free(common->devlink); 2532 } 2533 2534 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2535 { 2536 struct device *dev = common->dev; 2537 struct devlink_port *dl_port; 2538 struct am65_cpsw_port *port; 2539 int ret = 0, i; 2540 2541 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2542 if (ret) 2543 return ret; 2544 2545 ret = devm_request_irq(dev, common->rx_chns.irq, 2546 am65_cpsw_nuss_rx_irq, 2547 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2548 if (ret) { 2549 dev_err(dev, "failure requesting rx irq %u, %d\n", 2550 common->rx_chns.irq, ret); 2551 return ret; 2552 } 2553 2554 ret = am65_cpsw_nuss_register_devlink(common); 2555 if (ret) 2556 return ret; 2557 2558 for (i = 0; i < common->port_num; i++) { 2559 port = &common->ports[i]; 2560 2561 if (!port->ndev) 2562 continue; 2563 2564 ret = register_netdev(port->ndev); 2565 if (ret) { 2566 dev_err(dev, "error registering slave net device%i %d\n", 2567 i, ret); 2568 goto err_cleanup_ndev; 2569 } 2570 2571 dl_port = &port->devlink_port; 2572 devlink_port_type_eth_set(dl_port, port->ndev); 2573 } 2574 2575 ret = am65_cpsw_register_notifiers(common); 2576 if (ret) 2577 goto err_cleanup_ndev; 2578 2579 /* can't auto unregister ndev using devm_add_action() due to 2580 * devres release sequence in DD core for DMA 2581 */ 2582 2583 return 0; 2584 2585 err_cleanup_ndev: 2586 am65_cpsw_nuss_cleanup_ndev(common); 2587 am65_cpsw_unregister_devlink(common); 2588 2589 return ret; 2590 } 2591 2592 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2593 { 2594 int ret; 2595 2596 common->tx_ch_num = num_tx; 2597 ret = am65_cpsw_nuss_init_tx_chns(common); 2598 if (ret) 2599 return ret; 2600 2601 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2602 } 2603 2604 struct am65_cpsw_soc_pdata { 2605 u32 quirks_dis; 2606 }; 2607 2608 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2609 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2610 }; 2611 2612 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2613 { .family = "AM65X", 2614 .revision = "SR2.0", 2615 .data = &am65x_soc_sr2_0 2616 }, 2617 {/* sentinel */} 2618 }; 2619 2620 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2621 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2622 .ale_dev_id = "am65x-cpsw2g", 2623 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2624 }; 2625 2626 static const struct am65_cpsw_pdata j721e_pdata = { 2627 .quirks = 0, 2628 .ale_dev_id = "am65x-cpsw2g", 2629 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2630 }; 2631 2632 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2633 .quirks = 0, 2634 .ale_dev_id = "am64-cpswxg", 2635 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2636 }; 2637 2638 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2639 .quirks = 0, 2640 .ale_dev_id = "am64-cpswxg", 2641 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2642 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2643 }; 2644 2645 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2646 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2647 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2648 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2649 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2650 { /* sentinel */ }, 2651 }; 2652 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2653 2654 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2655 { 2656 const struct soc_device_attribute *soc; 2657 2658 soc = soc_device_match(am65_cpsw_socinfo); 2659 if (soc && soc->data) { 2660 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2661 2662 /* disable quirks */ 2663 common->pdata.quirks &= ~socdata->quirks_dis; 2664 } 2665 } 2666 2667 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2668 { 2669 struct cpsw_ale_params ale_params = { 0 }; 2670 const struct of_device_id *of_id; 2671 struct device *dev = &pdev->dev; 2672 struct am65_cpsw_common *common; 2673 struct device_node *node; 2674 struct resource *res; 2675 struct clk *clk; 2676 u64 id_temp; 2677 int ret, i; 2678 2679 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2680 if (!common) 2681 return -ENOMEM; 2682 common->dev = dev; 2683 2684 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2685 if (!of_id) 2686 return -EINVAL; 2687 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2688 2689 am65_cpsw_nuss_apply_socinfo(common); 2690 2691 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2692 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2693 if (IS_ERR(common->ss_base)) 2694 return PTR_ERR(common->ss_base); 2695 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2696 /* Use device's physical base address as switch id */ 2697 id_temp = cpu_to_be64(res->start); 2698 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2699 2700 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2701 if (!node) 2702 return -ENOENT; 2703 common->port_num = of_get_child_count(node); 2704 of_node_put(node); 2705 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2706 return -ENOENT; 2707 2708 common->rx_flow_id_base = -1; 2709 init_completion(&common->tdown_complete); 2710 common->tx_ch_num = 1; 2711 common->pf_p0_rx_ptype_rrobin = false; 2712 common->default_vlan = 1; 2713 2714 common->ports = devm_kcalloc(dev, common->port_num, 2715 sizeof(*common->ports), 2716 GFP_KERNEL); 2717 if (!common->ports) 2718 return -ENOMEM; 2719 2720 clk = devm_clk_get(dev, "fck"); 2721 if (IS_ERR(clk)) 2722 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2723 common->bus_freq = clk_get_rate(clk); 2724 2725 pm_runtime_enable(dev); 2726 ret = pm_runtime_resume_and_get(dev); 2727 if (ret < 0) { 2728 pm_runtime_disable(dev); 2729 return ret; 2730 } 2731 2732 node = of_get_child_by_name(dev->of_node, "mdio"); 2733 if (!node) { 2734 dev_warn(dev, "MDIO node not found\n"); 2735 } else if (of_device_is_available(node)) { 2736 struct platform_device *mdio_pdev; 2737 2738 mdio_pdev = of_platform_device_create(node, NULL, dev); 2739 if (!mdio_pdev) { 2740 ret = -ENODEV; 2741 goto err_pm_clear; 2742 } 2743 2744 common->mdio_dev = &mdio_pdev->dev; 2745 } 2746 of_node_put(node); 2747 2748 am65_cpsw_nuss_get_ver(common); 2749 2750 /* init tx channels */ 2751 ret = am65_cpsw_nuss_init_tx_chns(common); 2752 if (ret) 2753 goto err_of_clear; 2754 ret = am65_cpsw_nuss_init_rx_chns(common); 2755 if (ret) 2756 goto err_of_clear; 2757 2758 ret = am65_cpsw_nuss_init_host_p(common); 2759 if (ret) 2760 goto err_of_clear; 2761 2762 ret = am65_cpsw_nuss_init_slave_ports(common); 2763 if (ret) 2764 goto err_of_clear; 2765 2766 /* init common data */ 2767 ale_params.dev = dev; 2768 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2769 ale_params.ale_ports = common->port_num + 1; 2770 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2771 ale_params.dev_id = common->pdata.ale_dev_id; 2772 ale_params.bus_freq = common->bus_freq; 2773 2774 common->ale = cpsw_ale_create(&ale_params); 2775 if (IS_ERR(common->ale)) { 2776 dev_err(dev, "error initializing ale engine\n"); 2777 ret = PTR_ERR(common->ale); 2778 goto err_of_clear; 2779 } 2780 2781 ret = am65_cpsw_init_cpts(common); 2782 if (ret) 2783 goto err_of_clear; 2784 2785 /* init ports */ 2786 for (i = 0; i < common->port_num; i++) 2787 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2788 2789 dev_set_drvdata(dev, common); 2790 2791 common->is_emac_mode = true; 2792 2793 ret = am65_cpsw_nuss_init_ndevs(common); 2794 if (ret) 2795 goto err_free_phylink; 2796 2797 ret = am65_cpsw_nuss_register_ndevs(common); 2798 if (ret) 2799 goto err_free_phylink; 2800 2801 pm_runtime_put(dev); 2802 return 0; 2803 2804 err_free_phylink: 2805 am65_cpsw_nuss_phylink_cleanup(common); 2806 err_of_clear: 2807 of_platform_device_destroy(common->mdio_dev, NULL); 2808 err_pm_clear: 2809 pm_runtime_put_sync(dev); 2810 pm_runtime_disable(dev); 2811 return ret; 2812 } 2813 2814 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2815 { 2816 struct device *dev = &pdev->dev; 2817 struct am65_cpsw_common *common; 2818 int ret; 2819 2820 common = dev_get_drvdata(dev); 2821 2822 ret = pm_runtime_resume_and_get(&pdev->dev); 2823 if (ret < 0) 2824 return ret; 2825 2826 am65_cpsw_unregister_devlink(common); 2827 am65_cpsw_unregister_notifiers(common); 2828 2829 /* must unregister ndevs here because DD release_driver routine calls 2830 * dma_deconfigure(dev) before devres_release_all(dev) 2831 */ 2832 am65_cpsw_nuss_cleanup_ndev(common); 2833 am65_cpsw_nuss_phylink_cleanup(common); 2834 2835 of_platform_device_destroy(common->mdio_dev, NULL); 2836 2837 pm_runtime_put_sync(&pdev->dev); 2838 pm_runtime_disable(&pdev->dev); 2839 return 0; 2840 } 2841 2842 static struct platform_driver am65_cpsw_nuss_driver = { 2843 .driver = { 2844 .name = AM65_CPSW_DRV_NAME, 2845 .of_match_table = am65_cpsw_nuss_of_mtable, 2846 }, 2847 .probe = am65_cpsw_nuss_probe, 2848 .remove = am65_cpsw_nuss_remove, 2849 }; 2850 2851 module_platform_driver(am65_cpsw_nuss_driver); 2852 2853 MODULE_LICENSE("GPL v2"); 2854 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2855 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2856