1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * PS3 Platfom gelic network driver. 4 * 5 * Copyright (C) 2007 Sony Computer Entertainment Inc. 6 * Copyright 2006, 2007 Sony Corporation. 7 * 8 * This file is based on: spider_net.h 9 * 10 * (C) Copyright IBM Corp. 2005 11 * 12 * Authors : Utz Bacher <utz.bacher@de.ibm.com> 13 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com> 14 */ 15 #ifndef _GELIC_NET_H 16 #define _GELIC_NET_H 17 18 /* descriptors */ 19 #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */ 20 #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */ 21 22 #define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN 23 #define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN 24 #define GELIC_NET_RXBUF_ALIGN 128 25 #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */ 26 #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ 27 #define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL 28 29 #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */ 30 31 /* virtual interrupt status register bits */ 32 /* INT1 */ 33 #define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L 34 #define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L 35 #define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L 36 #define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L 37 #define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L 38 #define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L 39 #define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L 40 #define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L 41 #define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L 42 #define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L 43 #define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L 44 #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L 45 #define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L 46 #define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L 47 #define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L 48 /* INT 0 */ 49 #define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L 50 #define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L 51 #define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L 52 #define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L 53 #define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L 54 #define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L 55 #define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L 56 57 /* initial interrupt mask */ 58 #define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END 59 60 #define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \ 61 GELIC_CARD_NUMBER_OF_RX_FRAME) 62 63 /* RX descriptor data_status bits */ 64 enum gelic_descr_rx_status { 65 GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */ 66 GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */ 67 GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */ 68 GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */ 69 GELIC_DESCR_RXWTPKT = 0x00C00000, /* 70 * wakeup trigger packet 71 * 01: Magic Packet (TM) 72 * 10: ARP packet 73 * 11: Multicast MAC addr 74 */ 75 GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */ 76 /* bit 20..16 reserved */ 77 GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */ 78 /* bit 7..0 reserved */ 79 }; 80 81 #define GELIC_DESCR_DATA_STATUS_CHK_MASK \ 82 (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK) 83 84 /* TX descriptor data_status bits */ 85 enum gelic_descr_tx_status { 86 GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this 87 * descriptor was end of 88 * a tx frame 89 */ 90 }; 91 92 /* RX descriptor data error bits */ 93 enum gelic_descr_rx_error { 94 /* bit 31 reserved */ 95 GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */ 96 GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */ 97 GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */ 98 GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */ 99 GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */ 100 GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */ 101 GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */ 102 /* bit 18 reserved */ 103 GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */ 104 GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length 105 * error */ 106 GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */ 107 GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */ 108 /* bit 13..0 reserved */ 109 }; 110 #define GELIC_DESCR_DATA_ERROR_CHK_MASK \ 111 (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR) 112 113 /* DMA command and status (RX and TX)*/ 114 enum gelic_descr_dma_status { 115 GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */ 116 GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */ 117 GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */ 118 GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */ 119 GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */ 120 GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */ 121 GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */ 122 GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */ 123 }; 124 125 #define GELIC_DESCR_DMA_STAT_MASK (0xf0000000) 126 127 /* tx descriptor command and status */ 128 enum gelic_descr_tx_dma_status { 129 /* [19] */ 130 GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */ 131 /* [18] */ 132 GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of 133 * the packet 134 */ 135 /* [17..16] */ 136 GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */ 137 GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */ 138 GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */ 139 140 /* [1] */ 141 GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated 142 * due to chain end 143 */ 144 }; 145 146 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM \ 147 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ 148 GELIC_DESCR_TX_DMA_NO_CHKSUM) 149 150 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \ 151 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ 152 GELIC_DESCR_TX_DMA_TCP_CHKSUM) 153 154 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \ 155 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ 156 GELIC_DESCR_TX_DMA_UDP_CHKSUM) 157 158 enum gelic_descr_rx_dma_status { 159 /* [ 1 ] */ 160 GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated 161 * due to chain end 162 */ 163 }; 164 165 /* for lv1_net_control */ 166 enum gelic_lv1_net_control_code { 167 GELIC_LV1_GET_MAC_ADDRESS = 1, 168 GELIC_LV1_GET_ETH_PORT_STATUS = 2, 169 GELIC_LV1_SET_NEGOTIATION_MODE = 3, 170 GELIC_LV1_GET_VLAN_ID = 4, 171 GELIC_LV1_SET_WOL = 5, 172 GELIC_LV1_GET_CHANNEL = 6, 173 GELIC_LV1_POST_WLAN_CMD = 9, 174 GELIC_LV1_GET_WLAN_CMD_RESULT = 10, 175 GELIC_LV1_GET_WLAN_EVENT = 11, 176 }; 177 178 /* for GELIC_LV1_SET_WOL */ 179 enum gelic_lv1_wol_command { 180 GELIC_LV1_WOL_MAGIC_PACKET = 1, 181 GELIC_LV1_WOL_ADD_MATCH_ADDR = 6, 182 GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7, 183 }; 184 185 /* for GELIC_LV1_WOL_MAGIC_PACKET */ 186 enum gelic_lv1_wol_mp_arg { 187 GELIC_LV1_WOL_MP_DISABLE = 0, 188 GELIC_LV1_WOL_MP_ENABLE = 1, 189 }; 190 191 /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */ 192 enum gelic_lv1_wol_match_arg { 193 GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0, 194 GELIC_LV1_WOL_MATCH_ALL = 1, 195 }; 196 197 /* status returened from GET_ETH_PORT_STATUS */ 198 enum gelic_lv1_ether_port_status { 199 GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L, 200 GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L, 201 GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L, 202 203 GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L, 204 GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L, 205 GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L, 206 GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L, 207 }; 208 209 enum gelic_lv1_vlan_index { 210 /* for outgoing packets */ 211 GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L, 212 GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L, 213 214 /* for incoming packets */ 215 GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L, 216 GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L, 217 }; 218 219 enum gelic_lv1_phy { 220 GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L, 221 }; 222 223 /* size of hardware part of gelic descriptor */ 224 #define GELIC_DESCR_SIZE (32) 225 226 enum gelic_port_type { 227 GELIC_PORT_ETHERNET_0 = 0, 228 GELIC_PORT_WIRELESS = 1, 229 GELIC_PORT_MAX 230 }; 231 232 struct gelic_descr { 233 /* as defined by the hardware */ 234 __be32 buf_addr; 235 __be32 buf_size; 236 __be32 next_descr_addr; 237 __be32 dmac_cmd_status; 238 __be32 result_size; 239 __be32 valid_size; /* all zeroes for tx */ 240 __be32 data_status; 241 __be32 data_error; /* all zeroes for tx */ 242 243 /* used in the driver */ 244 struct sk_buff *skb; 245 dma_addr_t bus_addr; 246 struct gelic_descr *next; 247 struct gelic_descr *prev; 248 } __attribute__((aligned(32))); 249 250 struct gelic_descr_chain { 251 /* we walk from tail to head */ 252 struct gelic_descr *head; 253 struct gelic_descr *tail; 254 }; 255 256 struct gelic_vlan_id { 257 u16 tx; 258 u16 rx; 259 }; 260 261 struct gelic_card { 262 struct napi_struct napi; 263 struct net_device *netdev[GELIC_PORT_MAX]; 264 /* 265 * hypervisor requires irq_status should be 266 * 8 bytes aligned, but u64 member is 267 * always disposed in that manner 268 */ 269 u64 irq_status; 270 u64 irq_mask; 271 272 struct ps3_system_bus_device *dev; 273 struct gelic_vlan_id vlan[GELIC_PORT_MAX]; 274 int vlan_required; 275 276 struct gelic_descr_chain tx_chain; 277 struct gelic_descr_chain rx_chain; 278 /* 279 * tx_lock guards tx descriptor list and 280 * tx_dma_progress. 281 */ 282 spinlock_t tx_lock; 283 int tx_dma_progress; 284 285 struct work_struct tx_timeout_task; 286 atomic_t tx_timeout_task_counter; 287 wait_queue_head_t waitq; 288 289 /* only first user should up the card */ 290 struct mutex updown_lock; 291 atomic_t users; 292 293 u64 ether_port_status; 294 int link_mode; 295 296 /* original address returned by kzalloc */ 297 void *unalign; 298 299 /* 300 * each netdevice has copy of irq 301 */ 302 unsigned int irq; 303 struct gelic_descr *tx_top, *rx_top; 304 struct gelic_descr descr[]; /* must be the last */ 305 }; 306 307 struct gelic_port { 308 struct gelic_card *card; 309 struct net_device *netdev; 310 enum gelic_port_type type; 311 long priv[0]; /* long for alignment */ 312 }; 313 314 static inline struct gelic_card *port_to_card(struct gelic_port *p) 315 { 316 return p->card; 317 } 318 static inline struct net_device *port_to_netdev(struct gelic_port *p) 319 { 320 return p->netdev; 321 } 322 static inline struct gelic_card *netdev_card(struct net_device *d) 323 { 324 return ((struct gelic_port *)netdev_priv(d))->card; 325 } 326 static inline struct gelic_port *netdev_port(struct net_device *d) 327 { 328 return (struct gelic_port *)netdev_priv(d); 329 } 330 static inline struct device *ctodev(struct gelic_card *card) 331 { 332 return &card->dev->core; 333 } 334 static inline u64 bus_id(struct gelic_card *card) 335 { 336 return card->dev->bus_id; 337 } 338 static inline u64 dev_id(struct gelic_card *card) 339 { 340 return card->dev->dev_id; 341 } 342 343 static inline void *port_priv(struct gelic_port *port) 344 { 345 return port->priv; 346 } 347 348 #ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC 349 void udbg_shutdown_ps3gelic(void); 350 #else 351 static inline void udbg_shutdown_ps3gelic(void) {} 352 #endif 353 354 int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask); 355 /* shared netdev ops */ 356 void gelic_card_up(struct gelic_card *card); 357 void gelic_card_down(struct gelic_card *card); 358 int gelic_net_open(struct net_device *netdev); 359 int gelic_net_stop(struct net_device *netdev); 360 netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 361 void gelic_net_set_multi(struct net_device *netdev); 362 void gelic_net_tx_timeout(struct net_device *netdev, unsigned int txqueue); 363 int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card); 364 365 /* shared ethtool ops */ 366 void gelic_net_get_drvinfo(struct net_device *netdev, 367 struct ethtool_drvinfo *info); 368 void gelic_net_poll_controller(struct net_device *netdev); 369 370 #endif /* _GELIC_NET_H */ 371