1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2022 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* GSI EE registers as a group are shifted downward by a fixed constant amount 42 * for IPA versions 4.5 and beyond. This applies to all GSI registers we use 43 * *except* the ones that disable inter-EE interrupts for channels and event 44 * channels. 45 * 46 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to 47 * the mapped range is held in gsi->virt_raw. The inter-EE interrupt 48 * registers are accessed using that pointer. 49 * 50 * Most registers are accessed using gsi->virt, which is a copy of the "raw" 51 * pointer, adjusted downward by the fixed amount. 52 */ 53 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ 54 55 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ 56 57 #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ 58 (0x0000c020 + 0x1000 * GSI_EE_AP) 59 60 #define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \ 61 (0x0000c024 + 0x1000 * GSI_EE_AP) 62 63 /* All other register offsets are relative to gsi->virt */ 64 65 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 66 enum gsi_channel_type { 67 GSI_CHANNEL_TYPE_MHI = 0x0, 68 GSI_CHANNEL_TYPE_XHCI = 0x1, 69 GSI_CHANNEL_TYPE_GPI = 0x2, 70 GSI_CHANNEL_TYPE_XDCI = 0x3, 71 GSI_CHANNEL_TYPE_WDI2 = 0x4, 72 GSI_CHANNEL_TYPE_GCI = 0x5, 73 GSI_CHANNEL_TYPE_WDI3 = 0x6, 74 GSI_CHANNEL_TYPE_MHIP = 0x7, 75 GSI_CHANNEL_TYPE_AQC = 0x8, 76 GSI_CHANNEL_TYPE_11AD = 0x9, 77 }; 78 79 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 80 (0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 81 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 82 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 83 #define EE_FMASK GENMASK(7, 4) 84 #define CHID_FMASK GENMASK(12, 8) 85 /* The next field is present for IPA v4.5 and above */ 86 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 87 #define ERINDEX_FMASK GENMASK(18, 14) 88 #define CHSTATE_FMASK GENMASK(23, 20) 89 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 90 91 /* Encoded value for CH_C_CNTXT_0 register channel protocol fields */ 92 static inline u32 93 chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type) 94 { 95 u32 val; 96 97 val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK); 98 if (version < IPA_VERSION_4_5) 99 return val; 100 101 /* Encode upper bit(s) as well */ 102 type >>= hweight32(CHTYPE_PROTOCOL_FMASK); 103 val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK); 104 105 return val; 106 } 107 108 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 109 (0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 110 111 /* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */ 112 static inline u32 r_length_encoded(enum ipa_version version, u32 length) 113 { 114 if (version < IPA_VERSION_4_9) 115 return u32_encode_bits(length, GENMASK(15, 0)); 116 return u32_encode_bits(length, GENMASK(19, 0)); 117 } 118 119 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 120 (0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 121 122 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 123 (0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 124 125 #define GSI_CH_C_QOS_OFFSET(ch) \ 126 (0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 127 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 128 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 129 #define USE_DB_ENG_FMASK GENMASK(9, 9) 130 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 131 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 132 /* The next two fields are present for IPA v4.5 and above */ 133 #define PREFETCH_MODE_FMASK GENMASK(13, 10) 134 #define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16) 135 /* The next field is present for IPA v4.9 and above */ 136 #define DB_IN_BYTES GENMASK(24, 24) 137 138 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 139 enum gsi_prefetch_mode { 140 GSI_USE_PREFETCH_BUFS = 0x0, 141 GSI_ESCAPE_BUF_ONLY = 0x1, 142 GSI_SMART_PREFETCH = 0x2, 143 GSI_FREE_PREFETCH = 0x3, 144 }; 145 146 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 147 (0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 148 149 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 150 (0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 151 152 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 153 (0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 154 155 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 156 (0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 157 158 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 159 (0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 160 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 161 #define EV_CHTYPE_FMASK GENMASK(3, 0) 162 #define EV_EE_FMASK GENMASK(7, 4) 163 #define EV_EVCHID_FMASK GENMASK(15, 8) 164 #define EV_INTYPE_FMASK GENMASK(16, 16) 165 #define EV_CHSTATE_FMASK GENMASK(23, 20) 166 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 167 168 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 169 (0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 170 /* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */ 171 static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length) 172 { 173 if (version < IPA_VERSION_4_9) 174 return u32_encode_bits(length, GENMASK(15, 0)); 175 return u32_encode_bits(length, GENMASK(19, 0)); 176 } 177 178 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 179 (0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 180 181 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 182 (0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 183 184 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 185 (0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 186 187 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 188 (0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 189 #define MODT_FMASK GENMASK(15, 0) 190 #define MODC_FMASK GENMASK(23, 16) 191 #define MOD_CNT_FMASK GENMASK(31, 24) 192 193 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 194 (0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 195 196 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 197 (0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 198 199 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 200 (0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 201 202 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 203 (0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 204 205 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 206 (0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 207 208 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 209 (0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 210 211 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 212 (0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 213 214 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 215 (0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch)) 216 217 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 218 (0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev)) 219 220 #define GSI_GSI_STATUS_OFFSET \ 221 (0x0001f000 + 0x4000 * GSI_EE_AP) 222 #define ENABLED_FMASK GENMASK(0, 0) 223 224 #define GSI_CH_CMD_OFFSET \ 225 (0x0001f008 + 0x4000 * GSI_EE_AP) 226 #define CH_CHID_FMASK GENMASK(7, 0) 227 #define CH_OPCODE_FMASK GENMASK(31, 24) 228 229 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 230 enum gsi_ch_cmd_opcode { 231 GSI_CH_ALLOCATE = 0x0, 232 GSI_CH_START = 0x1, 233 GSI_CH_STOP = 0x2, 234 GSI_CH_RESET = 0x9, 235 GSI_CH_DE_ALLOC = 0xa, 236 GSI_CH_DB_STOP = 0xb, 237 }; 238 239 #define GSI_EV_CH_CMD_OFFSET \ 240 (0x0001f010 + 0x4000 * GSI_EE_AP) 241 #define EV_CHID_FMASK GENMASK(7, 0) 242 #define EV_OPCODE_FMASK GENMASK(31, 24) 243 244 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 245 enum gsi_evt_cmd_opcode { 246 GSI_EVT_ALLOCATE = 0x0, 247 GSI_EVT_RESET = 0x9, 248 GSI_EVT_DE_ALLOC = 0xa, 249 }; 250 251 #define GSI_GENERIC_CMD_OFFSET \ 252 (0x0001f018 + 0x4000 * GSI_EE_AP) 253 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 254 #define GENERIC_CHID_FMASK GENMASK(9, 5) 255 #define GENERIC_EE_FMASK GENMASK(13, 10) 256 #define GENERIC_PARAMS_FMASK GENMASK(31, 24) /* IPA v4.11+ */ 257 258 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 259 enum gsi_generic_cmd_opcode { 260 GSI_GENERIC_HALT_CHANNEL = 0x1, 261 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 262 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */ 263 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */ 264 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */ 265 }; 266 267 /* The next register is present for IPA v3.5.1 and above */ 268 #define GSI_GSI_HW_PARAM_2_OFFSET \ 269 (0x0001f040 + 0x4000 * GSI_EE_AP) 270 #define IRAM_SIZE_FMASK GENMASK(2, 0) 271 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 272 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 273 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 274 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 275 /* Fields below are present for IPA v4.0 and above */ 276 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 277 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 278 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 279 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 280 /* Fields below are present for IPA v4.2 and above */ 281 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 282 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 283 284 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 285 enum gsi_iram_size { 286 IRAM_SIZE_ONE_KB = 0x0, 287 IRAM_SIZE_TWO_KB = 0x1, 288 /* The next two values are available for IPA v4.0 and above */ 289 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 290 IRAM_SIZE_THREE_KB = 0x3, 291 /* The next two values are available for IPA v4.5 and above */ 292 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 293 IRAM_SIZE_FOUR_KB = 0x5, 294 }; 295 296 /* IRQ condition for each type is cleared by writing type-specific register */ 297 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 298 (0x0001f080 + 0x4000 * GSI_EE_AP) 299 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 300 (0x0001f088 + 0x4000 * GSI_EE_AP) 301 302 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ 303 enum gsi_irq_type_id { 304 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ 305 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ 306 GSI_GLOB_EE = 0x2, /* global/general event */ 307 GSI_IEOB = 0x3, /* TRE completion */ 308 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ 309 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ 310 GSI_GENERAL = 0x6, /* general-purpose event */ 311 }; 312 313 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 314 (0x0001f090 + 0x4000 * GSI_EE_AP) 315 316 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 317 (0x0001f094 + 0x4000 * GSI_EE_AP) 318 319 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 320 (0x0001f098 + 0x4000 * GSI_EE_AP) 321 322 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 323 (0x0001f09c + 0x4000 * GSI_EE_AP) 324 325 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 326 (0x0001f0a0 + 0x4000 * GSI_EE_AP) 327 328 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 329 (0x0001f0a4 + 0x4000 * GSI_EE_AP) 330 331 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 332 (0x0001f0b0 + 0x4000 * GSI_EE_AP) 333 334 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 335 (0x0001f0b8 + 0x4000 * GSI_EE_AP) 336 337 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 338 (0x0001f0c0 + 0x4000 * GSI_EE_AP) 339 340 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 341 (0x0001f100 + 0x4000 * GSI_EE_AP) 342 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 343 (0x0001f108 + 0x4000 * GSI_EE_AP) 344 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 345 (0x0001f110 + 0x4000 * GSI_EE_AP) 346 /* Values here are bit positions in the GLOB_IRQ_* registers */ 347 enum gsi_global_irq_id { 348 ERROR_INT = 0x0, 349 GP_INT1 = 0x1, 350 GP_INT2 = 0x2, 351 GP_INT3 = 0x3, 352 }; 353 354 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 355 (0x0001f118 + 0x4000 * GSI_EE_AP) 356 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 357 (0x0001f120 + 0x4000 * GSI_EE_AP) 358 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 359 (0x0001f128 + 0x4000 * GSI_EE_AP) 360 /* Values here are bit positions in the (general) GSI_IRQ_* registers */ 361 enum gsi_general_id { 362 BREAK_POINT = 0x0, 363 BUS_ERROR = 0x1, 364 CMD_FIFO_OVRFLOW = 0x2, 365 MCS_STACK_OVRFLOW = 0x3, 366 }; 367 368 #define GSI_CNTXT_INTSET_OFFSET \ 369 (0x0001f180 + 0x4000 * GSI_EE_AP) 370 #define INTYPE_FMASK GENMASK(0, 0) 371 372 #define GSI_ERROR_LOG_OFFSET \ 373 (0x0001f200 + 0x4000 * GSI_EE_AP) 374 375 /* Fields below are present for IPA v3.5.1 and above */ 376 #define ERR_ARG3_FMASK GENMASK(3, 0) 377 #define ERR_ARG2_FMASK GENMASK(7, 4) 378 #define ERR_ARG1_FMASK GENMASK(11, 8) 379 #define ERR_CODE_FMASK GENMASK(15, 12) 380 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 381 #define ERR_TYPE_FMASK GENMASK(27, 24) 382 #define ERR_EE_FMASK GENMASK(31, 28) 383 384 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 385 enum gsi_err_code { 386 GSI_INVALID_TRE = 0x1, 387 GSI_OUT_OF_BUFFERS = 0x2, 388 GSI_OUT_OF_RESOURCES = 0x3, 389 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 390 GSI_EVT_RING_EMPTY = 0x5, 391 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 392 /* 7 is not assigned */ 393 GSI_HWO_1 = 0x8, 394 }; 395 396 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 397 enum gsi_err_type { 398 GSI_ERR_TYPE_GLOB = 0x1, 399 GSI_ERR_TYPE_CHAN = 0x2, 400 GSI_ERR_TYPE_EVT = 0x3, 401 }; 402 403 #define GSI_ERROR_LOG_CLR_OFFSET \ 404 (0x0001f210 + 0x4000 * GSI_EE_AP) 405 406 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 407 (0x0001f400 + 0x4000 * GSI_EE_AP) 408 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 409 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 410 411 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 412 enum gsi_generic_ee_result { 413 GENERIC_EE_SUCCESS = 0x1, 414 GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2, 415 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 416 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 417 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 418 GENERIC_EE_RETRY = 0x6, 419 GENERIC_EE_NO_RESOURCES = 0x7, 420 }; 421 422 #endif /* _GSI_REG_H_ */ 423